TW201909340A - Dynamic random access memory and method of manufacturing the same - Google Patents

Abstract

A dynamic random access memory (DRAM) includes a substrate, isolation structures, word line sets, bit-line structures, spacers, capacitors, and capacitor contacts. The isolation structures are located in the substrate to divided the substrate into active regions. The active areas are configured in the shape of band and arranged as an array. The word line sets are disposed in the substrate in parallel in a Y direction. The bit-line structures are disposed on the substrate in parallel in a X direction and across the word line sets. The spacers are disposed on sidewalls of the substrate in parallel in the X direction, wherein the spacers include silicon oxide. The capacitors are respectively disposed at two terminal of the long side of each of the active areas. The capacitor contacts are respectively located between the capacitors and the active regions.

Description

Dynamic random access memory and manufacturing method thereof

The present invention relates to a memory element and a method of fabricating the same, and more particularly to a dynamic random access memory and a method of fabricating the same.

The DRAM is a kind of volatile memory, which is composed of a plurality of memory cells. In detail, each memory cell is mainly composed of a transistor and a capacitor controlled by a transistor, and each of the memory cells is electrically connected to each other by a word line and a bit line. In order to improve the accumulative degree of dynamic random access memory to speed up the operation speed of components and meet the consumer demand for miniaturized electronic devices, buried word line dynamic random access memory (buried word) has been developed in recent years. Line DRAM) to meet the above needs.

In the prior art, thicker bit line spacers are often used to reduce parasitic capacitance between adjacent bit lines. However, in the case where the memory is increased and the component size is reduced, the thicker bit line spacer compresses the line width of the capacitor contact window, so that the contact between the capacitor contact window and the active region is made. The area is reduced. As the contact area between the capacitor contact window and the active region becomes smaller, the resistance between the capacitor contact window and the active region is increased, thereby reducing product reliability. Therefore, how to develop a dynamic random access memory and a manufacturing method thereof, which can reduce the parasitic capacitance between adjacent bit lines and maintain the contact area between the capacitor contact window and the active area will become an important subject.

The present invention provides a dynamic random access memory and a method of fabricating the same that can reduce parasitic capacitance between adjacent bit lines and maintain a contact area between a capacitor contact window and an active area.

The present invention provides a dynamic random access memory comprising: a substrate, a plurality of isolation structures, a plurality of word line groups, a plurality of bit line structures, a plurality of spacers, a plurality of capacitors, and a plurality of capacitor contact windows. The isolation structure is located in the substrate to divide the substrate into a plurality of active regions. The active regions are arranged in a strip shape and arranged in an array. The word line groups are arranged in parallel in the substrate along the Y direction. The bit line structures are disposed in parallel along the X direction on the substrate and traverse the word line set. The spacers are disposed in parallel along the X direction on sidewalls of the bit line structure, wherein the spacers comprise ruthenium oxide. The capacitors are respectively disposed at two ends of the long sides of the active region. The capacitor contact windows are respectively located between the capacitor and the active region.

The present invention provides a method of fabricating a dynamic random access memory, the steps of which are as follows. A plurality of isolation structures are formed in the substrate to divide the substrate into a plurality of active regions. The active regions are arranged in a strip shape and arranged in an array. A plurality of word line groups are formed in the substrate. The set of word lines extends along the Y direction and passes through the isolation structure and the active area to divide the substrate into a plurality of first regions and a plurality of second regions. The first zone and the second zone are alternately arranged along the X direction and the word line group is located in the first zone. A plurality of bit line structures are formed on the substrate. The bit line structure extends along the X direction and spans the word line set. A plurality of spacers are respectively formed on sidewalls of the bit line structure. A plurality of conductor layers are formed on the substrate of the second region. A plurality of first dielectric layers are formed on the substrate of the first region. The top surface of the conductor layer is lower than the top surface of the first dielectric layer. A plurality of second dielectric layers are respectively formed in the conductor layer. Each of the second dielectric layers divides the corresponding conductor layer into two conductor posts. The material of the first dielectric layer is the same as the material of the second dielectric layer. A plurality of capacitors are respectively formed on the conductor post.

Based on the above, the present invention divides the conductor layer into a plurality of conductor pillars (or capacitor contact windows) by first forming a conductor layer and then forming a first dielectric layer and a second dielectric layer in the conductor layer. Therefore, the present invention can simplify the manufacturing method of the capacitor contact window and maintain the capacitor contact window as a columnar structure. Moreover, the bottom width of the formed capacitor contact window may be greater than or equal to the top width of the capacitor contact window, which may reduce the resistance between the capacitor contact window and the active region, thereby increasing the read speed of the dynamic random access memory. In turn, improve product efficiency and reliability. In addition, the present invention replaces the material of the spacers disposed on the sidewalls of the bit line structure with yttrium oxide to reduce the parasitic capacitance between adjacent bit line structures, thereby improving the performance of the memory. In addition, the present invention replaces the material of the dielectric layer next to the capacitor contact window with tantalum nitride, which avoids the problem of over-etching causing short-circuiting of adjacent two capacitor contact windows.

The above described features and advantages of the invention will be apparent from the following description.

The invention will be more fully described with reference to the drawings of the embodiments. However, the invention may be embodied in a variety of different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings will be exaggerated for clarity. The same or similar reference numerals indicate the same or similar elements, and the following paragraphs will not be repeated.

1 is a top plan view of a dynamic random access memory according to an embodiment of the present invention. Referring to FIG. 1, the embodiment provides a dynamic random access memory including: a substrate 100, a plurality of isolation structures 101, a plurality of active areas AA, a plurality of bit line structures 102, a plurality of word line groups 202, and a plurality of Capacitors contact windows CC1, CC2. For the sake of clarity of the drawing, FIG. 1 only shows the above-mentioned members, and other structures can be seen in the subsequent cross-sectional views of FIGS. 2A to 7.

As shown in FIG. 1, the substrate 100 includes a plurality of first regions R1 and a plurality of second regions R2. The first region R1 and the second region R2 are arranged to each other along the X direction. The isolation structure 101 is disposed in the substrate 100 to define the substrate 100 with a plurality of active areas AA. In other words, there is an isolation structure 101 between two adjacent active areas AA. In an embodiment, only one memory unit is formed on one active area AA, and each memory unit is separated by an isolation structure 101 to effectively reduce the interference problem between the memory units. In detail, the active areas AA are configured in a strip shape and arranged in an array. In this embodiment, the active area AA is arranged in three active area columns AC1~AC3, and the adjacent two active area lines are mirrored. For example, the long side direction of the active area row AC3 and the X direction are non-orthogonal and have an included angle θ, and the long side direction of the active area line AC2 and the X direction are non-orthogonal and have an included angle (180o-θ). In an embodiment, the included angle θ may be between 15 degrees and 75 degrees. However, the present invention is not limited thereto. In other embodiments, the adjacent two active area lines may also be the same configuration.

The bit line structure 102 is located on the substrate 100 and traverses the first region R1 and the second region R2. The bit line structures 102 extend in the X direction and are arranged in the Y direction. The word line group 202 is located in the substrate 100 of the first region R1. The word line group 202 is arranged along the Y direction D2 and along the X direction. Each word line set 202 has two buried word lines 202a, 202b. In an embodiment, the X direction and the Y direction are substantially perpendicular to each other.

In this embodiment, each active area AA has a long side L1 and a short side L2, and the long side L1 traverses the corresponding word line group 202 (ie, two buried word lines 202a, 202b), and Each of the active areas AA has a bit line contact window BC at an overlap with the corresponding bit line structure 102. Therefore, each bit line structure 102 can be electrically connected to a corresponding doped region (not shown) by using a bit line contact window BC when traversing the corresponding word line group 202, wherein the doping is performed. The zone is located between the two buried word lines 202a, 202b.

Capacitor contact windows CC1, CC2 are located on substrate 100 between bit line structures 102. In detail, the capacitor contact windows CC1 and CC2 are respectively disposed at the two end points of the long side L1 of the active area AA, and are electrically connected to the active area AA and a subsequently formed capacitor (not shown). In addition, although the capacitor contact windows CC1, CC2 are shown as rectangular in FIG. 1, the contact window actually formed is slightly rounded, and its size can be designed according to process requirements.

2A to 2C are schematic cross-sectional views showing a manufacturing flow of a dynamic random access memory along the line A-A' of Fig. 1. 3A to 3E, 4, 5A to 5C, and 6-7 are schematic cross-sectional views showing a manufacturing flow of the dynamic random access memory along the line B-B' of Fig. 1.

Referring to FIG. 1 and FIG. 2A simultaneously, the embodiment provides a method for manufacturing a dynamic random access memory, and the steps are as follows. First, an initial structure is provided that includes a substrate 100, a plurality of isolation structures 101, and a plurality of word line groups 202. The isolation structure 101 and the word line set 202 are all located in the substrate 100. Since the word line group 202 is not shown in the cross section of FIGS. 2A to 2C, a detailed description of the word line group 202 will be described later with reference to FIG. 3A. In this embodiment, the substrate 100 can be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (Semiconductor Over Insulator (SOI)).

As shown in FIG. 1 and FIG. 2A, the isolation structure 101 is disposed on the substrate 100 to separate the substrate 100 from the plurality of active regions AA. In an embodiment, the isolation structure 101 comprises a dielectric material, which may be tantalum oxide. In an embodiment, the isolation structure 101 can be, for example, a shallow trench isolation structure (STI).

As shown in FIGS. 1 and 3A, a plurality of word line groups 202 are disposed in the substrate 100 of the first region R1. In detail, each word line group 202 includes two buried word lines 202a, 202b. Each buried word line 202a includes a gate 204a and a gate dielectric layer 206a. The gate dielectric layer 206a surrounds the gate 204a to electrically isolate the gate 204a from the substrate 100. In one embodiment, the material of the gate 204a includes a conductive material, which may be, for example, a metal material, a barrier metal material, or a combination thereof, which may be formed by chemical vapor deposition or physical vapor deposition. The material of the gate dielectric layer 206a may be, for example, hafnium oxide, which may be formed by a chemical vapor deposition method, a thermal oxidation method, or an in situ steam generation (ISSG). Similarly, another buried word line 202b also includes a gate 204b and a gate dielectric layer 206b. The gate dielectric layer 206b surrounds the gate 204b to electrically isolate the gate 204b from the substrate 100. Additionally, the initial structure further includes a tantalum nitride layer 208. In detail, the tantalum nitride layer 208 is disposed on the buried word lines 202a and 202b. In an embodiment, the method of forming the tantalum nitride layer 208 may be a chemical vapor deposition method.

Referring back to Figures 1 and 2A, a plurality of bit line structures 102 are formed on the initial structure (or substrate 100). In the cross-section of FIG. 2A, the bit line structure 102 includes a hafnium oxide layer 104, a tantalum nitride layer 106, a barrier layer 108, a bit line 110, and a cap layer 112 from bottom to top. The first spacers 114 cover sidewalls of the tantalum nitride layer 106, sidewalls of the barrier layer 108, sidewalls of the bit lines 110, and sidewalls of the cap layer 112. The second spacer 116 covers the sidewall of the first spacer 114 and the sidewall of the ruthenium oxide layer 104. On the other hand, on the cross section along the active area AA, the bit line structure 102 includes a bit line contact window (not shown), a barrier layer 108, a bit line 110, and a cap layer 112 from bottom to top. The bit line structure 102 can be electrically connected to the active area AA (ie, the source/drain doped area) by a bit line contact window (not shown).

In an embodiment, the material of the bit line contact window (not shown) may be polysilicon or germanium. The material of the barrier layer 108 includes a barrier metal material, which may be, for example, TiN. The material of the bit line 110 may be a metal material, which may be, for example, W. The material of the cap layer 112 may be tantalum nitride. In addition, a deuterated metal layer (not shown) may be included between the bit line contact window (not shown) and the bit line 110, which may be, for example, TiSi, CoSi, NiSi, or a combination thereof.

It should be noted that the first spacers 114 and the second spacers 116 may be in the form of strips extending along the X direction, which may protect sidewalls of the bit line structures 102 to electrically isolate the bit line structures 102 and subsequent A conductor material 118 is formed (as shown in Figure 2B). In addition, the material of the first spacers 114 may be tantalum nitride, and the material of the second spacers 116 may be tantalum oxide. The method of forming the first spacers 114 and the second spacers 116 is similar to the conventional method of forming the spacers, and will not be described in detail herein. In one embodiment, since the second spacers 116 are yttria, the second spacers 116 of the present embodiment can effectively reduce the spacing between adjacent bit line structures 102 compared to conventional tantalum nitrides. The parasitic capacitance increases the performance of the memory. However, the present invention is not limited thereto, and the material of the second spacer 116 may be other low dielectric constant materials (that is, dielectric materials having a dielectric constant lower than 4). Additionally, after forming the second spacers 116 of the first spacers 114, there are a plurality of openings 10 between the bit line structures 102. The opening 10 exposes at least the top surface of the substrate 100 (or active area AA). In an alternate embodiment, as shown in FIG. 2A, a portion of the crucible substrate 100 may also be removed such that the bottom surface of the opening 10 is lower than the top surface of the substrate 100.

Referring to Figures 2A and 2B at the same time, conductor material 118 is formed on the initial structure (or substrate 100). Conductor material 118 fills into opening 10 between bit line structures 102 and extends over the top surface of bit line structure 102. The conductor material 118 may be polycrystalline germanium, which may be formed by chemical vapor deposition.

Referring to FIG. 2B and FIG. 2C simultaneously, a ruthenium oxide layer 120, a carbon layer 122, and a ruthenium oxynitride layer 124 are sequentially formed on the conductor material 118. In one embodiment, the composite layer of yttrium oxide layer 120, carbon layer 122, and yttrium oxynitride layer 124 can be considered a hard mask layer HM. In an embodiment, the ruthenium oxide layer 120 can be, for example, tetraethoxy decane.

Referring to FIG. 2C and FIG. 3A simultaneously, a photoresist pattern 126 is formed on the yttrium oxynitride layer 124 (or the hard mask layer HM). The photoresist pattern 126 has a plurality of openings 12. The opening 12 may be a strip-shaped opening that extends in the Y direction and exposes a portion of the surface of the yttria layer 124. On the other hand, the opening 12 is located only on the substrate 100 of the first region R1, which corresponds to the word line group 202 in the substrate 100 of the first region R1. In addition, since the opening 12 is only shown in the section of the line B-B' of Fig. 1 (i.e., Fig. 3A), the subsequent processes are described in detail along the section of the line B-B' of Fig. 1.

Referring to FIG. 3A and FIG. 3B simultaneously, a portion of the hard mask layer HM and a portion of the conductor material 118 are removed by using the photoresist pattern 126 as a mask to form a plurality of openings 14 in the remaining yttrium oxide layer 120a and the conductor layer 118a. . The opening 14 may be a strip-shaped opening that extends in the Y direction and exposes the top surface of the substrate 100 of the first region R1. That is, the opening 14 separates the adjacent two conductor layers 118a such that the conductor layer 118a is located on the substrate 100 of the second region R2. As shown in FIG. 3B, the conductor layer 118a may have a bottom width W1 and a top width W2. In an embodiment, the bottom width W1 may be greater than or equal to the top width W2. The conductor layer 118a covers at least the top surface of the substrate 100 (or active region AA) of the second region R1.

Referring to FIG. 3B and FIG. 3C simultaneously, a first dielectric material 128 is formed on the substrate 100. The first dielectric material 128 fills the opening 14 and covers the top surface 120T of the remaining ruthenium oxide layer 120a. In an embodiment, the first dielectric material 128 can be tantalum nitride.

Referring to FIG. 3C and FIG. 3D simultaneously, a planarization process is performed to remove a portion of the first dielectric material 128 to form a first dielectric layer 128a on the substrate of the first region R1. As shown in FIG. 3D, the top surface 128T of the first dielectric layer 128a is substantially coplanar with the top surface 120T of the yttrium oxide layer 120a. In an embodiment, the planarization process may be a chemical mechanical polishing (CMP) process or an Etching back process.

Referring to FIG. 3D and FIG. 3E simultaneously, the ruthenium oxide layer 120a is removed. As shown in FIG. 3E, the top surface 118T of the conductor layer 118a is lower than the top surface 128T of the first dielectric layer 128a. In an embodiment, there is a height difference H between the top surface 118T of the conductor layer 118a and the top surface 128T of the first dielectric layer 128a, and the height difference H may be between 20 nm and 150 nm.

Referring to FIG. 3E and FIG. 4 simultaneously, a dielectric layer 130 is formed on the substrate 100. The dielectric layer 130 is conformally formed on the conductor layer 118a and the first dielectric layer 128a. Since the top surface 118T of the conductor layer 118a and the top surface 128T of the first dielectric layer 128a have a height difference H, the top surface of the dielectric layer 130 can be, for example, a continuous relief structure. The dielectric layer 130 on the first dielectric layer 128a is a convex portion; and the dielectric layer 130 on the conductive layer 118a is a concave portion. As shown in FIG. 4, the dielectric layer 130 on the substrate 100 of the second region R2 has a recess opening 16 corresponding to the insulating structure 101 in the substrate 100. In an embodiment, the material of the dielectric layer 130 may be tantalum nitride.

Referring to FIG. 4 and FIG. 5A simultaneously, an etching process is performed to remove a portion of the dielectric layer 130 and a portion of the conductor layer 118a to form an opening 18 in the conductor post 118b of the second region R2 and the dielectric layer 130a. The opening 18 exposes the surface of the insulating structure 101 of the second region R2. In addition, when performing the above etching process, the dielectric layer 130 of the first region R1 is also removed to expose the top surface of the first dielectric layer 128a. On the other hand, the opening 18 divides one conductor layer 118a into two conductor posts 118b. In one embodiment, the opening 18 can be considered a self-aligned opening because the opening 18 does not require alignment with the insulating structure 101 of the second region R2 using a lithography process.

Referring to FIG. 5A and FIG. 5B simultaneously, a second dielectric material 132 is formed on the substrate 100. A second dielectric material 132 fills the opening 18 and covers the top surface of the remaining dielectric layer 130a. In an embodiment, the second dielectric material 132 can be tantalum nitride. In other words, the first dielectric material 128 is the same as the second dielectric material 132.

Referring to FIG. 5B and FIG. 5C simultaneously, a planarization process is performed to remove a portion of the second dielectric material 132 and the remaining dielectric layer 130a to expose the top surface of the conductor post 118b. In an embodiment, the planarization process may be a CMP process or an etch back process. Thereafter, an etching process is performed to remove a portion of the conductor post 118b to form an opening 20 on the conductor post 118c1 and form an opening 22 on the conductor post 118c2. In an embodiment, the etching process may be a wet etching or a dry etching process. In one embodiment, as shown in FIG. 5C, the bottom surface of the opening 20 is coplanar with the bottom surface of the opening 22.

Referring to FIG. 5C and FIG. 6 simultaneously, a deuterated metal layer 134 and a metal layer 136 are formed on the conductor post 118c1 and the conductor post 118c2, respectively. In an embodiment, the deuterated metal layer 134 can be, for example, TiSi, CoSi, NiSi, or a combination thereof. In an embodiment, the metal layer 136 can be, for example, W. As shown in FIG. 6, the composite structure of the conductor post 118c1, the deuterated metal layer 134, and the metal layer 136 can be regarded as the capacitor contact window CC1; and the composite structure of the conductor post 118c2, the deuterated metal layer 134, and the metal layer 136 can be regarded as the capacitor contact window CC2. . The capacitor contact window CC1 is disposed at one end of the active area AA to electrically connect the active area AA with the subsequently formed capacitor 142 (shown in FIG. 7). The capacitor contact window CC2 is disposed at the other end of the active area AA to electrically connect the active area AA with the subsequently formed capacitor 142 (shown in FIG. 7).

In one embodiment, as shown in FIG. 6, the capacitor contact window CC1 covers not only the surface of the active area AA but also the top surface of the partially buried word line 202a. Specifically, the capacitor contact window CC1 has a bottom width W3 and a top width W4, wherein the bottom width W3 is greater than or equal to the top width W4. That is, the capacitor contact window CC1 may be a trapezoidal structure or a rectangular structure. In an embodiment, the bottom width W3 of the capacitor contact window CC1 is between 10 nm and 80 nm. In other words, the present embodiment can maximize the contact area between the capacitor contact window CC1 and the active area AA, so that the resistance between the capacitor contact window CC1 and the active area AA is lowered, thereby increasing the reading of the dynamic random access memory. Speed, which in turn increases product efficiency and reliability. Similarly, the capacitor contact window CC2 also has the same effect, and will not be described again here.

In addition, in this case, the second dielectric layer 132a corresponds to the isolation structure 101 in the substrate 100 of the second region R2, respectively, to electrically isolate the adjacent two conductor posts 118c1, 118c2 (or capacitor contact windows CC1, CC2). .

Referring to FIG. 6 and FIG. 7 simultaneously, a dielectric layer 140 is first formed on the substrate 100. Thereafter, a plurality of capacitor openings 24 are formed in the dielectric layer 140, and a plurality of capacitors 142 are respectively formed in the capacitor openings 24. The capacitor 142 is electrically connected to the active area AA via the capacitor contact windows CC1 and CC2, respectively. Specifically, each capacitor 142 includes a lower electrode 142a, an upper electrode 142c, and a dielectric layer 142b. The dielectric layer 142b is located between the lower electrode 142a and the upper electrode 142c. The lower electrodes 142a are electrically connected to the capacitor contact windows CC1 and CC2, respectively. In an embodiment, the material of the dielectric layer 140 may be, for example, hafnium oxide. The material of the lower electrode 142a and the upper electrode 142c is, for example, titanium nitride, tantalum nitride, tungsten, titanium tungsten, aluminum, copper or metal telluride. The dielectric layer 142b may include a high dielectric constant material layer (ie, a dielectric material having a dielectric constant higher than 4), and the material thereof is, for example, an oxide of the following elements, such as germanium, zirconium, aluminum, titanium, germanium, germanium. , 釓 or 钽, or aluminum nitride, or any combination of the above.

It should be noted that, since the materials of the first dielectric layer 128a and the second dielectric layer 132a are both tantalum nitride, when the capacitor opening 24 is formed in the dielectric layer 140, the first dielectric layer 128a and the second layer Dielectric layer 132a can be used as an etch stop layer. The etch stop layer can avoid over-etching when forming the capacitor opening 24, resulting in a short circuit problem caused by the electrical connection of the adjacent two capacitor contact windows CC1, CC2. On the other hand, even if there is overlap shift or misalignment during the formation of the capacitor opening 24, the first dielectric layer 128a and the second dielectric layer 132a composed of tantalum nitride are also Over-etching of the capacitor opening 24 can be prevented to prevent short-circuit problems between adjacent two capacitor contact windows CC1, CC2. Therefore, the capacitor contact windows CC1, CC2 of the present embodiment can maintain the columnar structure without generating sharp corners at the bottom of the capacitor contact windows CC1, CC2.

In summary, the present invention divides the conductor layer into a plurality of conductor posts (or capacitor contact windows) by first forming a conductor layer and then forming a first dielectric layer and a second dielectric layer in the conductor layer. Therefore, the present invention can simplify the manufacturing method of the capacitor contact window and maintain the capacitor contact window as a columnar structure. Moreover, the bottom width of the formed capacitor contact window may be greater than or equal to the top width of the capacitor contact window, which may reduce the resistance between the capacitor contact window and the active region, thereby increasing the read speed of the dynamic random access memory. In turn, improve product efficiency and reliability. In addition, the present invention replaces the material of the spacers disposed on the sidewalls of the bit line structure with yttrium oxide to reduce the parasitic capacitance between adjacent bit line structures, thereby improving the performance of the memory. In addition, the present invention replaces the material of the dielectric layer next to the capacitor contact window with tantalum nitride, which avoids the problem of over-etching causing short-circuiting of adjacent two capacitor contact windows.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10,12,14,16,18,20,22,24‧‧

100‧‧‧Base

101‧‧‧Isolation structure

102‧‧‧ bit line structure

104‧‧‧Oxide layer

106‧‧‧layer of tantalum nitride

108‧‧‧Barrier layer

110‧‧‧ bit line

112‧‧‧Top cover

114‧‧‧First gap

116‧‧‧Second gap

118‧‧‧Conductor materials

118a‧‧‧ conductor layer

118b, 118c1, 118c2‧‧‧ conductor column

118T‧‧‧ top surface

120, 120a‧‧‧ yttrium oxide layer

120T‧‧‧ top surface

122‧‧‧ carbon layer

124‧‧‧Nitrogen oxide layer

126‧‧‧resist pattern

128‧‧‧First dielectric material

128a‧‧‧First dielectric layer

128T‧‧‧ top surface

130, 130a‧‧‧ dielectric layer

132‧‧‧Second dielectric material

132a‧‧‧Second dielectric layer

134‧‧‧Deuterated metal layer

136‧‧‧metal layer

140‧‧‧Dielectric layer

142‧‧‧ capacitor

142a‧‧‧ lower electrode

142b‧‧‧ dielectric layer

142c‧‧‧Upper electrode

202‧‧‧ character line group

202a, 202b‧‧‧ Buried word line

204a, 204b‧‧‧ gate

206a, 206b‧‧‧ gate dielectric layer

208‧‧‧ layer of tantalum nitride

AA‧‧‧Active Area

AC1~AC3‧‧‧Active Area

BC‧‧‧ bit line contact window

CC1, CC2‧‧‧ capacitor contact window

H‧‧‧ height difference

HM‧‧‧hard mask layer

L1‧‧‧ long side

L2‧‧‧ Short side

R1‧‧‧ first district

R2‧‧‧Second District

W1, W3‧‧‧ bottom width

W2, W4‧‧‧ top width

X, Y‧‧ direction

Θ‧‧‧ angle

1 is a top plan view of a dynamic random access memory according to an embodiment of the present invention. 2A to 2C are schematic cross-sectional views showing a manufacturing flow of a dynamic random access memory along the line A-A' of Fig. 1. 3A to 3E, 4, 5A to 5C, and 6-7 are schematic cross-sectional views showing a manufacturing flow of the dynamic random access memory along the line B-B' of Fig. 1.

Claims (20)

A dynamic random access memory, comprising: a plurality of isolation structures disposed in a substrate to divide the substrate into a plurality of active regions, the active regions being configured in a strip shape and arranged in an array; a plurality of word lines a plurality of bit line structures arranged in parallel along the X direction on the substrate and traversing the word line group; a plurality of spacers along the plurality of spacers The X direction is disposed in parallel on a sidewall of the bit line structure, wherein the spacer includes a ruthenium oxide; a plurality of capacitors respectively disposed at both ends of a long side of the active region; and a plurality of capacitors Contact windows are respectively located between the capacitor and the active region. The dynamic random access memory according to claim 1, wherein each of the spacers includes a first spacer and a second spacer, and the first spacer is located in the bit line structure and Between the second spacers. The dynamic random access memory of claim 2, wherein the first spacer comprises tantalum nitride and the second spacer comprises hafnium oxide. The dynamic random access memory according to claim 1, further comprising a plurality of dielectric layers respectively located between the capacitor contact windows, wherein the dielectric layer comprises tantalum nitride. The dynamic random access memory according to claim 1, wherein the word line group includes two buried word lines. The dynamic random access memory of claim 5, wherein one of the capacitor contact windows covers a portion of a top surface of the active region and one of the two buried word lines. The dynamic random access memory according to claim 1, wherein each of the capacitor contact windows is a composite structure including a conductor layer, a deuterated metal layer, and a metal layer. The dynamic random access memory of claim 1, wherein each of the capacitor contact windows has a bottom width and a top width, the bottom width being greater than or equal to the top width. The dynamic random access memory of claim 1, wherein the active areas of two adjacent rows are in a mirrored configuration. A method for manufacturing a dynamic random access memory, comprising: forming a plurality of isolation structures in a substrate to divide the substrate into a plurality of active regions, the active regions being arranged in a strip shape and arranged in an array; Forming a plurality of word line groups in the substrate, the word line groups extending along the Y direction and passing through the isolation structure and the active area to divide the substrate into a plurality of first areas and a plurality of a second area, wherein the first area and the second area are alternately arranged along the X direction and the word line group is located in the first area; forming a plurality of bit line structures on the substrate a bit line structure extending along the X direction and spanning the word line group; a plurality of spacers respectively formed on sidewalls of the bit line structure; on the substrate of the second area Forming a plurality of conductor layers; forming a plurality of first dielectric layers on the substrate of the first region, wherein a top surface of the conductor layer is lower than a top surface of the first dielectric layer; A plurality of second dielectric layers are respectively formed in the conductor layer, and each of the second dielectric layers has a corresponding conductor layer Dividing into two conductor pillars, wherein a material of the first dielectric layer is the same as a material of the second dielectric layer; and a plurality of capacitors are respectively formed on the conductor pillars. The method of manufacturing a dynamic random access memory according to claim 10, wherein the material of the first dielectric layer comprises tantalum nitride, and the material of the second dielectric layer comprises tantalum nitride. The method of manufacturing a dynamic random access memory according to claim 10, wherein the forming method of the first dielectric layer comprises: forming a conductor material on the substrate between the bit line structures Removing a portion of the conductor material to form a plurality of openings in the conductor material, the openings exposing a surface of the substrate of the first region and separating each of the conductor materials into two conductor layers ; filling a first dielectric material into the opening. The method for manufacturing a dynamic random access memory according to claim 10, wherein the second dielectric layer is electrically isolated from the isolation structure in the substrate of the second region. Two adjacent conductor posts. The method of manufacturing a dynamic random access memory according to claim 10, wherein each of the spacers includes a first spacer and a second spacer, and the first spacer is located in the bit line structure Between the second spacer and the second spacer. The method of manufacturing a dynamic random access memory according to claim 14, wherein the first spacer includes tantalum nitride, and the second spacer includes hafnium oxide. The method of manufacturing a dynamic random access memory according to claim 10, wherein the word line group includes two buried word lines. The method of manufacturing a dynamic random access memory according to claim 16, wherein the conductor post is a capacitor contact window covering the active area and one of the two buried word lines. Part of the top. The method of manufacturing a dynamic random access memory according to claim 17, wherein each of the capacitor contact windows has a bottom width and a top width, and the bottom width is greater than or equal to the top width. The method of manufacturing a dynamic random access memory according to claim 17, wherein each of the capacitor contact windows is a composite structure including a conductor layer, a deuterated metal layer, and a metal layer. The method for manufacturing a dynamic random access memory according to claim 10, wherein the active areas of two adjacent rows are in a mirror image configuration.