JP4882333B2 - Control system - Google Patents

Description

  The present invention relates to a control system for controlling a plurality of devices connected to a controller.

  Conventionally, in electronic devices, for example, devices are controlled by performing communication between devices using a dedicated bus such as an Internet integrated circuit (IIC), a serial peripheral interface (SPI), or a universal asynchronous receiver transmitter (UART). I was going. However, each of these buses has disadvantages, and it has been customary to control devices in the equipment while selecting an optimal communication method according to the conditions.

FIG. 7 is a configuration diagram of a control system according to a standard connection example of IIC, FIG. 8 shows a timing chart of data reading or writing, FIG. 8A is data, FIG. 8B is a clock, and FIG. It is.
In the control system based on IIC shown in FIG. 7, using two control lines of a clock 63 and data 64, modules 61-2, 62-2, which are devices to be controlled, from a device 61 that is a controller, ... 62-n can be controlled.

  For example, when the data shown in FIG. 8A is 1 to 8 bits and is “01111000” in binary display (“78” in hexadecimal display), the control of writing to the address assigned to the module 62-2 is shown. When the hexadecimal display is “01111001” (hexadecimal display “79”), the read control for the address assigned to the module 62-2 is shown.

  The data shown in FIG. 8A is set according to the number of clocks shown in FIG. 8B. When the data shown in FIG. 8A is 1 to 8 bits, the data content shown in FIG. 8C indicates the address 74. When the data shown in FIG. 8A is 9 bits and the high impedance 73, the data content shown in FIG. 8C is an acknowledge. 75. The data shown in FIG. 8A is 1 to 9 bits, which is one cycle.

Similarly, when the data shown in FIG. 8A is 1 to 8 bits in the next cycle, the data content shown in FIG. 8C indicates the sub-address 76, and the data shown in FIG. At this time, the data content shown in FIG.
9 is a configuration diagram of a control system according to a standard connection example in SPI. FIG. 10 is a timing chart of data output or data input by chip select, FIG. 10A is a clock, and FIG. 10B is a data output. FIG. 10C shows data input, and FIG. 10D shows chip select.

  In the control system based on the SPI shown in FIG. 9, three communication lines of the clock 83, the data output 84 and the data input 85 and one control line of the chip select 86 are used, and the clock synchronous method is performed at a speed of about 1 Mbps. It is possible to control the module 82-1 serving as a device by one-to-one communication from the device 81 serving as a controller.

  Further, when the modules 82-1, 82-2,... 82-n, which are a plurality of devices, are controlled by the one-to-many communication from the device 81 serving as the controller, the chip select 86, 87,. One-to-many communication is possible by arranging 88 control lines corresponding to the number of modules 82-1, 82-2,.

  For example, the device 81 serving as the controller selects modules 82-1, 82-2,... 82-n serving as devices controlled by the chip select 86, 87,. Next, the device 81 serving as a controller synchronizes with the clock shown in FIG. 10A, and the modules 82-1, 82-2,... 82 selected by the chip select 86, 87,. The data output 84 shown in FIG. 10B is transmitted to -n. As a result, the device 81 serving as the controller inputs the data shown in FIG. 10C from the modules 82-1, 82-2,... 82-n selected by the chip select 86, 87,. 85 is received.

  In addition, as an example of a conventional serial communication circuit, a circuit that generates and outputs a received data signal by receiving data from a communication system in which a frame synchronization signal is transmitted and received as a data signal on different communication lines, and a single communication line A device including a received frame synchronization signal and a circuit for generating and outputting received data from data from a communication system that includes a frame synchronization signal in the data signal sequence and is transmitted and received is disclosed (see Patent Document 1).

In addition, as an example of data transfer that eliminates transmission delay due to multi-stage connection, two sets of serial communication driver processes that receive and transmit serial data that handle different data rates, and command analysis of received data from serial communication drivers, In the case of a station, device control is performed by the command, command analysis / response assembly processing for assembling response data, transmission data from one serial communication driver to the other serial communication driver, and vice versa. (2) discloses one character transfer process for requesting transmission of data received from one serial communication driver and transmission data to the other serial communication driver (see Patent Document 2).
Japanese Utility Model Publication No. 4-15334 JP-A-5-284190

  However, in the control system based on IIC described above, when a large number of devices are connected inside the system, or when control is performed over a very long distance using a wire for connection between devices, the capacitance between the lines and the capacitance of the devices As a result, the signal level is lowered and the rise and fall of the signal waveform are dull. For this reason, there has been a disadvantage that the signal waveform cannot be detected and communication cannot be performed correctly due to the decrease in the level of the signal waveform and the decrease in the integral value.

  In the above-described control system based on the SPI, one-to-one communication is possible with a single control line. However, when a plurality of devices are controlled from a controller with one-to-many communication, control is performed. It is necessary to prepare as many lines as the number of devices to be controlled. For this reason, when controlling a large number of devices, a large number of control lines are required between the controller and a plurality of devices. Therefore, the controller must be replaced with one having a large number of pins, and in the system. There was an inconvenience of increased wiring.

  Therefore, the present invention can correctly communicate even if the signal waveform level is lowered and the integrated value is lowered due to the capacitance between the lines and the capacitance of the device, and a plurality of devices can be controlled from the controller by one-to-many communication. It is an object of the present invention to provide a control system that does not require an increase in the number of control lines.

In order to solve the above-described problems and achieve the object of the present invention, a controller that performs control and a plurality of devices that are controlled by the controller include one signal line for clock transmission and one output signal transmission. In a control system connected by a single signal line and a single input signal transmission signal line, a signal related to control of a controller for controlling a plurality of devices to the same state is based on a preset threshold value. The waveform shaping block to be shaped is provided in any one of a plurality of devices, and signals relating to the control of the controller shaped by the waveform shaping block are sequentially sent to the next stage via three signal lines .

  As a result, for example, in the connection between a controller and a plurality of devices in general electronic equipment, communication data can be sent to the next stage as it is by adding a waveform shaping block. Cascade connection can be performed continuously.

  In addition, since the quality of the communication signal does not deteriorate, it is possible to control a plurality of devices to the same state with hundreds to thousands of devices connected. In addition, when connecting hundreds to thousands of devices, it is not necessary to add signal lines and only a fixed number of signal lines need to be connected, contributing to downsizing of equipment. Can do. Further, since it is not necessary to increase the number of input / output pins of the controller and many devices can be connected to one controller, the configuration of the controller is simplified and the cost can be kept low.

  According to the present invention, communication can be performed correctly even if the signal waveform level decreases and the integrated value decreases due to the capacitance between the lines and the capacitance of the device, and a plurality of devices are controlled from the controller by one-to-many communication. In this case, a control system that does not require an increase in the number of control lines can be obtained.

  For example, when transferring data and clocks between modules, there is no signal degradation by regenerating the signal by waveform shaping, and even if there is a cable of several meters for communication between modules, it is sufficiently correct Since communication is possible, the cost of the device can be kept low.

Embodiments of the present invention will be described below with reference to the drawings as appropriate.
FIG. 1 is a configuration diagram of a control system applied to the present embodiment.
In FIG. 1, a device 1 indicates a host controller that controls a control system such as a CPU. Each of the modules 2-1, 2-2,... 2-n (for example, several hundred to several thousand) includes a device to be controlled.

Further, the modules 2-1, 2-2,..., 2-n of the present embodiment buffer the clock 11 and the data output signal 12 output from the device 1 and the input signal 13 input to the device 1. And a buffer circuit for waveform shaping. A device including the above-described buffer circuit in this device is referred to as a module in this embodiment.
Here, the modules 2-1, 2-2,... 2 -n are cascade-connected in succession by using only three signal lines of the clock 11, the output signal 12 and the input signal 13.

FIG. 2 is a block diagram showing the configuration of the module.
In FIG. 2, the clock 11-n-1, the output signal 12-n-1, and the input signal 13-n-1 are connected to the module 2- through three signal lines connected to one module 2-n. n is connected to the clock terminal 22-n, the data output terminal 23-n, and the data input terminal 24-n of the device 21-n.

  Further, the clock 11-n-1, the output signal 12-n-1 and the input signal 13-n-1 are connected to the buffer circuits 25-n, 26-n and 27-n in the module 2-n. . The buffer circuits 25-n, 26-n, and 27-n are buffer circuits configured by a plurality of gates arranged in a standard IC such as a model “74HL08”, for example.

The operation of the control system applied to this embodiment configured as described above will be described below.
First, the transmission timing of address data and control data in this control system will be described.
FIG. 3 is a timing chart showing address data and control data. FIG. 3A is a clock, FIG. 3B is a data output, and FIG. 3C is a data input.
In the present embodiment, which device 21 the device 1 accesses is determined by following the address data 31 for designating the address in the data signal in the data output shown in FIG. 2-2,..., 2-n devices 21-1, 21-2,.

  The device 1 transmits the address data and the control data 33 to the devices 21-1, 21-2,... 21-n of the modules 2-1, 2-2,. It is possible to control the specific devices 21-1, 21-2,... 21-n of the modules 2-1, 2-2,.

For example, the device 1 converts the 3-bit address data 31 based on the data A1, A2, and A3 in the data output shown in FIG. 3B to the module 2-1, at the falling edge of the clock shown in FIG. 3A at the time T1, time T2, and time T3. 2-2,..., 2-n devices 21-1, 21-2,..., 21-n are transmitted to a maximum of 2 ³ (= 8) modules 2-1, 2-2. ... 2-n addresses can be specified.

Further, the device 1 follows the address data 31, and the data shown in FIG. 3B at the falling edge of the clock shown in FIG. 3A at the times T4, T5, T6, T7, T8, T9, T10, and T11. 8-bit control data 32 based on the data D1, D2, D3, D4, D5, D6, D7, and D8 being output is converted into the devices 21-1, 21-21 of the modules 2-1, 2-2,. 2, ... 21-n followed by transmission, the devices 21-1, 21-2, ... 21 of the modules 2-1, 2-2, ... 2-n whose addresses are specified -N can be controlled to a maximum of 2 ⁸ (= 256) states.

For example, there are five (n = 5) control data of the devices 21-1, 21-2,..., 21-n of the modules 2-1, 2-2,. Is 8 bits, the amount of data transmitted by the device 1 is 3 bits + 8 bits = 11 bits.
Further, it is possible to control by changing the number of bits of the address data 31 and the control data 32 according to the number of devices to be controlled and the control state.

For example, when a plurality of devices are a plurality of light emitting elements and driving units (for example, hundreds to thousands) provided in the scanning line direction for each line in the display device, the plurality of light emitting elements and driving units are designated. A relatively large number of bits of the address data 31 are possible.
Further, when the plurality of light emitting elements and the drive unit are controlled to be in the same state, the number of bits of the control data 32 is set to a relatively small number of bits. Thereby, a plurality of light emitting elements can be caused to emit light with the same light emission pattern (for example, various test patterns) by controlling the drive unit of the device 1.

Next, the timing of waveform shaping of data output in this control system will be described.
FIG. 4 is a timing chart showing waveform shaping of data output. FIG. 4A shows data output 12, FIG. 4B shows data output 12-n-1, and FIG. 4C shows data output 12-n.
The data output 12 shown in FIG. 4A output from the device 1 rises to 5V at time T21, falls to 0V at time T22, rises to 5V at time T23, falls to 0V at time T24, and goes to 5V at time T25. It is a signal that rises, falls to 0V at time T26, and repeats.

  At this time, the data output 12-n-1 shown in FIG. 4B input to the module 2-n shown in FIG. 2 gradually increases from 0V to 3V from the time T21 to the time T22 and reaches 3V. From 3V to T23, it gradually decreases from 3V due to the transient characteristics and reaches 0V. From T23 to T24, it gradually increases from 0V to transient characteristics and reaches 3V, and from T24 to T25, transients from 3V. It is a signal that gradually decreases due to the characteristics and reaches 0 V, and gradually increases from 0 V to 3 V due to the transient characteristics from the time T25 to the time T26, and so on.

  Here, the data output 12-n shown in FIG. 4C output from the module 2-n shown in FIG. 2 is output from the buffer circuit 26-n by T31 when the data output 12-n-1 shown in FIG. 4B exceeds the threshold Th. It rises to 5V at the time point, falls to 0V at time T32 when the data output 12-n-1 shown in FIG. 4B falls below the threshold Th, and reaches 5V at time T33 when the data output 12-n-1 shown in FIG. 4B exceeds the threshold Th. 4B, the data output 12-n-1 shown in FIG. 4B falls to 0V at a time T34 below the threshold Th, and the data output 12-n-1 shown in FIG. 4B rises to 5V at a T35 time above the threshold Th. At time T36 when the data output 12-n-1 shown in FIG. 4B falls below the threshold Th, the signal falls to 0V and becomes a signal that repeats.

  At this time, the buffer circuit 26-n receives the data output 12-n-1 shown in FIG. 4B, which is input with a threshold value Th of about 2V to 2.5V, for example, as a minimum value for defining a high logic level. And the waveform is shaped so that it rises to 5 V that defines a predetermined high logic level.

Conversely, the buffer circuit 26-n receives the data output 12-n shown in FIG. 4B, which is input with a threshold Th of about 2.5V to 2V, for example, as the maximum value for defining the logic low level. -1 is buffered, and the waveform is shaped so as to fall to 0 V that defines a low level of a predetermined logic level.
Here, the data output 12-n shown in FIG. 4C is shaped so as to have a preset level of 5V and an integral value (a value that enables normal operation of the device).
Although only data output has been described here, the waveforms of the other clocks 11-n-1 and data input 13-n are similarly shaped by the buffer circuits 25-n and 27-n.

  Thus, when the clock 11-n, the output signal 12-n, and the input signal 13-n-1 are output, the waveform is shaped by the buffer circuits 25-n, 26-n, and 27-n. . For example, even when the waveform has a dullness at the rise and fall due to a long wiring inside the electronic device, the waveform is not transmitted to the next block by the buffer circuits 25-n, 26-n, and 27-n. This dullness will be resolved.

At this time, the clock 11-n, the output signal 12-n, and the input signal 13-n-1 are delayed with respect to the original signal, but have the same amount of delay within the same module 2-n. Therefore, no trouble occurs in the operation of the device 21-n.
In the above-described embodiment, the example in which the waveform shaping in the module is performed by the buffer circuit has been described.

FIG. 5 is a block diagram showing the configuration of another module.
5 differs from the module configuration 2-n shown in FIG. 2 in that the waveform shaping of the clock 11-n-1 is changed from the buffer circuit 25-n shown in FIG. Only the PLL circuit 55-n shown in FIG. Since other configurations and operations are the same as those in FIG. 2, only different points will be described.

FIG. 6 is a timing chart showing the waveform shaping of the clock. FIG. 6A shows the clock 11-n-1, FIG. 6B shows the clock 11-n− (when the PLL circuit is used), and FIG. 6C shows the clock 11-n (when the buffer is used). It is.
Here, using the PLL circuit 55-n, a new diagram is shown at the fall of the clock 11-n-1 shown in FIG. 6A at time T41, time T42, time T43, time T44, time T45, time T46,. If the clock 11-n ｀ (at the time of the PLL circuit) shown in 6B is generated, unlike the case where the delay τ of the clock 11-n (at the time of buffering) shown in FIG. 6C occurs at the time of waveform shaping by the buffer circuit 25-n. The clock signal can be generated without causing a delay.

  In this case, the PLL circuit 55-n receives the clock shown in FIG. 6A at the falling edge of the clock 11-n-1 shown in FIG. 6A at time T41, time T42, time T43, time T44, time T45, time T46,. 11-n-1 and the clock 11-n ｀ shown in FIG. 6B (at the time of the PLL circuit), the feedback is performed while performing the phase comparison, so that the clock 11-n-1 shown in FIG. 6A and the clock 11- shown in FIG. The phase of n ｀ (in the PLL circuit) is always kept in the same phase.

  When the clock 11-n (during buffering) shown in FIG. 6C is input to the buffer circuit 25-n, there is no control by the PLL circuit 55-n described above, so the clock 11-n shown in FIG. With respect to −1, a delay 11 corresponding to the buffering operation occurs in the clock 11-n (buffer time) shown in FIG. 6C.

  Here, a delay τ is generated between the clock 11-n ｀ (in the PLL circuit), the output signal 12-n, and the input signal 13-n-1, but within the same module 2-n. Since this is a delay amount of the buffering operation amount, there is no problem in the operation of the device 21-n.

  The above-described waveform shaping buffer circuit and PLL circuit may be provided in each module in the system. However, the present invention is not limited thereto, and may be provided in any module in the system. Also good.

  According to the above-described embodiment, the output from each module is shaped and always has a clean edge waveform, so that a large number of modules can be connected to the cascade. Regardless of the number of modules connected, only one system is required, and it is not necessary to increase the pin arrangement of the device, so the cost can be kept low.

  In addition, since the rising and falling edges of the signal from the bus wiring inside the system are always shaped, the operating state of the devices in the module can be kept normal, and many devices can be connected on the same bus. Therefore, the system configuration becomes very simple.

  Further, since many modules can be connected to one bus on one device and address data and control data can be transmitted on the same line, the configuration of the device is simplified and the cost can be kept low.

  In addition, since the devices in the system and each module are cascade-connected, wiring between the modules is simpler than in the case where a large number of wires are wired from one device.

  It goes without saying that the configuration can be changed as appropriate within the scope of the present invention, not limited to the above-described embodiment.

It is a block diagram of the control system applied to this Embodiment. It is a block diagram which shows the structure of a module. FIG. 3A is a timing chart showing address data and control data, FIG. 3A is a clock, FIG. 3B is a data output, and FIG. 3C is a data input. 4A and 4B are timing charts showing waveform shaping of data output, in which FIG. 4A shows data output 12, FIG. 4B shows data output 12-n-1, and FIG. 4C shows data output 12-n. It is a block diagram which shows the structure of another module. FIGS. 6A and 6B are timing charts showing the waveform shaping of the clock, FIG. 6B is the clock 11-n ｀ (in the PLL circuit), and FIG. 6C is the clock 11-n (in the buffer). It is a block diagram of the conventional control system. FIG. 8A shows data, FIG. 8B shows a clock, and FIG. 8C shows data contents. It is a block diagram of the other conventional control system. FIG. 10A shows a clock, FIG. 10B shows a data output, FIG. 19C shows a data input, and FIG. 10D shows a chip select.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Device, 2-1, 2-2, ... 2-n ... Module, 11 ... Clock, 12 ... Data output signal, 13 ... Data input signal, 11-n-1 ... Clock, 12-n-1 ... Output signal, 13-n-1 ... Input signal, 21-n ... Device, 22-n ... Clock terminal, 23-n ... Data output terminal, 24-n ... Data input terminal, 25-n, 26-n, 27-n buffer: circuit, 55-n: PLL circuit, 11-n ｀: clock (when PLL circuit is used)

Claims (5)

A controller that controls the control and a plurality of devices to be controlled by the controller include a single signal line for clock transmission, a single signal line for output signal transmission, and a single signal line for input signal transmission. In a control system connected by a total of three signal lines ,
A waveform shaping block that shapes a signal related to control of the controller for controlling the plurality of devices to the same state based on a preset threshold is provided in any of the plurality of devices,
A signal relating to control of the controller, which is shaped by the waveform shaping block, it sent sequentially to the next stage via the three signal lines above
Control system. The waveform shaping block, you shaped such that the predetermined level and the integration value signals related to the control of the controller
The control system according to 請 Motomeko 1. The waveform shaping block, Ru using integrated circuit the waveform shaping of the control data of the controller
The control system according to 請 Motomeko 2. The waveform shaping block, Ru using phase-locked loop circuit with respect to the waveform shaping of the controller clock
The control system according to 請 Motomeko 2. The plurality of devices are a plurality of light emitting portions provided in the display device, Ru emit light in the same emission pattern of the plurality of light emitting portions by the control of the controller
The control system according to 請 Motomeko 1.

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