JP4794838B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a CMOS semiconductor device and a manufacturing method thereof.

  When a contact stress etch stopper film covering the CMOS transistor is formed using a plasma CVD method, a compressive stress in the gate length direction and a tensile stress in the depth direction are applied to the channel region. It has been reported that on-current increases in p-channel transistors and on-current decreases in n-channel transistors (see Non-Patent Document 1). On the other hand, when a tensile stress in the gate length direction is applied to the channel region and a compressive stress is applied in the depth direction by the silicon nitride film formed using the thermal CVD method, the contact etch stopper film, Conversely, it has been reported that the on-current decreases in the p-channel transistor and the on-current increases in the n-channel transistor (see Non-Patent Document 2). In this way, if one contact etch stopper film is used, the on-current of one conductivity type channel transistor increases and the on-current of the other conductivity type channel transistor decreases. The performance of the CMOS transistor could not be improved.

  Therefore, a CMOS transistor has been proposed that increases the on-current of the n-channel transistor without reducing the on-current of the p-channel transistor by implanting Ge ions into the contact stress etch stopper film covering the p-channel transistor. (See Non-Patent Document 3).

Further, as shown in FIG. 1, a silicon nitride film 102 for applying a compressive stress is formed on the p-channel transistor 101, and a silicon nitride film 104 for applying a tensile stress is formed on the n-channel transistor 103. A CMOS transistor 100 that increases both on-currents has been proposed (see, for example, Patent Document 1).
Ito et al., “Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design” IEDM Tech. Dig., P.247-250 (2000) Ootsuka et al., “A highly dense, high-performance 130 nm node CMOS technology for large scale system-on-a-chip applications” IEDM Tech. Dig., P.575-578 (2000) Shimizu et al., “Local mechanical-stress control (LMC): a new technique for CMOS-performance enhancement” IEDM Tech. Dig., P.19.4.1-19.4.4 (2001) JP 2003-273240 A Japanese Patent Laid-Open No. 2003-60076

  By the way, in the CMOS transistor 100 shown in FIG. 1, as shown in FIG. 2A, a silicon nitride film 104 for applying a tensile stress is formed across the p-type MOS region 105p and the n-type MOS region 105n. The n-type MOS region 105n is covered with the resist film 106, and the silicon nitride film 104 in the p-type MOS region 105p is etched. Then, as shown in FIG. 2B, the p-type MOS region 105p and the n-type MOS region 105n are formed. A silicon nitride film 102 to which compressive stress is applied is formed. Then, the p-type MOS region 105p is covered with the second resist film 108, and the silicon nitride film 102 in the n-type MOS region 105n is removed.

  In such a formation method, since the two resist films of the first resist film 106 and the second resist film 108 are used, the mask is likely to be displaced relatively during exposure. For example, FIG. ), When the position of the second resist film 108 is shifted to the right, the silicon nitride film 102 in the p-type MOS region 105p is removed, and the surface 109a of the element isolation region 109 is exposed. In such a case, as shown in FIG. 3B, in the region where the silicon nitride film 102 as the etching stopper film is missing when the contact hole 110a is formed in the interlayer insulating film 110, it is made of a silicon oxide film. The element isolation region 109 is etched to form a groove 110b reaching the silicon substrate 111, resulting in junction leakage.

  Further, when the position of the second resist film is shifted to the left, there is a possibility that a region where the silicon nitride film 102 and the silicon nitride film 104 overlap in the n-type MOS region 105n shown in FIG. In the case where the contact holes of a plurality of contacts shown in FIG. 1 are formed at a time, the contact holes hardly reach the silicon substrate in the overlapped region, resulting in a problem of contact failure.

  In order to avoid such a problem of mask misalignment, the silicon nitride film 102 is not removed in the n-type MOS region 105n using the second resist film 108 in FIG. Has been proposed (for example, see Patent Document 2). In this semiconductor device, even if the mask is displaced, exposure of the surface of the silicon substrate or the element isolation region can be avoided at the connection portion between the first silicon nitride film and the second silicon nitride film, and a contact hole is formed. It is thought that this problem can be solved.

  However, in this semiconductor device, the on-current of the p-type MOS transistor increases, but the on-current does not increase in the n-type MOS transistor in which the first silicon nitride film and the second silicon nitride film overlap.

  Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of improving the performance of a CMOS transistor and a manufacturing method thereof. It is an object to provide a semiconductor device and a method for manufacturing the same that can increase the on-current of both the n-type MOS transistor and the n-type MOS transistor and prevent the occurrence of contact failure.

  According to one aspect of the present invention, a p-type MOS transistor disposed in a first region of a semiconductor substrate and having an impurity region, a gate stacked body including a gate oxide film and a gate electrode, and a second of the semiconductor substrate. A semiconductor device including an impurity region and an n-type MOS transistor having a gate stack including a gate oxide film and a gate electrode, the semiconductor device being disposed in the first region, A first stress control film having a compressive stress covering the surface and the gate stacked body; and a second stress control film having a tensile stress disposed in the second region and covering the surface of the semiconductor substrate and the gate stacked body. And the first stress control film covering the second stress control film, the magnitude of the compressive stress of the first stress control film is P1, the film thickness is t1, and the second stress control film is pulled. Stress magnitude The P2, and the thickness and t2, a semiconductor device having a relationship of t1 × P1 <t2 × P2 are provided.

  According to the present invention, the surface of the semiconductor substrate and the gate stack are covered with the first stress control film in the first region, and the surface of the semiconductor substrate and the gate stack are in the second stress control in the second region. The film and the first stress control film are covered. In the second region, the first stress control film and the second stress control film have a compressive stress magnitude P1, a film thickness t1, and a second stress control film of the first stress control film. Assuming that the magnitude of the tensile stress is P2 and the film thickness is t2, tensile stress is applied to the channel region of the n-type MOS transistor because the relationship is set to have a relationship of t1 × P1 <t2 × P2. Further, compressive strain is applied to the channel region of the p-type MOS transistor by the first stress control film. Therefore, the on-currents of both the p-type MOS transistor and the n-type MOS transistor can be increased, and the surface of the semiconductor substrate and the gate stacked body are the first stress control film and the second stress control film as the etching stopper film. As a result, it is possible to prevent contact failure.

  According to another aspect of the present invention, a p-type MOS transistor disposed in a first region of a semiconductor substrate and having an impurity region, a gate stack including a gate oxide film and a gate electrode, and a first of the semiconductor substrate 2 is a semiconductor device including an impurity region and an n-type MOS transistor having a gate stacked body including a gate oxide film and a gate electrode, the semiconductor substrate being disposed in the second region, A second stress control film having a tensile stress covering the surface of the semiconductor substrate and the gate stacked body, and a first stress control film having a compressive stress disposed in the first region and covering the surface of the semiconductor substrate and the gate stacked body And the second stress control film covering the first stress control film, the magnitude of the compressive stress of the first stress control film is P1, the thickness is t1, and the second stress control film is Large tensile stress P2, and the thickness is t2 the of a semiconductor device having a relationship t1 × P1> t2 × P2 are provided.

  According to the present invention, the first region has the surface of the semiconductor substrate and the gate stack covered with the first stress control film and the second stress control film, and the second region has the surface of the semiconductor substrate and the gate stack. Is covered with a second stress control film. In the first region, the first stress control film and the second stress control film have a compressive stress magnitude of P1, a thickness of t1, and a second stress control film of the first stress control film. Assuming that the magnitude of the tensile stress is P2 and the film thickness is t2, the relation of t1 × P1> t2 × P2 is set so that compressive strain is applied to the channel region of the p-type MOS transistor. The Further, tensile strain is applied to the channel region of the n-type MOS transistor by the second stress control film. Therefore, the on-currents of both the p-type MOS transistor and the n-type MOS transistor can be increased, and the surface of the semiconductor substrate and the gate stacked body are the first stress control film and the second stress control film as the etching stopper film. As a result, it is possible to prevent contact failure.

  According to another aspect of the present invention, a p-type MOS transistor disposed in a first region of a semiconductor substrate and having an impurity region, a gate stack including a gate oxide film and a gate electrode, and a first of the semiconductor substrate 2 is a semiconductor device including an impurity region and an n-type MOS transistor having a gate stacked body including a gate oxide film and a gate electrode, the semiconductor device being disposed in the first region, A first stress control film having a compressive stress covering the surface of the semiconductor substrate and the gate laminate, and a second stress control film having a tensile stress disposed in the second region and covering the surface of the semiconductor substrate and the gate laminate. And a third stress control film modified by introducing impurities into the first stress control film that covers the second stress control film and extends to the second region, Stress control A semiconductor device having a relationship of t3 × P3 <t2 × P2 where P3 is the magnitude of the compressive stress, t3 is the film thickness, P2 is the tensile stress of the second stress control film, and t2 is the film thickness. Provided.

  According to the present invention, in the second region, impurities are applied to the second stress control film having a tensile stress that covers the surface of the semiconductor substrate and the gate stacked body, and the first stress control film having a compressive stress thereon. A third stress control film introduced and modified is formed. In the third stress control film, the compressive stress is relieved by introducing impurities. When the magnitude of the compressive stress of the third stress control film is P3, the film thickness is t3, the magnitude of the tensile stress of the second stress control film is P2, and the film thickness is t2, t3 × P3 <t2 × P2. Therefore, tensile strain is applied to the channel region of the n-type MOS transistor. Further, compressive strain is applied to the channel region of the p-type MOS transistor by the first stress control film. Therefore, both the on-currents of the p-type MOS transistor and the n-type MOS transistor can be increased, and the surface of the semiconductor substrate and the gate stack are the first stress control film and the second stress control film as the etching stopper film. And the third stress control film covers the contact failure.

  According to another aspect of the present invention, a p-type MOS transistor disposed in a first region of a semiconductor substrate and having an impurity region, a gate stack including a gate oxide film and a gate electrode, and a first of the semiconductor substrate 2 is a method for manufacturing a semiconductor device comprising an impurity region and an n-type MOS transistor having a gate stacked body composed of a gate oxide film and a gate electrode, the surface of the semiconductor substrate and the gate stacked body A step of forming a second stress control film having a tensile stress covering the substrate, a step of selectively removing the second stress control film in the first region, and exposing a surface of the semiconductor substrate and a gate stack; Forming a first stress control film having a compressive stress covering the surface of the semiconductor substrate in the first region and the gate stack and the second stress control film in the second region; If the magnitude of the compressive stress of the first stress control film is P1, the film thickness is t1, the tensile stress of the second stress control film is P2, and the film thickness is t2, then t1 × P1 <t2. A method of manufacturing a semiconductor device having a relationship of × P2 is provided.

  According to the present invention, the second stress control film having a tensile stress is formed on the entire surface, and only the second stress control film in the first region is removed to form the second stress control film in the second region. Then, since the first stress control film is formed in the first region and the second region, the surface of the semiconductor substrate and the gate stack are covered with the first stress control film and the second stress control film. Is called. Conventionally, the present invention prevents the occurrence of a region in which the silicide film or the element isolation region is not covered with either the first stress control film or the second stress control film near the boundary between the first region and the second region. it can. Therefore, when the contact hole is formed, damage to the surface of the silicide film and overetching of the element isolation region can be suppressed.

According to another aspect of the present invention, a p-type MOS transistor disposed in a first region of a semiconductor substrate and having an impurity region, a gate stack including a gate oxide film and a gate electrode, and a first of the semiconductor substrate 2 is a method for manufacturing a semiconductor device comprising an impurity region and an n-type MOS transistor having a gate stacked body composed of a gate oxide film and a gate electrode, the surface of the semiconductor substrate and the gate stacked body Forming a first stress control film having a compressive stress that covers the first stress control film; forming a first insulating film covering the first stress control film; and a first insulating film in the second region; A step of selectively removing the first stress control film to expose the surface of the semiconductor substrate and the gate stacked body; and a step of exposing the surface of the first insulating film in the first region and the surface of the semiconductor substrate in the second region. Forming a second stress control film having a tensile stress to cover the fine gate stack, forming a second insulating film covering the second stress control film,
Planarizing a part of the second insulating film and the second stress control film so that the first insulating film in the first region is exposed; and the first insulating film and the second insulating film There is provided a method of manufacturing a semiconductor device including a film and a removing step of removing a part of the second stress control film sandwiched between the first insulating film and the second insulating film.

  According to the present invention, the first stress control film and the first insulating film covering the first region and the second region are formed in this order, and the first insulating film and the first stress in the second region are formed. When the control film is selectively etched and further the second stress control film is formed, the first stress control film in the second region is covered with the first insulating film having the same shape as that of the mask used for etching. Therefore, the first stress control film and the second stress control film do not overlap each other, or the end portions of the first stress control film and the second stress control film are separated from each other, so that the element isolation region And exposure of the surface of the source / drain region is avoided. Therefore, when the contact hole is formed, the contact hole does not reach the surface of the source / drain region, so that contact failure between the contact and the source / drain region is prevented, and the device isolation region is not punched. Occurrence can be prevented.

  According to the present invention, it is possible to provide a semiconductor device that can increase both the on-currents of the p-type MOS transistor and the n-type MOS transistor and prevent the occurrence of contact failure, and a method of manufacturing the same.

  Embodiments will be described below with reference to the drawings.

(First embodiment)
FIG. 4 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention. FIG. 4 shows a cross section in a direction parallel to the gate length direction.

  Referring to FIG. 4, a semiconductor device 10 includes a p-type MOS transistor 14 formed in a first region 13p and an n-type formed in a second region 13n, separated from each other by a device isolation region 12 on a silicon substrate 11. It comprises a type MOS transistor 15 and contacts 42 connected to these transistors 14 and 15.

  The p-type MOS transistor 14 in the first region 13 p includes a source / drain region 19 in which a p-type impurity is implanted in an n-type well region 18, a gate oxide film 20 formed on the surface of the silicon substrate 11, and a gate electrode 21. , And a gate laminate 23 composed of the sidewall insulating film 22, and silicide films 24 and 25 formed on the surface side of the source / drain regions 19 and the gate electrode 21.

  Further, a first stress control film 26 that covers the surfaces of the silicon substrate 11 and the element isolation region 12 and the gate stacked body 23 is provided in the first region 13p. The first stress control film 26 is made of, for example, a silicon nitride film formed by a plasma CVD method. The first stress control film 26 has a compressive stress as an internal stress, and applies the compressive stress to the channel region 28 immediately below the gate oxide film 20 in the gate length direction. As a result, the hole mobility of the channel region 28 is improved. The material and manufacturing method of the first stress control film 26 are not limited as long as the first stress control film 26 has a compressive stress as an internal stress. On the other hand, the n-type MOS transistor 15 in the second region includes a source / drain region 30 implanted with an n-type impurity formed in the p-type well region 29, a gate oxide film 31, a gate electrode on the surface of the silicon substrate 11. 32, and a gate stack 34 composed of the sidewall insulating film 33, and silicide films 35 and 36 formed on the surface side of the source / drain regions 30 and the gate electrode 32.

  Further, a second stress control film 38 that covers the surfaces of the silicon substrate 11 and the element isolation region 12 and the gate stack 34 and a first stress control film 26 that covers the second stress control film 38 are provided in the second region 13n. It is done. The second stress control film 38 is made of, for example, a silicon nitride film formed by a thermal CVD method. The second stress control film 38 has a tensile stress as an internal stress, and applies a tensile stress to the channel region 39 immediately below the gate oxide film 31 in the gate length direction. As long as the second stress control film 38 has tensile stress as an internal stress, the material and manufacturing method of the second stress control film 38 are not limited.

In the second region 13n, the first stress control film 26 having compressive stress as the internal stress described above is provided on the second stress control film 38 so as to extend from the first region 13p. In the second region 13n, the first stress control film 26 and the second stress control film 38 are set to have a relationship of the following formula (1).
t1 × P1 <t2 × P2 (1)
Here, the thickness t1 of the first stress control film 26, the magnitude P1 of the compressive stress, the thickness t2 of the second stress control film 38, and the magnitude P2 of the tensile stress. The film thickness t1 of the first stress control film 26 and the film thickness t2 of the second stress control film 38 are film thicknesses in a region where the base is flat, and are laminated on the surface of the silicon substrate 11 in the second region 13n, for example. The film thicknesses of the first stress control film 26 and the second stress control film 38 are set. However, the film thickness of the first stress control film 26 may be the film thickness of the first stress control film 26 deposited on the surface of the silicon substrate 11 in the first region 13p.

  The relationship of the above formula (1) is that the product of the film thickness and the magnitude of the internal stress is made larger in the tensile stress term than in the compressive stress term, so that the channel region 39 immediately below the gate oxide film 31 The net tensile stress is applied in the gate length direction. As a result, the electron mobility of the channel region 39 is improved. Here, when the film thickness t1 of the first stress control film 26 and the film thickness t2 of the second stress control film 38 are substantially equal, the magnitudes P1 and P2 of the internal stress are set to satisfy P1 <P2. It can be controlled with.

  When the magnitude P1 of the compressive stress of the first stress control film 26 and the magnitude P2 of the tensile stress of the second stress control film 38 are substantially equal, the film thickness t2 of the second stress control film 38 is set to the first stress control. It is set to be larger than the film thickness t1 of the film 26, that is, t1 <t2. By doing so, a tensile stress is applied to the channel region 39 in the gate length direction.

結晶方位のうちいずれかであることを示す。 The surface of the silicon substrate 11 is preferably a {100} crystal plane, and the gate length direction is substantially <110> crystal orientation and parallel to the {100} crystal plane. The on-current increases more than when the gate length direction is set to a crystal orientation other than this. Here, since the {100} crystal plane has a crystal structure of a face-centered cubic lattice, silicon has a (100) crystal plane, a (010) crystal plane equivalent to this crystal plane, and a (001) crystal plane. Indicates one of them. Note that the substrate having the {100} crystal plane may be a slightly inclined substrate. The <110> crystal orientation is equivalent to the [110] crystal orientation and the [110] crystal orientation.

Indicates one of the crystal orientations.

The gate oxide films 20 and 31 are made of a silicon oxide film. The gate oxide films 20 and 31 may be any one of a silicon nitride film, a silicon oxynitride film, Al ₂ O ₃ , Ta ₂ O ₅ , HfO ₂ , ZrO ₂ , and a laminated film thereof. Other components of the semiconductor device 10 will be described in the following manufacturing method.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be specifically described with reference to FIGS. 5 to 7 are manufacturing process diagrams of the semiconductor device according to the first embodiment of the present invention.

  First, in the process of FIG. 5A, an element isolation region 12 is formed on a silicon substrate 11 by an STI (Shallow Trench Isolation) method, and an n-type conductivity type is formed in a first region 13p where a p-type MOS transistor is formed. N-type well region 18 is formed, and p-type conductivity type impurity is implanted into second region 13n where the n-type MOS transistor is formed, thereby forming p-type well region 29.

  5A, gate oxide films 20 and 31 and gate electrodes 21 and 32 made of polysilicon are formed on the surface of the silicon substrate 11, and the first region 13p is formed using the gate electrodes 21 and 32 as a mask. Are implanted with p-type conductivity type impurities, and the second region is implanted with n-type conductivity type impurities to form shallow junction regions 19a and 30a, respectively. Next, an insulating film made of a silicon oxide film or the like is formed so as to cover the surface of the silicon substrate 11 and the gate electrodes 21 and 32, and the insulating film is etched back to form a sidewall insulating film 22, and the gate oxide films 20 and 31 are formed. Gate laminates 23 and 34 including gate electrodes 21 and 32 and sidewall insulating films 22 and 33 are formed.

  In the step of FIG. 5A, p-type conductivity impurities are implanted into the first region 13p using the gate stacked bodies 23 and 34 as masks, and n-type conductivity impurities are implanted into the second region 13n. To form deep junction regions 19b and 30b. Next, heat treatment is performed to activate the impurities, and the source / drain regions 19 and 30 are formed.

5A, for example, a Ni film (not shown) that covers the surface of the silicon substrate 11 and the gate stacks 23 and 34 is formed, and a heat treatment at about 450 ° C. is performed, so that the NiSi ₂ silicide film 24 is formed. , 25, 35, and 36 are formed in the source / drain regions 19 and 30 and the gate electrodes 21 and 32, and then the unreacted Ni film is removed.

Next, in the process of FIG. 5B, a silicon nitride film (second stress control film 38 having a tensile stress of, eg, a film thickness of 80 nm is formed on the entire surface of the structure of FIG. Hereinafter, the same symbol “38” as that of the second stress control film is used. Specifically, the silicon nitride film 38 has, for example, a substrate temperature of 500 ° C. to 700 ° C., a pressure of 13.3 Pa to 5.32 × 10 ⁴ Pa, SiH ₂ Cl ₂ + SiH ₄ + Si ₂ H ₄ + Si ₂ H ₆ gas. (Flow rate 5-50 sccm), NH ₃ gas (flow rate 500-10000 sccm), and N ₂ + Ar gas (flow rate 500-10000 sccm) are supplied to form. The silicon nitride film 38 formed under this condition has a tensile stress of 1.4 GPa as an internal stress.

  The internal stress is measured by the following method. A silicon nitride film having a thickness of 100 nm is formed on the surface of a circular silicon substrate (plate thickness 0.6 mm) having a diameter of 20 cm by the same method as described above. The substrate thus obtained is measured for the amount of bending of the substrate using the Newton ring method, and the internal stress σ is calculated by the following equation (2).

Here, E is the Young's modulus of the substrate, b is the thickness of the substrate, ν is the Poisson's ratio of the substrate, r is the radius of curvature of the substrate obtained by measurement, and d is the thickness of the silicon nitride film.

  6A, a resist film 40 is formed on the silicon nitride film 38, and then an opening 40-1 is formed in the first region 13p.

In the step of FIG. 6A, the silicon nitride film 38 in the first region 13p is etched using CHF ₃ gas by the RIE method using the resist film 40 as a mask, and the surface of the silicon substrate 11 and the gate stacked body 23 are removed. Expose.

Next, in the step of FIG. 6B, the resist film 40 of FIG. 6A is removed. Next, a silicon nitride film (hereinafter referred to as a first stress control film 26) is formed by plasma CVD so as to cover the surface of the silicon substrate 11 in the first region 13p, the gate stacked body 23, and the silicon nitride film 38 in the second region 13n. , The same sign “26” as that of the first stress control film is used). Specifically, the silicon nitride film 26 includes, for example, a pressure of 13.3 Pa to 5.32 × 10 ⁴ Pa, SiH ₄ gas (flow rate 100 to 1000 sccm), NH ₃ gas (flow rate 500 to 10,000 sccm), and N ₂ + Ar. A gas (flow rate: 500 to 10000 sccm) is supplied, and an RF power of 100 to 1000 W is formed. Under these conditions, a silicon nitride film 26 having a thickness of 60 nm and a compressive stress of 1.4 GPa is formed. As a result, in the second region 13n, t1 × P1 = 84 Pa · m and t2 × P2 = 112 Pa · m, and the relationship of the above formula (1) is satisfied.

  In the step of FIG. 6B, an interlayer insulating film 16 made of, for example, a silicon oxide film having a thickness of 600 nm is formed on the silicon nitride film 26, and then the surface thereof is flattened by the CMP method. The semiconductor device shown in FIG. Is formed.

Next, in the step of FIG. 7, a resist film 41 is formed on the surface of the interlayer insulating film 16, and the resist film 41 having the openings 41-1 and 41-2 is used as a mask by CF ₄ and H ₂ by the RIE method. Using the mixed gas, part of contact holes 16-1 and 16-2 penetrating the interlayer insulating film 16 made of a silicon oxide film is formed using the first stress control film 26 as an etching stopper film.

Further, in the step of FIG. 7, the CHF ₃ gas is used to penetrate the first stress control film 26 in the first region and the first stress control film 26 and the second stress control film 38 in the second region by RIE. The silicide films 24 and 35 are exposed to complete the contact holes 16-1 and 16-2. Here, the second stress control film 38 is preferably made of a material having an etching rate higher than that of the first stress control film 26, or the etching rate of the second stress control film 38 is higher than that of the first stress control film 26. It is preferable to use a high etching gas in terms of suppressing damage to the silicide film 24 in the first region 13p.

  Further, in the step of FIG. 7, the contact holes 16-1 and 16-2 are filled with a barrier metal film (not shown) made of a laminated film of Ti film / TiN film and a conductive material such as Cu, W, Al and the contact 42 is filled. Form.

  In the semiconductor device 10 according to the present embodiment, the first region 13p is covered with the first stress control film 26 that covers the surface of the silicon substrate 11 and the element isolation region 12 and the gate stack 23, and the second region 13n is formed of silicon. A second stress control film 38 that covers the surface of the substrate 11 and the element isolation region 12 and the gate stack 34, and a first stress control film 26 that covers the second stress control film 38 and extends from the first region 13p are provided. In the second region 13n, the first stress control film 26 and the second stress control film 38 are set so as to have the relationship of the above formula (1), so that the channel region 28 of the p-type MOS transistor 14 The compression strain is applied to the channel region 39 of the n-type MOS transistor 15. Therefore, both the on-currents of the p-type MOS transistor 14 and the n-type MOS transistor 15 can be increased, and the surface of the silicon substrate 11 and the element isolation region 12 and the gate stacked bodies 23 and 34 are used as the etching stopper film for the first stress. Since it is covered with the control film 26 and the second stress control film 38, it is possible to prevent contact failure.

  In the manufacturing method according to the present embodiment, the second stress control film 38 having a tensile stress is formed on the entire surface, and only the second stress control film 38 in the first region 13p is etched, and the second stress in the second region 13n. Since the control film 38 is left and then the first stress control film 26 is formed in the first region 13p and the second region 13n, the silicon substrate 11 and the element isolation are formed by the first stress control film 26 and the second stress control film 38. The surface of region 12 and gate stacks 23 and 34 are covered. Conventionally, in this embodiment, it is possible to prevent the occurrence of a region in which the silicide film or the element isolation region is not covered with either the first stress control film or the second stress control film near the boundary between the first region and the second region. . Therefore, when the contact holes 16-1 and 16-2 are formed, damage to the surface of the silicide films 24 and 35 and overetching of the element isolation region 12 can be suppressed.

  Next, a semiconductor device according to a modification of the first embodiment will be described.

  FIG. 8 is a sectional view of a semiconductor device according to a modification of the first embodiment. In the figure, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

  Referring to FIG. 8, in the semiconductor device 50, a silicon oxide film 51 is formed so as to cover the surface of the silicon substrate 11 and the element isolation region 12 and the gate stacked bodies 23 and 34, and the first region 13p has the first region 13p. The first stress control film 26 is the same as the semiconductor device according to the first embodiment shown in FIG. 4 except that the second stress control film 38 and the first stress control film 26 are formed in the second region 13n. It is configured.

In the manufacturing method of the semiconductor device 50 according to this modification, the above-described process of FIG. 5A is performed, and then the silicon oxide film 51 is formed to a thickness of 20 nm by, for example, plasma CVD. Specifically, the silicon oxide film 51 is formed by using a mixed gas of SiH ₄ and O ₂ and setting the substrate temperature around 400 ° C. The silicon oxide film 51 is not limited to a silicon oxide film as long as it is a material having etching selectivity with respect to the first stress control film 26 and the second stress control film 38.

  Next, the process of forming the contact holes 16-1 and 16-2 penetrating the first stress control film 26 and the second stress control film 38 in FIGS. 5B to 7 is performed. In the forming step, by providing the silicon oxide film 51, when the contact holes 16-1 and 16-2 penetrating the first stress control film 26 and the second stress control film 38 are formed, the first region 13p becomes the first region 13p. Even if the second stress control film 38 is thinner than the second region 13n, the etching is stopped by the silicon oxide film 51, and damage to the silicide film 24 in the first region 13p can be prevented.

Next, the surface of the silicide films 24 and 35 is exposed from the silicon oxide film 51 by RIE using a mixed gas of CF ₄ and H ₂ . Thereafter, contacts are formed in the same manner as in the step of FIG.

  According to the modification of the present embodiment, damage to the silicide film 24 in the first region 13p can be more reliably prevented in addition to the effects of the above-described embodiment.

  FIG. 9 is a diagram for explaining the effect when the thickness of the second stress control film having tensile stress in the semiconductor device of the present embodiment is varied. FIG. 9 is a diagram showing the relationship between the strain of the channel region 28 of the p-type MOS transistor 14 and the channel region 39 of the n-type MOS transistor 15 shown in FIG. 4 and the thickness of the second stress control film 38 having tensile stress. The configuration of the semiconductor device is the same as that shown in FIG. The internal stress of each of the first stress control film 26 having compressive stress and the second stress control film 38 having tensile stress is 1.4 GPa, the thickness of the first stress control film 26 is 60 nm, 2 The film thickness of the stress control film 38 was varied from 80 nm to 140 nm. The gate length was 50 nm, and the gate height (height from the surface of the silicon substrate 11 to the surfaces of the silicide films 25 and 36 of the gate electrodes 21 and 32) was 100 nm. The distortion amount of the channel regions 28 and 39 was calculated using a process simulator (trade name: TSUPREM4, manufactured by Synopsys).

  Referring to FIG. 9, it can be seen that the strain amount at the center of the channel region of the n-type MOS transistor increases as the thickness of the second stress control film increases. On the other hand, as the film thickness of the second stress control film increases, the amount of strain in the channel region of the p-type MOS transistor is constant, and the channel region of the p-type MOS transistor has a film thickness of the second stress control film. It can be seen that it is not affected by the increase in the channel region and is not affected by the distortion of the channel region of the n-type MOS transistor. Therefore, by controlling the film thickness of the second stress control film, the amount of tensile strain in the channel region of the n-type MOS transistor can be controlled against the compressive stress of the first stress control film. It can be seen that the on-current of the n-type MOS transistor can be increased, and can be increased in a balanced manner.

  Here, the amount of strain is the lattice constant L0 in the gate length direction when the internal stress of the first stress control film and the second stress control film is 0, and the lattice constant L1 in the gate length direction when stress is applied. Amount = (L1-L0) / L0.

  FIG. 10 is a diagram for explaining the effect when the magnitude of the internal stress of the second stress control film having the tensile stress of the semiconductor device of the present embodiment is varied. FIG. 10 is a diagram showing the relationship between the strain of the channel region 28 of the p-type MOS transistor 14 and the channel region 39 of the n-type MOS transistor 15 shown in FIG. 4 and the internal stress of the second stress control film 38 having a tensile stress. The configuration of the semiconductor device is the same as that shown in FIG. Note that the magnitude of the internal stress of the first stress control film 26 having compressive stress is 1.4 GPa, and the magnitude of the internal stress of the second stress control film 38 having tensile stress is different from 1.4 GPa to 2.2 GPa. Let The film thicknesses of the first stress control film 26 and the second stress control film 38 were 60 nm. The gate length and gate height were the same as those in FIG. 9, and the distortion amounts of the channel regions 28 and 39 were calculated using the same process simulator as in FIG.

  Referring to FIG. 10, it can be seen that the amount of strain at the center of the channel region of the n-type MOS transistor increases as the internal stress (tensile stress) of the second stress control film increases. On the other hand, as the internal stress of the second stress control film increases, the amount of strain in the channel region of the p-type MOS transistor is constant, and the channel region of the p-type MOS transistor has an internal stress of the second stress control film. It can be seen that the channel region of the n-type MOS transistor is not affected. Therefore, by controlling the internal stress of the second stress control film, the amount of tensile strain in the channel region of the n-type MOS transistor can be controlled against the compressive stress of the first stress control film. It can be seen that the on-current of the n-type MOS transistor can be increased, and can be increased in a balanced manner.

(Second Embodiment)
FIG. 11 is a cross-sectional view of a semiconductor device according to the second embodiment of the present invention. FIG. 11 shows a cross section in a direction parallel to the gate length direction. In the figure, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

  Referring to FIG. 11, in the semiconductor device 60, a first stress control film 26 having a compressive stress and a second stress control film 38 having a tensile stress are stacked in this order in the first region 13p. The structure is the same as that of the first embodiment except that the two-stress control film 38 is provided.

  A first stress control film 26 that covers the surfaces of the silicon substrate 11 and the element isolation region 12 and the gate stack 23 is formed in the first region 13p, and a second stress control film 38 that covers the first stress control film 26 is further formed. Is formed.

The first stress control film 26 and the second stress control film 38 are set so as to have the relationship of the following formula (3).
t1 × P1> t2 × P2 (3)
Here, the thickness t1 of the first stress control film 26, the magnitude P1 of the compressive stress, the thickness t2 of the second stress control film 38, and the magnitude P2 of the tensile stress. The film thickness t1 of the first stress control film 26 and the film thickness t2 of the second stress control film 38 are set in the same manner as in the first embodiment. By setting the relationship of the above formula (3), the stress applied to the channel region 28 of the p-type MOS transistor becomes a compressive stress, and the hole mobility increases. Since the internal stress control method and measurement method are the same as those in the first embodiment, the description thereof is omitted. When P1 and P2 are substantially equal, t1> t2. Alternatively, t1 and t2 may be substantially equal, and P1> P2.

  Next, a method for manufacturing a semiconductor device according to the second embodiment will be specifically described with reference to FIGS.

  12 and 13 are manufacturing process diagrams of the semiconductor device according to the second embodiment.

  First, in the process of FIG. 12A, the silicide films 24, 25, 35, and 36 are formed in the same manner as in the process of FIG. 5A of the first embodiment.

  In the step of FIG. 12A, a silicon nitride film (hereinafter referred to as a first stress control film 26 having a compressive stress) is further formed by plasma CVD so as to cover the surface of the silicon substrate 11 and the gate stacked bodies 23 and 34, for example. The same reference numeral “26” as that of the one stress control film is used. Specifically, the silicon nitride film 26 has a thickness t1 of 80 nm and a compressive stress of 1.4 GPa using the same conditions as the first stress control film in the step of FIG. become.

  12B, a resist film 61 is formed on the silicon nitride film 26, and then an opening 61-1 is formed in the resist film in the second region 13n.

In the step of FIG. 12B, the silicon nitride film 26 in the second region 13n is further etched using CHF ₃ gas by the RIE method using the resist film 61 as a mask, and the surfaces of the silicon substrate 11 and the element isolation region 12 are formed. The gate stack 34 is exposed.

  Next, in the step of FIG. 13, the resist film 61 of FIG. 12B is removed. Next, a silicon nitride film (hereinafter referred to as a second stress control film 38) is formed by thermal CVD so as to cover the silicon nitride film 26 in the first region 13p, the surface of the silicon substrate 11 in the second region 13n, and the gate stacked body 34. , The same sign “38” as that of the second stress control film is used. Specifically, the film thickness t2 of the silicon nitride film 38 is set to 60 nm using the same conditions as the silicon nitride film in the step of FIG. The tensile stress of the silicon nitride film is 1.4 GPa.

  When formed in this manner, in the first region 13p, t1 × P1 = 112 Pa · m and t2 × P2 = 84 Pa · m, and the relationship of the above formula (3) is established, and compressive stress is applied to the channel region 28.

  Next, after the step of FIG. 13, an interlayer insulating film 16 is formed on the surface of the structure of FIG. 13, and a contact 42 is formed in the same manner as in FIG. Here, formation of a contact hole that penetrates the second stress control film in the first region 13p and the first stress control film, and formation of a contact hole that penetrates the second stress control film in the second region At the same time. The first stress control film 26 is preferably made of a material having an etching rate higher than that of the second stress control film 38, or the etching rate of the first stress control film 26 is higher than that of the second stress control film 38. It is preferable to use an etching gas in terms of suppressing damage to the silicide film 35 in the second region 13n. Thus, the semiconductor device 60 shown in FIG. 11 is formed.

  According to the present embodiment, since compressive stress and tensile stress are applied to the channel region 28 of the p-type MOS transistor 14 and the channel region 39 of the n-type MOS transistor 15, respectively, the carrier mobility increases, In any of the transistors, the on-current increases, and the performance of the semiconductor device 60 as a CMOS transistor is improved.

  Further, according to the present embodiment, the first stress control film 26 is formed on the entire surface, and only the first stress control film 26 in the second region 13n is removed, and the first stress control film 26 in the first region 13p is removed. Then, since the second stress control film 38 is formed on the entire surface of the first region 13p and the second region 13n, the first stress control film 26 and the second stress control film 38 are formed on the surface of the silicon substrate 11 and the gate stack. The bodies 23 and 34 are covered. Therefore, when the contact hole is formed, over-etching of the element isolation region 12 and damage to the surface of the silicide films 24, 25, 35, and 36 can be avoided.

(Third embodiment)
FIG. 14 is a cross-sectional view of a semiconductor device according to the third embodiment of the present invention. FIG. 14 shows a cross section in a direction parallel to the gate length direction. In the figure, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

  Referring to FIG. 14, the semiconductor device 70 is the same as the first stress control film 26 except that the first stress control film 26 having compressive stress is modified by introducing impurities into the portion formed in the second region 13 n. The semiconductor device is configured in the same manner as the semiconductor device of the embodiment.

  In the first stress control film (hereinafter referred to as “third stress control film 26a”) formed in the second region 13n, impurities are implanted into the first stress control film 26 having compressive stress. Since the internal stress of the third stress control film 26a is relaxed by the implantation of impurities, the compressive stress applied to the channel region 39 is reduced, and the net stress applied to the channel region 39 increases the tensile stress. In addition, although an impurity is not specifically limited, A tetravalent element is preferable at the point which does not form an ion, and Ge and C are especially preferable.

  FIG. 15 is a manufacturing process diagram of the semiconductor device according to the third embodiment.

  In the process of FIG. 15, the processes up to the process of forming the first stress control film 26 in the process of FIG. 6B of the first embodiment are performed in the same manner. Next, a resist film 71 is formed on the first stress control film 26, and then an opening 71-1 is formed in the resist film in the second region 13n.

Further, in the process of FIG. 15, an impurity is implanted into the first stress control film 26 in the second region 13n by using the ion implantation method with the resist film 71 as a mask, and the internal stress of the first stress control film 26 is relaxed. The three-stress control film 26a is converted. For example, the impurity is implanted by using Ge as an impurity and setting an acceleration voltage of 100 keV and a dose of 5 × 10 ¹⁴ / cm ² . By implanting the impurities, stress relaxation occurs in the first stress control film 26 having compressive stress, and the compressive stress applied to the channel region 39 is reduced. As a result, the tensile stress is increased and the on-current is increased. At this time, selection of impurities, acceleration voltage, and dose are appropriately selected so as to satisfy the relationship of the following formula (4).
t3 × P3 <t2 × P2 (4)
Here, the thickness t3 of the third stress control film 26a, the magnitude P3 of the compressive stress, the thickness t2 of the second stress control film 38, and the magnitude P2 of the tensile stress.

  After the step of FIG. 15, the resist film 71 is removed, and then the interlayer insulating film 16 and the contact 42 are formed in the same manner as in the step of FIG. 7, and the semiconductor device of FIG. 14 is formed.

  According to the present embodiment, the second stress control film 38 in the second region 13n can be thinned by reducing the compressive stress of the first stress control film 26 formed in the second region 13n. As a result, when the contact hole is formed through the interlayer insulating film 16 and the first stress control film 26, or the third stress control film 26 a and the second stress control film 38, the first region 13 p of the first region 13 p is formed. The difference in film thickness between the stress control film 26, the third stress control film 26a in the second region 13n, and the second stress control film 38 can be reduced, and contact holes can be easily formed at one time.

  Similarly, in the semiconductor device according to the second embodiment shown in FIG. 11 described above, the first region in which the first stress control film 26 and the second stress control film 38 are laminated is also described. At 13p, impurities may be introduced into the second stress control film 38 having a tensile stress to cause stress relaxation and reduce the tensile stress.

  FIG. 16 is a cross-sectional view of a semiconductor device according to a modification of the third embodiment. In the figure, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

  Referring to FIG. 16, the semiconductor device 75 is the same as the second stress control film 38 except that the second stress control film 38 having tensile stress is modified by introducing impurities into the portion formed in the first region 13 p. The semiconductor device is configured in the same manner as the semiconductor device of the embodiment.

  In the second stress control film (hereinafter referred to as “fourth stress control film 38a”) formed in the first region 13p, impurities are implanted into the second stress control film 38 having tensile stress. Since the internal stress of the fourth stress control film 38a is relieved by impurity implantation, the tensile stress applied to the channel region 28 of the p-type MOS transistor 14 is reduced, and the compression applied from the first stress control film 26 is reduced. The net stress with the stress increases the compressive stress. The impurity is the same as that in the third embodiment described above.

  FIG. 17 is a manufacturing process diagram of the semiconductor device according to the modification of the third embodiment.

  In the process of FIG. 17, the processes up to the process of forming the second stress control film 38 in the process of FIG. 13 of the second embodiment are performed in the same manner. Next, a resist film 76 is formed on the second stress control film 38, and then an opening 76-1 is formed in the resist film in the first region 13p.

Further, in the process of FIG. 17, an impurity is introduced into the second stress control film 38 in the first region using the resist film 76 as a mask and converted into a fourth stress control film 38a in which the internal stress is relaxed. For example, Ge is used as an impurity, and the acceleration voltage is set to 100 keV and the dose amount is set to 5 × 10 ¹⁴ / cm ² . By introducing the impurities, the stress relaxation of the second stress control film 38 occurs, the tensile stress applied to the channel region 28 of the p-type MOS transistor is reduced, and as a result, the compressive stress increases to increase the on-current. . At this time, selection of impurities, acceleration voltage, and dose are appropriately selected so as to satisfy the relationship of the following formula (5).
t1 × P1> t4 × P4 (5)
Here, the thickness t1 of the first stress control film 26, the magnitude P1 of the compressive stress, the thickness t4 of the fourth stress control film 38a, and the magnitude P4 of the tensile stress.

  After the process of FIG. 17, the resist film is removed, and then the interlayer insulating film 16 and the contact 42 are formed in the same manner as in the process of FIG. 7, and the semiconductor device of FIG. 16 is formed.

  According to the modification of the present embodiment, the thickness of the first stress control film 26 can be reduced, and the same effect as that of the present embodiment described above can be obtained.

(Fourth embodiment)
FIG. 18 is a cross-sectional view of a semiconductor device formed by the manufacturing method according to the fourth embodiment of the present invention. In the figure, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

  Referring to FIG. 18, a semiconductor device 80 includes a p-type MOS transistor 14 formed in a first region 13p and an n-type formed in a second region 13n. A MOS transistor 15 and an interlayer insulating film 16 covering these transistors 14 and 15 are formed.

  A first stress control film 81 is formed in the first region 13p so as to cover the surfaces of the silicon substrate 11 and the element isolation region 12 and the gate stacked body 23. The first stress control film 81 improves the hole mobility of the channel region 28 by applying a compressive stress to the channel region 28 immediately below the gate oxide film 20 in the gate length direction. As the first stress control film 81, a film similar to the first stress control film 26 of the first embodiment described above can be used.

  On the other hand, a second stress control film 82 is formed in the second region 13n so as to cover the surfaces of the silicon substrate 11 and the element isolation region 12 and the gate stacked body 34. The second stress control film 82 improves the electron mobility of the channel region 39 by applying a tensile stress to the channel region 39 immediately below the gate oxide film 31 in the gate length direction. As the second stress control film 82, a film similar to the second stress control film 38 of the first embodiment described above can be used.

  Next, a method for manufacturing a semiconductor device according to the fourth embodiment will be specifically described with reference to FIGS. 19 to 21 are manufacturing process diagrams of the semiconductor device according to the fourth embodiment of the present invention.

  First, in the process of FIG. 19A, silicide films 24, 25, 35, and 36 are formed in the same manner as in FIG. 5A of the first embodiment.

In the step of FIG. 19A, a first stress control film 81 having a compressive stress is further formed so as to cover the surfaces of the silicon substrate 11 and the element isolation region 12 and the gate stacked bodies 23 and 34. The first stress control film 81 forms a silicon nitride film using a plasma CVD method. Specifically, using a plasma CVD apparatus, for example, a pressure of 13.3 Pa to 5.32 × 10 ⁴ Pa, SiH ₄ gas (flow rate 100 to 1000 sccm), NH ₃ gas (flow rate 500 to 10,000 sccm), and N ₂ + Ar gas (flow rate: 500 to 10000 sccm) is supplied, RF power is set to 100 to 1000 W, and a silicon nitride film having a thickness of 60 nm is formed.

  In the step of FIG. 19A, a first insulating film 83 made of a silicon oxide film (for example, having a film thickness of 600 nm) formed using TEOS gas by CVD is further formed to cover the first stress control film 81. The first insulating film 83 is not particularly limited as long as it has etching selectivity with the first stress control film 81. For example, a BPSG (Boro-Phospho Silicate Glass) film or the like may be used.

  In the step of FIG. 19A, the surface of the first insulating film 83a is further planarized by the CMP method. Note that the planarization process may be omitted when the step coverage of the first insulating film 83a is good.

  Next, in the step of FIG. 19B, a resist film 84 is formed on the first insulating film 83 whose surface is flattened in FIG. 19A, and then an opening is formed in the resist film 84 in the second region 13n. 84-1.

In the step of FIG. 19B, the first insulating film 83 in the second region 13n is further etched by the RIE method using a mixed gas of CF ₄ and H ₂ using the resist film 84 as a mask, and the first stress control film 81 is exposed. As long as the etching gas has a high etching rate with respect to the first insulating film 83 and has etching selectivity with respect to the first stress control film 81 made of a silicon nitride film, a mixed gas of CF ₄ and H ₂ is used. It is not limited to.

In the step of FIG. 19B, the first stress control film 81 in the second region 13n is further etched using CHF ₃ gas by the RIE method using the resist film as a mask, and the surface of the silicon substrate 11 and the gate stacked body 34 are etched. To expose. Here, the etching gas is not limited to the CHF ₃ gas as long as it has a high etching rate with respect to the silicon nitride film and has etching selectivity with respect to the silicon oxide film and silicon.

Next, in the process of FIG. 20A, the resist film 84 of FIG. 19B is removed, and the first insulating film 83 in the first region 13p is exposed. Next, a second stress control film 82 is formed to cover the first insulating film 83 in the first region 13p, the surface of the silicon substrate 11 and the element isolation region 12 in the second region 13n, and the gate stacked body 34. The second stress control film 82 applies a tensile stress to the channel region 31, and here, a silicon nitride film is formed using a thermal CVD method. Specifically, using a thermal CVD apparatus, for example, the substrate temperature is 500 ° C. to 700 ° C., the pressure 13.3 Pa to 5.32 × 10 ⁴ Pa, SiH ₂ Cl ₂ + SiH ₄ + Si ₂ H ₄ + Si ₂ H _6. A gas (flow rate 5 to 50 sccm), NH ₃ gas (flow rate 500 to 10,000 sccm), and N ₂ + Ar gas (flow rate 500 to 10,000 sccm) are supplied to form a silicon nitride film having a thickness of 60 nm. At this time, the second stress control film 82 is also thinly attached to the side wall of the first insulating film 83.

  Next, in the process of FIG. 20B, a second insulating film 85a is formed to cover the structure of FIG. The second insulating film 85 is selected from the same material as the first insulating film 83 described above, and may be the same material or a different material. Here, the same silicon oxide film as the first insulating film 83 is used.

  In the step of FIG. 20B, the surface of the second insulating film 85a is further flattened by CMP to expose the second stress control film 82 on the surface of the first insulating film. Next, the second stress control film 82 on the surface of the first insulating film 83 is removed by CMP, and the second insulating film 85a is planarized to expose the first insulating film 83 in the first region.

  Next, in the process of FIG. 21, the second stress control film 82 sandwiched between the first insulating film 83 and the second insulating film 85 is etched by time control using, for example, a phosphoric acid solution. In the etching of the second stress control film 82, the portion sandwiched between the first insulating film 83 and the second insulating film 85 is removed, and the etched second stress control film 82a becomes another second stress control film. This is performed until the film thickness is about the same as that of the portion 82.

  After the step of FIG. 21, the first insulating film 83 and the second insulating film 85 of FIG. 21 are removed using a hydrofluoric acid solution using the first stress control film 81 and the second stress control film 82 as an etching stopper film. Then, an interlayer insulating film 85 that covers the first stress control film 81 and the second stress control film 82 is formed, and the semiconductor device shown in FIG. 18 is formed.

  According to the present embodiment, the first stress control film 81 and the first insulating film 83 covering the first region 13p and the second region 13n are formed in this order, covering the first region 13p and opening the second region 13n. When the first insulating film 83 and the first stress control film 81 in the second region 13n are etched using the resist film 84, and the second stress control film 82 is formed, the first region 13p of the first region 13p is formed. Since the stress control film 81 is covered with the first insulating film 83 having the same shape as the resist film 84, the first stress control film 81 and the second stress control film 82 do not overlap each other or the first stress control film 81. And the ends of the second stress control film 82 are separated from each other, and the surfaces of the element isolation region 12 and the source / drain regions 19 and 30 are prevented from being exposed. Therefore, when the contact hole is formed, the contact hole does not reach the surface of the source / drain regions 19, 30, the contact failure between the contact and the source / drain regions 19, 30 occurs, or the element isolation region 12 is punched out. This can prevent the occurrence of junction leakage.

  As shown in the step of FIG. 22 instead of the step of FIG. 21, the first insulating film 83 and the second insulating film 85 are first etched, and the first stress control film 81 and the second stress control film 82 are etched and stopped. The film may be removed using a hydrofluoric acid solution. Then, the portion of the second stress control film 82b sandwiched between the first insulating film 83 and the second insulating film 85 is etched by time control using, for example, a phosphoric acid solution. At this time, the other portions of the first stress control film 81 and the second stress control film 82 are slightly eroded, but the second stress control film sandwiched between the first insulating film 83 and the second insulating film 85 is used. The portion 82b has a thin plate shape and is etched from its two surfaces, so that the etching rate is high and can be removed without affecting the others.

(Fifth embodiment)
The manufacturing method of the semiconductor device according to the fifth embodiment of the present invention is substantially the same as that of the fourth embodiment except that the second stress control film is formed before the first stress control film and the order thereof is different. It forms similarly.

  23 to 25 are manufacturing process diagrams of the semiconductor device according to the fifth embodiment. In the figure, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

  First, in the process of FIG. 23A, the formation of the silicide films 24, 25, 35, and 36 is performed as in the process of FIG. 19A of the fourth embodiment.

  In the step of FIG. 23A, the second stress control film 82 having a tensile stress is further covered by the thermal CVD method described above so as to cover the surfaces of the silicon substrate 11 and the element isolation region 12 and the gate stacked bodies 23 and 34. Form.

  In the step of FIG. 23A, a first insulating film 83 made of a silicon oxide film (for example, a film thickness of 600 nm) covering the second stress control film 82 is further formed, and the surface thereof is flattened by the CMP method. Note that the planarization process may be omitted when the step coverage of the first insulating film 83 is good.

  23B, a resist film 86 is formed on the first insulating film 83 in FIG. 23A, and then an opening 86-1 is formed in the resist film 86 in the first region 13p. .

  In the step of FIG. 23B, the first insulating film 83 in the first region 13p is etched by the RIE method using the resist film 86 as a mask to expose the second stress control film 82, and further, the first region 13p. The second stress control film 82 is etched by RIE to expose the silicon substrate surface and the gate stack. Note that the etching gas is the same as that in the step of FIG. 19B in the fourth embodiment.

  Next, in the step of FIG. 24A, the resist film 86 of FIG. 23B is removed, and the first insulating film 83 in the second region 13n is exposed. Next, the first stress control film 81 that covers the surface of the silicon substrate 11 and the element isolation region 12 in the first region 13p, the gate stacked body 23, and the first insulating film 83 in the second region 13n is formed by plasma CVD. Form. The first stress control film 81 applies compressive stress to the channel region 28. At this time, the first stress control film 81 is also thinly attached to the side wall of the first insulating film 83.

  Next, in a process of FIG. 24B, a second insulating film 85 that covers the structure of FIG. The material of the fourth embodiment described above can be used for the second insulating film 85, but here the silicon oxide film is the same as the first insulating film 83. Next, the surface of the second insulating film 85 is planarized by CMP, and the first stress control film 81 on the surface of the first insulating film 83 is exposed.

  In the step shown in FIG. 24B, the first stress control film 81 on the surface of the first insulating film 83 is further removed and planarized by CMP to expose the first insulating film 83 in the second region 13n.

  Next, in the process of FIG. 25A, the first stress control film 81 sandwiched between the first insulating film 83 and the second insulating film 85 is etched by time control using, for example, a phosphoric acid solution. In the etching of the first stress control film 81, a portion sandwiched between the first insulating film 83 and the second insulating film 85 is removed, and the etched first stress control film 81a becomes another first stress control film. The process is performed until the film thickness is about the same as that of the 81 part.

  Next, in the step of FIG. 25B, the first insulating film 83 and the second insulating film 85 of FIG. 25A are used as the etching stopper film with the first stress control film 81 and the second stress control film 82 as the etching stopper film. After removing using the acid solution, the interlayer insulating film 16 covering the first stress control film 81 and the second stress control film 82 is formed, and the semiconductor device shown in FIG. 25B is formed.

  As in the fourth embodiment, in the step of FIG. 25A, the first insulating film 83 and the second insulating film 85 are first formed, and the first stress control film 81 and the second stress control film 82 are formed. The etching stopper film may be removed using a hydrofluoric acid solution. As a result, the structure shown in FIG. 26 is obtained. Then, the portion 81b of the first stress control film sandwiched between the first insulating film 83 and the second insulating film 85 is etched by time control using, for example, a phosphoric acid solution.

  According to the present embodiment, the second stress control film 82 and the first insulating film 83 covering the first region 13p and the second region 13n are formed in this order, covering the second region 13n and opening the first region 13n. The first insulating film 83 and the second stress control film 82 in the first region 13p are etched using the resist film 86, and the second stress in the second region 13n is formed when the first stress control film 81 is formed. Since the stress control film 82 is covered with the first insulating film 83 having the same shape as the resist film 86, the first stress control film 81 and the second stress control film 82 do not overlap each other or the first stress control film 81. Therefore, it is avoided that the end portions of the second stress control film 82 are separated from each other and the surfaces of the element isolation region 12 and the source / drain regions 19 and 30 are exposed. Therefore, as in the fourth embodiment, when the contact hole is formed, the contact hole does not reach the surface of the source / drain regions 19 and 30 and contact failure between the contact and the source / drain region occurs. Further, it is possible to prevent the occurrence of junction leakage by avoiding the punching of the element isolation region 12.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the present invention described in the claims. It can be changed.

In addition to the above description, the following additional notes are disclosed.
(Additional remark 1) It arrange | positions in the 1st area | region of a semiconductor substrate, and is arrange | positioned in the 2nd area | region of this semiconductor substrate which has a gate laminated body which consists of an impurity region, a gate oxide film, and a gate electrode. A semiconductor device comprising: an impurity region; and an n-type MOS transistor having a gate stack composed of a gate oxide film and a gate electrode,
A first stress control film disposed in the first region and having a compressive stress covering the surface of the semiconductor substrate and the gate stack;
A second stress control film disposed in the second region and having a tensile stress covering the surface of the semiconductor substrate and the gate stacked body; and the first stress control film covering the second stress control film. Prepared,
When the magnitude of the compressive stress of the first stress control film is P1, the film thickness is t1, the magnitude of the tensile stress of the second stress control film is P2, and the film thickness is t2, t1 × P1 <t2 × P2. A semiconductor device having the following relationship:
(Additional remark 2) The film thickness of the said 1st stress control film and the film thickness of the 2nd stress control film are substantially equivalent, and the magnitude | size of the tensile stress of a 2nd stress control film is 1st stress control film 2. The semiconductor device according to appendix 1, wherein the semiconductor device is larger than the compressive stress of 1.
(Additional remark 3) The magnitude | size of the compressive stress of the said 1st stress control film | membrane and the magnitude | size of the tensile stress of the 2nd stress control film | membrane are substantially equivalent, and the film thickness of a 2nd stress control film | membrane is 1st stress. 2. The semiconductor device according to appendix 1, wherein the semiconductor device is larger than the thickness of the control film.
(Additional remark 4) It arrange | positions in the 1st area | region of a semiconductor substrate, a p-type MOS transistor which has a gate laminated body which consists of an impurity region and a gate oxide film and a gate electrode, and is arrange | positioned in the 2nd area | region of this semiconductor substrate. A semiconductor device comprising: an impurity region; and an n-type MOS transistor having a gate stack composed of a gate oxide film and a gate electrode,
A second stress control film disposed in the second region and having a tensile stress covering the surface of the semiconductor substrate and the gate stack;
A first stress control film disposed in the first region and having a compressive stress covering the surface of the semiconductor substrate and the gate stack; and the second stress control film covering the first stress control film. Prepared,
When the magnitude of the compressive stress of the first stress control film is P1, the film thickness is t1, the magnitude of the tensile stress of the second stress control film is P2, and the film thickness is t2, t1 × P1> t2 × P2. A semiconductor device having the following relationship:
(Additional remark 5) The film thickness of the first stress control film and the film thickness of the second stress control film are substantially equal, and the magnitude of the compressive stress of the first stress control film is the second stress control film. The semiconductor device as set forth in appendix 4, wherein the tensile stress is larger than the tensile stress.
(Additional remark 6) The magnitude | size of the compressive stress of the said 1st stress control film | membrane and the magnitude | size of the tensile stress of the 2nd stress control film | membrane are substantially equivalent, and the film thickness of a 1st stress control film | membrane is 2nd stress. The semiconductor device according to appendix 4, wherein the thickness is larger than the thickness of the control film.
(Supplementary note 7) The semiconductor device according to any one of supplementary notes 4 to 6, wherein the second stress control film is formed over the first region and the second region.
(Appendix 8) An interlayer insulating film covering the first stress control film or the second stress control film;
Further comprising: the interlayer film; and a contact penetrating the first stress control film and / or the second stress control film and electrically contacting a silicide film formed on the surface of the silicon substrate. 7. The semiconductor device according to claim 1.
(Additional remark 9) It arrange | positions in the 1st area | region of a semiconductor substrate, a p-type MOS transistor which has a gate laminated body which consists of an impurity region and a gate oxide film and a gate electrode, and is arrange | positioned in the 2nd area | region of this semiconductor substrate. A semiconductor device comprising: an impurity region; and an n-type MOS transistor having a gate stack composed of a gate oxide film and a gate electrode,
A first stress control film disposed in the first region and having a compressive stress covering the surface of the semiconductor substrate and the gate stack;
A second stress control film disposed in the second region and having a tensile stress covering the surface of the semiconductor substrate and the gate stack; and covering the second stress control film and extending to the second region. A third stress control film modified by introducing impurities into the first stress control film,
When the magnitude of the compressive stress of the third stress control film is P3, the film thickness is t3, the magnitude of the tensile stress of the second stress control film is P2, and the film thickness is t2, t3 × P3 <t2 × P2. A semiconductor device having the following relationship:
(Additional remark 10) It arrange | positions in the 1st area | region of a semiconductor substrate, a p-type MOS transistor which has a gate laminated body which consists of an impurity region and a gate oxide film and a gate electrode, and is arrange | positioned in the 2nd area | region of this semiconductor substrate. A semiconductor device comprising: an impurity region; and an n-type MOS transistor having a gate stack composed of a gate oxide film and a gate electrode,
A second stress control film disposed in the second region and having a tensile stress covering the surface of the semiconductor substrate and the gate stack;
A first stress control film disposed in the first region and having a compressive stress covering the surface of the semiconductor substrate and the gate stacked body; and covering the first stress control film and extending to the first region And a fourth stress control film modified by introducing impurities into the second stress control film,
When the magnitude of the compressive stress of the first stress control film is P1, the film thickness is t1, the magnitude of the tensile stress of the fourth stress control film is P4, and the film thickness is t4, t1 × P1> t4 × P4. A semiconductor device having the following relationship:
(Additional remark 11) While covering the surface of the said semiconductor substrate and a gate laminated body, the 1st stress control film below the 1st stress control film of the 1st field and the 2nd stress control film of the 2nd field The semiconductor device according to appendix 10, further comprising an etching stopper film made of a material different from the film.

(Additional remark 12) It arrange | positions in the 1st area | region of a semiconductor substrate, and is arrange | positioned in the 2nd area | region of this semiconductor substrate which has an impurity region, and has a gate laminated body which consists of a gate oxide film and a gate electrode. And a method of manufacturing a semiconductor device comprising an impurity region and an n-type MOS transistor having a gate stack composed of a gate oxide film and a gate electrode,
Forming a second stress control film having a tensile stress covering the surface of the semiconductor substrate and the gate stack;
Selectively removing the second stress control film in the first region to expose the surface of the semiconductor substrate and the gate stack;
Forming a first stress control film having a compressive stress covering the surface of the semiconductor substrate in the first region and the gate stack and the first stress control film in the second region,
When the magnitude of the compressive stress of the first stress control film is P1, the film thickness is t1, the magnitude of the tensile stress of the second stress control film is P2, and the film thickness is t2, t1 × P1 <t2 × P2. A method for manufacturing a semiconductor device, characterized in that:
(Supplementary Note 13) After the step of forming the first stress control film, a step of forming an interlayer insulating film that covers the first stress control film;
Forming a groove portion penetrating the interlayer insulating film;
In the first region, a contact hole that communicates with the groove and penetrates the first stress control film is formed, and in the second region, communicates with the groove and communicates with the first stress control film and the first stress control film. Further comprising a step of forming a contact hole penetrating the stress control film 2;
13. The method of manufacturing a semiconductor device according to appendix 12, wherein the second stress control film is made of a material having an etching rate larger than that of the first stress control film.
(Additional remark 14) It arrange | positions in the 1st area | region of a semiconductor substrate, a p-type MOS transistor which has a gate laminated body which consists of an impurity region and a gate oxide film and a gate electrode, and is arrange | positioned in the 2nd area | region of this semiconductor substrate And a method of manufacturing a semiconductor device comprising an impurity region and an n-type MOS transistor having a gate stack composed of a gate oxide film and a gate electrode,
Forming a first stress control film having a compressive stress covering the surface of the semiconductor substrate and the gate stack;
Selectively removing the first stress control film in the second region to expose the surface of the semiconductor substrate and the gate stack;
Forming a first stress control film in the first region, and forming a second stress control film having a tensile stress covering the surface of the semiconductor substrate and the gate stack in the second region,
When the magnitude of the compressive stress of the first stress control film is P1, the film thickness is t1, the magnitude of the tensile stress of the second stress control film is P2, and the film thickness is t2, t1 × P1> t2 × P2. A method for manufacturing a semiconductor device, characterized in that:
(Supplementary Note 15) After the step of forming the second stress control film, forming an interlayer insulating film that covers the second stress control film;
Forming a groove portion penetrating the interlayer insulating film;
In the first region, the second stress control film and a contact hole penetrating the first stress control film are formed in communication with the groove, and in the second region, in communication with the groove. Further comprising a step of forming a contact hole penetrating the stress control film 2;
15. The method of manufacturing a semiconductor device according to appendix 14, wherein the first stress control film is made of a material having an etching rate larger than that of the second stress control film.

(Supplementary Note 16) A p-type MOS transistor disposed in a first region of a semiconductor substrate and having an impurity region, a gate stack including a gate oxide film and a gate electrode, and disposed in a second region of the semiconductor substrate And a method of manufacturing a semiconductor device comprising an impurity region and an n-type MOS transistor having a gate stack composed of a gate oxide film and a gate electrode,
Forming a first stress control film having a compressive stress covering the surface of the semiconductor substrate and the gate stack;
Forming a first insulating film covering the first stress control film;
Selectively removing the first insulating film and the first stress control film in the second region to expose the surface of the semiconductor substrate and the gate stack;
Forming a second stress control film having a tensile stress covering the surface of the first insulating film in the first region and the semiconductor substrate in the second region and the gate stack;
Forming a second insulating film covering the second stress control film;
Planarizing a part of the second insulating film and the second stress control film so that the first insulating film in the first region is exposed;
And a removal step of removing a part of the second stress control film sandwiched between the first insulating film and the second insulating film, and the first insulating film and the second insulating film. A method of manufacturing a semiconductor device.
(Supplementary Note 17) In the semiconductor device according to supplementary note 16, in the removing step, a part of the second stress control film is removed, and then the first insulating film and the second insulating film are removed. Production method.
(Supplementary note 18) In the semiconductor device according to supplementary note 16, in the removing step, the first insulating film and the second insulating film are removed, and then a part of the second stress control film is removed. Production method.
(Supplementary Note 19) Arranged in a first region of a semiconductor substrate, a p-type MOS transistor having an impurity region, a gate stack including a gate oxide film and a gate electrode, and disposed in a second region of the semiconductor substrate And a method of manufacturing a semiconductor device comprising an impurity region and an n-type MOS transistor having a gate stack composed of a gate oxide film and a gate electrode,
Forming a second stress control film having a tensile stress covering the surface of the semiconductor substrate and the gate stack;
Forming a first insulating film covering the second stress control film;
Selectively removing the first insulating film and the second stress control film in the first region to expose the surface of the semiconductor substrate and the gate stack;
Forming a first stress control film having a compressive stress covering the surface of the semiconductor substrate in the first region and the gate stack and the first insulating film in the second region;
Forming a second insulating film covering the first stress control film;
Planarizing a part of the second insulating film and the first stress control film so that the first insulating film in the second region is exposed;
And a removing step of removing a part of the first stress control film sandwiched between the first insulating film and the second insulating film, and the first insulating film and the second insulating film. A method of manufacturing a semiconductor device.
(Supplementary note 20) In the semiconductor device according to supplementary note 19, in the removing step, a part of the first stress control film is removed, and then the first insulating film and the second insulating film are removed. Production method.
(Supplementary note 21) In the semiconductor device according to supplementary note 19, in the removing step, the first insulating film and the second insulating film are removed, and then a part of the first stress control film is removed. Production method.

It is sectional drawing of the conventional semiconductor device. (A) And (B) is a figure which shows the manufacturing process of the semiconductor device shown in FIG. (A) And (B) is a figure for demonstrating the problem of the semiconductor device shown in FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. (A) And (B) is a manufacturing-process figure (the 1) of the semiconductor device which concerns on 1st Embodiment. (A) And (B) is a manufacturing process figure (the 2) of a semiconductor device concerning a 1st embodiment. FIG. 7 is a manufacturing process diagram (No. 3) of the semiconductor device according to the first embodiment; It is sectional drawing of the semiconductor device which concerns on the modification of 1st Embodiment. It is FIG. (1) for demonstrating the effect of the semiconductor device of 1st Embodiment. FIG. 6 is a diagram (part 2) for explaining the effect of the semiconductor device of the first embodiment; It is sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A) And (B) is a manufacturing process figure (the 1) of a semiconductor device concerning a 2nd embodiment. It is a manufacturing process figure (the 2) of a semiconductor device concerning a 2nd embodiment. It is sectional drawing of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a manufacturing process figure of the semiconductor device concerning a 3rd embodiment. It is sectional drawing of the semiconductor device which concerns on the modification of 3rd Embodiment. It is a manufacturing process figure of the semiconductor device concerning the modification of a 3rd embodiment. It is sectional drawing of the semiconductor device formed with the manufacturing method which concerns on the 4th Embodiment of this invention. (A) And (B) is a manufacturing process figure (the 1) of a semiconductor device concerning a 4th embodiment. (A) And (B) is a manufacturing process figure (the 2) of a semiconductor device concerning a 4th embodiment. It is a manufacturing process figure (the 3) of a semiconductor device concerning a 4th embodiment. It is a figure which shows the modification of the manufacturing process of the semiconductor device which concerns on 4th Embodiment. (A) And (B) is a manufacturing process figure (the 1) of a semiconductor device concerning a 5th embodiment of the present invention. (A) And (B) is a manufacturing process figure (the 2) of a semiconductor device concerning a 5th embodiment. (A) And (B) is a manufacturing process figure (the 3) of a semiconductor device concerning a 5th embodiment. It is a figure which shows the modification of the manufacturing process of the semiconductor device which concerns on 5th Embodiment.

Explanation of symbols

10, 50, 60, 70, 75, 80 Semiconductor device 11 Silicon substrate 12 Element isolation region 13n Second region 13p First region 14 p-type MOS transistor 15 n-type MOS transistor 16 Interlayer insulating film 16-1 to 16-2 Contact Hole 18 n-type well region 19, 30 Source / drain region 20, 31 Gate oxide film 21, 32 Gate electrode 22, 33 Side wall insulating film 23, 34 Gate stack 24, 25, 35, 36 Silicide film 26, 81 First Stress control film 28, 39 Channel region 29 P-type well region 38, 82 Second stress control film 40, 61, 71, 76, 84, 86 Resist film 42 Contact 83 First insulating film 85 Second insulating film

Claims (6)

A first region of a semiconductor substrate, a first impurity region, a p-type MOS transistor having a first gate oxide film and the first gate electrodes are formed, the second region of the semiconductor substrate, the second impurity region When a step of forming an n-type MOS transistor having a second gate oxide film and the second gate electrodes,
Forming a first stress control film having a compressive stress covering the surface of the semiconductor substrate , the first gate electrode, and the second gate electrode ;
Forming a first insulating film covering the first stress control film;
A step of causing exposing the first insulating film and the first stress control layer selectively removed to surface and the second gate electrode of said semiconductor substrate in said second region,
Forming a second stress control film having a first first insulating film and said semiconductor substrate surface and the second pulling cover the gate electrode stress of the second region of the region,
Forming a second insulating film covering the second stress control film;
Removing and planarizing a part of the second insulating film and the second stress control film so that the first insulating film in the first region is exposed;
And a removal step of removing a part of the second stress control film sandwiched between the first insulating film and the second insulating film, and the first insulating film and the second insulating film. A method of manufacturing a semiconductor device.   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the removing step, a part of the second stress control film is removed, and then the first insulating film and the second insulating film are removed. .   2. The method of manufacturing a semiconductor device according to claim 1, wherein the removing step removes the first insulating film and the second insulating film, and then removes a part of the second stress control film. . A first region of a semiconductor substrate, a first impurity region, a p-type MOS transistor having a first gate oxide film and the first gate electrodes are formed, the second region of the semiconductor substrate, the second impurity region When a step of forming an n-type MOS transistor having a second gate oxide film and the second gate electrodes,
Forming a second stress control film having a tensile stress covering the surface of the semiconductor substrate , the first gate electrode, and the second gate electrode ;
Forming a first insulating film covering the second stress control film;
A step of causing exposing the first insulating film and the second stress control film selectively removed to the surface and the first gate electrode of said semiconductor substrate in said first region,
Forming a first stress control film having a compressive stress to cover the first insulating film between the surface and the first gate electrode of said semiconductor substrate of the first region and the second region,
Forming a second insulating film covering the first stress control film;
Removing and planarizing a part of the second insulating film and the first stress control film so that the first insulating film in the second region is exposed;
And a removing step of removing a part of the first stress control film sandwiched between the first insulating film and the second insulating film, and the first insulating film and the second insulating film. A method of manufacturing a semiconductor device.   5. The method of manufacturing a semiconductor device according to claim 4, wherein in the removing step, a part of the first stress control film is removed, and then the first insulating film and the second insulating film are removed. .   5. The method of manufacturing a semiconductor device according to claim 4, wherein the removing step removes the first insulating film and the second insulating film, and then removes a part of the first stress control film. .

Images