JP5002891B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention is related to a method of manufacturing a semiconductor equipment.

In order to increase the operating frequency of the microprocessor, the operating speed of the CMOS transistor is increased. The increase in speed has been achieved mainly by miniaturization of CMOS transistors. The miniaturization of a CMOS transistor has been promoted by reducing the channel length of the transistor by shortening the wavelength of light used for lithography and reducing the thickness of the gate oxide film of the gate electrode of the transistor. However, the minimum photoetching dimension has become smaller than the wavelength of light used for lithography, and it has become difficult to reduce the thickness of the gate oxide film of the gate electrode because it is necessary to ensure a breakdown voltage. For this reason, miniaturization of CMOS transistors is becoming difficult.

  Therefore, in the generation of CMOS transistors with a minimum photoetching dimension of 50 nm or less, stress is applied to the channel portion of the transistor and the silicon crystal is distorted to increase the electron movement speed in the channel region (increasing the on-current of the transistor). Technology has been developed.

  A schematic cross-sectional view of a conventional CMOS transistor is shown in FIG. The CMOS transistor is composed of an n-channel transistor 60a and a p-channel transistor 60b. The n-channel transistor 60a includes a p-type well region 68a, a source / drain 66a, and a gate stack 70a including a gate electrode 64a, a gate oxide film 62a, and a gate electrode sidewall insulating film 65a. , An n-type well region 68b, a source / drain 66b, and a gate stacked body 70b including a gate electrode 64b, a gate oxide film 62b, and a gate electrode sidewall insulating film 65b. Since the CMOS transistor increases the on-current of both the n-channel transistor 60a and the p-channel transistor 60b, the silicon nitride film 61a is applied so that tensile stress is applied to the channel portion of the n-channel transistor 60a as shown in FIG. And the silicon nitride film 61b is formed so that compressive stress is applied to the channel portion of the p-channel transistor 60b, thereby improving the on-current of each transistor.

  When tensile stress is applied to the channel portions of the n-channel transistor 60a and the p-channel transistor 60b, the silicon nitride film 61b is made thinner than the silicon nitride film 61a, and the n-channel transistors 60a and p When compressive stress is applied to the channel portion of the channel type transistor 60b, the film thickness of the silicon nitride film 61a is made thinner than the film thickness of the silicon nitride film 61b, that is, the film thickness of the silicon nitride films 61a and 61b is controlled. The on-current of each transistor is improved by providing a difference in stress applied to the channel portions of the n-channel transistor 60a and the p-channel transistor 60b. As another method, there is a method of controlling the area of the portion of the silicon nitride films 61a and 61b extending adjacent to the source / drain 66a and 66b.

  In addition, although the effect is smaller than the above method, a tensile stress is applied to the channel portion of the n-channel transistor 60a, and the channel portion of the p-channel transistor 60b is compressed more than the n-channel transistor 60a although it is a tensile stress. There is also a method for improving the on-current of each transistor by applying stress on the stress side. On the contrary, compressive stress is applied to the channel portion of the p-channel transistor 60a, and stress on the tensile stress side from the p-channel transistor 60b is applied to the channel portion of the n-channel transistor 60a. There is also a method for improving the on-current of each transistor. These methods are described below. Although not shown in each description, the reference numerals used in FIG. 17 are applied to the respective parts.

  By making the thickness of the silicide film 63a of the n-channel transistor 60a larger than the thickness of the silicide film 63b of the p-channel transistor 60b, the on-current of the n-channel transistor 60a is improved, and the on-state of the p-channel transistor 60b is increased. The decrease in current is suppressed.

  Further, after the gate electrode 64a of the n-channel transistor 60a is formed of amorphous silicon and is subjected to heat treatment without adding impurities, impurities are implanted, and tensile stress is applied to the channel portion of the n-channel transistor 60a. To be added. The gate electrode 64b of the p-channel transistor 60b is formed of amorphous silicon, and after impurities are implanted, the gate electrode 64b is heat-treated so as to have a tensile crystallization stress. The portion is applied with a stress on the compression side rather than the tensile stress applied to the channel portion of the n-channel transistor 60a, thereby suppressing a decrease in on-current of the p-channel transistor 60b.

  Further, by forming the gate electrode 64a of the n-channel transistor 60a in two layers, the crystal grain size of the gate electrode 64b of the p-channel transistor 60b in which the gate electrode 64a has a single crystal grain size is formed. The stress applied to the channel portion of the n-channel transistor 60a is reduced by making it smaller than the diameter, thereby suppressing a decrease in on-current of the n-channel transistor 60a.

  In addition, the stress applied to the channel portion of the p-channel transistor 60b is such that the distance between the channel portion of the transistor and the adjacent element isolation region 69 is smaller in the p-channel transistor 60b than in the n-channel transistor 60a. The stress applied to the channel portion of the n-channel transistor 60a is made higher.

  Further, by changing the film quality of the gate electrode sidewall insulating films 65a and 65b of the n-channel transistor 60a and the p-channel transistor 60b, the stress of the gate electrode sidewall insulating film 65a of the n-channel transistor 60a is changed to the p-channel transistor 60b. The stress of the gate electrode sidewall insulating film 65b of the n-channel transistor 60a is the stress of the gate electrode sidewall insulating film 65a of the n-channel transistor 60a. The on-current of each transistor is improved so as to be relatively on the compression side.

Further, the Young's modulus of the gate electrode sidewall insulating films 65a and 65b of the n-channel transistor 60a and the p-channel transistor 60b is changed, that is, the n-channel transistor 60a and the p-channel transistor 60b are covered with the same silicon nitride film. When the silicon nitride film applies compressive stress to the transistor, the Young's modulus of the gate electrode sidewall insulating film 65a of the n-channel transistor 60a is made smaller than the Young's modulus of the gate electrode sidewall insulating film 65b of the p-channel transistor 60b. In addition, the material of the gate electrode sidewall insulating films 65a and 65b is selected. Conversely, when the silicon nitride film applies a tensile stress to the transistor, the Young's modulus of the gate electrode sidewall insulating film 65a of the n-channel transistor 60a is made larger than the Young's modulus of the gate electrode sidewall insulating film 65b of the p-channel transistor 60b. The material of the gate electrode sidewall insulating film 65a, 65b is selected. This improves the on-current of each transistor.
JP 2003-86708 A

However, in the generation of CMOS transistors having a minimum photoetching dimension of 50 nm or less, in order to operate at higher speed, a silicon nitride film is applied so that tensile stress is applied to the channel portion of the n-channel transistor as shown in FIG. There is a limit in simply forming the silicon nitride film 61b so that compressive stress is applied to the channel portion of the p-channel transistor 60b by forming 61a and improving the on-current of each transistor. Further, the method of forming the silicon nitride film 61a so that tensile stress is applied to the channel portion of the n-channel transistor and forming the silicon nitride film 61b so as to apply compressive stress to the channel portion of the p-channel transistor 60b is described above. Even if other methods for improving the on-current of each of the transistors are combined, performance improvement cannot be expected.
For example, the silicon nitride film 61a is formed so that tensile stress is applied to the channel portion of the n-channel transistor 60a shown in FIG. 17, and the silicon nitride film 61b is formed so that compressive stress is applied to the channel portion of the p-channel transistor 60b. Even if the film quality of the gate electrode sidewall insulating films of the n-channel transistor 60a and the p-channel transistor 60b is changed or the Young's modulus of the gate electrode sidewall insulating film is changed, the silicon nitride film 61a as described above. , 61b is effective only in a film having the stress in the same direction. That is, in the CMOS transistor in which the silicon nitride film 61a is formed so that tensile stress is applied to the channel portion of the n-channel transistor 60a, and the silicon nitride film 61b is formed so that compressive stress is applied to the channel portion of the p-channel transistor 60b. The on-current cannot be improved.
The present invention has been made in view of the above circumstances, and a silicon nitride film is formed so that tensile stress is applied to the channel portion of the n-channel transistor, and silicon is applied to compressive stress in the channel portion of the p-channel transistor. An object of the present invention is to provide a manufacturing method in which the on-state current of both an n-channel transistor and a p-channel transistor is further improved and the efficiency of the manufacturing process is improved in a CMOS transistor in which a nitride film is formed.

In the first method for manufacturing a semiconductor device, a first active region is formed on a semiconductor substrate, a first gate oxide film is formed on the first active region, and on the first gate insulating film. A first gate electrode is formed and a first impurity is implanted into the first active region using the first gate electrode as a mask to form a first diffusion layer. In addition, a first gate electrode sidewall insulating film is formed on a sidewall of the first gate electrode, and the first active region is formed on the first active region using the first gate electrode and the first gate electrode sidewall insulating film as a mask. A second impurity is implanted to form a second diffusion layer deeper than the first diffusion layer. In addition, after forming the second diffusion layer, the first gate electrode sidewall insulating film is etched. Further, after etching at least a part of the first gate electrode sidewall insulating film, a first stress control film covering the first active region is formed.

In the method of manufacturing a semi-conductor device, a semiconductor substrate, a first forming an active region and a second active region, a first gate oxide film formed on the first active region, the first A first gate electrode is formed on the gate oxide film, and a first impurity is implanted into the first active region using the first gate electrode as a mask to form a first diffusion layer. Further, a first gate electrode sidewall insulating film is formed on the first gate electrode sidewall, and the first active region is formed in the first active region using the first gate electrode and the first gate electrode sidewall insulating film as a mask. Two impurities are implanted to form a second diffusion layer deeper than the first diffusion layer. In addition, a second gate oxide film is formed on the second active region, a second gate electrode is formed on the second gate oxide film, and the second gate electrode is used as a mask to form the second gate electrode. A third impurity is implanted into the second active region to form a third diffusion layer. In addition, a second gate electrode sidewall insulating film is formed on the sidewall of the second gate electrode, and the second active region is formed on the second active region using the second gate electrode and the second gate electrode sidewall insulating film as a mask. A fourth impurity is implanted to form a fourth diffusion layer deeper than the third diffusion layer. Further, a first stress control film that covers the first active region and the second active region is formed, a mask layer that covers the second active region is formed, and the first layer is formed using the mask layer as a mask. The first stress control film in the active region is removed, the first gate electrode sidewall insulating film is removed by etching, and a second stress control film covering the first active region is removed from the first gate. It forms so that the side wall of an electrode may be contact | connected.

  According to the present invention, the first gate stack of the n-channel transistor disposed in the first region of the semiconductor substrate and the second gate of the p-channel transistor disposed in the second region of the semiconductor substrate. By employing a structure in which one or both of the stacked bodies do not have the gate electrode side wall insulating film, more stress is applied to the channel portion of each transistor, and the on-current of each transistor is improved, and the manufacturing process is performed. A CMOS transistor with improved efficiency can be realized.

  Embodiments of the present invention will be described using examples.

  FIG. 1 shows a basic structure of a CMOS transistor according to a first specific example of an embodiment of the present invention.

  A schematic diagram of the manufacturing flow of the CMOS transistor shown in FIG. 1 will be described with reference to FIGS.

  First, as shown in FIG. 2A, an element isolation region 12 is formed on a Si substrate 11 by an STI (Shallow Trench Isolation) method, and a p-type conductivity type is formed in a first region 13n where an n-channel transistor is formed. Impurities are implanted to form the p-type well region 18, and n-type conductivity type impurities are implanted into the second region 13p where the p-channel transistor is formed to form the n-type well region 28.

  Next, after forming a gate oxide film and a polysilicon film on the surface of the Si substrate 11, gate oxide films 20 and 31, and gate electrodes 21 and 32 made of a polysilicon film are formed by an etching method. 32 is used as a mask, n-type conductivity type impurities are implanted into the first region 13n, and p-type conductivity type impurities are implanted into the second region 13p to form shallow junction regions 19a and 30a, respectively. . Subsequently, an insulating film made of a silicon oxide film is formed so as to cover the surface of the Si substrate 11 and the gate electrodes 21 and 32, and the insulating film is etched back to form gate electrode sidewall insulating films 22 and 33. In this way, the first gate stacked body 23 and the second gate stacked body 34 are formed.

  Next, using the gate electrodes 21 and 32 and the gate electrode sidewall insulating films 22 and 33 as a mask, an n-type conductivity type impurity is implanted into the first region 13n, and a p-type conductivity type is implanted into the second region 13p. Then, deep junction regions 19b and 30b are formed. Subsequently, the impurity implanted by the heat treatment is activated to form the source / drain regions 19 and 30.

Next, a Ni film is formed to cover the surface of the Si substrate 11 and the first gate stacked body 23 and the second gate stacked body 34 (not shown). NiSi ₂ silicide films 24, 25, 35, and 36 are formed in the drain regions 19 and 30 and the gate electrodes 21 and 32, and then the unreacted Ni film is removed.

Next, as shown in FIG. 2B, a silicon nitride film (first stress control film) 26 having a tensile stress of 60 nm thickness is formed on the entire surface of the structure shown in FIG. Form. The first stress control film 26 is formed of SiH ₂ Cl ₂ + SiH ₄ + Si ₂ H ₄ + Si ₂ H ₆ gas (flow rate 5 to 50 sccm), NH ₃ gas (flow rate 500 to 10,000 sccm), and N ₂ + Ar gas (flow rate 500). 10000 sccm), a chemical reaction is performed under conditions of a substrate temperature of 500 ° C. to 700 ° C. and a pressure of 0.1 Torr to 400 Torr. The first stress control film 26 formed under these conditions has a tensile stress of 1.4 GPa as an internal stress. The internal stress was measured by the following method. A second stress control film having a thickness of 100 nm is formed on the surface of a Si substrate having a diameter of 200 mm and a thickness of 0.6 mm by the above-described formation method. Subsequently, the amount of curvature (curvature radius) of the Si substrate is measured by a measurement method using a Newton ring, and the internal stress is the longitudinal elastic modulus of the Si substrate, the thickness of the Si substrate, the Poisson's ratio of the Si substrate, It is calculated from the relationship between the radius of curvature and the thickness of the second stress control film.

Next, a silicon oxide film 41 serving as an etching stopper film is formed by plasma CVD. The silicon oxide film 41 is formed by chemically reacting SiH ₄ + O ₂ gas with a substrate temperature of 400 ° C.

As shown in FIG. 2C, a resist film 40 is applied on the silicon oxide film 41, and an opening is formed in the second region 13p. Subsequently, the first stress control film 26 is exposed by reactive ion etching (RIE). Note that C ₄ F ₈ + Ar + O ₂ gas was used for the RIE method. Subsequently, the surface of the Si substrate 11, the gate electrode 32, and the side walls of the gate oxide film 31 are exposed by RIE. Here, the gate electrode 32 shows a state where the gate electrode sidewall insulating film 33 is removed from the second gate stacked body 34. Note that CHF ₃ + Ar + O ₂ gas was used for the RIE method.

Next, the resist film 40 in FIG. 2C is removed. Subsequently, as shown in FIG. 2D, the surface of the Si substrate 11 in the second region 13p, the side walls of the gate electrode 32 and the gate oxide film 31, and the silicon oxide film 41 in the first region 13n are covered. Then, a silicon nitride film (second stress control film) 38 having a compressive stress with a film thickness of 80 nm is formed by plasma CVD. The second stress control film 38 supplies SiH ₄ gas (flow rate 100 to 1000 sccm), NH ₃ gas (flow rate 500 to 10,000 sccm), and N ₂ + Ar gas (flow rate 500 to 10,000 sccm), and the substrate temperature is 400 ° C. It is formed by chemical reaction under conditions of ˜700 ° C., pressure of 0.1 Torr to 400 Torr, and RF power of 100 W to 1000 W. The second stress control film 38 formed under these conditions has a compressive stress of 1.4 GPa as an internal stress.

As shown in FIG. 2E, a resist film 50 is formed on the second stress control film 38, and an opening is formed in the first region 13n. Subsequently, the silicon oxide film 41 is exposed by RIE. Note that CHF ₃ + Ar + O ₂ gas was used for the RIE method.

  Next, after removing the resist film 50 from the structure shown in FIG. 2E, an interlayer insulating film 17 having a thickness of 600 nm made of a silicon oxide film is formed as shown in FIG. The surface is planarized by a chemical mechanical polishing (CMP) method.

  Further, a schematic diagram of a contact manufacturing flow in the CMOS transistor shown in FIG. 1 will be described with reference to FIGS.

As shown in FIG. 3A, a resist film 43 is formed on the surface of the interlayer insulating film 17, and openings 44-1 and 44-2 are formed in the first region 13n and the second region 13p, respectively. Subsequently, as shown in FIG. 3B, the contact holes 16-1 and 16-2 are first formed through the silicon oxide film 41 and the second stress control film 38 in the first region 13n by the RIE method. Let Note that CF ₄ + H ₂ gas was used for the RIE method. Next, the silicon oxide film 41 in the first region 13n is removed by RIE, and the first stress control film 26 is exposed. Note that the RIE method using a _{C 4 F 8 + Ar + 0} 2 gas. Next, as shown in FIG. 3C, the silicide films 24 and 35 are penetrated by the RIE method to complete. Since the first stress control film 26 and the second stress control film 38 have different etching rates, it is desirable to select a gas that minimizes damage to the silicide films 24 and 35. Here, CHF ₃ gas was used for the RIE method.

  Finally, after removing the resist film 43, the contact holes 16-1 and 16-2 are formed by forming a barrier metal film (not shown) made of a deposited layer of Ti film / TiN film, Cu (copper), W (tungsten), The contact 42 shown in FIG. 3D is formed by filling with a conductive material such as Al (aluminum).

  As described above, the first specific example which is the basic structure of the CMOS transistor is completed.

  In the p-channel transistor fabricated in this way, the second gate stack 34 is removed from the gate electrode side wall insulating film 33, and the surface of the Si substrate 11 and the gate electrode side wall insulating film 33 are removed. By forming the second stress control film 38 having a compressive stress on the surface of the gate stacked body 34, the amount of strain in the channel portion increases, and the on-current of the p-channel transistor increases. It was confirmed using a process simulator (trade name: TSUPREM4, manufactured by Synopsys). The simulation conditions are as follows. In the present invention, the internal stress of the first stress control film 26 having tensile stress and the second stress control film 38 having compressive stress are 1.4 GPa, and the thickness of the first stress control film 26 is The thickness of the second stress control film 38 is 60 nm, the gate length is 50 nm, and the gate height (the height from the surface of the Si substrate 11 to the surfaces of the silicide films 21 and 36 of the gate electrodes 21 and 32). ) Is 100 nm, the width of the gate electrode sidewall insulating film 22 of the n-channel transistor is 80 nm, and the width of the gate electrode sidewall insulating film 33 of the p-channel transistor is zero. For comparison with the present invention, when the width of the gate electrode sidewall insulating film 33 of the p-channel transistor according to the prior art becomes 80 nm (other parameters of the p-channel transistor and parameters of the n-channel transistor are the same as those of the present invention) ) Was also added to the conditions.

FIG. 4 is a diagram showing the relationship between the width of the gate electrode sidewall insulating film and the amount of strain in the channel portion in the p-channel transistor. Here, the strain amount of the channel portion is expressed by the ratio (Δx / x) of the change amount (Δx) of the channel length when the stress is applied to the channel portion with respect to the channel length (x) before the stress is applied to the channel portion. Is done. In the prior art, it was -1.70 × 10 ⁻³ , whereas in the present invention, −3.42 × 10 ⁻³ , it can be seen that the amount of strain in the compression direction is approximately doubled. By increasing the amount of strain in the compression direction, the on-current of the p-channel transistor can be increased by about 20%.

  A semiconductor device according to a modification of the first specific example will be described.

  FIG. 5 shows a basic structure of a CMOS transistor according to a modification of the first specific example. In the figure, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

  The semiconductor device according to a modification of the first specific example is formed by reducing the width and height dimensions of the gate electrode sidewall insulating film 33 of the p-channel transistor. Other parts are configured in the same manner as the semiconductor device of the first specific example shown in FIGS. The semiconductor device manufacturing method according to the modification of the first specific example is the first stress control that covers the surface of the Si substrate 11 and the second gate stacked body 34 in the second region 13p described with reference to FIG. In the step of removing the film 26 and the gate electrode side wall insulating film 33 by the RIE method, the gate electrode side wall insulating film 33 is not completely removed but the gate electrode side wall insulating film 33 is formed so as to recede (part remains). Is done. The formation of the second stress control film 38 described with reference to FIG. 2D includes the surface of the Si substrate 11, the gate stacked body 34 (including the gate electrode sidewall insulating film that remains partially), and the first region. This is performed on the 13n silicon oxide film 41. The other steps are the same as those in FIGS. 2A, 2B, 2E, and 3F and FIG.

  FIG. 6 shows the relationship between the width of the gate electrode sidewall insulating film 33 of the p-channel transistor and the amount of strain in the channel portion. Similar to FIG. 4, the amount of strain in the channel portion was confirmed using a process simulator. When the width of the gate electrode sidewall insulating film 33 of the p-channel transistor is 80 nm of the prior art, and the width of the gate electrode sidewall insulating film 22 of the p-channel transistor is 60 nm, 40 nm, 30 nm and 20 nm as a modification of the first specific example. A simulation was performed. The simulation conditions are the same as those described above, except that the width of the gate electrode sidewall insulating film 22 of the p-channel transistor is different. Note that the height of the gate electrode sidewall insulating film 33 of the p-channel transistor was reduced at the same ratio as the width.

The distortion amount of the channel portion is −1.70 × 10 ⁻³ in the prior art, whereas in the modification of the first specific example, the width of the gate electrode sidewall insulating film 33 of the p-channel transistor is In the case of 60 nm, 40 nm, 30 nm, and 20 nm, the gate electrode is −2.10 × 10 ⁻³ , −2.54 × 10 ⁻³ , −2.80 × 10 ⁻³ , −3.00 × 10 ⁻³ , respectively. It can be seen that the amount of strain in the compression direction of the channel portion increases in proportion to the decrease in the width of the sidewall insulating film 33. That is, by increasing the width of the gate electrode sidewall insulating film 33, the amount of increase in on-current of the p-channel transistor can be adjusted.

  FIG. 7 shows a basic structure of a CMOS transistor according to a second specific example of the embodiment of the present invention.

  A schematic diagram of the manufacturing flow of the CMOS transistor shown in FIG. 7 will be described with reference to FIGS.

  First, as shown in FIG. 8A, an element isolation region 112 is formed on an Si substrate 111 by an STI method, and p-type conductivity type impurities are implanted into a first region 113n where an n-channel transistor is formed. An n-type well region 118 is formed, and an n-type conductivity region is implanted into the second region 113p where the p-channel transistor is formed, thereby forming an n-type well region 128.

  Next, after forming a gate oxide film and a polysilicon film on the surface of the Si substrate 111, gate oxide films 120 and 131 and gate electrodes 121 and 132 made of a polysilicon film are formed by an etching method. Using the mask 132 as a mask, an n-type conductivity type impurity is implanted into the first region 113n, and a p-type conductivity type impurity is implanted into the second region 113p to form shallow junction regions 119a and 130a, respectively. . Subsequently, an insulating film made of a silicon oxide film is formed so as to cover the surface of the Si substrate 111 and the gate electrodes 121 and 132, and the insulating film is etched back to form gate electrode sidewall insulating films 122 and 133. In this way, the first gate stacked body 123 and the second gate stacked body 134 are formed.

  Next, using the gate electrodes 121 and 132 and the gate electrode sidewall insulating films 122 and 133 as masks, an n-type conductivity impurity is implanted into the first region 113n, and a p-type conductivity type is implanted into the second region 113p. Then, deep junction regions 119b and 130b are formed. Subsequently, the impurity implanted by the heat treatment is activated to form source / drain regions 119 and 130.

Next, a Ni film is formed to cover the surface of the Si substrate 111, the first gate stacked body 123, and the second gate stacked body 134 (not shown), and then heat treatment at about 450 ° C. NiSi ₂ silicide films 124, 125, 135, 136 are formed in the drain regions 119, 130 and the gate electrodes 121, 132, and then the unreacted Ni film is removed.

Next, as shown in FIG. 8B, a silicon nitride film (second stress control film) 138 having a compressive stress of 80 nm thickness is formed on the entire surface of the structure of FIG. 8A by plasma CVD. Form. The second stress control film 138 supplies SiH ₄ gas (flow rate 100 to 1000 sccm), NH ₃ gas (flow rate 500 to 10,000 sccm), and N ₂ + Ar gas (flow rate 500 to 10,000 sccm), and the substrate temperature is 400 ° C. It is formed by chemical reaction under conditions of ˜700 ° C., pressure of 0.1 Torr to 400 Torr, and RF power of 100 W to 1000 W. The second stress control film 138 formed under these conditions has a compressive stress of 1.4 GPa as an internal stress. The internal stress was measured by the following method. A second stress control film having a thickness of 100 nm is formed on the surface of a Si substrate having a diameter of 200 mm and a thickness of 0.6 mm by the above-described formation method. Subsequently, the amount of curvature (curvature radius) of the Si substrate is measured by a measurement method using a Newton ring, and the internal stress is the longitudinal elastic modulus of the Si substrate, the thickness of the Si substrate, the Poisson's ratio of the Si substrate, It is calculated from the relationship between the radius of curvature and the thickness of the second stress control film.

Next, a silicon oxide film 141 serving as an etching stopper film is formed by plasma CVD. Note that the silicon oxide film 141 is formed by a chemical reaction of SiH ₄ + O ₂ gas with a substrate temperature of 400 ° C.

As shown in FIG. 8C, a resist film 140 is applied on the second stress control film 138, and an opening is formed in the first region 113n. Subsequently, the second stress control film 138 is exposed by the RIE method. Note that C ₄ F ₈ + Ar + O ₂ gas was used for the RIE method. Subsequently, the surface of the Si substrate 111, the gate electrode 121, and the side walls of the gate oxide film 120 are exposed by RIE. Here, the gate electrode 121 shows a state in which the gate electrode sidewall insulating film 122 is removed from the first gate stacked body 123. Note that CHF ₃ + Ar + O ₂ gas was used for the RIE method.

Next, the resist film 140 in FIG. 8C is removed. Subsequently, as shown in FIG. 8D, the surface of the Si substrate 111 in the first region 113n, the side walls of the gate electrode 121 and the gate oxide film 120, and the silicon oxide film 141 in the second region 113p are covered. Then, a silicon nitride film (first stress control film) 126 having a tensile stress of 60 nm is formed by thermal CVD. The first stress control film 126 is formed of SiH ₂ Cl ₂ + SiH ₄ + Si ₂ H ₄ + Si ₂ H ₆ gas (flow rate 5 to 50 sccm), NH ₃ gas (flow rate 500 to 10,000 sccm), and N ₂ + Ar gas (flow rate 500). 10000 sccm), a chemical reaction is performed under conditions of a substrate temperature of 500 ° C. to 700 ° C. and a pressure of 0.1 Torr to 400 Torr. The first stress control film 126 formed under these conditions has a tensile stress of 1.4 GPa as an internal stress.

As shown in FIG. 8E, a resist film 150 is formed on the first stress control film 126, and an opening is formed in the second region 113p. Subsequently, the silicon oxide film 141 is exposed by the RIE method. Note that CHF ₃ + Ar + O ₂ gas was used for the RIE method.

  Next, after removing the resist film 150 from the structure of FIG. 8E, an interlayer insulating film 117 made of a silicon oxide film having a thickness of 600 nm is formed as shown in FIG. The surface is planarized by a chemical mechanical polishing (CMP) method.

  Further, a schematic diagram of a contact manufacturing flow in the CMOS transistor shown in FIG. 7 will be described with reference to FIGS.

As shown in FIG. 9A, a resist film 143 is formed on the surface of the interlayer insulating film 117, and openings 144-1 and 144-2 are formed in the first region 113n and the second region 113p, respectively. Subsequently, as shown in FIG. 9B, the contact holes 116-1 and 116-2 are formed first through the first stress control film 126 and the silicon oxide film 141 in the second region 113p by the RIE method. Let Note that CF ₄ + H ₂ gas was used for the RIE method. Next, the silicon oxide film 141 in the first region 113p is removed by the RIE method, and the second stress control film 138 is exposed. Note that the RIE method using a _{C 4 F 8 + Ar + 0} 2 gas. Next, as shown in FIG. 9C, the silicide films 124 and 135 are penetrated by the RIE method to complete. Since the first stress control film 126 and the second stress control film 138 have different etching rates, it is desirable to select a gas that minimizes damage to the silicide films 124 and 135. Here, CHF ₃ gas was used for the RIE method.

  Finally, after removing the resist film 143, the contact holes 116-1 and 116-2 are formed with a barrier metal film (not shown) made of a deposited layer of Ti film / TiN film, Cu (copper), W (tungsten), The contact 142 shown in FIG. 9D is formed by filling with a conductive material such as Al (aluminum).

  As described above, the second specific example which is the basic structure of the CMOS transistor is completed.

  In the n-channel transistor manufactured as described above, the first gate laminate 123 is removed from the gate electrode sidewall insulating film 122, and the surface of the Si substrate 111 and the gate electrode sidewall insulating film 122 are removed. Since the first stress control film 126 having tensile stress is formed on the surface of the gate stacked body 123, the amount of strain in the channel portion increases and the on-current of the n-channel transistor increases. It was confirmed using a process simulator as in Example 1. The simulation conditions are as follows. In the present invention, the first stress control film 126 having a tensile stress and the second stress control film 138 having a compressive stress each have an internal stress of 1.4 GPa and the thickness of the first stress control film 126. The thickness of the second stress control film 138 is 80 nm, the gate length is 50 nm, and the gate height (the height from the surface of the Si substrate 111 to the surfaces of the silicide films 121 and 136 of the gate electrodes 121 and 132). The width of the gate electrode sidewall insulating film 122 of the p-channel transistor is 80 nm, and the width of the gate electrode sidewall insulating film 122 of the n-channel transistor is zero. For comparison with the present invention, when the width of the gate electrode sidewall insulating film 122 of the n-channel transistor according to the prior art is 80 nm (other parameters of the n-channel transistor and parameters of the p-channel transistor are the same as those of the present invention) ) Was also added to the conditions.

FIG. 10 is a diagram showing the relationship between the width of the gate electrode sidewall insulating film and the amount of strain in the channel portion in an n-channel transistor. It is represented by a ratio (Δx / x) of the change amount (Δx) of the channel length when the stress is applied to the channel portion with respect to the channel length (x) before the stress is applied to the channel portion. In the prior art, it was 1.68 × 10 ⁻³ , whereas in the present invention, it is 3.42 × 10 ⁻³ , indicating that the strain amount in the tensile direction is approximately doubled. By increasing the amount of strain in the tensile direction, the on-current of the n-channel transistor can be increased by about 20%.

  A semiconductor device according to a modification of the second specific example will be described.

  FIG. 11 shows a basic structure of a CMOS transistor according to a modification of the second specific example. In the figure, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

  The semiconductor device according to a modification of the second specific example is formed by reducing the width and height dimensions of the gate electrode sidewall insulating film 122 of the n-channel transistor. Other parts are configured in the same manner as the semiconductor device of the second specific example shown in FIGS. The manufacturing method of the semiconductor device according to the modified example of the second specific example includes the first stress control that covers the surface of the Si substrate 111 in the first region 113n and the first gate stacked body 123 described with reference to FIG. In the step of removing the film 126 and the gate electrode side wall insulating film 122 by the RIE method, the gate electrode side wall insulating film 122 is not completely removed, but the gate electrode side wall insulating film 122 is formed so as to partially remain. Then, the formation of the first stress control film 126 described with reference to FIG. 8D includes the surface of the Si substrate 111, the gate stacked body 123 (including the gate electrode side wall insulating film with a part remaining), and the second region. It is performed on the silicon oxide film 141 of 113p. The other steps are the same as those in FIGS. 8A, 8B, 8E, and 8F and FIG.

  FIG. 12 shows the relationship between the width of the gate electrode sidewall insulating film 122 of the n-channel transistor and the strain amount of the channel portion. Similar to FIG. 10, the amount of strain in the channel portion was confirmed using a process simulator. In the case where the width of the gate electrode sidewall insulating film 122 of the n-channel transistor is 80 nm of the prior art and the width of the gate electrode sidewall insulating film 122 of the n-channel transistor is 60 nm, 40 nm, 30 nm and 20 nm as a modification of the second specific example. A simulation was performed. The simulation conditions are the same as those described above, except that the width of the gate electrode sidewall insulating film 122 of the n-channel transistor is different. Note that the height of the gate electrode sidewall insulating film 122 of the n-channel transistor was reduced at the same ratio as the width.

The distortion amount of the channel portion is 1.70 × 10 ⁻³ in the conventional technique, whereas in the modification of the second specific example, the width of the gate electrode sidewall insulating film 122 of the n-channel transistor is 60 nm. , 40 nm, 30 nm, and 20 nm, 2.00 × 10 ⁻³ , 2.44 × 10 ⁻³ , 2.70 × 10 ⁻³ , 2.94 × 10 ⁻³ , and gate electrode sidewall insulating film 122, respectively. It can be seen that the amount of strain in the tensile direction of the channel portion increased in proportion to the decrease in width. That is, by increasing the width of the gate electrode sidewall insulating film 122, the amount of increase in on-current of the n-channel transistor can be adjusted.

  FIG. 13 shows a basic structure of a CMOS transistor according to a third specific example of the embodiment of the present invention.

  A schematic diagram of the manufacturing flow of the CMOS transistor shown in FIG. 13 will be described with reference to FIGS.

  First, as shown in FIG. 14A, an element isolation region 212 is formed on an Si substrate 211 by an STI method, and p-type conductivity type impurities are implanted into a first region 213n where an n-channel transistor is formed. An n-type well region 218 is formed, and an n-type conductivity region is implanted into the second region 213p where the p-channel transistor is formed, thereby forming an n-type well region 228.

  Next, after forming a gate oxide film and a polysilicon film on the surface of the Si substrate 211, gate oxide films 220 and 231 and gate electrodes 221 and 232 made of a polysilicon film are formed by an etching method. 232 is used as a mask, n-type conductivity type impurities are implanted into the first region 213n, and p-type conductivity type impurities are implanted into the second region 213p to form shallow junction regions 219a and 230a, respectively. . Subsequently, an insulating film made of a silicon oxide film is formed so as to cover the surface of the Si substrate 211 and the gate electrodes 221 and 232, and the insulating film is etched back to form gate electrode side wall insulating films 222 and 233. In this way, the first gate stacked body 223 and the second gate stacked body 234 are formed.

  Next, using the gate electrodes 221 and 232 and the gate electrode sidewall insulating films 222 and 233 as masks, an n-type conductivity type impurity is implanted into the first region 213n, and a p-type conductivity type is implanted into the second region 213p. Then, deep junction regions 219b and 230b are formed. Subsequently, the impurity implanted by the heat treatment is activated to form source / drain regions 219 and 230.

Next, a Ni film is formed to cover the surface of the Si substrate 211, the first gate stacked body 223, and the second gate stacked body 234 (not shown), and then heat treatment at about 450 ° C. is performed. NiSi ₂ silicide films 224, 225, 235, 236 are formed on the drain regions 219, 230 and the gate electrodes 221, 232, and then the unreacted Ni film is removed.

Next, as shown in FIG. 14B, the surface of the Si substrate 211, the side walls of the gate electrodes 221 and 232, and the gate oxide films 210 and 231 are exposed by the RIE method (the gate electrode side wall insulating films 222 and 233 are removed). . Note that C ₄ F ₈ + Ar + O ₂ gas was used for the RIE method.

Next, a silicon nitride film (first stress control film) 226 having a tensile stress of 60 nm thickness is formed by thermal CVD so as to cover the sidewalls of the silicon substrate 211, the gate electrodes 221, 232, and the gate oxide films 210, 231. Form. Note that the first stress control film 226 includes SiH ₂ Cl ₂ + SiH ₄ + Si ₂ H ₄ + Si ₂ H ₆ gas (flow rate 5 to 50 sccm), NH ₃ gas (flow rate 500 to 10,000 sccm), and N ₂ + Ar gas (flow rate 500). 10000 sccm), a chemical reaction is performed under conditions of a substrate temperature of 500 ° C. to 700 ° C. and a pressure of 0.1 Torr to 400 Torr. The first stress control film 226 formed under these conditions has a tensile stress of 1.4 GPa as an internal stress. The internal stress was measured by the following method. A second stress control film having a thickness of 100 nm is formed on the surface of a Si substrate having a diameter of 200 mm and a thickness of 0.6 mm by the above-described formation method. Subsequently, the amount of curvature (curvature radius) of the Si substrate is measured by a measurement method using a Newton ring, and the internal stress is the longitudinal elastic modulus of the Si substrate, the thickness of the Si substrate, the Poisson's ratio of the Si substrate, It is calculated from the relationship between the radius of curvature and the thickness of the second stress control film.

Next, a silicon oxide film 241 serving as an etching stopper film is formed by plasma CVD. The silicon oxide film 241 is formed by chemically reacting a SiH ₄ + O ₂ gas with a substrate temperature of 400 ° C.

As shown in FIG. 14C, a resist film 240 is applied on the first stress control film 226, and an opening is formed in the second region 213p. Subsequently, the first stress control film 226 is exposed by the RIE method. Note that C ₄ F ₈ + Ar + O ₂ gas was used for the RIE method. Subsequently, the surface of the Si substrate 211, the gate electrode 232, and the side walls of the gate oxide film 231 are exposed by RIE. Note that CHF ₃ + Ar + O ₂ gas was used for the RIE method.

Next, the resist film 240 in FIG. 14C is removed. Subsequently, as shown in FIG. 14D, the surface of the Si substrate 211 in the second region 213p, the side walls of the gate electrode 232 and the gate oxide film 231 and the silicon oxide film 241 in the first region 213n are covered. Then, a silicon nitride film (second stress control film) 238 having a compressive stress with a film thickness of 80 nm is formed by plasma CVD. The second stress control film 238 supplies SiH ₄ gas (flow rate 100 to 1000 sccm), NH ₃ gas (flow rate 500 to 10,000 sccm), and N ₂ + Ar gas (flow rate 500 to 10,000 sccm), and the substrate temperature is 400 ° C. It is formed by chemical reaction under conditions of ˜700 ° C., pressure of 0.1 Torr to 400 Torr, and RF power of 100 W to 1000 W. The second stress control film 238 formed under these conditions has a compressive stress of 1.4 GPa as an internal stress.

As shown in FIG. 14E, a resist film 250 is formed on the second stress control film 238, and an opening is formed in the first region 213n. Subsequently, the silicon oxide film 241 is exposed by RIE. Note that CHF ₃ + Ar + O ₂ gas was used for the RIE method.

  Next, after removing the resist film 250 from the structure of FIG. 14E, an interlayer insulating film 217 having a thickness of 600 nm made of a silicon oxide film is formed as shown in FIG. The surface is planarized by a chemical mechanical polishing (CMP) method.

  Further, a schematic diagram of a contact manufacturing flow in the CMOS transistor shown in FIG. 13 will be described with reference to FIGS.

As shown in FIG. 15A, a resist film 243 is formed on the surface of the interlayer insulating film 217, and openings 244-1 and 244-2 are formed in the first region 213n and the second region 213p, respectively. Subsequently, as shown in FIG. 15B, the contact holes 216-1 and 216-2 are formed first through the silicon oxide film 241 and the second stress control film 238 in the first region 213n by the RIE method. Let Note that CF ₄ + H ₂ gas was used for the RIE method. Next, the silicon oxide film 241 in the first region 213n is removed by RIE, and the first stress control film 226 is exposed. Note that the RIE method using a _{C 4 F 8 + Ar + 0} 2 gas. Next, as shown in FIG. 15C, the silicide films 224 and 235 are penetrated by the RIE method to complete. Since the first stress control film 226 and the second stress control film 238 have different etching rates, it is desirable to select a gas that minimizes damage to the silicide films 224 and 235. Here, CHF ₃ gas was used for the RIE method.

  Finally, after removing the resist film 243, the contact holes 216-1 and 216-2 are formed with a barrier metal film (not shown) made of a deposited layer of Ti film / TiN film, Cu (copper), W (tungsten), The contact 242 shown in FIG. 15D is formed by filling with a conductive material such as Al (aluminum).

  As described above, the third specific example which is the basic structure of the CMOS transistor is completed.

  In the CMOS transistor thus manufactured, the gate electrode sidewall insulating films 222 and 233 are removed from both the n-channel transistor and the p-channel transistor, and the surface of the Si substrate 211 and the gate electrode sidewall insulating films 222 and 233 are removed. By forming the first stress control film 226 having a tensile stress and the second stress control film 238 having a compressive stress on the surface of the removed gate stacks 213 and 234, the strain amount of each channel portion is increased. As a result, the on-current of each transistor increases. The confirmation was performed using a process simulator as in Example 1 and Example 2. The simulation conditions are as follows. In the present invention, the first stress control film 226 having tensile stress and the second stress control film 238 having compressive stress each have an internal stress of 1.4 GPa, and the thickness of the first stress control film 226. The thickness of the second stress control film 238 is 80 nm, the gate length is 50 nm, the gate height (the height from the surface of the Si substrate 211 to the surfaces of the silicide films 221 and 236 of the gate electrodes 221 and 232). The width of the gate electrode sidewall insulating film 222 of the n-channel transistor and the p-channel transistor was set to zero. The conventional technique for comparison with the present invention is that the width of the gate electrode sidewall insulating film 222 of the n-channel transistor and the p-channel transistor is 80 nm (other parameters of the n-channel transistor and the p-channel transistor are the same as those of the present invention). ).

  The relationship between the width of the gate electrode sidewall insulating film of each transistor and the strain amount of the channel portion is as follows. The relationship shown in FIG. 4 is the same for the n-channel transistor and that shown in FIG. The amount of distortion in the channel portions of both transistors of the present invention is about twice that of the prior art, and the on-current of both transistors can be increased by about 20%.

  A semiconductor device according to a modification of the third specific example will be described.

  FIG. 16 shows a basic structure of a CMOS transistor according to a modification of the third specific example. In the figure, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

  A semiconductor device according to a modification of the third specific example is formed by reducing the width and height dimensions of the gate electrode sidewall insulating films 222 and 233 of the n-channel transistor and the p-channel transistor. Other parts are configured in the same manner as the semiconductor device of the third specific example shown in FIGS. In the semiconductor device manufacturing method according to the modification of the third specific example, the gate electrode sidewall insulating films 222 and 233 of the first gate stacked body 223 and the second gate stacked body 234 described with reference to FIG. In the step of removing by the method, the gate electrode sidewall insulating film 222 is not completely removed, but is formed so that part of the gate electrode sidewall insulating films 222 and 233 remains. In other steps, the first gate stacked body 223 and the second gate stacked body 234 having the gate oxide films 220 and 231, the gate electrodes 221 and 232, and the gate electrode side wall insulating films 222 and 233 that are partially left by the RIE method. The first stress control film 226, the second stress control film 238, and the silicon oxide film 241 are formed on the surface of the Si substrate 211, the first gate stacked body 223, and the second gate stacked body 234. The steps of forming the interlayer insulating film 217 and the contact holes 216-1 and 216-2 are the same as those in FIGS. 14A and 14C and FIG.

  The relationship between the width of the gate electrode sidewall insulating film of each transistor and the distortion amount of the channel portion is the same as that shown in FIG. 12 for the n-channel transistor and FIG. 6 for the p-channel transistor. Similar to the third specific example, the process is performed using a process simulator. In proportion to the reduction in the width of the gate electrode sidewall insulating films 222 and 233, the channel portion of the n-channel transistor has a large strain in the tensile direction. The channel portion of the channel transistor has a large amount of strain in the compression direction. That is, by arbitrarily changing the widths of the gate electrode sidewall insulating films 222 and 233 of the n-channel transistor and the p-channel transistor, the amount of increase in the on-current of each transistor can be made finer than in the first and second embodiments. Can be adjusted.

  In the present invention, the gate stack structure described in each of the above embodiments, the stress control film, the silicon oxide film formed for the etching stopper film, the interlayer insulating film, the contact, etc. It is only an example of processing methods and conditions. For example, the silicon oxide film is not limited to the silicon oxide film as long as it is a material having etching selectivity with respect to the stress control film. The gate electrode sidewall insulating film is a silicon nitride film, but may be a silicon oxide film.

  In the present invention, a step is observed in the first stress control film or the second stress control film at the boundary between the first region and the second region in each of the above embodiments. This step is preferably formed so that no step occurs in a situation where the miniaturization advances and the interval between the transistors becomes narrow. However, there may be a step.

  Further, each of the embodiments of the present invention is different from the original MOS transistor in which the gate stack does not have the gate electrode side wall insulating film in order to reduce the electric field strength in the channel generated during the transistor operation. A gate electrode sidewall insulating film is formed in the stacked body, and source / drain impurity implantation is formed in two portions. Along with the miniaturization of CMOS transistors, silicide films are formed to reduce the resistance of the gate electrode and the source / drain.

  As described above, the present invention provides stress control in a CMOS transistor that increases the on-current of a transistor by applying tensile or compressive strain to the channel portion of the transistor due to the stress of the stress control film having tensile or compressive stress. By removing the gate electrode sidewall insulating film interposed between the film and the channel, the on-current of the transistor is further increased. Furthermore, the amount of increase in the on-state current of the transistor can be adjusted by retracting the gate electrode sidewall insulating film interposed between the stress control film and the channel.

  Therefore, in a CMOS transistor having at least a stress control film, a gate electrode, and a gate electrode side wall insulating film, it is an essential technique for increasing the on-current of the transistor, and the minimum photoetch dimension is reduced to 100 nm or less. It is also very effective in the manufacturing method.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

  The features of the present invention will be described below.

  (Appendix 1) A semiconductor substrate, a first gate electrode formed on a first active region of the semiconductor substrate via a first gate oxide film, and alignment with the first gate electrode It has a formed first diffusion layer and a first stress control film covering the first active region, the first stress control film is in contact with the first diffusion layer A semiconductor device.

  (Supplementary Note 2) A second gate electrode formed on the second active region of the semiconductor substrate via a second gate oxide film, and a second gate electrode formed in alignment with the second gate electrode 2. The semiconductor device according to claim 1, comprising two diffusion layers and a second stress control film covering the second region.

  (Supplementary note 3) The semiconductor device according to supplementary note 2, wherein the second stress control film is in contact with the second diffusion layer.

  (Additional remark 4) The said 1st stress control film | membrane has a compressive stress, The semiconductor device of Additional remark 1 characterized by the above-mentioned.

  (Supplementary note 5) The semiconductor device according to supplementary note 2, wherein the second stress control film has a tensile stress.

  (Supplementary note 6) The semiconductor device according to supplementary note 1, wherein the first active region is n-type.

  (Supplementary note 7) The semiconductor device according to supplementary note 2, wherein the second active region is p-type.

  (Supplementary note 8) The semiconductor device according to supplementary note 2, wherein the semiconductor device has a silicon oxide film extending on the second stress control film.

  (Supplementary Note 9) A semiconductor substrate, a first gate electrode formed on the first active region of the semiconductor substrate via a first gate oxide film, and alignment with the first gate electrode A first diffusion layer formed; a first gate electrode sidewall insulating film covering a sidewall of the first gate oxide film; a first stress control film covering the first active region; and the semiconductor substrate. A second gate electrode formed on the second active region via a second gate oxide film, a second diffusion layer formed in alignment with the second gate electrode, and the second And a second stress control film covering the second region, wherein the second stress control film is in contact with the second diffusion layer.

  (Supplementary note 10) The semiconductor device according to supplementary note 9, wherein the first stress control film has a compressive stress.

  (Supplementary note 11) The semiconductor device according to supplementary note 9, wherein the second stress control film has a tensile stress.

  (Supplementary note 12) The semiconductor device according to supplementary note 9, wherein the first active region is n-type, and the second active region is p-type.

  (Additional remark 13) The semiconductor device according to additional remark 9, characterized by having a silicon oxide film extending on the first stress control film.

  (Supplementary Note 14) A step of forming a first active region on a semiconductor substrate, a step of forming a first gate oxide film on the first active region, and a first gate insulating film through the first gate insulating film Forming a first gate electrode; forming a first diffusion layer in alignment with the first gate electrode; and forming a first gate electrode sidewall insulating film on the sidewall of the first gate electrode. A method of manufacturing a semiconductor device, comprising: a step of forming; a step of etching the first gate electrode sidewall insulating film; and a step of forming a first stress control film covering the first active region.

  (Supplementary Note 15) A step of forming a second active region on the semiconductor substrate, a step of forming a second gate oxide film on the second active region, and a second step through the second gate oxide film Forming a second gate electrode, forming a second diffusion layer in alignment with the second gate electrode, and forming a second gate electrode sidewall insulating film on the sidewall of the second gate electrode A step of forming, a step of forming a second stress control film covering the first region and the second region, and a step of etching the second stress control film in the first region. 15. A method for manufacturing a semiconductor device according to appendix 14.

  (Supplementary note 16) The method for manufacturing a semiconductor device according to supplementary note 15, further comprising a step of etching the second gate electrode sidewall insulating film.

  (Supplementary note 17) The method of manufacturing a semiconductor device according to supplementary note 15, wherein the first gate electrode sidewall insulating film and the second gate electrode sidewall insulating film are etched simultaneously.

  (Supplementary note 18) The method for manufacturing a semiconductor device according to supplementary note 15, further comprising a step of forming a silicon oxide film extending on the second stress control film.

  (Supplementary Note 19) A step of forming a first active region and a second active region on a semiconductor substrate, a step of forming a first gate oxide film on the first active region, Forming a first gate electrode through a gate oxide film; forming a first diffusion layer in alignment with the first gate electrode; and a first gate electrode sidewall on the first gate electrode Forming a gate electrode sidewall insulating film; forming a second gate oxide film on the second active region; and forming a second gate electrode through the second gate oxide film. Forming a second diffusion layer in alignment with the second gate electrode; forming a second gate electrode sidewall insulating film on a sidewall of the second gate electrode; and Forming a first stress control film covering the first region and the second region; and Removing the first stress control film in the region, etching the second gate electrode sidewall insulating film, and forming a second stress control film covering the second region. A method for manufacturing a semiconductor device.

  (Supplementary note 20) The method of manufacturing a semiconductor device according to supplementary note 19, further comprising a step of etching the first gate electrode sidewall insulating film.

  (Supplementary note 21) The method for manufacturing a semiconductor device according to supplementary note 19, wherein the first gate electrode sidewall insulating film and the second gate electrode sidewall insulating film are etched simultaneously.

  (Supplementary note 22) The method of manufacturing a semiconductor device according to supplementary note 19, further comprising a step of forming a silicon oxide film extending on the first stress control film.

It is a figure which shows the basic structure of the CMOS transistor which concerns on the 1st specific example of embodiment of this invention. It is the schematic of the manufacturing flow of the CMOS transistor which concerns on the 1st specific example of embodiment of this invention. It is the schematic of the manufacturing flow of the contact of the CMOS transistor which concerns on the 1st specific example of embodiment of this invention. It is a figure which shows the relationship between the width | variety of the gate electrode side wall insulating film, and the distortion amount of a channel part in the 1st example of this invention, and the p channel type transistor which concerns on a prior art. 2 shows a basic structure of a CMOS transistor according to a modification of the first specific example of the present invention. It is a figure which shows the relationship between the width | variety of the gate electrode side wall insulating film, and the distortion amount of a channel part in the p-channel type transistor which concerns on the modification of the 1st specific example of embodiment of this invention. It is a figure which shows the basic structure of the CMOS transistor which concerns on the 2nd example of embodiment of this invention. It is the schematic of the manufacturing flow of the CMOS transistor which concerns on the 2nd specific example of embodiment of this invention. It is the schematic of the manufacturing flow of the contact of the CMOS transistor which concerns on the 2nd specific example of embodiment of this invention. It is a figure which shows the relationship between the 2nd example of embodiment of this invention, and the width | variety of the gate electrode side wall insulating film in the n-channel transistor which concerns on a prior art, and the distortion amount of a channel part. It is a figure which shows the basic structure of the CMOS transistor which concerns on the modification of the 2nd specific example of this invention. It is a figure which shows the relationship between the width | variety of the gate electrode side wall insulating film of the p channel type transistor which concerns on the modification of the 2nd specific example of this invention, and the distortion amount of a channel part. It is a figure which shows the basic structure of the CMOS transistor which concerns on the 3rd specific example of embodiment of this invention. It is the schematic of the manufacturing flow of the CMOS transistor which concerns on the 3rd specific example of embodiment of this invention. It is the schematic of the manufacturing flow of the contact of the CMOS transistor which concerns on the 3rd specific example of embodiment of this invention. It is a figure which shows the basic structure of the CMOS transistor which concerns on the modification of the 3rd example of this invention. It is a figure which shows the basic structure of a CMOS transistor of a prior art.

Explanation of symbols

11, 111, 211 Si substrate,
12, 112, 212, 68 element isolation region,
13n, 113n, 213n first region,
13p, 113p, 213p second region,
16-1, 116-1, 216-1 contact holes in the first region,
16-2, 116-2, 216-2 contact holes in the first region,
17, 117, 217 interlayer insulation film,
18, 118, 218 p-type well region,
19, 119, 219 First region source / drain,
19a, 119a, 219a Shallow junction region of the source / drain of the first region,
19b, 119b, 219b A deep junction region between the source and drain of the first region,
20, 120, 220 gate insulating film of the first region,
21, 121, 221 gate electrode of the first region,
22, 122, 222 Gate electrode side wall insulating films of the first region and the second region,
23, 123, 223 first region gate stack,
24, 124, 224 first region silicide films (source / drain regions),
25, 125, 225 first region silicide film (gate electrode),
26, 126, 226 First stress control film,
28, 128, 228 n-type well region,
30, 130, 230 Source / drain of the second region,
30a, 130a, 230a Shallow junction region of the source / drain of the second region,
30b, 130b, 230b Deep junction region of the source / drain of the second region,
31, 131, 231 second region gate insulating film,
32, 132, 232 second region gate electrodes,
34, 134, 234 second region gate stack,
35, 135, 235 Second region silicide film (source / drain region),
36, 136, 236 second region silicide film (gate electrode),
38, 138, 238 second stress control film,
40, 43, 50, 140, 143, 150, 240, 243, 250 resist film,
41 silicon oxide film,
44-1, 144-1, 244-1 Openings in the first region,
44-2, 144-2, 244-2 Openings in the first region,
60a n-channel transistor,
60b p-channel transistor,
61a, 61b silicon nitride film,
62a, 62b gate oxide film,
63a, 63b silicide film,
64a, 64b gate electrodes,
65a, 65b gate electrode side wall insulating film,
66a, 66b source / drain,
66c, 66e Shallow junction region of source / drain,
66d, 66f Deep junction region between source and drain,
67 interlayer insulation film,
68a p-type well region,
68b n-type well region,
69 element isolation region,
70a, 70b gate stack,
71 Si substrate,

Claims (1)

Forming a first active region and a second active region on a semiconductor substrate;
Forming a first gate oxide film on the first active region;
Forming a first gate electrode on the first gate oxide film;
Forming a first diffusion layer by implanting a first impurity into the first active region using the first gate electrode as a mask;
Forming a first gate electrode sidewall insulating film on the first gate electrode sidewall;
Using the first gate electrode and the first gate electrode sidewall insulating film as a mask, a second impurity is implanted into the first active region, and a second diffusion layer deeper than the first diffusion layer is formed. Forming, and
Forming a second gate oxide film on the second active region;
Forming a second gate electrode on the second gate oxide film;
Using the second gate electrode as a mask, implanting a third impurity into the second active region to form a third diffusion layer;
Forming a second gate electrode sidewall insulating film on the sidewall of the second gate electrode;
Using the second gate electrode and the second gate electrode sidewall insulating film as a mask, a fourth impurity is implanted into the second active region, and a fourth diffusion layer deeper than the third diffusion layer is formed. Forming, and
Forming a first stress control film covering the first active region and the second active region;
Forming a mask layer covering the second active region, and removing the first stress control film in the first active region using the mask layer as a mask;
Etching and removing the first gate electrode sidewall insulating film ;
Forming a second stress control film covering the first active region so as to be in contact with a side wall of the first gate electrode ;
A method for manufacturing a semiconductor device, comprising:

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