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JP4635418B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

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JP4635418B2
JP4635418B2 JP2003283465A JP2003283465A JP4635418B2 JP 4635418 B2 JP4635418 B2 JP 4635418B2 JP 2003283465 A JP2003283465 A JP 2003283465A JP 2003283465 A JP2003283465 A JP 2003283465A JP 4635418 B2 JP4635418 B2 JP 4635418B2
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靖長 小谷
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Description

本発明は、半導体装置の製造方法半導体装置に関し、より詳細には、半導体レーザ素子における電極部分における電極と半導体層及び誘電体膜との密着膜を確保し得る半導体装置の製造方法及び半導体装置に関する。   The present invention relates to a semiconductor device manufacturing method, and more particularly to a semiconductor device manufacturing method and a semiconductor device capable of securing an adhesion film between an electrode, a semiconductor layer, and a dielectric film in an electrode portion of a semiconductor laser element. .

近年、半導体装置、特に半導体レーザ素子は、小型、軽量、高信頼性及び高出力化が進み、パーソナルコンピュータ、DVD等の電子機器や医療機器等の光源に利用されている。なかでも、III−V族窒化物半導体は、比較的短波長の発光が可能であるため、盛んに研究されている。   2. Description of the Related Art In recent years, semiconductor devices, particularly semiconductor laser elements, have become smaller, lighter, more reliable, and have higher output, and are used as light sources for electronic devices such as personal computers and DVDs and medical devices. Among these, group III-V nitride semiconductors are actively studied because they can emit light with a relatively short wavelength.

例えば、窒化物半導体を用いた半導体レーザは、図2に示すように、サファイア基板30上に、中間層31を介して、n型GaN層等からなるn型半導体層32、InGaN多重量子井戸からなる活性層35及び表面にリッジが形成されたp型AlGaN層等からなるp型半導体層36がこの順に積層されて構成されている。n型半導体層32上にはn型オーミック電極33及びn型パッド電極34が形成されている。p型半導体層36上にはリッジ上面以外の表面が絶縁膜38で覆われ、リッジ上面においてp型半導体層36にオーミック接続されたp型オーミック電極39が形成されている。さらに、p型オーミック電極39上の一部の領域を除いて、n型半導体層32、活性層35及びp型半導体層36の表面には、保護膜37が形成されており、保護膜37上に、p型オーミック電極39と電気的に接続されたp型パッド電極40が配置している。   For example, as shown in FIG. 2, a semiconductor laser using a nitride semiconductor includes an n-type semiconductor layer 32 made of an n-type GaN layer and the like on an sapphire substrate 30 via an intermediate layer 31 and an InGaN multiple quantum well. An active layer 35 and a p-type semiconductor layer 36 made of a p-type AlGaN layer having a ridge formed on the surface are laminated in this order. An n-type ohmic electrode 33 and an n-type pad electrode 34 are formed on the n-type semiconductor layer 32. A surface other than the top surface of the ridge is covered with an insulating film 38 on the p-type semiconductor layer 36, and a p-type ohmic electrode 39 is formed in ohmic contact with the p-type semiconductor layer 36 on the top surface of the ridge. Further, a protective film 37 is formed on the surface of the n-type semiconductor layer 32, the active layer 35 and the p-type semiconductor layer 36 except for a part of the region on the p-type ohmic electrode 39. In addition, a p-type pad electrode 40 electrically connected to the p-type ohmic electrode 39 is disposed.

このような半導体レーザでは、特定の電極材料を選択したり(例えば、特許文献1及び2)、p型半導体層の不純物濃度を調整したりして(例えば、特許文献3)、半導体層と電極とのオーミック接続をより低抵抗化して、駆動電圧の低減及び発光効率の向上を図っている。
特開平5−291621号公報 特開平6−275868号公報 特開平10−303504号公報
In such a semiconductor laser, a specific electrode material is selected (for example, Patent Documents 1 and 2), or the impurity concentration of the p-type semiconductor layer is adjusted (for example, Patent Document 3), so that the semiconductor layer and the electrode In order to reduce the driving voltage and improve the light emission efficiency, the ohmic connection with the resistor is further reduced in resistance.
JP-A-5-291621 JP-A-6-275868 JP-A-10-303504

上述したような種々の方法により、半導体層と電極とのオーミック接続を確保したとしても、半導体層と電極とがオーミック接続された領域以外の領域において絶縁膜や保護膜等が介在している場合には、これらの絶縁膜等と電極材料との密着性の悪さに起因して、半導体装置の製造工程で、電極のオーミック接続が損なわれたり、電極自体が剥がれたりするという課題があった。   Even if the ohmic connection between the semiconductor layer and the electrode is secured by various methods as described above, an insulating film, a protective film, or the like is interposed in a region other than the region where the semiconductor layer and the electrode are ohmic-connected. However, due to the poor adhesion between these insulating films and the electrode material, there is a problem that the ohmic connection of the electrode is impaired or the electrode itself is peeled off in the manufacturing process of the semiconductor device.

本発明は、上記課題に鑑みなされたものであり、半導体層と電極とがオーミック接続された領域以外の領域において絶縁膜や保護膜等が介在している場合においても、電極材料との良好な密着性を得ることにより、電極の剥がれ等を防止して、信頼性が高く、低電圧化及び高輝度化を実現することができる半導体装置の製造方法及び半導体装置を提供することを目的とする。   The present invention has been made in view of the above problems, and even when an insulating film, a protective film, or the like is interposed in a region other than the region where the semiconductor layer and the electrode are ohmic-connected, the electrode material is excellent. It is an object of the present invention to provide a method for manufacturing a semiconductor device and a semiconductor device capable of preventing peeling of electrodes and the like by obtaining adhesion, achieving high reliability, and realizing low voltage and high luminance. .

本発明は、  The present invention
表面にリッジを有する半導体層上に、該半導体層の少なくともリッジ上面を露出させるようにZrO  On the semiconductor layer having a ridge on the surface, at least the upper surface of the ridge of the semiconductor layer is exposed. 22 からなる誘電体膜を形成し、A dielectric film made of
該誘電体膜を被覆するようにRh又はHfOからなる密着膜を積層し、  An adhesion film made of Rh or HfO is laminated so as to cover the dielectric film,
該密着膜を熱処理した後、  After heat-treating the adhesion film,
前記リッジ上面と接続され、前記リッジ側面において密着膜を介して配置するニッケル膜又はその合金膜を含む電極を形成する  An electrode including a nickel film or an alloy film thereof connected to the top surface of the ridge and disposed on the side surface of the ridge via an adhesion film is formed.
ことを特徴とする半導体装置の製造方法である。This is a method for manufacturing a semiconductor device.
この方法では、  in this way,
半導体層がp型の窒化物半導体からなることが好ましい。  The semiconductor layer is preferably made of a p-type nitride semiconductor.
熱処理を、酸化雰囲気下にて400℃以上の温度で行うことが好ましい。  The heat treatment is preferably performed at a temperature of 400 ° C. or higher in an oxidizing atmosphere.

また、本発明は、表面にリッジを有する半導体層における少なくともリッジ上面で電気的に接続された電極を有する半導体装置であって、前記半導体層と電極との間の一部の領域において、ZrO  The present invention also provides a semiconductor device having an electrode electrically connected to at least the ridge upper surface in a semiconductor layer having a ridge on the surface, wherein ZrO is formed in a partial region between the semiconductor layer and the electrode. 22 からなる誘電体膜とRh又はHfOからなる密着膜とがこの順に積層され、前記電極はニッケル膜又はその合金膜を含んでおり、前記誘電体膜がリッジ側面において直接接触せず、かつ前記密着膜がリッジ側面においてニッケル膜又はその合金膜と接触するように介在してなることを特徴とする半導体装置である。A dielectric film made of Rh or HfO is laminated in this order, the electrode includes a nickel film or an alloy film thereof, and the dielectric film is not in direct contact with the side surface of the ridge; The semiconductor device is characterized in that the film is interposed on the side surface of the ridge so as to be in contact with the nickel film or an alloy film thereof.
この半導体装置では、半導体層がp型の窒化物半導体からなることが好ましい。  In this semiconductor device, the semiconductor layer is preferably made of a p-type nitride semiconductor.

上記のような構成にすることにより、電極材料の半導体層及び保護膜(誘電体膜)への良好な密着性を得ることができ、電極の剥がれ等を防止して、信頼性が高く、低電圧化及び高輝度化を実現した半導体装置を得ることができる。   With the above configuration, good adhesion to the semiconductor layer and protective film (dielectric film) of the electrode material can be obtained, and peeling of the electrode and the like can be prevented, and the reliability is high and low. A semiconductor device in which voltage and high luminance are realized can be obtained.

本発明の半導体装置の製造方法では、まず、半導体層上に誘電体膜を形成する。   In the method of manufacturing a semiconductor device according to the present invention, first, a dielectric film is formed on the semiconductor layer.

ここで、本発明の半導体装置としては、半導体層をその構成の一部に含む装置の全てを包含する。例えば、発光素子、受光素子、CCD、トランジスタ、キャパシタ、抵抗、サイリスタ、光電変換装置等の変換装置、半導体レーザ及びこれらを2以上組み合わせた回路等が挙げられる。なかでも半導体レーザを構成する半導体層であることが適当である。このような半導体装置を構成する半導体層としては、例えば、シリコン、ゲルマニウム等の元素半導体層、GaAs、AlN、InP、GaN、AlGaN、AlInGaN、InN等のIII−V族化合物半導体層、ZnSe、CdTe、CdS等のII−VI族化合物半導体層等、種々の半導体層が挙げられる。なかでも、窒化物半導体、つまり、GaN、AlN、InN又はこれらの混晶(例えば、InAlGa1−x−yN、0≦x、0≦y、x+y≦1)等が好ましい。半導体層は、p型不純物(例えば、Mg、Zn、Cd、Be、Ca、Ba等)又はn型不純物(例えば、Si、Sn、Ge、Se、C、Ti等)をドープしたものであってもよく、ドーピング濃度は、例えば、1×1016〜1019cm−3程度が挙げられる。特に、p型不純物を含有した窒化物半導体層がより好ましい。これらの半導体層は、MOVPE、MOCVD(有機金属化学気相成長法)、HVPE(ハライド気相成長法)、MBE(分子線気相成長法)等、当該分野で公知の方法のいずれによっても形成することができる。 Here, the semiconductor device of the present invention includes all devices including a semiconductor layer as part of its configuration. For example, a light-emitting element, a light-receiving element, a CCD, a transistor, a capacitor, a resistor, a thyristor, a conversion device such as a photoelectric conversion device, a semiconductor laser, and a circuit combining two or more of these may be used. In particular, the semiconductor layer constituting the semiconductor laser is appropriate. Examples of the semiconductor layer constituting such a semiconductor device include elemental semiconductor layers such as silicon and germanium, III-V group compound semiconductor layers such as GaAs, AlN, InP, GaN, AlGaN, AlInGaN, and InN, ZnSe, and CdTe. And various semiconductor layers such as II-VI compound semiconductor layers such as CdS. Among these, nitride semiconductors, that is, GaN, AlN, InN, or mixed crystals thereof (for example, In x Al y Ga 1-xy N, 0 ≦ x, 0 ≦ y, x + y ≦ 1) and the like are preferable. The semiconductor layer is doped with p-type impurities (for example, Mg, Zn, Cd, Be, Ca, Ba, etc.) or n-type impurities (for example, Si, Sn, Ge, Se, C, Ti, etc.). The doping concentration is, for example, about 1 × 10 16 to 10 19 cm −3 . In particular, a nitride semiconductor layer containing a p-type impurity is more preferable. These semiconductor layers are formed by any method known in the art, such as MOVPE, MOCVD (metal organic chemical vapor deposition), HVPE (halide vapor deposition), MBE (molecular beam vapor deposition). can do.

誘電体膜としては、例えば、SiO、SiN、AlN、Al、Ta、ZrO、SiON、HfO、Sc、Y、MgO等の単層又は積層層が挙げられる。なかでも、ZrOが好ましい。これらの誘電体膜は、例えば、スパッタリング法、ECRスパッタリング法、CVD法、ECR−CVD法、ECR−プラズマCVD法、蒸着法、EB法等の公知の方法で形成することができる。誘電体膜の膜厚は、用いる材料等により適宜調整することができ、例えば、400〜2500オングストローム程度、好ましくは400〜1000オングストローム程度が挙げられる。 As the dielectric film, for example, a single layer such as SiO 2 , SiN x , AlN, Al 2 O 3 , Ta 2 O 5 , ZrO 2 , SiON, HfO 2 , Sc 2 O 3 , Y 2 O 3 , MgO or the like A laminated layer is mentioned. Of these, ZrO 2 is preferable. These dielectric films can be formed by known methods such as sputtering, ECR sputtering, CVD, ECR-CVD, ECR-plasma CVD, vapor deposition, and EB. The film thickness of the dielectric film can be appropriately adjusted depending on the material used and the like, for example, about 400 to 2500 angstroms, preferably about 400 to 1000 angstroms.

半導体層上に、この半導体層上の一部の領域を露出させるように誘電体膜を形成するのは、後述するように、半導体層上に電極を接続させる領域を確保するとともに、誘電体膜によって電極との接続領域以外の半導体層表面を絶縁、保護等するためである。一部の領域を露出させるように誘電体膜を形成する方法としては、半導体層上全面に、誘電体膜を積層した後、当該分野で公知の方法、例えば、フォトリソグラフィ及びエッチング工程により所望の形状のマスクを形成し、このマスクを用いて誘電体膜をエッチングする方法が挙げられる。あるいは、リフトオフ法等を利用してもよい。   The dielectric film is formed on the semiconductor layer so as to expose a part of the region on the semiconductor layer. As will be described later, the dielectric film is secured on the semiconductor layer and a region for connecting electrodes is secured. This is to insulate and protect the surface of the semiconductor layer other than the connection region with the electrode. As a method of forming a dielectric film so as to expose a part of the region, after a dielectric film is laminated on the entire surface of the semiconductor layer, a desired method is used by a method known in the art, for example, photolithography and etching processes. There is a method of forming a mask having a shape and etching the dielectric film using the mask. Alternatively, a lift-off method or the like may be used.

次いで、誘電体膜上に密着膜を積層する。密着膜としては、例えば、白金族系金属等の単層又は積層層が挙げられる。白金族系金属としては、長周期律表及び短周期律表のいずれかにおけるVIII族の金属、例えば、Rh、Ru、Pd、Pt、Os、Ir、Hf等が挙げられる。なかでも、Rhを含有する単層膜又は後述する電極側にRhを含有する層が配置する積層膜が好ましい。   Next, an adhesion film is laminated on the dielectric film. Examples of the adhesion film include a single layer or a laminated layer of a platinum group metal or the like. Examples of the platinum group metal include group VIII metals in either the long periodic table or the short periodic table, such as Rh, Ru, Pd, Pt, Os, Ir, and Hf. Among these, a single layer film containing Rh or a laminated film in which a layer containing Rh is disposed on the electrode side described later is preferable.

なお、誘電体膜を被覆するように密着膜を形成するとは、少なくとも後述する電極が誘電体膜とは直接接触することなく、密着膜にのみ接触するように、密着膜を形成することを意味する。したがって、密着膜は、誘電体膜上の一部のみに形成されていてもよいし、誘電体膜上の全部に、つまり誘電体膜と同じ大きさ及び形状で形成されていてもよいし、誘電体膜の一部の上から半導体層上の一部の上にわたって形成されていてもよいし、誘電体膜よりも大きく、半導体層と直接接触し、誘電体膜の一部又は全部の上にわたって形成されていてもよい。   Note that forming an adhesion film so as to cover the dielectric film means that the adhesion film is formed so that at least an electrode described later is in direct contact with the adhesion film without being in direct contact with the dielectric film. To do. Therefore, the adhesion film may be formed only on a part of the dielectric film, or may be formed all over the dielectric film, that is, with the same size and shape as the dielectric film, It may be formed over a part of the dielectric film to a part of the semiconductor layer, or larger than the dielectric film and in direct contact with the semiconductor layer, over a part or all of the dielectric film. It may be formed over.

密着膜は、上述した誘電体膜と同様に、当該分野で公知の方法によって形成することができ、所定の形状にパターニングする場合には、上述したように、フォトリソグラフィ及びエッチング法、リフトオフ法等を利用することができる。パターニングは密着膜の形状によっては、上述した誘電体膜と同時に行ってもよい。密着膜の膜厚は、用いる材料等により適宜調整することができ、例えば、50〜500オングストローム程度、好ましくは100〜300オングストローム程度が挙げられる。   The adhesion film can be formed by a method known in the art, similarly to the dielectric film described above. When patterning into a predetermined shape, as described above, photolithography and etching methods, lift-off methods, etc. Can be used. Patterning may be performed simultaneously with the above-described dielectric film depending on the shape of the adhesion film. The film thickness of the adhesion film can be appropriately adjusted depending on the material used and the like, for example, about 50 to 500 angstroms, preferably about 100 to 300 angstroms.

次いで、密着膜を熱処理する。ここでの熱処理は、密着膜が形成された半導体層を、例えば、400℃以上の温度、好ましくは500〜700℃程度の温度で、1〜30分間、好ましくは5〜20分間程度加熱することにより行うことができる。熱処理は、電気炉を利用したファーネスアニール法によって行ってもよいし、ハロゲンランプ、電子ビーム、エキシマレーザ等を利用したRTA法によって行ってもよい。熱処理は、大気雰囲気下又は酸素雰囲気下で行うことが好ましい。このような熱処理によって、密着膜の表面から密着膜の内部に酸素が取り込まれることにより、後述する電極との密着性を向上させることができる。   Next, the adhesion film is heat-treated. In this heat treatment, the semiconductor layer on which the adhesion film is formed is heated, for example, at a temperature of 400 ° C. or higher, preferably about 500 to 700 ° C. for 1 to 30 minutes, preferably about 5 to 20 minutes. Can be performed. The heat treatment may be performed by a furnace annealing method using an electric furnace or an RTA method using a halogen lamp, an electron beam, an excimer laser, or the like. The heat treatment is preferably performed in an air atmosphere or an oxygen atmosphere. By such heat treatment, oxygen is taken into the inside of the adhesion film from the surface of the adhesion film, whereby adhesion with an electrode described later can be improved.

続いて、半導体層上及び密着膜上に電極を形成する。電極は、例えば、パラジウム、白金、ニッケル、金、チタン、タングステン、銅、銀、亜鉛、錫、インジウム、アルミニウム等の金属又は合金の単層膜又は積層膜により形成することができる。なかでも、ニッケル又はその合金を含む単層膜、あるいは密着膜と接触する側においてニッケル又はその合金を含む層が配置された積層膜であることが好ましい。電極の膜厚は、用いる材料等により適宜調整することができ、例えば、500〜1500オングストローム程度が適当である。電極材料は、例えば、誘電体膜と同様に、当該分野で公知の方法等により形成することができる。電極材料は、半導体層上のほぼ全面に形成した後、フォトリソグラフィ及びエッチング工程、リフトオフ法、EB法等によりパターニングする。なお、電極は、少なくとも半導体層上にのみ形成していればよいが、半導体層の一部とオーミック接続するとともに、密着膜上において密着膜と強固に密着した状態で配置させることが好ましい。また、この際、電極が誘電体膜と直接接触しないように形成することが重要である。
以下に本発明の半導体装置の製造方法及び半導体装置の実施例を詳細に説明する。
Subsequently, an electrode is formed on the semiconductor layer and the adhesion film. The electrode can be formed of, for example, a single layer film or a multilayer film of a metal or an alloy such as palladium, platinum, nickel, gold, titanium, tungsten, copper, silver, zinc, tin, indium, and aluminum. Among these, a single layer film containing nickel or an alloy thereof or a laminated film in which a layer containing nickel or an alloy thereof is arranged on the side in contact with the adhesion film is preferable. The film thickness of the electrode can be appropriately adjusted depending on the material used, and for example, about 500 to 1500 angstroms is appropriate. The electrode material can be formed, for example, by a method known in the art as in the case of the dielectric film. The electrode material is formed on almost the entire surface of the semiconductor layer, and then patterned by photolithography and etching processes, a lift-off method, an EB method, and the like. Note that the electrode only needs to be formed at least on the semiconductor layer, but it is preferable that the electrode be in ohmic contact with a part of the semiconductor layer and disposed in a state of being in close contact with the adhesion film on the adhesion film. At this time, it is important that the electrode is formed so as not to be in direct contact with the dielectric film.
Embodiments of a semiconductor device manufacturing method and a semiconductor device according to the present invention will be described in detail below.

まず、半導体装置として図1に示す半導体レーザを製造するために、直径2インチ、C面を主面とするサファイア基板10上に、GaNからなるバッファ層及びアンドープGaNからなる窒化物半導体層を成長させることにより、下地層11を形成する。
次に、下地層の上に、Siを1×1018/cmドープさせたGaNからなるn型コンタクト層、In0.06Ga0.94Nからなるクラック防止層、アンドープのAlGaNからなるA層とSiを5×1018/cmドープしたGaNからなるB層とを交互積層させたn型クラッド層、n型光ガイド層を成長させる。これにより、n型半導体層12を形成する。
First, in order to manufacture the semiconductor laser shown in FIG. 1 as a semiconductor device, a buffer layer made of GaN and a nitride semiconductor layer made of undoped GaN are grown on a sapphire substrate 10 having a diameter of 2 inches and a C plane as a main surface. By doing so, the underlayer 11 is formed.
Next, an n-type contact layer made of GaN doped with Si of 1 × 10 18 / cm 3 , a crack prevention layer made of In 0.06 Ga 0.94 N, and an A made of undoped AlGaN on the underlayer. An n-type cladding layer and an n-type light guide layer are grown by alternately laminating layers and B layers made of GaN doped with Si at 5 × 10 18 / cm 3 . Thereby, the n-type semiconductor layer 12 is formed.

続いて、Siを5×1018/cmドープしたIn0.05Ga0.95Nからなる障壁層とアンドープIn0.1Ga0.9Nからなる井戸層とを交互3回積層させ、その上に障壁層を積層させた多重量子井戸構造(MQW)の活性層15を成長させる。
次いで、Mgを1×1019/cmドープしたAlGaNからなるp型電子閉じ込め層、アンドープのGaNからなるp型光ガイド層、アンドープAl0.16Ga0.84Nからなる層とMgドープGaNからなる層とを交互積層させた超格子層からなるp型クラッド層、Mgを1×1020/cmドープしたp型GaNからなるp型コンタクト層を成長させる。これによりp型半導体層16を形成する。その後、窒素雰囲気中でウェハを700℃でアニーリングして、p型半導体層16をさらに低抵抗化する。
Subsequently, a barrier layer made of In 0.05 Ga 0.95 N doped with Si 5 × 10 18 / cm 3 and a well layer made of undoped In 0.1 Ga 0.9 N were alternately stacked three times. An active layer 15 having a multiple quantum well structure (MQW) in which a barrier layer is stacked thereon is grown.
Next, a p-type electron confinement layer made of AlGaN doped with 1 × 10 19 / cm 3 of Mg, a p-type light guide layer made of undoped GaN, a layer made of undoped Al 0.16 Ga 0.84 N, and Mg-doped GaN Then, a p-type cladding layer made of a superlattice layer in which layers made of these are alternately stacked, and a p-type contact layer made of p-type GaN doped with Mg at 1 × 10 20 / cm 3 are grown. Thereby, the p-type semiconductor layer 16 is formed. Thereafter, the wafer is annealed at 700 ° C. in a nitrogen atmosphere to further reduce the resistance of the p-type semiconductor layer 16.

このようにして窒化物半導体を積層した後、所望の形状のマスクを用いて、p型半導体層、活性層、n型半導体層の一部を順次エッチングし、n電極を形成するn型コンタクト層の表面を露出させる。
その後、最上層のp型コンタクト層上に、所定形状のマスクを形成し、このマスクを用いて、p型コンタクト層にストライプ状のリッジを形成する。
After stacking the nitride semiconductors in this manner, a p-type semiconductor layer, an active layer, and a part of the n-type semiconductor layer are sequentially etched using a mask having a desired shape to form an n-type contact layer. To expose the surface.
Thereafter, a mask having a predetermined shape is formed on the uppermost p-type contact layer, and a striped ridge is formed on the p-type contact layer using this mask.

続いて、p型層表面に、ECRスパッタリング法によって、誘電体膜18としてZrO膜を、膜厚600オングストローム程度形成する。この上に、スパッタ装置を用いて、密着膜21としてRh膜を、膜厚100オングストローム程度形成し、酸素雰囲気下、600℃にて10分間程度アニール処理を行う。
その後、BHF液に20分間浸漬して、水洗、超音波洗浄及びリンスを行い、ストライプ状のリッジの上面に形成した誘電体膜18及び密着膜21を溶解除去する。
Subsequently, a ZrO 2 film is formed on the p-type layer surface as a dielectric film 18 to a thickness of about 600 Å by ECR sputtering. On top of this, an Rh film is formed as the adhesion film 21 to a thickness of about 100 angstrom using a sputtering apparatus, and an annealing process is performed at 600 ° C. for about 10 minutes in an oxygen atmosphere.
Thereafter, it is immersed in a BHF solution for 20 minutes, followed by washing with water, ultrasonic washing and rinsing to dissolve and remove the dielectric film 18 and the adhesion film 21 formed on the upper surface of the striped ridge.

次に、p型コンタクト層上のリッジ上及びn型コンタクト層上に、スパッタ法によってNi−Auからなるp型オーミック電極19及びTi−Alからなるn型オーミック電極13を形成する。   Next, the p-type ohmic electrode 19 made of Ni—Au and the n-type ohmic electrode 13 made of Ti—Al are formed on the ridge and the n-type contact layer on the p-type contact layer by sputtering.

その後、150℃にて約10分間アッシャーし、さらにアニール処理を行う。次いで、p型オーミック電極19とn型オーミック電極13との一部を被覆する保護膜17を、SiOにより形成し、p型オーミック電極19及びn型オーミック電極13に接続されるように、Ni−Ti−Auからなるp型パッド電極20及びn型パッド電極14を形成する。
その後、150℃にて約10分間アッシャーを行う。
Thereafter, asher is performed at 150 ° C. for about 10 minutes, and an annealing process is further performed. Next, a protective film 17 covering a part of the p-type ohmic electrode 19 and the n-type ohmic electrode 13 is formed of SiO 2 , and Ni is connected to the p-type ohmic electrode 19 and the n-type ohmic electrode 13. A p-type pad electrode 20 and an n-type pad electrode 14 made of -Ti-Au are formed.
Thereafter, asher is performed at 150 ° C. for about 10 minutes.

このようにして得られた半導体装置において、半導体層と密着膜との上に形成されたp型オーミック電極の密着性を評価した。   In the semiconductor device thus obtained, the adhesion of the p-type ohmic electrode formed on the semiconductor layer and the adhesion film was evaluated.

まず、得られた半導体装置を、超音波での30分間の処理に2回付した後、超音波で30分間処理し、180℃で30分間熱処理し、さらに冷水に浸漬し、この処理を3回行った。その後、超音波で60分間処理し、220〜300℃で30分間熱処理し、さらに冷水に浸漬し、この処理を8回行い、最後に超音波で60分間処理した。このような一連の超音波処理及び熱衝撃試験によっても、p型オーミック電極の剥がれは見られず、その後の製造プロセスにも十分に耐えることができる密着性が確保されることが確認された。   First, the obtained semiconductor device was subjected to ultrasonic treatment for 30 minutes twice, then treated with ultrasonic waves for 30 minutes, heat-treated at 180 ° C. for 30 minutes, and further immersed in cold water. I went twice. Then, it processed for 60 minutes with ultrasonic waves, heat-processed for 30 minutes at 220-300 degreeC, and also immersed in cold water, this process was performed 8 times, and finally, it processed with ultrasonic waves for 60 minutes. Even by such a series of ultrasonic treatment and thermal shock test, it was confirmed that no peeling of the p-type ohmic electrode was observed, and adhesion capable of sufficiently withstanding the subsequent manufacturing process was secured.

また、上述した実施例において、密着膜としてRh膜を形成する代わりにHfO膜を形成した以外、同様に作成した半導体装置についても超音波処理を行った。つまり、超音波での30分間の処理に2回付した後、超音波で30分間処理し、180℃で30分間熱処理し、さらに冷水に浸漬し、この処理を2回行った。その結果、このような一連の超音波処理及び熱衝撃試験においても、p型オーミック電極の剥がれは見られず、通常の半導体装置の製造プロセスに十分耐えることができる密着性の良好な電極が得られることが確認された。   Further, in the above-described example, ultrasonic treatment was also performed on a semiconductor device similarly manufactured except that an HfO film was formed instead of an Rh film as an adhesion film. That is, after 30 times of treatment with ultrasonic waves twice, treatment with ultrasonic waves for 30 minutes, heat treatment at 180 ° C. for 30 minutes, and further immersed in cold water, this treatment was performed twice. As a result, even in such a series of ultrasonic treatment and thermal shock test, the p-type ohmic electrode is not peeled off, and an electrode having good adhesion that can sufficiently withstand the manufacturing process of a normal semiconductor device is obtained. It was confirmed that

一方、比較のため、上述した実施例において、密着膜としてRh膜を形成した代わりにZr膜を形成した以外、同様に作成した半導体装置についても超音波処理及び熱衝撃試験を行った。その結果、最初の30分間の超音波処理及び熱衝撃試験で、p型オーミック電極が剥がれることが確認された。   On the other hand, for comparison, ultrasonic treatment and thermal shock tests were performed on the semiconductor devices similarly manufactured except that a Zr film was formed instead of an Rh film as an adhesion film in the above-described example. As a result, it was confirmed that the p-type ohmic electrode peeled off in the first 30 minutes of ultrasonic treatment and thermal shock test.

本発明は、半導体層をその構成の一部に含む装置、例えば、発光素子、受光素子、CCD、トランジスタ、キャパシタ、抵抗、サイリスタ、光電変換装置等の変換装置、半導体レーザ及びこれらを2以上組み合わせた回路等の全てに対して適用することができる。   The present invention provides a device including a semiconductor layer as a part of its structure, for example, a light emitting element, a light receiving element, a CCD, a transistor, a capacitor, a resistor, a thyristor, a photoelectric conversion device or other conversion device, a semiconductor laser, and a combination of two or more thereof It can be applied to all of the circuits.

本発明の半導体装置の一実施形態を示す概略断面図である。It is a schematic sectional drawing which shows one Embodiment of the semiconductor device of this invention. 従来の半導体装置である半導体レーザを示す概略断面図である。It is a schematic sectional drawing which shows the semiconductor laser which is the conventional semiconductor device.

符号の説明Explanation of symbols

10 サファイア基板
11 下地層
12 n型半導体層
13 n型オーミック電極
14 n型パッド電極
15 活性層
16 p型半導体層(半導体層)
17 保護膜
18 誘電体膜
19 p型オーミック電極(電極)
20 p型パッド電極
21 密着膜
DESCRIPTION OF SYMBOLS 10 Sapphire substrate 11 Underlayer 12 N-type semiconductor layer 13 n-type ohmic electrode 14 n-type pad electrode 15 Active layer 16 p-type semiconductor layer (semiconductor layer)
17 Protective film 18 Dielectric film 19 P-type ohmic electrode (electrode)
20 p-type pad electrode 21 adhesion film

Claims (5)

表面にリッジを有する半導体層上に、該半導体層の少なくともリッジ上面を露出させるようにZrO 2 からなる誘電体膜を形成し、
該誘電体膜を被覆するようにRh又はHfOからなる密着膜を積層し、
該密着膜を熱処理した後、
前記リッジ上面と接続され、前記リッジ側面において密着膜を介して配置するニッケル膜又はその合金膜を含む電極を形成する
ことを特徴とする半導体装置の製造方法。
A semiconductor layer having a ridge on the surface, forming a dielectric film made of ZrO 2 so as to expose at least the ridge top surface of the semiconductor layer,
An adhesion film made of Rh or HfO is laminated so as to cover the dielectric film,
After heat-treating the adhesion film,
A method of manufacturing a semiconductor device, comprising forming an electrode including a nickel film or an alloy film thereof connected to an upper surface of the ridge and disposed on the side surface of the ridge via an adhesion film.
半導体層がp型の窒化物半導体からなる請求項1に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer is made of a p-type nitride semiconductor. 熱処理を、酸化雰囲気下にて400℃以上の温度で行う請求項1又は2に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed at a temperature of 400 ° C. or higher in an oxidizing atmosphere. 表面にリッジを有する半導体層における少なくともリッジ上面で電気的に接続された電極を有する半導体装置であって、前記半導体層と電極との間の一部の領域において、ZrO 2 からなる誘電体膜とRh又はHfOからなる密着膜とがこの順に積層され、前記電極はニッケル膜又はその合金膜を含んでおり、前記誘電体膜がリッジ側面において直接接触せず、かつ前記密着膜がリッジ側面においてニッケル膜又はその合金膜と接触するように介在してなることを特徴とする半導体装置。 A semiconductor device having an electrode electrically connected to at least an upper surface of a ridge in a semiconductor layer having a ridge on the surface, wherein a dielectric film made of ZrO 2 is formed in a partial region between the semiconductor layer and the electrode; An adhesion film made of Rh or HfO is laminated in this order, the electrode includes a nickel film or an alloy film thereof, the dielectric film is not in direct contact with the ridge side surface , and the adhesion film is nickel on the ridge side surface. A semiconductor device comprising a film or an alloy film thereof in contact with the film . 半導体層がp型の窒化物半導体からなる請求項4に記載の半導体装置。   The semiconductor device according to claim 4, wherein the semiconductor layer is made of a p-type nitride semiconductor.
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