JP4608999B2 - Electronic circuit driving method, electronic circuit, electronic device, electro-optical device, electronic apparatus, and electronic device driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve flexibility in the operation design by conducting Vth compensation and reverse bias application in a single operating process. <P>SOLUTION: By connecting the gate of a driving transistor T3 and one of its own terminals and applying a non-forward bias to the driving transistor T3, the voltage of a node N1 connected to the gate of the driving transistor T3 is set to an offset level corresponding to the Vth of the driving transistor. Then, by applying a data voltage Vdata to a data line X which is coupled in capacitance to the node N1, data writing is conducted to capacitors C1 and C2 connected to the node N1 using the offset level as a reference. Then, by applying a forward bias to the driving transistor T3, a driving current Ioled is generated, and luminance of an organic EL element OLED is set by the driving current. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

  The present invention relates to an electronic circuit driving method suitable for driving a driven element such as an electro-optical element, an electronic circuit, an electro-optical device, an electronic device, an electronic device driving method, and an electronic apparatus.

  In recent years, a display using an organic EL (Electronic Luminescence) element has attracted attention. The organic EL element is one of current-driven elements whose luminance is set according to the drive current flowing through the organic EL element. In the case of active matrix driving, in order to obtain luminance accurately, it is necessary to compensate for variations in the characteristics of transistors constituting the pixel circuit. As a method for compensating the characteristic variation, driving methods such as a voltage programming method and a current programming method have been proposed.

  An example of a prior application for Vth compensation is Japanese Patent Application No. 2002-255251 already filed by the present applicant.

  One object of the present invention is to provide a novel electronic circuit or the like that compensates for variations in transistor characteristics.

  Another object of the present invention is to improve flexibility in operation design by performing Vth compensation and reverse bias application in one operation process in such an electronic circuit or the like.

  In order to solve such a problem, a first electronic circuit driving method of the present invention is arranged between a first terminal, a second terminal, and the first terminal and the second terminal. The first terminal so that the first terminal functions as the drain of the driving transistor in a state where the gate of the driving transistor having the channel region is electrically connected to the first terminal. A first step for generating a potential difference with the second terminal; and a driving voltage and a driving current corresponding to a conduction state of the driving transistor set by supplying a data signal to the gate of the driving transistor. And a second step of supplying at least one of the second element to the driven element so that the second terminal functions as a drain of the driving transistor.

  In the driving method of the electronic circuit, the relative potential relationship between the first terminal and the second terminal varies depending on a step or the like, which causes the driving transistor to have a forward bias and a reverse bias ( Alternatively, non-forward bias) is applied, and the change and deterioration of the characteristics of the driving transistor can be suppressed.

  Here, the “drain” is defined by a potential relationship relative to the conductivity type of the transistor. For example, when the transistor is n-type, the high-potential side terminal is the “drain” of the two terminals arranged with the channel region in between. When the transistor is p-type, the transistor is arranged with the channel region in between. Of the two terminals, the terminal on the low potential side is defined as “drain”.

  In the electronic circuit driving method, an initialization current is caused to flow between the first terminal and the second terminal in response to the first step, and the gate voltage of the driving transistor is set to the driving transistor. An offset level corresponding to the threshold value may be set.

  Here, “as an opportunity” means that the first step is performed as an initial operation, and the offset level setting process is performed after performing the first step or after performing the first step. You may go while you go.

  In the electronic circuit driving method, the electronic circuit includes a capacitor having a first electrode and a second electrode, and a capacitor formed between the first electrode and the second electrode. The gate is connected to the first electrode, and after performing the first step, the gate is in a floating state, and the data signal is supplied to the gate by capacitive coupling through the capacitor; The conduction state may be set.

  In the electronic circuit driving method, it is preferable that the first terminal and the gate of the driving transistor are disconnected from each other in at least a part of the period in which the second step is performed.

  Here, “disconnecting electrical connection” means that the first terminal and the gate are not in a conductive state, and a capacitor or the like is interposed between the first terminal and the gate. It may be.

  In the electronic circuit driving method, the driven element includes an operating electrode connected to the first terminal, a counter electrode, and a functional layer disposed between the operating electrode and the counter electrode. And during the first step and the second step, at least the voltage of the counter electrode may be fixed to a predetermined voltage level.

  In the electronic circuit driving method described above, the voltage level of the second terminal may be set lower than the predetermined voltage level in at least one period during which the first step is performed. Thereby, for example, a non-forward bias can be applied to the driving transistor or the driven element.

  The electronic circuit driving method may further include a third step of setting the voltage level of the first terminal to a voltage level lower than the predetermined voltage level, and the period during which the third step is performed. The voltage of the counter electrode may be fixed at the predetermined voltage level. Thereby, for example, a non-forward bias can be applied to the driven element.

  In the driving method of the second electronic circuit of the present invention, the electronic circuit includes a first terminal, a second terminal, and a channel region disposed between the first terminal and the second terminal. A driving transistor having: a third terminal; a fourth terminal; a channel region disposed between the third terminal and the fourth terminal; A compensation transistor connected to the third terminal, and a potential difference is provided between the third terminal and the fourth terminal so that the third terminal functions as a drain of the compensation transistor. At least one of a first step to be generated and a driving voltage and a driving current corresponding to a conduction state of the driving transistor set by supplying a data signal to the gate of the driving transistor; Drive element And supplying a voltage level of the fourth terminal in the period during which the first step is being performed in at least a part of the period during which the second step is being performed. The voltage level is different from the voltage level of the fourth terminal.

  In the electronic circuit driving method described above, with the first step as an opportunity, an initialization current is passed between the third terminal and the fourth terminal, and the gate of the driving transistor is connected to the compensation transistor. You may make it set to the offset level according to a threshold value.

  Here, “as an opportunity” means that the first step is performed as an initial operation, and the offset level setting process is performed after performing the first step or after performing the first step. You may go while you go.

  In the electronic circuit driving method, the electrical connection between the third terminal and the fourth terminal is substantially disconnected during at least a part of the period during which the second step is performed. Is preferred. Thereby, for example, the gate of the driving transistor can be floated, and the gate voltage of the gate can be maintained at a voltage level corresponding to the data signal.

  In the electronic circuit driving method, the voltage level of the first terminal is set higher than the voltage level of the second terminal in at least a part of the period during which the first step is performed, It is preferable that the voltage level of the second terminal is set higher than the voltage level of the first terminal in at least a part of the period in which the second step is performed.

  In the electronic circuit driving method, the driven element includes an operating electrode connected to the first terminal, a counter electrode, and a functional layer disposed between the operating electrode and the counter electrode. The voltage level of the counter electrode may be fixed to a predetermined level at least during the period in which the first step and the second step are performed.

  In the electronic circuit driving method described above, it is preferable that the voltage level of the second terminal is set lower than the predetermined voltage level in at least one part period in which the first step is performed.

  The electronic circuit driving method may further include a third step of setting the voltage level of the first terminal to a voltage level lower than the predetermined voltage level, and the period during which the third step is performed. The voltage of the counter electrode is preferably fixed at the predetermined voltage level.

  In the driving method for the electronic circuit, the voltage level of the fourth terminal may be set to the same voltage level as that of the second terminal through the first step and the second step. .

  A first electronic circuit according to the present invention is an electronic circuit for driving a driven element, and includes a first terminal and a second terminal, and the first terminal and the second terminal A first capacitor having a drive transistor having a channel region therebetween, a first electrode and a second electrode, and a capacitor formed between the first electrode and the second electrode; A first transistor disposed between the first terminal and the gate of the driving transistor and controlling an electrical connection between the first terminal and the gate; and the first electrode Is connected to the gate, and the second electrode is connected to the first terminal.

  The electronic circuit further includes a third capacitor and a fourth electrode, and a second capacitor in which a capacitance is formed between the third electrode and the fourth electrode; A second transistor comprising: a terminal terminal; a fourth terminal; and a channel region disposed between the third terminal and the fourth terminal, and the gate of the driving transistor. May be connected to the third electrode, and the fourth electrode may be connected to the third terminal.

  In the above electronic circuit, in at least a part of a first period in which the first terminal and the gate of the driving transistor are electrically connected to each other through the first transistor, A voltage level of at least one of the first terminal and the second terminal is set so that the first terminal functions as a drain of the driving transistor, and the first terminal, the gate of the driving transistor, The first terminal and the second terminal so that the second terminal functions as a drain of the driving transistor in at least a part of the second period in which is electrically disconnected At least one of the voltage levels may be set.

  A second electronic circuit according to the present invention is an electronic circuit for driving a driven element, and includes a first terminal and a second terminal, and the first terminal and the second terminal A drive transistor having a channel region therebetween, and a first transistor disposed between the first terminal and the gate of the drive transistor and controlling an electrical connection between the first terminal and the gate And at least a part of the first period in which the first terminal and the gate of the driving transistor are electrically connected via the first transistor. However, the voltage level of at least one of the first terminal and the second terminal is set so as to function as the drain of the driving transistor, and the first terminal and the gate of the driving transistor are connected to each other. In at least a part of the second period that is in an electrically disconnected state, the second terminal functions as the drain of the driving transistor so that the second terminal functions as the drain of the driving transistor. At least one of the voltage levels is set.

  In the above electronic circuit, with the first period as an opportunity, the voltage level of the gate of the driving transistor is set to an offset level corresponding to the threshold voltage of the driving transistor, and at least a part of the second period is set. In the period, a driving voltage or a driving current corresponding to the conduction state of the driving transistor may be supplied to the driven element.

  Here, the process of setting the offset level may be performed after the elapse of the first period or during the first period.

  A third electronic circuit of the present invention is an electronic circuit for driving a driven element, and includes a first terminal and a second terminal, wherein the first terminal and the second terminal A driving transistor having a channel region in between, a third terminal, a fourth terminal, and a channel region disposed between the third terminal and the fourth terminal; A compensation transistor in which a terminal of the first transistor and a gate of the compensation transistor are connected to each other, and one of the third terminal and the fourth terminal is connected to the gate of the driving transistor, and the third terminal The voltage of the fourth terminal can be set to a plurality of voltage levels.

  In the above electronic circuit, in the first period, the voltage level of at least one of the third terminal and the fourth terminal is set so that the third terminal becomes the drain of the compensation transistor, In the second period, the voltage level of at least one of the third terminal and the fourth terminal is set so that the third terminal and the fourth terminal are electrically disconnected, In at least a part of the second period, a driving voltage or a driving current corresponding to a conduction state of the driving transistor set when the data signal is supplied is supplied to the driven element, and the first element The voltage level of the fourth terminal in the period and the voltage level of the fourth terminal in the second period may be different from each other.

  In the above electronic circuit, the electronic circuit further includes a first electrode and a second electrode, and includes a capacitor in which a capacitance is formed between the first electrode and the second electrode. The first electrode is connected to the gate of the driving transistor, and an initialization current flows between the third terminal and the fourth terminal of the compensation transistor in response to the first period. Thus, after the voltage level of the gate of the drive transistor is set to an offset level corresponding to the threshold voltage of the compensation transistor, a data voltage corresponding to the data signal is applied to the second electrode. The gate of the driving transistor is set to a voltage level corresponding to the offset level and the data voltage by capacitive coupling through the capacitor caused by It is preferable that the conduction state is set.

  In the electronic circuit, the voltage level of any one of the fourth terminal and the third terminal is the same voltage level as that of the second terminal throughout the first period and the second period. It is preferable to set to.

  An electronic apparatus according to the present invention includes a plurality of the electronic circuits described above and the driven element provided for each of the plurality of electronic circuits.

  The first electro-optical device of the present invention corresponds to a plurality of data lines, a plurality of scanning lines, a plurality of first power supply lines, and intersections of the plurality of data lines and the plurality of scanning lines. And each of the plurality of pixel circuits includes an electro-optic element, a first terminal, and a second terminal, wherein the first terminal and the second terminal A driving transistor having a channel region therebetween, and a first switching circuit disposed between the first terminal and the gate of the driving transistor to control an electrical connection between the first terminal and the gate A conduction state of the drive transistor is set according to a data signal supplied via one data line of the plurality of data lines, and a drive voltage or a voltage corresponding to the conduction state of the drive transistor The drive current is The first terminal is drained during at least a part of a period in which the first terminal and the gate of the driving transistor are electrically connected via the first switching transistor. So that the voltage level of at least one of the first terminal and the second terminal is set, and at least one of the periods when the driving voltage or the driving current is supplied to the electro-optic element. In the period of the portion, the voltage level of at least one of the first terminal and the second terminal is set so that the second terminal functions as a drain.

  In the electro-optical device, each of the plurality of pixel circuits further includes a first electrode and a second electrode, and a capacitor is formed between the first electrode and the second electrode. A first capacitor, and a second switching transistor that controls electrical connection between the one data line and the second electrode, and the gate of the driving transistor is the first electrode. And an initialization current flows between the first terminal and the second terminal in at least a part of a period in which the first terminal functions as a drain of the driving transistor, and the driving The gate of the transistor is set to an offset level corresponding to the driving transistor threshold value, and after the offset level is set, the second switching transistor is turned on. By capacitive coupling through the first capacitor of the supplied the data signal, the gate voltage of the driving transistor may be set so the voltage level corresponding to the offset level and the data signal.

  In the electro-optical device, each of the plurality of pixel circuits further includes a third electrode and a fourth electrode, and a capacitor is formed between the third electrode and the fourth electrode. A second capacitor, wherein the third electrode is connected to the gate of the driving transistor, and the fourth electrode is connected to the first terminal. Thereby, for example, the voltage level of the gate of the driving transistor can be automatically adjusted with respect to the fluctuation of the voltage level of the first terminal by capacitive coupling via the second capacitor.

  In the electro-optical device, it is preferable that the second terminal is connected to one power supply line of the plurality of power supply lines, and the one power supply line can be set to a plurality of voltage levels.

  The second electro-optical device of the present invention corresponds to a plurality of data lines, a plurality of scanning lines, a plurality of power supply lines, and intersections of the plurality of data lines and the plurality of scanning lines. Each of the plurality of pixel circuits provided and each of the plurality of pixel circuits includes an electro-optical element, a first terminal, and a second terminal, and is provided between the first terminal and the second terminal. A drive transistor having a channel region, a third terminal, a fourth terminal, and a channel region disposed between the third terminal and the fourth terminal, and A compensation transistor having a terminal and its gate connected to each other, and a conduction state of the driving transistor is set according to a data signal supplied through one data line of the plurality of data lines, Either one of the third terminal and the fourth terminal is the A drive voltage or a drive current corresponding to the conduction state of the drive transistor is supplied to the electro-optic element, and the voltage of the one power line is a plurality of voltages. It can be set to a level.

  In the electro-optical device, a voltage level of the one power supply line is set to a first voltage level in at least a part of a period in which the third terminal functions as a drain of the compensation transistor, During at least a part of the period in which the drive voltage or the drive current is supplied to the electro-optic element, the voltage level of the one power supply line is set to the second voltage level, and the first voltage level and the first voltage level are set. The two voltage levels may be different from each other.

  In the electro-optical device, the voltage level of the gate of the driving transistor depends on a threshold voltage of the compensation transistor during at least a part of the period in which the third terminal functions as the drain of the compensation transistor. Alternatively, the offset level may be set.

  In the electro-optical device, the fourth terminal may be connected to the one power line, and the first voltage level may be lower than the second voltage level.

  In the electro-optical device, any one of the first terminal and the second terminal may be connected to the one power supply line.

  Thereby, for example, the number of wirings per pixel circuit can be reduced.

  In the electro-optical device, any one of the first terminal and the second terminal may be connected to another power line different from the one power line among the plurality of power lines. Good.

  In the electro-optical device, it is preferable that the plurality of power supply lines extend in a direction intersecting with the plurality of data lines.

  In the above electro-optical device, it is preferable that the number of transistors included in the plurality of pixel circuits is only three.

  Thereby, an aperture ratio can be improved.

  According to another aspect of the invention, there is provided an electronic apparatus including the electro-optical device described above.

  In the driving method of the electronic device according to the present invention, the voltage of the node connected to the gate of the driving transistor is changed by connecting the gate of the driving transistor and one terminal and applying a non-forward bias to the driving transistor. A first step of setting an offset level in accordance with a threshold value of the driving transistor; and supplying a voltage from a variable voltage source to a data line capacitively coupled to the node, whereby a capacitor connected to the node is A second step of writing data based on the offset level, and applying a forward bias to the driving transistor to generate a current corresponding to the data held in the capacitor, And a third step of supplying to the current detection circuit.

  A second electronic device driving method according to the present invention, comprising: a first terminal; a second terminal; and a channel region disposed between the first terminal and the second terminal. The voltage level of the first terminal is set to be higher than the voltage level of the second terminal in at least a part of the period in which the step of compensating for the characteristic variation of the driving transistor is included. The voltage level of the first terminal is made lower than the voltage level of the second terminal in at least a part of the period in which the driving voltage or driving current corresponding to the conduction state of the driving transistor is supplied. .

  In the driving method of the electronic device, it is preferable that the compensation step is performed in a state where the first terminal and the gate of the driving transistor are electrically connected.

  In the pixel circuit driving method according to the present invention, the voltage of the node connected to the gate of the driving transistor is reduced by connecting the gate of the driving transistor and one of its own terminals and applying a non-forward bias to the driving transistor. A first step of setting an offset level in accordance with a threshold value of the driving transistor; and supplying a data voltage defining a pixel gray level to a data line capacitively coupled to the node, whereby a capacitor connected to the node is connected On the other hand, a second step of writing data with reference to the offset level and a forward bias applied to the drive transistor generate a drive current according to the data held in the capacitor. The luminance of the electro-optic element is set by supplying the electro-optic element connected to the driving transistor. And a third step.

  In the above pixel circuit driving method, the other terminal of the driving transistor may be connected to a power supply line whose voltage is variably set. In this case, the first step includes a step of setting the voltage of the power supply line to the first voltage, and the third step is configured to set the voltage of the power supply line to a second voltage higher than the first voltage. Preferably the step of setting is included. The second step preferably includes a step of setting the voltage of the power supply line to the first voltage.

  In the above pixel circuit driving method, the first voltage is lower than the voltage at one terminal of the driving transistor when the non-forward bias is applied, and the second voltage is one of the driving transistors when the forward bias is applied. It is preferable that the voltage is higher than the terminal voltage. Further, it is desirable that a predetermined voltage is fixedly applied to the counter electrode of the electro-optic element.

  The above-described pixel circuit driving method further includes a fourth step of applying a non-forward bias to the electro-optical element by setting the voltage of the power supply line to a third voltage lower than a predetermined voltage. Also good. And a fifth step of applying a non-forward bias to the electro-optic element by applying a third voltage lower than a predetermined voltage to a node connecting the driving transistor and the electro-optic element. Also good.

  According to the second pixel circuit driving method of the present invention, a predetermined bias is applied to a compensation transistor in which its own gate and one of its terminals are connected to form a forward diode connection, and this compensation A first step of setting a voltage of a node connected to a gate of the compensation transistor to an offset level corresponding to a threshold value of the compensation transistor by applying a non-forward bias to a driving transistor different from the transistor; After applying a bias in the direction opposite to that of the compensation transistor to the compensation transistor and supplying a data voltage that defines the gray level of the pixel to the data line capacitively coupled to the node, the capacitor connected to the node is Second step of writing data based on offset voltage and forward bias applied to drive transistor Thus, a drive current corresponding to the data held in the capacitor is generated, and the drive current is supplied to the electro-optic element connected to one terminal of the drive transistor, thereby setting the luminance of the electro-optic element. And a third step.

  Here, in the driving method of the pixel circuit, the other terminal of the driving transistor is connected to the first power supply line in which the voltage is variably set, and the other terminal of the compensation transistor is variable in voltage. It may be connected to the second power line to be set. In this case, the first step includes a step of setting the voltage of the first power supply line to the first voltage and a step of setting the voltage of the second power supply line to the second voltage. The second step includes a step of setting the voltage of the second power supply line to a third voltage higher than the second voltage, and the third step sets the voltage of the first power supply line to the first voltage. Preferably, the method includes a step of setting a higher fourth voltage. The second step includes a step of setting the voltage of the first power supply line to the first voltage, and the third step is a step of setting the voltage of the second power supply line to the third voltage. It is desirable to include.

  In the above pixel circuit driving method, the first voltage is lower than the voltage at one terminal of the driving transistor when the non-forward bias is applied, and the second voltage is the voltage of the compensation transistor when the non-forward bias is applied. The third voltage is lower than the voltage at one terminal, the third voltage is higher than the voltage at one terminal of the compensation transistor when the forward bias is applied, and the fourth voltage is one of the drive transistors when the forward bias is applied. The voltage is preferably higher than the terminal voltage. Further, it is desirable that a predetermined voltage is fixedly applied to the counter electrode of the electro-optic element.

  The pixel circuit driving method further includes a fourth step of applying a non-forward bias to the electro-optic element by setting the voltage of the power supply line to a fifth voltage lower than a predetermined voltage. Also good.

  The first pixel circuit of the present invention is connected to an electro-optical element whose luminance is set by a driving current flowing through itself, a power supply line whose one terminal is variably set, and the other terminal is an electro-optical element A drive transistor that is connected to the element and generates a drive current according to the gate voltage, a first capacitor having one electrode connected to the gate of the drive transistor, and one electrode connected to the gate of the drive transistor A first capacitor in which the other electrode is connected to the other terminal of the driving transistor, one terminal is connected to the other electrode of the first capacitor, and the other terminal is connected to the data line. Switching transistor, and a second switch having one terminal connected to the gate of the driving transistor and the other terminal connected to the other terminal of the driving transistor And a grayed transistor.

  Here, in the above pixel circuit, in the initialization period in which the first switching transistor is turned off and the second switching transistor is turned on, the voltage of the power supply line is set to the first voltage, so that the driving transistor is not turned on. It is preferable to apply a forward bias and set the gate voltage of the drive transistor to an offset level corresponding to the threshold value of the drive transistor. Further, in a data write period after the initialization period, in which the first switching transistor is turned on and the second switching transistor is turned off, a data voltage for defining the gradation of the pixel is applied to the data line. By supplying, data may be written to the first capacitor and the second capacitor based on the offset level. Further, the voltage of the power supply line is set to a second voltage higher than the first voltage in the driving period after the data writing period and in the driving period in which the first switching transistor and the second switching transistor are turned off. By setting, the forward bias is applied to the drive transistor, and the drive current corresponding to the data held in the first capacitor and the second capacitor is supplied to the electro-optic element, thereby reducing the luminance of the electro-optic element. It may be set.

  The second pixel circuit of the present invention is connected to an electro-optical element whose luminance is set by a driving current flowing through itself, a first power source line whose voltage is variably set, and the other terminal. Is connected to the electro-optic element, and generates a drive current according to the gate voltage, a first capacitor having one electrode connected to the gate of the drive transistor, and one electrode being the drive transistor And a second capacitor connected to the other terminal of the driving transistor, one terminal connected to the other electrode of the first capacitor, and the other terminal connected to the data line. A second transistor whose gate is connected to the gate of the switching transistor, the gate of the switching transistor, the gate of the driving transistor, and the other terminal of which the voltage is controlled variably. And a connected compensating transistor line.

  Here, in the above pixel circuit, in the initialization period in which the switching transistor is turned off, the voltage of the first power supply line is set to the first voltage, thereby applying a non-forward bias to the driving transistor, By setting the voltage of the power supply line to the second voltage, a forward diode connection in the compensation transistor can be formed, and the gate voltage of the driving transistor can be set to an offset voltage corresponding to the threshold value of the compensation transistor. preferable. Further, by setting the voltage of the second power supply line to a third voltage higher than the second voltage in the data write period after the initialization period and turning on the switching transistor, The bias applied to the compensation transistor is set in the opposite direction to the initialization period, and the data voltage defining the gray level of the pixel is supplied to the data line, whereby the first capacitor and the second capacitor are supplied. Alternatively, data may be written based on the offset voltage. Further, in the driving period after the data writing period and in which the switching transistor is turned off, the voltage of the first power supply line is set to a fourth voltage higher than the first voltage. The luminance of the electro-optical element may be set by applying a forward bias to the transistor and supplying a driving current corresponding to data held in the first capacitor and the second capacitor to the electro-optical element.

  The third pixel circuit of the present invention is connected to an electro-optical element whose luminance is set by a driving current flowing through itself and a first power supply line whose one terminal is variably set, and in accordance with a gate voltage. A drive transistor for generating a drive current, a first capacitor having one electrode connected to the gate of the drive transistor, one electrode connected to the gate of the drive transistor, and the other electrode connected to the other of the drive transistor. A second capacitor connected to the terminal; a first switching transistor having one terminal connected to the other electrode of the first capacitor; the other terminal connected to the data line; and one terminal being a drive transistor A second switching transistor having the other terminal connected to the other terminal of the driving transistor and one terminal connected to the driving transistor. A third switching transistor connected to the second power supply line whose voltage is variably set, and one terminal connected to the other terminal of the driving transistor, The other terminal has a fourth switching transistor connected to the electro-optic element.

  Here, in the above pixel circuit, the first switching transistor is turned off, the second switching transistor is turned on, the third switching transistor is turned on for a partial period, and the fourth switching transistor is turned off. In the period, by setting the voltage of the first power supply line to the first voltage and the voltage of the second power supply line to the second voltage, a non-forward bias is applied to the drive transistor, and the drive transistor Is preferably set to an offset voltage corresponding to the threshold value of the driving transistor. In addition, data that is after the initialization period, turns on the first switching transistor, turns off the second switching transistor, turns off the third switching transistor, and turns off the fourth switching transistor. In the writing period, data can be written to the first capacitor and the second capacitor with reference to the offset level by supplying a data voltage that defines the gradation of the pixel to the data line. Good. Further, in a period after the data writing period, the first switching transistor is turned off, the second switching transistor is turned off, the third switching transistor is turned off, and the fourth switching transistor is turned on. During the driving period, the voltage of the first power supply line is set to a third voltage higher than the first voltage, so that a forward bias is applied to the driving transistor and held in the first capacitor and the second capacitor. The luminance of the electro-optical element may be set by supplying a driving current corresponding to the data thus obtained to the electro-optical element. A reverse bias that is after the driving period and turns off the first switching transistor, turns off the second switching transistor, turns on the third switching transistor, and turns on the fourth switching transistor. In the period, it is preferable to apply a non-forward bias to the electro-optic element by setting the voltage of the second power supply line to a fourth voltage lower than the second voltage.

  According to a fourth pixel circuit of the present invention, an electro-optical element whose luminance is set by a driving current flowing through the pixel circuit and a power supply line whose one terminal is variably set in voltage are connected to the other terminal. A driving transistor that generates a driving current according to a gate voltage, a capacitor having one electrode connected to the gate of the driving transistor, and one terminal connected to the other electrode of the capacitor. A first switching transistor having the other terminal connected to the data line, a second switching transistor having one terminal connected to the gate of the driving transistor and the other terminal connected to the other terminal of the driving transistor; Have

  Here, in the initialization period in which the first switching transistor is turned off and the second switching transistor is turned on by the above-described pixel circuit, the voltage of the power supply line is set to the first voltage so that the driving transistor is not turned on. It is preferable to apply a forward bias and set the gate voltage of the driving transistor to an offset voltage corresponding to the threshold value of the driving transistor.

  Further, in a data write period after the initialization period, in which the first switching transistor is turned on and the second switching transistor is turned off, a data voltage for defining the gradation of the pixel is applied to the data line. By supplying, data may be written to the capacitor based on the offset voltage. Further, the voltage of the power supply line is set to a second voltage higher than the first voltage in the driving period after the data writing period and in the driving period in which the first switching transistor and the second switching transistor are turned off. The luminance of the electro-optical element may be set by applying a forward bias to the driving transistor by setting and supplying a driving current corresponding to the data held in the capacitor to the electro-optical element.

  The electro-optical device including the pixel circuit may be an electronic device.

  As one effect of the present invention, by performing the transistor characteristic compensation step and the non-forward bias application in one operation process, it is possible to improve flexibility in operation design.

(First embodiment)
FIG. 1 is a block diagram of the electro-optical device according to the present embodiment. The display unit 1 is an active matrix display panel that drives an electro-optical element by, for example, a TFT (Thin Film Transistor). In the display unit 1, a group of pixels corresponding to m dots × n lines are arranged in a matrix (in a two-dimensional plane). The display unit 1 is provided with scanning line groups Y1 to Yn each extending in the horizontal direction and data line groups X1 to Xm each extending in the vertical direction. Pixel 2 (pixel circuit) is arranged corresponding to the above. The power supply lines L1 to Ln are provided corresponding to the scanning lines Y1 to Yn and extend in the direction intersecting with the data lines X1 to Xm, in other words, in the extending direction of the scanning lines Y1 to Yn. . A pixel row (for m dots) corresponding to the extending direction of one scanning line Y is commonly connected to each of the power supply lines L1 to Ln. In the present embodiment, one pixel 2 is the minimum display unit of an image, but one pixel 2 may be composed of three RGB sub-pixels as in a color panel.

  Note that, in relation to the configuration of the pixel circuit according to each embodiment to be described later, a case where one scanning line Y shown in FIG. 1 represents one scanning line (FIG. 6) and a set of a plurality of scanning lines. In some cases (FIGS. 2, 9, and 11). Similarly, there are cases where one power supply line L shown in FIG. 1 represents one power supply line (FIGS. 2 and 11) and cases where a plurality of power supply lines are set (FIGS. 6 and 9).

  The control circuit 5 is based on a vertical synchronization signal Vs, a horizontal synchronization signal Hs, a dot clock signal DCLK, gradation data D, and the like input from a host device (not shown), and the scanning line drive circuit 3, the data line drive circuit 4, and the power supply. The line control circuit 6 is synchronously controlled. Under this synchronous control, these circuits 3, 4, and 6 perform display control of the display unit 1 in cooperation with each other.

  The scanning line driving circuit 3 is mainly composed of a shift register, an output circuit and the like, and sequentially scans the scanning lines Y1 to Yn by outputting a scanning signal SEL to the scanning lines Y1 to Yn. The scanning signal SEL takes a binary signal level of a high potential level (hereinafter referred to as “H level”) or a low potential level (hereinafter referred to as “L level”), and corresponds to a pixel row to which data is to be written. The scanning line Y is set to the H level, and the other scanning lines Y are set to the L level. The scanning line driving circuit 3 sequentially selects each scanning line Y in a predetermined selection order (generally from the top to the bottom) every period (1F) for displaying an image of one frame. Sequential scanning is performed. The data line driving circuit 4 is mainly composed of a shift register, a line latch circuit, an output circuit, and the like.

  In one horizontal scanning period (1H) corresponding to a period for selecting one scanning line Y, the data line driving circuit 4 simultaneously outputs the data voltage Vdata to the pixel row to which data is written this time, and writes data at the next 1H. Point-sequential latching of data relating to the pixel row to be performed is simultaneously performed. In a certain 1H, m pieces of data corresponding to the number of data lines X are sequentially latched. In the next 1H, the latched m data voltages Vdata are simultaneously output to the corresponding data lines X1 to Xm.

  On the other hand, the power supply line control circuit 6 is mainly composed of a shift register, an output circuit and the like, and in synchronization with scanning by the scanning line driving circuit 3, the voltages of the power supply lines L1 to Ln are variably set for each pixel row. To do.

  FIG. 2 is a pixel circuit diagram of a voltage follower type voltage program system according to the present embodiment. With respect to this pixel circuit, one scanning line Y shown in FIG. 1 includes a first scanning line Ya to which a first scanning signal SEL1 is supplied and a second scanning line to which a second scanning signal SEL2 is supplied. Yb is included. One pixel circuit includes an organic EL element OLED that is one form of a driven element, three transistors T1 to T3, and two capacitors C1 and C2 that hold data. In the present embodiment, since the TFT is formed of amorphous silicon, the channel type is all n-type. Of course, a transistor other than amorphous silicon may be used, or the channel type may be used. However, the present invention is not limited to this (the same applies to the embodiments described later). In this specification, regarding a transistor which is a three-terminal element including a source, a drain, and a gate, one of the source and the drain is referred to as “one terminal” and the other is referred to as “the other terminal”.

  The gate of the first switching transistor T1 is connected to the first scanning line Ya to which the first scanning signal SEL1 is supplied, and the conduction is controlled by the scanning signal SEL1. One terminal of the transistor T1 is connected to the data line X, and the other terminal is connected to one electrode of the first capacitor C1. The other electrode of the capacitor C1 is connected to the node N1. In addition to the first capacitor C1, the node N1 is commonly connected to the gate of the drive transistor T3, one terminal of the second switching transistor T2, and one electrode of the second capacitor C2. One terminal of the driving transistor T3 is connected to the power supply line L, and the other terminal is connected to the node N2. In addition to the drive transistor T3, the anode (anode) of the organic EL element OLED, the other terminal of the second switching transistor T2, and the other electrode of the second capacitor C2 are commonly connected to the node N2. A reference voltage Vss (for example, 0 V) lower than the power supply voltage Vdd is fixedly applied to the cathode (cathode) of the organic EL element OLED, that is, the counter electrode. The second capacitor C2 is provided between the gate of the driving transistor T3 and the node N2, thereby forming a voltage follower type circuit. The second switching transistor T2 is provided in parallel with the second capacitor C2. The switching transistor T2 has a gate connected to the second scanning line Yb to which the second scanning signal SEL2 is supplied, and the conduction of the switching transistor T2 is controlled by the scanning signal SEL2.

  FIG. 3 is an operation timing chart of the pixel circuit shown in FIG. A series of operation processes in the period t0 to t3 corresponding to 1F described above includes an initialization process in the first period t0 to t1, a data writing process in the subsequent period t1 to t2, and driving in the last period t2 to t3. Broadly divided into processes.

  First, in the initialization period t0 to t1, reverse bias application and Vth compensation are simultaneously performed on the drive transistor T3. Specifically, the first scanning signal SEL1 becomes L level, the first switching transistor T1 is turned off, and the first capacitor C1 and the data line X are electrically separated. In response to this, the second scanning signal SEL2 becomes H level, and the second switching transistor T2 is turned on. Here, the power supply line L is set to VL = Vss, and the voltage V2 at the node N2 is at least higher than Vss + Vth by the previous 1F driving process (the specific value is the same as in the previous 1F). Data, characteristics of the driving transistor T3, organic EL element OLED, etc.). Due to such a voltage relationship, a bias in a direction opposite to a direction in which a driving current Ioled described later flows is applied to the driving transistor T3, and its own gate and its own drain (terminal on the node N2 side) are forwardly directed. Connected diode connection. As a result, as shown in FIG. 4A, the voltage at the node N2 (and the voltage V1 at the node N1 directly connected thereto) reaches the offset level (Vss + Vth) corresponding to the Vth of the drive transistor T3. A current I in the direction opposite to the drive current Ioled flowing in the drive period t2 to t3 flows from the power source line L toward the power supply line L. The capacitors C1 and C2 connected to the node N1 are set to a charge state such that the voltage V1 of the node N1 becomes an offset level (Vss + Vth) prior to data writing. As described above, the threshold value Vth of the driving transistor T3 can be compensated by offsetting the voltage of the node N1 to the offset level (Vss + Vth) prior to the data writing.

  Next, in the data writing period t1 to t2, data is written to the capacitors C1 and C2 with reference to the offset level (Vss + Vth) set in the initialization period t0 to t1.

  Specifically, the second scanning signal SEL2 falls to the L level, the second switching transistor T2 is turned off, and the diode connection of the driving transistor T3 is released. In synchronization with the fall of the scanning signal SEL2, the first scanning signal SEL1 rises to the H level, and the first switching transistor T1 is turned on. As a result, the data line X and the first capacitor C1 are electrically connected. In this specification, the term “synchronization” is used not only for the same timing but also for allowing a slight time offset for reasons such as a design margin. When a predetermined time elapses from the timing t1, the voltage Vx of the data line X rises from the reference voltage Vss to the data voltage Vdata (voltage level data defining the display gradation of the pixel 2). As shown in FIG. 4B, the data line X and the node N1 are capacitively coupled via the first capacitor C1. Therefore, the voltage V1 of the node N1 rises by α · delta Vdata based on the offset voltage (Vss + Vth) according to the voltage change amount ΔVdata (= Vdata−Vss) of the data line X, as shown in Equation 1. To do. In the equation, the coefficient α is a coefficient specified by the capacitance ratio between the capacitance Ca of the first capacitor C1 and the capacitance Cb of the second capacitor C2 (α = Ca / (Ca + Cb)).

(Formula 1)
V1 = Vss + Vth + α ・ ΔVdata
= Vss + Vth + α (Vdata−Vss)

  In the capacitors C1 and C2, charges corresponding to the voltage V1 calculated from Equation 1 are written as data. Although the nodes N1 and N2 are capacitively coupled via the second capacitor C2, if the capacitance of the capacitor C2 is set to be sufficiently smaller than the capacitance of the organic EL element OLED, the node N2 is present during this period t1 to t2. The voltage V2 is maintained substantially at Vss + Vth without being substantially affected by the voltage fluctuation of the node N1. In this period t1 to t2, by setting the power supply line L to VL = Vss, it is possible to regulate the light emission of the organic EL element OLED without flowing the driving current Ioled.

  In the driving period t2 to t3, the driving current Ioled corresponding to the channel current of the driving transistor T3 is supplied to the organic EL element OLED, and the organic EL element OLED emits light. Specifically, the first scanning signal SEL1 becomes L level again, and the first switching transistor T1 is turned off. As a result, the data line X to which the data voltage Vdata is supplied is electrically separated from the first capacitor C1, but the gate N1 of the driving transistor T3 is connected to the data held in the capacitors C1 and C2. The applied voltage continues to be applied. Then, in synchronization with the fall of the first scanning signal SEL1, the power supply line L becomes VL = Vdd. As a result, as shown in FIG. 4C, a path of the drive current Ioled is formed in the direction from the power supply line L toward the cathode side of the organic EL element OLED. At this time, the terminal on the opposite side across the channel region of the notebook N2 and the drive transistor T3 functions as the drain of the drive transistor T3.

  Assuming that the drive transistor T3 operates in the saturation region, the drive current Ioled (channel current Ids of the drive transistor T3) flowing through the organic EL element OLED is calculated based on Equation 2. In the equation, Vgs is a gate-source voltage of the driving transistor T3. The gain coefficient β is a coefficient specified by the carrier mobility μ, the gate capacitance A, the channel width W, and the channel length L of the driving transistor T3 (β = μAW / L).

(Formula 2)
Ioled = Ids
= Β / 2 (Vgs−Vth) ²

  Here, when V1 calculated by Expression 1 is substituted as the gate voltage Vg of the driving transistor T3, Expression 2 can be transformed as Expression 3.

(Formula 3)
Ioled = β / 2 (Vg−Vs−Vth) ²
= Β / 2 {(Vss + Vth + α · ΔVdata) −Vs−Vth} ²
= Β / 2 (Vss + α · ΔVdata−Vs) ²

The point to be noted in Formula 3 is that the drive current Ioled generated by the drive transistor T3 does not depend on the threshold value Vth of the drive transistor T3 due to cancellation of Vth. Therefore, if data writing to the capacitors C1 and C2 is performed with reference to Vth, the drive current Ioled can be generated without being affected by variations in Vth due to manufacturing variations or changes over time.

  The light emission luminance of the organic EL element OLED is determined by the drive current Ioled corresponding to the data voltage Vdata (voltage change amount ΔVdata), and thereby the gradation of the pixel 2 is set. When the drive current Ioled flows through the path shown in FIG. 4C, the source voltage V2 of the drive transistor T3 rises from the original Vss + Vth due to the self resistance of the organic EL element OLED and the like. However, the gate N1 and the node N2 of the driving transistor T3 are capacitively coupled via the second capacitor C2, and the gate voltage V1 increases as the source voltage V2 increases. It is possible to reduce the influence of fluctuations in the source voltage V2.

  As described above, in this embodiment, the voltage VL of the power supply line L is made variable, and is set to Vss in the initialization period t0 to t1, and higher to Vdd in the driving period t2 to t3. The set voltage Vss in the initialization period t0 to t1 needs to be lower than the voltage V2 at the node N2 connecting the drive transistor T3 and the organic EL element OLED in order to apply a reverse bias to the drive transistor T3. Further, the set voltage Vdd in the driving period t2 to t3 needs to be higher than the voltage V2 of the node N2 in order to apply a forward bias to the driving transistor T3 and allow the path of the driving current Ioled to be formed. By setting VL = Vss in the initialization period t0 to t1, a reverse bias is applied to the drive transistor T3, and Vth compensation is performed under this bias state. By performing Vth compensation, it is possible to reduce the influence of Vth variation on the drive current Ioled. Also, by applying a reverse bias, it is possible to effectively suppress the shift of Vth in the drive transistor T3, that is, the phenomenon that Vth changes with time. By performing Vth compensation and reverse bias application in the same operation process (initialization period t0 to t1), it is possible to improve flexibility in operation design.

  In the present embodiment, the reverse bias is applied to the drive transistor T3 by dropping the voltage VL of the power supply line L to the reference voltage Vss in the initialization period t0 to t1. However, the voltage VL in the period t0 to t1 may be set to a voltage Vrvs lower than Vss. In this case, since the voltage Vrvs of the power supply line L is lower than the voltage Vss on the counter electrode side of the organic EL element OLED, a reverse bias can be applied not only to the driving transistor T3 but also to the organic EL element OLED. As a result, it is possible to extend the life of the organic EL element OLED. If the concept of the present embodiment is expanded, the above-described effects can be achieved by performing Vth compensation after applying a non-forward bias to the driving transistor T3, that is, applying a non-forward bias. Therefore, although the reverse bias which is one of the non-forward biases is the best embodiment, the present invention is not limited to this. In addition, these points are the same also about each embodiment mentioned later.

(Second Embodiment)
The present embodiment relates to a technique for more positively applying a reverse bias to the drive transistor T3 in the pixel circuit shown in FIG. Since the configuration of the pixel circuit is as described above, description thereof is omitted here.

  FIG. 5 is an operation timing chart according to the present embodiment. In the present embodiment, reverse bias periods t2 'to t3 are provided in the latter half of the driving periods t2 to t3, and the voltage VL of the power supply line L is lower than the reference voltage Vss (the voltage of the counter electrode) in these periods t2' to t3. Set to Vrvs. As a result, the light emission of the organic EL element OLED stops, and a reverse bias is applied to both the organic EL element OLED and the drive transistor T3.

  According to this embodiment, in addition to the same effects as those of the first embodiment described above, the reverse bias is more effectively applied to the organic EL element OLED in the reverse-ias period t2 'to t3. It is possible to extend the life of the EL element OLED.

(Third embodiment)
FIG. 6 is a pixel circuit diagram of a voltage follower type voltage program system according to the present embodiment. Regarding this pixel circuit, one power supply line L shown in FIG. 1 includes a first power supply line La and a second power supply line Lb. One pixel circuit includes an organic EL element OLED, three n-channel transistors T1 to T3, and two capacitors C1 and C2 that hold data. The threshold value Vth2 of the compensation transistor T2 is set to be substantially equal to the threshold value Vth1 of the drive transistor T3. With respect to the transistors T2 and T3 manufactured by the same process and arranged very close to each other on the display unit 1, their electrical characteristics can be set almost the same even in an actual product.

  The gate of the switching transistor T1 is connected to the scanning line Y to which the scanning signal SEL is supplied. One terminal of the transistor T1 is connected to the data line X, and the other terminal is connected to one electrode of the first capacitor C1. The other electrode of the capacitor C1 is connected to the node N1. In addition to the first capacitor C1, the node N1 is connected in common to the gate of the drive transistor T3, one terminal (and its gate) of the compensation transistor T2, and one electrode of the second capacitor C2. . One terminal of the driving transistor T3 is connected to the first power supply line La, and the other terminal is connected to the node N2. In addition to the drive transistor T3, the anode of the organic EL element OLED and the other electrode of the second capacitor C2 are commonly connected to the node N2. A reference voltage Vss is fixedly applied to the cathode of the organic EL element OLED. The second capacitor C2 is provided between the gate of the driving transistor T3 and the node N2, thereby forming a voltage follower type circuit. The other terminal of the compensation transistor T2 is connected to the second power supply line Lb.

  FIG. 7 is an operation timing chart of the pixel circuit shown in FIG. As in the first embodiment, the period t0 to t3 corresponding to 1F is roughly divided into an initialization period t0 to t1, a data writing period t1 to t2, and a driving period t2 to t3.

  First, in the initialization period t0 to t1, reverse bias application and Vth compensation are simultaneously performed for both the compensation transistor T2 and the drive transistor T3. Specifically, the scanning signal SEL becomes L level, the switching transistor T1 is turned off, and the first capacitor C1 and the data line X are electrically separated. Here, the voltage VLb of the second power supply line Lb is set to Vss, and becomes lower than the voltage V1 of the node N1 by the driving process of 1F. Due to this potential relationship, of the two terminals arranged across the channel region of the compensation transistor T2, the terminal connected to its own gate functions as a drain, and forward bias (during the driving period t2 to t3). If the bias relationship is a forward bias, a reverse-biased diode connection is obtained.

  As a result, as shown in FIG. 8A, a current I1 that is an initialization current flows from the node N1 toward the second power supply line Lb until the voltage V1 of the node N1 reaches the offset level (Vss + Vth1). The capacitors C1 and C2 connected to the node N1 are set to a charge state such that the voltage V1 of the node N1 becomes an offset level (Vss + Vth) prior to data writing.

  Further, the voltage VLa of the first power supply line La is also set to Vss, and becomes lower than the voltage V2 of the node N2 by the previous 1F driving process. Therefore, a reverse bias is also applied to the driving transistor T3, and a current I2 flows from the node N2 toward the first power supply line La. The current I2 contributes to a change in characteristics and deterioration of the drive transistor T3.

  In the data writing period t1 to t2, data is written to the capacitors C1 and C2 based on the offset level (Vss + Vth1) set in the initialization period t0 to t1. Specifically, first, the voltage VLb of the second power supply line Lb rises from Vss to Vdd, and the voltage VLb becomes higher than the voltage V1 of the node N1. As a result, a bias in the opposite direction to the initialization period t0 to t1 (a forward bias when the bias relationship of the drive periods t2 to t3 is a forward direction) is applied to the compensation transistor T2, and the node N1 and the second power supply line Lb And are electrically separated. In synchronization with the rise of the voltage VLb, the scanning signal SEL rises to the H level, and the switching transistor T1 is turned on. As a result, the data line X and the first capacitor C1 are electrically connected. When a predetermined time elapses from the timing t1, the voltage Vx of the data line X rises from the reference voltage Vss to the data voltage Vdata. As shown in FIG. 8B, the data line X and the node N1 are capacitively coupled via the first capacitor C1. Therefore, the voltage V1 of the node N1 rises by α · delta Vdata with reference to the offset level (Vss + Vth1) as shown in Equation 4. Capacitors C1 and C2 are set in a charge state such that voltage V1 calculated from Equation 4 is obtained. In this period t1 to t2, since the first power supply line La is set to VLa = Vss, the drive current Ioled does not flow and the organic EL element OLED does not emit light.

(Formula 4)
V1 = Vss + Vth1 + α ・ ΔVdata
= Vss + Vth1 + α (Vdata−Vss)

  In the driving period t2 to t3, the driving current Ioled corresponding to the channel current Ids of the driving transistor T3 flows through the organic EL element OLED, and the organic EL element OLED emits light. Specifically, the scanning signal SEL again becomes L level, and the switching transistor T1 is turned off. As a result, the data line X to which the data voltage Vdata is supplied is electrically separated from the first capacitor C1, but the gate N1 of the driving transistor T3 is connected to the data held in the capacitors C1 and C2. The gate voltage Vg continues to be applied. Then, in synchronization with the fall of the scanning signal SEL, the first power supply line La becomes VLa = Vdd. As a result, as shown in FIG. 8C, a path of the drive current Ioled is formed in the direction from the first power supply line La toward the cathode side of the organic EL element OLED. Assuming that the drive transistor T3 operates in the saturation region, the drive current Ioled flowing through the organic EL element OLED is calculated based on Equation 5.

(Formula 5)
Ioled = Ids
= Β / 2 (Vgs−Vth2) ²

  Here, when V1 calculated by Equation 1 is substituted as the gate voltage Vg of the driving transistor T3, Equation 5 can be transformed into Equation 6.

(Formula 6)
Ioled = β / 2 (Vg−Vs−Vth2) ²
= Β / 2 {(Vss + Vth1 + α · ΔVdata) −Vs−Vth2} ²

  In this embodiment, the threshold value Vth1 of the compensation transistor T2 and the threshold value Vth2 of the drive transistor T3 are set to be approximately equal. Therefore, Vth1 and Vth2 cancel each other in the equation, and as a result, they can be summarized as Equation 7. As can be seen from the equation, the organic EL element OLED emits light based on the drive current Ioled that does not depend on the thresholds Vth1 and Vth2 of the transistors T2 and T3, and thereby the gradation of the pixel 2 is set.

(Formula 7)
Ioled = β / 2 (Vss + α · ΔVdata−Vs) ²

  Thus, according to the present embodiment, when Vth compensation is performed, reverse bias is applied to both the compensation transistor T2 and the drive transistor T3. Thus, for the same reason as in the first embodiment, Vth compensation and suppression of Vth shift can be performed in the same operation process (initialization period t0 to t1), and flexibility in operation design is improved. Can be planned.

  In the present embodiment, for the same reason as in the second embodiment, reverse bias periods t2 'to t3 are provided in the latter half of the drive periods t2 to t3, and the power supply lines La and Lb are provided in the periods t2' to t3. The voltages VLa and VLb may be set to Vrvs.

  Further, the drive transistor T3 and the compensation transistor T2 may be connected to the same power supply line instead of being connected to the different first power supply line La and second power supply line Lb as in this embodiment. That is, the voltage level of one of the two terminals arranged across the own channel region of the compensation transistor T2 is set to the voltage level of one of the two terminals arranged across the own channel region of the drive transistor T3. You may make it set so that it may become the same level as the voltage level of any one terminal. Thereby, the number of wirings per pixel circuit can be reduced.

(Fourth embodiment)
FIG. 9 is a pixel circuit diagram of a voltage follower type voltage program system according to the present embodiment. With respect to this pixel circuit, one scanning line Y shown in FIG. 1 includes four scanning lines Ya to Yd supplied with scanning signals SEL1 to SEL4, respectively, and one power supply line L shown in FIG. Two power supply lines La and Lb are included. One pixel circuit includes an organic EL element OLED, five n-channel transistors T1 to T5, and two capacitors C1 and C2 for holding data. This pixel circuit is based on the pixel circuit shown in FIG. 2, and has two transistors T4 and T5 added thereto.

  Specifically, the gate of the first switching transistor T1 is connected to the first scanning line Ya to which the first scanning signal SEL1 is supplied. One terminal of the transistor T1 is connected to the data line X, and the other terminal is connected to one electrode of the first capacitor C1. The other electrode of the capacitor C1 is connected to the node N1. In addition to the first capacitor C1, the node N1 is connected in common to the gate of the drive transistor T3, one terminal of the second switching transistor T2, and one electrode of the second capacitor C2. One terminal of the driving transistor T3 is connected to the first power supply line La, and the other terminal is connected to the node N2. In addition to the driving transistor T3, the node N2 includes the other terminal of the second switching transistor T2, the other electrode of the second capacitor C2, one terminal of the third switching transistor T4, and the fourth switching transistor. The anodes of the organic EL elements OLED are commonly connected via T5. A reference voltage Vss is fixedly applied to the cathode of the organic EL element OLED. The second capacitor C2 is provided between the gate of the driving transistor T3 and the node N2, thereby forming a voltage follower type circuit. The second switching transistor T2 is provided in parallel with the second capacitor C2, and the gate thereof is connected to the second scanning line Yb to which the second scanning signal SEL2 is supplied. The other terminal of the third switching transistor T4 is connected to the second power supply line Lb, and its gate is connected to the third scanning line Yc to which the third scanning signal SEL3 is supplied. The gate of the fourth switching transistor T5 is connected to the fourth scanning line Yd to which the fourth scanning signal SEL4 is supplied.

  FIG. 10 is an operation timing chart of the pixel circuit shown in FIG. In this embodiment, in a period t0 to t3 corresponding to 1F, a reverse bias is applied to the organic EL element OLED in addition to the initialization period t0 to t1, the data writing period t1 to t2 and the driving period t2 to t2 ′. Reverse bias periods t2 'to t3 are set.

  In the initialization period t0 to t1, reverse bias application and Vth compensation are simultaneously performed on the drive transistor T3. Specifically, the scanning signals SEL1 and SEL4 become L level, and both the switching transistors T1 and T5 are turned off. Thereby, the first capacitor C1 and the data line X are electrically separated, and the organic EL element OLED and the node N2 are electrically separated. Further, the second scanning signal SEL2 becomes H level, and the second switching transistor T2 is turned on. Further, in a partial period (first half) of the initialization period t0 to t1, the third scanning signal SEL3 becomes H level, and the third switching transistor T4 is turned on. Here, the first power supply line La is set to VLa = Vss, and the voltage VLb of the second power supply line Lb is set to VLb = Vdd. Due to this voltage relationship, a bias in the direction opposite to the direction in which the drive current Ioled flows is applied to the drive transistor T3, and its own gate and its own drain (terminal on the node N2 side) are connected in the forward direction. Diode connection. Thereafter, when the third scanning signal SEL3 falls to the L level and the third switching transistor T4 is turned off, the voltage V2 at the node N2 (and the voltage V1 at the node N1 directly connected thereto) is set to the offset level (Vss + Vth). Is set. The capacitors C1 and C2 connected to the node N1 are set to a charge state such that the voltage V1 of the node N1 becomes an offset level (Vss + Vth) prior to data writing.

  In the data writing period t1 to t2, data is written to the capacitors C1 and C2 with reference to the offset level (Vss + Vth) set in the initialization period t0 to t1. Specifically, the second scanning signal SEL2 falls to the L level, the second switching transistor T2 is turned off, and the diode connection of the driving transistor T3 is released. In synchronization with the fall of the scanning signal SEL2, the first scanning signal SEL1 rises to H level, and the first switching transistor T1 is turned on. As a result, the data line X and the first capacitor C1 are electrically connected. When a predetermined time elapses from the timing t1, the voltage Vx of the data line X rises from the reference voltage Vss to the data voltage Vdata. Due to the capacitive coupling through the first capacitor C1, the voltage V1 at the node N1 rises by α · ΔVdata with reference to the offset level (Vss + Vth), and data corresponding thereto is written in the capacitors C1 and C2. In this period t1 to t2, since the fourth switching transistor T5 is off, the drive current Ioled does not flow and the organic EL element OLED does not emit light.

  In the driving period t2 to t2 ′, the first scanning signal SEL1 falls to the L level, and the first switching transistor T1 is turned off. In synchronization with this fall, the fourth scanning signal SEL4 rises to the H level, the fourth switching transistor T5 is turned on, and the first power supply line La becomes VLa = Vdd. As a result, the drive current Ioled flows through the organic EL element OLED, and the organic EL element OLED emits light. For the reasons described above, the drive current Ioled is almost independent of the threshold value Vth of the drive transistor T3.

  In the reverse bias period t2 'to t3, the third scanning signal SEL3 rises to the H level, and the voltage VLa of the first power supply line La falls from Vdd to Vss. Further, during this period t2 ′ to t3, the second power supply line Lb is VLb = Vrvs. Accordingly, the voltage Vrvs of the second power supply line Lb is directly applied to the node N2, and V2 = Vrvs, so that a reverse bias is applied to the organic EL element OLED.

  According to the present embodiment, Vth compensation and Vth shift suppression can be performed in the same operation process (initialization period t0 to t1), as in the above-described embodiments. Improvements can be made. Further, since the reverse bias is applied to the organic EL element OLED in the reverse bias period t2 'to t3, the life of the organic EL element OLED can be extended.

(Fifth embodiment)
FIG. 11 is a pixel circuit diagram of a voltage program method according to the present embodiment. Unlike the above-described embodiments, this pixel circuit is not a voltage follower type. One pixel circuit includes an organic EL element OLED, three n-channel transistors T1 to T3, and one capacitor C1 that holds data.

  The gate of the first switching transistor T1 is connected to the first scanning line Ya to which the first scanning signal SEL1 is supplied. One terminal of the transistor T1 is connected to the data line X, and the other terminal is connected to one electrode of the first capacitor C1. The other electrode of the capacitor C1 is connected to the node N1. In addition to the first capacitor C1, the node N1 is commonly connected to the gate of the drive transistor T3 and one terminal of the second switching transistor T2. One terminal of the driving transistor T3 is connected to the power supply line L, and the other terminal is connected to the node N2. In addition to the drive transistor T3, the anode (anode) of the organic EL element OLED and the other terminal of the second switching transistor T2 are commonly connected to the node N2. A reference voltage Vss (for example, 0 V) lower than the power supply voltage Vdd is fixedly applied to the cathode (cathode) of the organic EL element OLED. The gate of the second switching transistor T2 is connected to the second scanning line Yb to which the second scanning signal SEL2 is supplied.

  The operation of this pixel circuit is as shown in the timing chart of FIG. 3, and the operation is the same as that of the first embodiment except that the second capacitor C2 is not interposed. Omitted.

  According to the present embodiment, Vth compensation and suppression of Vth shift can be performed in the same operation process (initialization period t0 to t1) even in a voltage-programmed pixel circuit that is not a voltage follower type. As a result, it is possible to improve flexibility in operation design in such a pixel circuit.

  In the above embodiment, when the gate voltage of the driving transistor is set to the offset level, the potential of the electrode of the other capacitor opposite to one electrode of the capacitor connected to the gate of the driving transistor is set to a predetermined value. It is preferable. Thereby, the gate voltage of the drive transistor can be accurately set by capacitive coupling.

  For example, as shown in the timing chart of FIG. 3, a period is provided in which both the second switching transistor T2 and the first switching transistor T1 are in the ON state, and the voltage Vx in this period is set to a predetermined value such as Vss. By setting the value, the potential of the electrode opposite to the electrode of the capacitor C1 connected to the node N1 is accurately set when the node N1 is set to the offset level, and thus the data voltage Vdata is supplied. Thus, the voltage level of the node N1 can be accurately set by capacitive coupling.

  Similarly, as shown in the timing chart of FIG. 7, a part of the period in which the compensation transistor T2 is in the on state (the voltage is set to VLb is set to Vss) is a period in which the switching transistor T1 is in the on state. During this period when both the compensation transistor T2 and the switching transistor T1 are on, the potential of the electrode opposite to the electrode connected to the node N1 of the capacitor C1 is set at a predetermined voltage. By setting Vss to a certain value, the voltage level of the node N1 can be accurately set by capacitive coupling by the subsequent supply of the data voltage Vdata.

  In the above-described embodiment, the example in which the organic EL element OLED is used as the electro-optical element has been described. However, the present invention is not limited to this, and an electro-optical element (inorganic LED display device, field emission display device, etc.) whose luminance is set according to the drive current, or transmittance according to the drive current. -Widely applicable to electro-optical devices (electrochromic display devices, electrophoretic display devices, etc.) exhibiting reflectivity.

  Further, the electro-optical device according to the above-described embodiment can be mounted on various electronic devices including, for example, a television, a projector, a mobile phone, a mobile terminal, a mobile computer, a personal computer, and the like. When the above-described electro-optical device is mounted on these electronic devices, the commercial value of the electronic devices can be further increased, and the product appeal of electronic devices in the market can be improved.

  Further, the present invention is characterized in that the Vth compensation of the driving transistor and the application of the reverse bias are performed in the same operation process. Therefore, the concept of the present invention is disclosed in an electronic circuit other than the electro-optical device, for example, a fingerprint sensor disclosed in Japanese Patent Laid-Open No. 8-305832, or Japanese Patent Application No. 2003-107936, which is a prior application of the present applicant. The present invention can be widely applied to a variety of sensing devices with high sensitivity such as a biochip. The basic configuration of the electronic circuit is the same except that the electro-optical element (organic EL element OLED) in the pixel circuit according to each embodiment described above is replaced with a current detection circuit. As an operation of this electronic circuit, first, the gate of the driving transistor and one terminal are connected, and a non-forward bias is applied to the driving transistor. As a result, the voltage of the node connected to the gate of the driving transistor is set to the offset voltage (Vss + Vth). Next, by supplying a voltage from the variable voltage source to the data line capacitively coupled to the node, data is written to the capacitor connected to the node with reference to the offset level (Vss + Vth). Then, by applying a forward bias to the drive transistor, a current corresponding to the data held in the capacitor is generated and supplied to the current detection circuit. The current detection circuit measures the amount of current flowing through the drive transistor.

FIG. 3 is a block diagram of an electro-optical device. FIG. 2 is a pixel circuit diagram according to the first embodiment. The operation | movement timing chart concerning 1st Embodiment. Operation | movement explanatory drawing concerning 1st Embodiment. The operation | movement timing chart concerning 2nd Embodiment. FIG. 6 is a pixel circuit diagram according to a third embodiment. The operation | movement timing chart concerning 3rd Embodiment. Operation | movement explanatory drawing concerning 3rd Embodiment. FIG. 10 is a pixel circuit diagram according to a fourth embodiment. The operation | movement timing chart concerning 4th Embodiment. FIG. 10 is a pixel circuit diagram according to a fifth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Display part 2 Pixel 3 Scan line drive circuit 4 Data line drive circuit 5 Control circuit 6 Power supply line control circuit T1-T5 Transistor C1-C2 Capacitor
OLED organic EL device

Claims (18)

A method of driving an electronic circuit comprising a plurality of driving transistors and a plurality of driven elements,
The driving transistor includes a gate, a first terminal, a second terminal, and a channel region disposed between the first terminal and the second terminal, and the driving transistor includes: The first terminal functions as a drain of the driving transistor in a state where the gate and the first terminal are electrically connected by a transistor connected between the gate and the first terminal. A first step of generating a potential difference between the first terminal and the second terminal;
Between the first terminal and the second terminal so that the second terminal functions as a drain of the driving transistor in a state where the gate and the first terminal are made non-conductive by the transistor. A potential difference is generated in the drive transistor, and a drive voltage or a drive current corresponding to a conduction state of the drive transistor set by supplying a data signal to the gate of the drive transistor is supplied to the driven element. A second step of:
An electronic circuit driving method characterized by the above. The method of driving an electronic circuit according to claim 1,
In response to the first step, an initialization current is passed from the first terminal to the second terminal, and the gate voltage of the driving transistor is set to an offset level corresponding to the threshold value of the driving transistor. Setting,
An electronic circuit driving method characterized by the above. The method for driving an electronic circuit according to claim 1 or 2,
The electronic circuit is
A capacitor including a first electrode and a second electrode, and a capacitor formed between the first electrode and the second electrode;
The gate is connected to the first electrode;
After performing the first step, the gate is in a floating state, the data signal is supplied to the gate by capacitive coupling via the capacitor, and the conduction state is set;
An electronic circuit driving method characterized by the above. The method for driving an electronic circuit according to claim 1,
The driven element includes an operating electrode connected to the first terminal, a counter electrode, and a functional layer disposed between the operating electrode and the counter electrode,
While performing the first step and the second step, at least the voltage of the counter electrode is fixed to a predetermined voltage level;
An electronic circuit driving method characterized by the above. The method for driving an electronic circuit according to claim 4,
Setting the voltage level of the second terminal lower than the predetermined voltage level in at least a part of the period in which the first step is performed;
An electronic circuit driving method characterized by the above. The method for driving an electronic circuit according to claim 4,
A third step of setting the voltage level of the first terminal to a voltage level lower than the predetermined voltage level;
During the period of performing the third step, fixing the voltage of the counter electrode to the predetermined voltage level;
An electronic circuit driving method characterized by the above. 5. The electronic circuit driving method according to claim 4, further comprising: a power supply line for supplying a voltage to the first terminal, wherein the voltage of the power supply line is different between the first step and the second step. An electronic circuit driving method characterized by comprising: An electronic circuit for driving a plurality of driven elements,
A plurality of the electronic circuits are provided, each of which
A drive transistor comprising a first terminal and a second terminal, and having a channel region between the first terminal and the second terminal;
A first transistor disposed between the first terminal and the gate of the driving transistor and controlling an electrical connection between the first terminal and the gate;
In at least part of a first period in which the first terminal and the gate of the driving transistor are electrically connected via the first transistor,
A voltage level of at least one of the first terminal and the second terminal is set so that the first terminal functions as a drain of the driving transistor;
In at least part of the second period in which the first terminal and the gate of the driving transistor are electrically disconnected,
A voltage level of at least one of the first terminal and the second terminal is set so that the second terminal functions as a drain of the driving transistor;
An electronic circuit characterized by The electronic circuit according to claim 8 ,
With the first period as an opportunity, the voltage level of the gate of the drive transistor is set to an offset level according to the threshold voltage of the drive transistor,
In at least a portion of the second period,
A driving voltage or a driving current corresponding to the conduction state of the driving transistor is supplied to the driven element;
An electronic circuit characterized by The electronic circuit according to claim 8 ,
The voltage level of any one of the fourth terminal and the third terminal is set to the same voltage level as the second terminal throughout the first period and the second period,
An electronic circuit characterized by An electronic device,
A plurality of electronic circuits according to any of claims 8 to 10 ;
The driven element provided for each of the plurality of electronic circuits;
An electronic device with An electro-optic device,
Multiple data lines,
A plurality of scan lines;
A plurality of first power lines;
A plurality of pixel circuits provided corresponding to intersections of the plurality of data lines and the plurality of scanning lines ,
Each of the plurality of pixel circuits is
An electro-optic element;
A drive transistor comprising a first terminal and a second terminal, and having a channel region between the first terminal and the second terminal;
A first switching transistor connected between the first terminal and the gate of the driving transistor and controlling an electrical connection between the first terminal and the gate;
A conduction state of the driving transistor is set according to a data signal supplied through one data line of the plurality of data lines;
A driving voltage or a driving current corresponding to the conduction state of the driving transistor is supplied to the electro-optic element,
The first terminal functions as a drain in at least a part of a period in which the first terminal and the gate of the driving transistor are electrically connected via the first switching transistor. A voltage level of at least one of the first terminal and the second terminal is set;
In at least a part of the period in which the drive voltage or the drive current is supplied to the electro-optical element,
A voltage level of at least one of the first terminal and the second terminal is set so that the second terminal functions as a drain;
An electro-optical device. The electro-optical device according to claim 12 ,
Each of the plurality of pixel circuits further includes a first electrode and a second electrode, and a first capacitor in which a capacitance is formed between the first electrode and the second electrode;
A second switching transistor for controlling an electrical connection between the one data line and the second electrode;
The gate of the driving transistor is connected to the first electrode;
An initialization current flows between the first terminal and the second terminal during at least a part of a period in which the first terminal functions as a drain of the driving transistor, and the gate of the driving transistor Is set to an offset level corresponding to the drive transistor threshold value,
After the offset level is set, the gate voltage of the driving transistor is set to the offset level and the data signal supplied via the second switching transistor by capacitive coupling via the first capacitor. Set to a voltage level according to the data signal,
An electro-optical device. The electro-optical device according to claim 12 or 13 ,
Each of the plurality of pixel circuits is
A second capacitor having a third electrode and a fourth electrode and a capacitor formed between the third electrode and the fourth electrode;
The third electrode is connected to the gate of the driving transistor;
The fourth electrode is connected to the first terminal;
An electro-optical device. The electro-optical device according to claim 12 ,
The second terminal is connected to one power line of the plurality of power lines.
The one power line can be set to a plurality of voltage levels;
An electro-optical device. The electro-optical device according to claim 12 ,
The plurality of power lines extending in a direction intersecting with the plurality of data lines;
An electro-optical device. The electro-optical device according to claim 12 ,
The number of transistors included in the plurality of pixel circuits is only three;
An electro-optical device. An electronic apparatus comprising the electro-optical device according to claim 12 mounted thereon.

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