JP2009048212A - Electrooptical device, driving method of the electrooptical device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of power supply lines which supply voltages to pixel circuits. <P>SOLUTION: Individual pixels 2 are arranged according to crossings of scanning lines Y1 to Yn and data lines X1 to Xm and are commonly connected to mutually adjacent power supply lines (L1 and L2, for example) among power supply lines L1 to Ln+1 that are corresponding provided to the scanning lines Y1 to Yn. A scanning line drive circuit 3 selects a scanning line Y, by outputting a scanning signal to the scanning lines Y1 to Yn. A power supply line control circuit 6 sets the variable voltages of the power supply lines L1 to Ln+1, in synchronism with the selection of the scanning line Y by the scanning line drive circuit 3. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electronic device such as an electro-optical device, a driving method of the electro-optical device, and an electronic apparatus, and more particularly to common use of a power supply line for supplying a voltage to a pixel circuit.

  In recent years, a display using an organic EL (Electronic Luminescence) element has attracted attention. The organic EL element is one of current-driven elements whose luminance is set according to the drive current flowing through the organic EL element. There are a current program method and a voltage program method for writing data into a pixel using an organic EL element. The current program method is a method for supplying data to the data line on a current basis, and the voltage program method is a method for supplying data to the data line on a voltage basis.

  One of the objects of the present invention is to prevent changes in characteristics or deterioration of characteristics of electro-optical elements and transistors, and to reduce the number of power supply lines for supplying voltage to the pixel circuit.

  In order to solve such a problem, a first electro-optical device of the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality of power supply lines extending in a direction intersecting the plurality of data lines, A plurality of pixel circuits are provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines, and each of the plurality of pixel circuits is a pair of adjacent ones of the plurality of power supply lines. A pixel group commonly connected to a power supply line, a scanning line driving circuit for selecting the scanning line by outputting a scanning signal to the plurality of scanning lines, and selection and synchronization of the scanning line by the scanning line driving circuit And a power line control circuit for variably setting the voltages of the plurality of power lines.

  In the second electro-optical device of the present invention, a plurality of scanning lines, a plurality of data lines, a plurality of power supply lines extending in a direction intersecting with the plurality of data lines, the plurality of scanning lines, and the plurality of the plurality of scanning lines. A plurality of pixel circuits provided corresponding to intersections of the plurality of data lines, and one power line of the plurality of power lines includes the plurality of data lines of the plurality of pixel circuits. Among these, pixel circuits arranged adjacent to each other along one data line are connected.

  In the above electro-optical device, the change with time in the voltage value of one of the two adjacent power supply lines among the plurality of power supply lines is the change with time in the voltage value of the other power supply line of the two power supply lines. On the other hand, it is preferable to shift by a predetermined time.

  The predetermined time may be, for example, a horizontal scanning period.

  In the electro-optical device, each of the plurality of pixel circuits includes a capacitor that holds a charge corresponding to a data current or a data voltage supplied via one data line of the plurality of data lines, and a capacitor. It is preferable to include a driving transistor whose conduction state is set based on the held electric charge and an electro-optic element whose luminance is set according to the conduction state.

  In the electro-optical device, the power line control circuit may variably set voltage values of two power lines connected to each of the plurality of pixel circuits among the plurality of power lines. The direction of the bias applied to the transistor may be changed.

  In the electro-optical device, one power line of the two power lines is connected to one end of the drive transistor, and the other power line of the two power lines is connected to the drive transistor. It is preferable to be connected to a node between the other end and the electro-optic element.

  In the electro-optical device, the power supply line control circuit sets the voltage of the one power supply line higher than the predetermined voltage in the drive period that is a part of the predetermined period, thereby causing the drive transistor to The driving is performed by applying a forward bias and setting the voltage of the other power supply line higher than the voltage of the one power supply line in a part of the predetermined period and different from the driving period. A non-forward bias may be applied to the transistor.

  In the above electro-optical device, the power supply line control circuit variably sets voltage values of two power supply lines connected to each of the plurality of pixel circuits among the plurality of power supply lines, whereby the electric power line control circuit The bias direction applied to the optical element may be changed.

  In the electro-optical device, one power line of the two power lines is connected to one end of the driving transistor, and the other power line of the two power lines is the You may make it connect to the node between the other edge part of a drive transistor, and the said electro-optical element.

  In the above electro-optical device, the power supply line control circuit sets the voltage of the one power supply line higher than the predetermined voltage in a driving period that is a part of the predetermined period, so that the electro-optical element And applying a forward bias to the electro-optics by setting a voltage of the other power line lower than the predetermined voltage in a part of the predetermined period and different from the driving period. A non-forward bias may be applied to the element.

  According to another aspect of the invention, there is provided an electronic apparatus including the electro-optical device described above.

  According to the first driving method of the electro-optical device of the present invention, a plurality of pixel circuits each including an electro-optical element and a driving transistor are provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines. In the driving method of the electro-optical device in which each of the plurality of pixel circuits is commonly connected to a pair of power supply lines adjacent to each other among the plurality of power supply lines provided corresponding to the plurality of scanning lines, A first step of supplying a data signal to each of a plurality of pixel circuits via one of the plurality of data lines, and an order corresponding to a conduction state of the driving transistor set by the data signal. A second step of applying a bias to the electro-optic element; a non-forward bias third step of applying to the electro-optic element; and a change in characteristics of the drive transistor due to the application of the forward bias. Others and having a, a fourth step for recovering the deterioration.

  In the driving method of the electro-optical device, the third step and the fourth step may be performed using different periods.

  In the driving method of the electro-optical device, the fourth step may be performed in a state where the electrical connection between the electro-optical element and the driving transistor is cut off.

  In the driving method of the electro-optical device, it is preferable that a non-forward bias is applied to the driving transistor in the fourth step.

  In the driving method of the electro-optical device, in the second step, by setting a voltage of the one power supply line higher than the predetermined voltage, a forward bias is applied to the driving transistor, and the fourth step In this step, a non-forward bias may be applied to the drive transistor by setting the voltage of the other power supply line higher than the voltage of the one power supply line.

  According to the second driving method of the electro-optical device of the present invention, an electric device including a plurality of pixel circuits each including an electro-optical element and a driving transistor corresponding to the intersection of the plurality of scanning lines and the plurality of data lines. A method for driving an optical device, comprising: a first step of supplying a data signal to each of the plurality of pixel circuits via one data line of the plurality of data lines; and the data signal is set A second step of applying a forward bias to the electro-optic element in accordance with a conduction state of the driving transistor; a third step of applying a non-forward bias to the electro-optic element; and a second step of applying a non-forward bias to the driving transistor. And 4 steps.

  In the driving method of the electro-optical device, it is preferable that the conduction state of the driving transistor is set after compensating for the characteristic variation of the driving transistor.

  According to a third method of driving an electro-optical device of the present invention, an electric device including a plurality of pixel circuits each including an electro-optical element and a driving transistor corresponding to the intersection of a plurality of scanning lines and a plurality of data lines. A method for driving an optical device, comprising: a first step of supplying a data signal to each of the plurality of pixel circuits via one data line of the plurality of data lines; and the data signal is set A second step of applying a forward bias to the electro-optic element in accordance with a conduction state of the drive transistor; and a third step of applying a non-forward bias to at least one of the electro-optic element and the drive transistor; , And the conduction state of the drive transistor is set after compensating for the characteristic variation of the drive transistor.

  In the present invention, the “forward bias” is not limited to being uniquely set, but may be appropriately set according to the application. Further, in the present invention, “non-forward bias” is defined according to the setting of “forward bias” and means a state in which no bias or current flows in the opposite direction to “forward bias”.

  One of the effects of the present invention is that the number of power supply lines can be reduced while suppressing changes and deterioration of characteristics of the drive transistor and the electro-optic element.

(First embodiment)
FIG. 1 is a block diagram of the electro-optical device according to the present embodiment. The display unit 1 is an active matrix display panel that drives an electro-optical element by, for example, a TFT (Thin Film Transistor). In the display unit 1, a group of pixels corresponding to m dots × n lines are arranged in a matrix (in a two-dimensional plane). The display unit 1 is provided with scanning line groups Y1 to Yn each extending in the horizontal direction and data line groups X1 to Xm each extending in the vertical direction. Pixel 2 (pixel circuit) is arranged corresponding to the above. Note that one scanning line Y shown in FIG. 1 represents a set of four scanning lines Ya to Yd in relation to the configuration of the pixel circuit according to each embodiment described later (see FIGS. 2 and 8). reference). In the present embodiment, one pixel 2 is the minimum display unit of an image, but one pixel 2 may be composed of three RGB sub-pixels.

  The power supply lines L1 to Ln + 1 are provided corresponding to the scanning lines Y1 to Yn. In order to supply a variable voltage to each pixel 2 constituting the display unit 1, the extending direction of the scanning lines Y1 to Yn, In other words, it extends in a direction intersecting with the data lines X1 to Xm. In the pixel row for m dots corresponding to the i-th (1 ≦ i ≦ n) scanning line Yi, the i-th power line L (i) and the (i + 1) -th power line L (i) adjacent thereto are provided. +1) are connected in common. In this way, a pair of upper and lower adjacent power supply lines L are connected to one pixel row, so that the number of power supply lines L required for the entire display unit is one more than the number n of scanning lines Y.

  The control circuit 5 is based on a vertical synchronization signal Vs, a horizontal synchronization signal Hs, a dot clock signal DCLK, gradation data D, and the like input from a host device (not shown), and the scanning line drive circuit 3, the data line drive circuit 4, and the power supply. The line control circuit 6 is synchronously controlled. Under this synchronous control, these circuits 3, 4, and 6 perform display control of the display unit 1 in cooperation with each other.

  The scanning line driving circuit 3 is mainly composed of a shift register, an output circuit and the like, and selects the scanning lines Y1 to Yn by outputting a scanning signal SEL to the scanning lines Y1 to Yn. The scanning signal SEL takes a binary signal level of a high potential level (hereinafter referred to as “H level”) or a low potential level (hereinafter referred to as “L level”), and corresponds to a pixel row to which data is to be written. The scanning line Y is set to the H level, and the other scanning lines Y are set to the L level. As a result, for each period (1F) for displaying an image of one frame, sequential scanning for selecting each scanning line Y in order is performed in a predetermined selection order (generally from the top to the bottom). Is called.

  The data line driving circuit 4 is mainly composed of a shift register, a line latch circuit, an output circuit, and the like. The data line driving circuit 4 outputs the data simultaneously to the pixel row in which the current data is written and the pixel to be written in the next 1H in one horizontal scanning period (1H) corresponding to the period for selecting one scanning line Y. Dot-sequential latching of data about rows at the same time. In a certain 1H, m pieces of data corresponding to the number of data lines X are sequentially latched. In the next 1H, the latched m pieces of data are simultaneously output to the corresponding data lines X1 to Xm as the data current Idata. The present embodiment relates to a current programming method. When this method is employed, the data line drive circuit 4 is a variable that converts data (data voltage Vdata) corresponding to the display gradation of the pixel 2 into a data current Idata. Includes current source. On the other hand, when the voltage programming method is employed as in the second embodiment to be described later, the data line driving circuit 4 does not have to include such a variable current source, and the voltage level that defines the gradation of the pixel 2 is not required. The data voltage Vdata is output to the data lines X1 to Xm.

  On the other hand, the power supply line control circuit 6 is mainly composed of a shift register, an output circuit, and the like. The voltages of the power supply lines L1 to Ln + 1 are variably set in synchronization with the selection of the scanning line Y by the scanning line driving circuit 3, and are higher than the power supply voltage Vdd or the reference voltage Vss higher than the reference voltage Vss (for example, 0V). One of the low voltages Vrvs is set.

  FIG. 2 is a pixel circuit diagram of a voltage follower type current programming method according to the present embodiment. One pixel circuit in the i-th pixel row includes four scanning lines Ya to Yd constituting the i-th scanning line Yi, i-th power supply lines L (i) and (i + 1) corresponding to the scanning line Yi. ) Th power line L (i + 1) is connected. Here, the i-th and (i + 1) -th are physically adjacent on the arrangement of the display unit 1, but are also adjacent in the order of line-sequential scanning.

  This pixel circuit is composed of an organic EL element OLED which is a form of a current driven element, six transistors T1 to T6, and a capacitor C1 for holding data. In this embodiment, since the TFT is formed of amorphous silicon, the channel types of the transistors T1 to T6 are all n-type, but the channel type is not limited to this (the second type described later). The same applies to the embodiment). In this specification, regarding a transistor which is a three-terminal element including a source, a drain, and a gate, one of the source and the drain is referred to as “one terminal” and the other is referred to as “the other terminal”.

  The gate of the switching transistor T1 is connected to the first scanning line Ya to which the first scanning signal SEL1 is supplied, and the conduction of the switching transistor T1 is controlled by the scanning signal SEL1. One terminal of the switching transistor T1 is connected to the data line X to which the data current Idata is supplied, and the other terminal is connected to the node N3. In addition to the switching transistor T1, one terminal of the switching transistor T6 and one terminal of the driving transistor T3 are commonly connected to the node N3. The switching transistor T6 has the other terminal connected to the power supply line L (i) and the gate connected to the fourth scanning line Yd to which the fourth scanning signal SEL4 is supplied. The conduction is controlled by SEL4. On the other hand, the gate of the switching transistor T2 is connected to the first scanning line Ya to which the first scanning signal SEL1 is supplied, and the conduction of the switching transistor T2 is controlled by the scanning signal SEL1 as in the switching transistor T1. One terminal of the switching transistor T2 is connected to the data line X, and the other terminal is connected to the node N1. In addition to the switching transistor T2, one electrode of the capacitor C1 and the gate of the driving transistor T3 are commonly connected to the node N1. The other electrode of the capacitor C1 is connected to the node N2. In addition to the capacitor C1, the other terminal of the driving transistor T3, one terminal of the switching transistor T4, and one terminal of the switching transistor T5 are commonly connected to the node N2. By providing a capacitor C1 between nodes N1 and N2 corresponding to the source and gate of the driving transistor T3, a voltage follower type circuit is formed. The other terminal of the switching transistor T4 is connected to the power supply line L (i + 1), and its gate is connected to the second scanning line Yb to which the second scanning signal SEL2 is supplied. The conduction is controlled by the signal SEL2. The other terminal of the switching transistor T5 is connected to the anode (anode) of the organic EL element OLED and the gate thereof is connected to the third scanning line Yc to which the third scanning signal SEL3 is supplied. The conduction is controlled by the scanning signal SEL3. The reference voltage Vss is fixedly applied to the cathode (cathode) of the organic EL element OLED, that is, the counter electrode.

  FIG. 3 is an operation timing chart of the pixel circuit shown in FIG. A series of operation processes in the period t0 to t4 corresponding to 1F described above are a data writing process in the first period t0 to t1, a driving process in the period t1 to t2, and a first reverse bias application process in the period t2 to t3. And a second reverse bias application process in the period t3 to t4.

  First, in the data writing period t0 to t1, data is written to the capacitor C1 by the operation shown in FIG. Specifically, the first scanning signal SEL1 becomes H level, and both the switching transistors T1 and T2 are turned on. As a result, the node N3 corresponding to the drain of the driving transistor T3 and the data line X are electrically connected. At the same time, the driving transistor T3 has a diode connection in which its own gate and its own drain are electrically connected via the transistors T1 and T2 and the data line X. Further, since the second scanning signal SEL2 is L level and the third scanning signal SEL3 is H level, the switching transistor T4 is turned off and the switching transistor T5 is turned on. As a result, the supply of the voltage VL (i + 1) (= Vrvs) to the node N2 via the power supply line L (i + 1) is stopped, and the node N2 and the anode of the organic EL element OLED are electrically connected. Is done. Further, since the fourth scanning signal SEL4 is at L level, the switching transistor T6 is turned off. As a result, the supply of the voltage VL (i) to the node N3 via the power supply line L (i) is stopped. As a result, as indicated by an arrow in the figure, a path of the data current Idata flowing in the order of the transistors T1, T3, T5 and the organic EL element OLED from the data line X toward the reference voltage Vss is formed. The drive transistor T3 causes the data current Idata supplied from the data line X to flow through its own channel, and generates a gate voltage Vg corresponding to the data current Idata at the node N1. Thereby, charges corresponding to the generated gate voltage Vg are accumulated in the capacitor C1, and data corresponding to the accumulated charge amount is written. Thus, in the data writing period t0 to t1, the drive transistor T3 functions as a programming transistor for writing data to the capacitor C1. Since the organic EL element OLED is included in the path of the data current Idata, the organic EL element OLED starts to emit light in this data writing process.

  Next, in the driving period t1 to t2, the driving current Ioled flows through the organic EL element OLED and the organic EL element OLED emits light by the operation shown in FIG. When a writing period t0 to t1 corresponding to 1H (that is, a selection period in which one scanning line Y is selected) elapses, the first scanning signal SEL1 falls to the L level, and the switching transistors T1 and T2 are turned on. Turn off both. As a result, the data line X to which the data current Idata is supplied and the node N3 are electrically separated, and the diode connection of the driving transistor T3 is also released. However, even after the diode connection is released, the gate voltage Vg corresponding to the data held in the capacitor C1 is continuously applied to the node N1 corresponding to the gate of the drive transistor T3. Then, in synchronization with the first scanning signal SEL1 being at the L level, the fourth scanning signal SEL4 rises to the H level, and the switching transistor T6 is turned on. In this specification, the term “synchronization” is used not only for the same timing but also for allowing a slight time offset for reasons such as a design margin. As a result, the voltage VL (i) of the power supply line L (i), that is, the power supply voltage Vdd higher than the reference voltage Vss is supplied to the node N3. Note that the switching transistor T4 remains off and the switching transistor T5 remains on during this period t1 to t2, similarly to the previous data writing period t0 to t1. As a result, a forward bias is applied to both the drive transistor T3 and the organic EL element OLED, and the transistor T6 moves from the power supply line L (i) set to VL (i) = Vdd toward the reference voltage Vss on the counter electrode side. , T3, T5, and the organic EL element OLED are formed in the order of the drive current Ioled. The drive current Ioled flowing through the organic EL element OLED corresponds to the channel current of the drive transistor T3, and the current level is set by the gate voltage Vg caused by the accumulated charge (retained data) of the capacitor C1. The organic EL element OLED emits light with a luminance corresponding to the drive current Ioled generated by the drive transistor T3, and thereby the gradation of the pixel 2 is set.

  In the subsequent first reverse bias application period t2 to t3, the operation shown in FIG. 6 applies a non-forward bias to the drive transistor T3, that is, a bias in a direction different from the forward bias in the drive period t1 to t2. . Specifically, the third scanning signal SEL3 falls to the L level, and the second scanning signal SEL2 rises to the H level in synchronization therewith. Thereby, the node N2 and the anode of the organic EL element OLED are electrically separated, and the voltage V2 of the node N2 is set to Vdd by the power supply line L (i + 1) set to VL (i + 1) = Vdd. Is done. Also, the switching transistor T6 remains on during this period t2 to t3, but the voltage VL (i) of the power supply line L (i) is equal to VL (i) = Vdd in the previous driving period t1 to t2. In contrast, the voltage Vrvs is set lower than the reference voltage Vss. Therefore, the voltage V2 at the node N2 becomes Vdd higher than the voltage VL (i) (= Vrvs) of the power supply line L (i). As a result, the bias acting on the driving transistor T3 (the voltage relationship between the nodes N2 and N3) is opposite to that in the previous driving period t1 to t2. In this way, by applying a reverse bias (a form of non-forward bias) to the drive transistor T3, only the bias in the same direction continues to be applied by driving the Vth shift of the drive transistor T3. Changes in characteristics such as a phenomenon in which the threshold value Vth changes with time can be suppressed.

  Finally, in the second reverse bias application period t3 to t4, the operation shown in FIG. 7 causes a non-forward bias to the organic EL element OLED, that is, a bias in a direction different from the forward bias in the drive period t1 to t2. Applied. Specifically, the fourth scanning signal SEL4 falls to the L level, and the third scanning signal SEL3 rises to the H level in synchronization therewith. Thereby, the node N3 and the power supply line L (i) are electrically separated, and the node N2 and the anode of the organic EL element OLED are electrically connected. In addition, the switching transistor T4 remains on during this period t3 to t4, but the voltage VL (i + 1) of the power supply line L (i + 1) is VL (i + 1) in the previous period t2 to t3. ) = Vrvs unlike Vdd. Therefore, the voltage V2 at the node N2 becomes Vrvs lower than the reference voltage Vss of the counter electrode. As a result, the bias acting on the organic EL element OLED is opposite to that in the driving periods t1 to t2. Thus, by applying a reverse bias to the organic EL element OLED, it is possible to extend the life of the organic EL element OLED.

  The change over time of the voltage VL (i + 1) of the power supply line L (i + 1) shown in FIG. 3 is offset by 1H with respect to the power supply line L (i). For the (i + 1) th pixel row, the operation process using the power supply lines L (i + 1) and L (i + 2) is described above, starting from the timing t1 when 1H has elapsed from the timing t0. The same process is performed (the same applies to the subsequent pixel rows).

  Thus, in this embodiment, a pair of adjacent power supply lines L (i) and L (i + 1) are connected in common to the pixel circuit, and these voltages VL (i) and VL (i + 1) are scanned. It is set to be variable in synchronization with the selection of the line Y. These voltages VL (i) and VL (i + 1) have the same waveform and are offset by a predetermined period (here, 1H). The power supply line L (i + 1) that should be used in the operation process of the (i + 1) th pixel row is also used in the operation process of the i-th pixel row. Thus, by sharing the power supply lines L, the number of power supply lines L can be reduced.

  In addition, according to the present embodiment, the voltages VL (i) and VL (i + 1) of the power supply lines L (i) and L (i + 1) are variably set so that the drive transistor T3 is non-forward biased. And a non-forward bias is also applied to the organic EL element OLED. By applying a non-forward bias to the drive transistor T3, it is possible to effectively suppress changes in characteristics such as a Vth shift in the drive transistor T3. Moreover, the lifetime of the organic EL element OLED can be extended by applying a non-forward bias to the organic EL element OLED. Compared with the method of oscillating the voltage Vca of the counter electrode, the method of oscillating the voltages VL (i) and VL (i + 1) of the power lines L (i) and L (i + 1) can reduce the circuit burden. This is also advantageous for frame setting and the like.

(Second Embodiment)
FIG. 8 is a pixel circuit diagram of a voltage follower type voltage program system according to the present embodiment. One pixel circuit in the i-th pixel row includes four scanning lines Ya to Yd constituting the i-th scanning line Yi, an i-th power supply line L (i) corresponding to the scanning line Yi, and The (i + 1) th power line L (i + 1) adjacent to this is connected. This pixel circuit includes an organic EL element OLED, five transistors T1 to T5, and capacitors C1 and C2 for holding data.

  The gate of the switching transistor T1 is connected to the first scanning line Ya to which the first scanning signal SEL1 is supplied, and the conduction of the switching transistor T1 is controlled by the scanning signal SEL1. One terminal of the switching transistor T1 is connected to the data line X to which the data voltage Vdata is supplied, and the other terminal is connected to one electrode of the first capacitor C1. The other electrode of the capacitor C1 is connected to the node N1. In addition to the first capacitor C1, the node N1 is connected in common to the gate of the drive transistor T3, one terminal of the switching transistor T2, and one electrode of the second capacitor C2. One terminal of the driving transistor T3 is connected to the power supply line L (i), and the other terminal is connected to the node N2. In addition to the driving transistor T3, the other terminal of the switching transistor T2, the other electrode of the second capacitor C2, one terminal of the switching transistor T4, and one terminal of the switching transistor T5 are commonly connected to the node N2. ing. By providing a capacitor C2 between nodes N1 and N2 corresponding to the source and gate of the driving transistor T3, a voltage follower type circuit is configured. The other terminal of the switching transistor T4 is connected to the power supply line L (i + 1), and its gate is connected to the third scanning line Yc to which the third scanning signal SEL3 is supplied. The conduction is controlled by the signal SEL3. The other terminal of the switching transistor T5 is connected to the anode (anode) of the organic EL element OLED, and its gate is connected to the fourth scanning line Yd to which the fourth scanning signal SEL4 is supplied. The conduction is controlled by the scanning signal SEL4. A reference voltage Vss is fixedly applied to the cathode (cathode) of the organic EL element OLED, that is, the counter electrode.

  FIG. 9 is an operation timing chart of the pixel circuit shown in FIG. In the present embodiment, a series of operation processes in the period t0 to t5 corresponding to 1F are an initialization process in the period t0 to t1, a data writing process in the period t1 to t2, a driving process in the driving period t2 to t3, and a period t3. Are roughly divided into a reverse bias application process at t4 and a standby process at periods t4 to t5.

  First, in the initialization period t0 to t1, non-forward bias is applied to the driving transistor T3 and Vth compensation is simultaneously performed by the operation shown in FIG. Specifically, the scanning signals SEL1 and SEL4 become L level, and both the switching transistors T1 and T5 are turned off. Thereby, the first capacitor C1 and the data line X are electrically separated, and the organic EL element OLED and the node N2 are electrically separated. Further, the second scanning signal SEL2 becomes H level, and the switching transistor T2 is turned on. Furthermore, in a partial period (first half) of the initialization period t0 to t1, the third scanning signal SEL3 becomes H level and the switching transistor T4 is turned on. Here, the power supply line L (i) is set to VL (i) = Vrvs, and the voltage V2 at the node N2 is supplied by the supply of the voltage Vdd via the power supply line L (i + 1). The voltage VL (i) of i) is higher than Vrvs. Due to this voltage relationship, a bias in the direction opposite to the direction in which the drive current Ioled flows is applied to the drive transistor T3, and its own gate and its own drain (terminal on the node N2 side) are connected in the forward direction. Diode connection. Thereafter, when the third scanning signal SEL3 falls to the L level and the switching transistor T4 is turned off, the voltage V2 at the node N2 (and the voltage V1 at the node N1 directly connected thereto) is set to the offset voltage (Vrvs + Vth). . The capacitors C1 and C2 connected to the node N1 are set to a charge state such that the voltage V1 of the node N1 becomes an offset voltage (Vrvs + Vth) prior to data writing. As described above, the threshold voltage Vth of the drive transistor T3 can be compensated by offsetting the voltage of the node N1 to the offset voltage (Vrvs + Vth) prior to data writing.

  Next, in the data writing period t1 to t2, data is written to the capacitors C1 and C2 based on the offset voltage (Vss + Vth) set in the initialization period t0 to t1 by the operation shown in FIG. . Specifically, the second scanning signal SEL2 falls to the L level, the switching transistor T2 is turned off, and the diode connection of the driving transistor T3 is released. In synchronization with the fall of the scanning signal SEL2, the first scanning signal SEL1 rises to H level and the switching transistor T1 is turned on. As a result, the data line X and the first capacitor C1 are electrically connected. When a predetermined time elapses from the timing t1, the voltage Vx of the data line X rises from the reference voltage Vrvs to the data voltage Vdata. The data line X and the node N1 are capacitively coupled via the first capacitor C1. Therefore, the voltage V1 of the node N1 rises by α · ΔVdata based on the offset voltage (Vrvs + Vth) according to the voltage change amount ΔVdata (= Vdata−Vss) of the data line X, as shown in Equation 1. . In the equation, the coefficient α is a coefficient uniquely specified by the capacitance ratio between the capacitance Ca of the first capacitor C1 and the capacitance Cb of the second capacitor C2 (α = Ca / (Ca + Cb)). .

(Formula 1)
V1 = Vrvs + Vth + α ・ ΔVdata
= Vrvs + Vth + α (Vdata−Vss)

  In the capacitors C1 and C2, charges corresponding to the voltage V1 calculated from Equation 1 are written as data. During this period t1 to t2, the voltage V2 at the node N2 is maintained at approximately Vrvs + Vth without being affected by the voltage fluctuation at the node N1. This is because although the nodes N1 and N2 are capacitively coupled via the second capacitor C2, the capacitance of the capacitor C2 is usually sufficiently smaller than the self-capacitance of the organic EL element OLED. Note that the reason why the power supply line L (i) is set to VL = Vss in this period t1 to t2 is to restrict the light emission of the organic EL element OLED by not passing the driving current Ioled. In this period t1 to t2, since the switching transistor T5 is off, the drive current Ioled does not flow and the organic EL element OLED does not emit light.

  In the driving period t2 to t3, the driving current Ioled corresponding to the channel current of the driving transistor T3 is supplied to the organic EL element OLED by the operation shown in FIG. 12, and the organic EL element OLED emits light. Specifically, the first scanning signal SEL1 falls to the L level, and the switching transistor T1 is turned off. As a result, the data line X to which the data voltage Vdata is supplied is electrically separated from the first capacitor C1, but the gate N1 of the driving transistor T3 is connected to the data held in the capacitors C1 and C2. The applied voltage continues to be applied. Then, in synchronization with the fall of the first scanning signal SEL1, the fourth scanning signal SEL4 rises to H level, the switching transistor T5 is turned on, and the voltage VL (i) of the power supply line L (i) is also Vrvs. To Vdd. As a result, a path of the drive current Ioled is formed in the direction from the power supply line L (i) toward the reference voltage Vss of the counter electrode. Assuming that the drive transistor T3 operates in the saturation region, the drive current Ioled (channel current Ids of the drive transistor T3) flowing through the organic EL element OLED is calculated based on Equation 2. In the equation, Vgs is a gate-source voltage of the driving transistor T3. The gain coefficient β is a coefficient uniquely specified by the carrier mobility μ, the gate capacitance A, the channel width W, and the channel length L of the driving transistor T3 (β = μAW / L).

(Formula 2)
Ioled = Ids
= Β / 2 (Vgs−Vth) ²

  Here, when V1 calculated by Expression 1 is substituted as the gate voltage Vg of the driving transistor T3, Expression 2 can be transformed as Expression 3.

(Formula 3)
Ioled = β / 2 (Vg−Vs−Vth) ²
= Β / 2 {(Vrvs + Vth + α · ΔVdata) −Vs−Vth} ²
= Β / 2 (Vrvs + α · ΔVdata−Vs) ²

  The point to be noted in Formula 3 is that the drive current Ioled generated by the drive transistor T3 does not depend on the threshold value Vth of the drive transistor T3 due to cancellation of Vth. Therefore, if data writing to the capacitors C1 and C2 is performed with reference to Vth, the drive current Ioled can be generated without being affected by variations in Vth due to manufacturing variations or changes with time.

  The light emission luminance of the organic EL element OLED is determined by the drive current Ioled corresponding to the data voltage Vdata (voltage change amount ΔVdata), and thereby the gradation of the pixel 2 is set. When the drive current Ioled flows through the path shown in FIG. 12, the source voltage V2 of the drive transistor T3 rises from the original Vrvs + Vth according to the voltage drop Vel caused by the self resistance of the organic EL element OLED. However, the gate N1 and the source N2 of the driving transistor T3 are capacitively coupled via the second capacitor C2, and the gate voltage V1 increases as the source voltage V2 increases, resulting in a gate-source connection. The voltage Vgs is maintained almost constant.

  In the subsequent reverse bias period t3 to t4, a non-forward bias is applied to the organic EL element OLED in order to extend the life of the organic EL element OLED by the operation shown in FIG. Specifically, the third scanning signal SEL3 rises to the H level, and the voltage VL (i) of the power supply line L (i) is changed from Vdd to Vrvs. In this period t3 to t4, the power supply line L (i + 1) is VL (i + 1) = Vrvs. Therefore, since the voltage Vrvs of the power supply line L (i + 1) is directly applied to the node N2 and V2 = Vrvs, a reverse bias, which is a form of non-forward bias, is applied to the organic EL element OLED.

  The standby periods t4 to t5 adjust the timing that occurs when the voltages VL (i) and VL (i + 1) shown in FIG. 9 have the same waveform offset by a predetermined period (here, 1H). It is a period for. For the (i + 1) -th pixel row selected following the i-th pixel row, the power supply lines L (i + 1) and L (i + 2) are connected at a timing offset by 1H. The operation process used is performed in the same manner as described above (the same applies to the subsequent pixel rows).

  Thus, according to the present embodiment, the number of power supply lines L can be reduced for the same reason as in the first embodiment. At the same time, it is possible to suppress the Vth shift by applying a non-forward bias to the driving transistor T3 and to extend the life of the organic EL element OLED by applying a non-forward bias to the organic EL element OLED.

  In this embodiment, when the gate voltage of the driving transistor is set to the offset voltage, the potential of the electrode of the other capacitor facing the one electrode of the capacitor connected to the gate of the driving transistor is set to a predetermined value. It is preferable to do. Thereby, the gate voltage of the drive transistor can be accurately set by capacitive coupling.

  For example, as shown in the timing chart of FIG. 9, by providing a period in which both the switching transistor T2 and the switching transistor T1 are turned on, and further setting the voltage Vx in this period to a predetermined value such as Vss When the node N1 is set to the offset voltage, the potential of the electrode on the side opposite to the electrode of the capacitor C1 connected to the node N1 is accurately set. For this reason, the data voltage Vdata is supplied and capacitive coupling is performed. The voltage level of the node N1 can also be set accurately.

  In the above-described embodiment, the example in which the organic EL element OLED is used as the electro-optical element has been described. However, the present invention is not limited to this, and an electro-optical element (inorganic LED display device, field emission display device, etc.) whose luminance is set according to the drive current, or transmittance according to the drive current. -Widely applicable to electro-optical devices (electrochromic display devices, electrophoretic display devices, etc.) exhibiting reflectivity.

  Further, the electro-optical device according to the above-described embodiment can be mounted on various electronic devices including, for example, a television, a projector, a mobile phone, a mobile terminal, a mobile computer, a personal computer, and the like. When the above-described electro-optical device is mounted on these electronic devices, the commercial value of the electronic devices can be further increased, and the product appeal of electronic devices in the market can be improved.

  As an application other than the electro-optical device of the present invention, for example, the configuration of the pixel circuit of the present invention can be adopted as an electronic circuit of an electronic device such as a biochip.

FIG. 3 is a block diagram of an electro-optical device. FIG. 2 is a pixel circuit diagram according to the first embodiment. The operation | movement timing chart concerning 1st Embodiment. Operation | movement explanatory drawing in a data writing period. FIG. 9 is an operation explanatory diagram in a driving period. Operation | movement explanatory drawing in a 1st reverse bias period. Operation | movement explanatory drawing in a 2nd reverse bias period. FIG. 6 is a pixel circuit diagram according to a second embodiment. The operation | movement timing chart concerning 2nd Embodiment. Operation | movement explanatory drawing in an initialization period. Operation | movement explanatory drawing in a data writing period. FIG. 9 is an operation explanatory diagram in a driving period. Operation | movement explanatory drawing in a reverse bias period.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Display part, 2 ... Pixel, 3 ... Scan line drive circuit, 4 ... Data line drive circuit, 5 ... Control circuit, 6 ... Power supply line control circuit, T1-T6 ... Transistor, C1-C2 ... Capacitor, OLED ... Organic EL element, N1-N3... Node.

Claims (19)

A plurality of scan lines;
Multiple data lines,
A plurality of power supply lines extending in a direction intersecting with the plurality of data lines;
A plurality of pixel circuits are provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines, and each of the plurality of pixel circuits is a pair of adjacent ones of the plurality of power supply lines. A group of pixels commonly connected to a power line;
A scanning line driving circuit for selecting the scanning line by outputting a scanning signal to the plurality of scanning lines;
An electro-optical device comprising: a power supply line control circuit that variably sets voltages of the plurality of power supply lines in synchronization with selection of the scanning line by the scanning line driving circuit. A plurality of scan lines;
Multiple data lines,
A plurality of power supply lines extending in a direction intersecting with the plurality of data lines;
A plurality of pixel circuits provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines,
One power line of the plurality of power lines is connected to a pixel circuit arranged adjacent to one another along one data line of the plurality of data lines. An electro-optical device.   The change over time in the voltage value of one of the two adjacent power supply lines among the plurality of power supply lines is shifted by a predetermined time with respect to the change over time in the voltage value of the other power supply line of the two power supply lines. The electro-optical device according to claim 1, wherein the electro-optical device is provided. Each of the plurality of pixel circuits is
A capacitor for holding a charge corresponding to a data current or a data voltage supplied via one data line of the plurality of data lines;
A drive transistor whose conduction state is set based on the charge held in the capacitor;
The electro-optical device according to claim 1, further comprising an electro-optical element whose luminance is set according to the conduction state.   The power supply line control circuit is configured to variably set a voltage value of two power supply lines connected to each of the plurality of pixel circuits among the plurality of power supply lines to thereby apply a bias direction applied to the drive transistor. The electro-optical device according to claim 4, wherein:   One power line of the two power lines is connected to one end of the drive transistor, and the other power line of the two power lines is connected to the other end of the drive transistor and the electric power. 6. The electro-optical device according to claim 5, wherein the electro-optical device is connected to a node between the optical element.   The power supply line control circuit applies a forward bias to the drive transistor by setting the voltage of the one power supply line higher than the predetermined voltage in a drive period that is a part of the predetermined period. A non-forward bias is applied to the drive transistor by setting the voltage of the other power supply line higher than the voltage of the one power supply line in a part of the predetermined period that is different from the drive period. The electro-optical device according to claim 6.   The power supply line control circuit is configured to variably set a voltage value of two power supply lines connected to each of the plurality of pixel circuits among the plurality of power supply lines, thereby applying a bias applied to the electro-optical element. The electro-optical device according to claim 4, wherein the direction is changed. One of the two power lines is connected to one end of the drive transistor,
The electro-optical device according to claim 8, wherein the other power line of the two power lines is connected to a node between the other end of the driving transistor and the electro-optical element.   The power supply line control circuit applies a forward bias to the electro-optic element by setting a voltage of the one power supply line higher than the predetermined voltage in a driving period that is a part of the predetermined period. Applying a non-forward bias to the electro-optic element by setting the voltage of the other power line lower than the predetermined voltage in a part of the predetermined period that is different from the driving period. The electro-optical device according to claim 8.   An electronic apparatus comprising the electro-optical device according to claim 1 mounted thereon. A plurality of pixel circuits each including an electro-optic element and a driving transistor are provided corresponding to the intersections of the plurality of scanning lines and the plurality of data lines, and each of the plurality of pixel circuits includes the plurality of pixel circuits. In the driving method of the electro-optical device commonly connected to a pair of power supply lines adjacent to each other among the plurality of power supply lines provided corresponding to the scanning lines,
A first step of supplying a data signal to each of the plurality of pixel circuits via one of the plurality of data lines;
A second step of applying a forward bias to the electro-optic element in accordance with a conduction state of the drive transistor set by the data signal;
A non-forward bias third step on the electro-optic element;
A fourth step for recovering a change or deterioration in characteristics of the driving transistor due to the application of the forward bias;
A method for driving an electro-optical device. The driving method of the electro-optical device according to claim 12,
The third step and the fourth step are performed using different periods;
A driving method for an electro-optical device. The method of driving an electro-optical device according to claim 12 or 13,
The method of driving an electro-optical device, wherein the fourth step is performed in a state where the electrical connection between the electro-optical element and the driving transistor is cut off. The method for driving an electro-optical device according to claim 12,
In the fourth step, a non-forward bias is applied to the driving transistor. The method for driving an electro-optical device according to claim 12,
In the second step, a forward bias is applied to the drive transistor by setting the voltage of the one power line higher than a predetermined voltage;
In the fourth step, the non-forward bias is applied to the drive transistor by setting the voltage of the other power supply line higher than the voltage of the one power supply line. Method. A driving method of an electro-optical device including a plurality of pixel circuits each including an electro-optical element and a driving transistor corresponding to the intersection of a plurality of scanning lines and a plurality of data lines,
A first step of supplying a data signal to each of the plurality of pixel circuits via one of the plurality of data lines;
A second step of applying a forward bias to the electro-optic element in accordance with a conduction state of the drive transistor set by the data signal;
A non-forward bias third step on the electro-optic element;
A fourth step of applying a non-forward bias to the drive transistor;
A method for driving an electro-optical device. The method of driving an electro-optical device according to claim 12,
A driving method of an electro-optical device, wherein a conduction state of the driving transistor is set after compensating for variation in characteristics of the driving transistor. A driving method of an electro-optical device including a plurality of pixel circuits each including an electro-optical element and a driving transistor corresponding to the intersection of a plurality of scanning lines and a plurality of data lines,
A first step of supplying a data signal to each of the plurality of pixel circuits via one of the plurality of data lines;
A second step of applying a forward bias to the electro-optic element in accordance with a conduction state of the drive transistor set by the data signal;
Applying a non-forward bias to at least one of the electro-optic element and the driving transistor, and
A driving method of an electro-optical device, wherein the conduction state of the driving transistor is set after compensating for the characteristic variation of the driving transistor.

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