JP4603234B2 - Pixel clock and pulse modulation signal generating apparatus, optical scanning apparatus, and image forming apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technology for generating a pixel clock and a pulse modulation signal used in a laser printer, a digital copying machine, and the like. More specifically, the present invention relates to high-precision position control of a pixel clock and modulation of light output from a laser light source or the like. The present invention relates to a pixel clock and pulse modulation signal generation device that generates a pulse modulation signal optimal for the above, an optical scanning device including the same, and an image forming apparatus.
[0002]
[Prior art]
FIG. 63 shows a general configuration of an image forming apparatus such as a laser printer or a digital copying machine. In FIG. 63, the laser light emitted from the semiconductor laser unit 2001 is scanned by a rotating polygon mirror 2002 to form a light spot on a photosensitive member 2004 that is a medium to be scanned through a scanning lens 2003, and the photosensitive member. 2004 is exposed to form an electrostatic latent image. At this time, an image clock (pixel clock) that is phase-synchronized for each line is generated for each line based on the output signal of the photodetector 2005 and supplied to the image processing unit 2006 and the laser drive circuit 2007. In this way, the semiconductor laser unit 2001 controls the emission time of the semiconductor laser according to the image data generated by the image processing unit 2006 and the image clock whose phase is set for each line by the phase synchronization circuit 2009. The electrostatic latent image on the scanned medium 2004 is controlled.
[0003]
In such a scanning optical system, variation in the distance from the rotation axis of the deflecting reflection surface of a deflector such as a polygon scanner causes uneven scanning speed of a light spot (scanning beam) that scans the surface to be scanned. This uneven scanning speed causes image fluctuations and image quality degradation. When high quality image quality is required, it is necessary to correct scanning unevenness.
[0004]
Further, in the case of a multi-beam optical system, if there is a difference in the oscillation wavelength of each light source, an exposure position shift occurs in the case of an optical system in which the chromatic aberration of the scanning lens is not corrected, and a spot corresponding to each light source is generated. The scanning width at the time of scanning on the scanning medium is different for each light source, which causes deterioration in image quality. Therefore, it is necessary to correct the scanning width.
[0005]
Conventionally, as a technique for correcting scanning unevenness or the like, a method of controlling a light spot position along a scanning line by basically changing a frequency of a pixel clock is known (for example, Patent Document 1, Patent). Reference 2).
[0006]
On the other hand, as a method of modulating the light output of the light source, a power modulation method that modulates the amount of light itself, a pulse width modulation method that modulates the lighting time of light, and a combined power / pulse width modulation method that combines the two There is. Among them, in the pulse width modulation method, a triangular wave or sawtooth wave corresponding to each pulse generation period is generated, and a pulse width modulation signal is generated by comparing each with an analog video signal using a comparator. And a method of generating a delay pulse by digitally dividing the clock and generating a pulse width modulation signal by the logical sum or logical product (see, for example, Patent Document 3).
[0007]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-167081
[Patent Document 2]
Japanese Patent Laid-Open No. 2001-228415
[Patent Document 3]
Japanese Patent Laid-Open No. 2001-15853
[0008]
[Problems to be solved by the invention]
However, the conventional method (frequency modulation method) for changing the frequency of the pixel clock generally has a complicated configuration of the pixel clock control unit, and the complexity increases as the frequency modulation width becomes minute. There is a problem that it cannot be controlled.
[0009]
Further, it is desired to increase the operation speed in the image forming apparatus. When a triangular wave or sawtooth wave is used in the pulse width modulation signal, the linearity / reproducibility of the triangular wave or sawtooth wave and the increase in the operation speed are compatible. In the case of a digital frequency divider, the maximum operating frequency depends on the device, and there is a problem that the gradation of the image and the increase in the operating speed are not compatible. For example, if a 256-value modulation is performed with a pulse width at a pixel clock of 50 MHz, it is difficult for a triangular wave or a sawtooth wave to have good linearity and swing in a cycle of 20 nS. It is difficult to realize a configuration having a clock of 50 MHz × 256 = 12.8 GHz.
[0010]
An object of the present invention is to generate a pixel clock that enables phase control of the pixel clock with a simple configuration, and similarly generate a pulse modulation signal having a desired pattern with a simple configuration, for example, when the operation speed is high However, it is an object of the present invention to provide a pixel clock and pulse modulation signal generation device that can realize fine high gradation characteristics of an image, and further to provide an optical scanning device and an image forming device provided with the device.
[0011]
[Means for Solving the Problems]
The pixel clock and pulse modulation signal generation device according to the present invention is based on high frequency clock generation means for generating a high frequency clock, and high frequency clock output from the high frequency clock generation means and phase data indicating the phase shift amount of the pixel clock. Pixel clock generation means for changing the period of the pixel clock, and modulation data representing a desired bit pattern corresponding to the image data Synchronized with the pixel clock Serial modulation signal generation means for inputting, converting to a serial pulse train based on the high-frequency clock, and outputting a pulse modulation signal, and the pixel clock generation means includes phase data indicating the phase shift amount of the pixel clock and the pixel clock Control data generating means for generating first control data and second control data from a status signal indicating the status of the high-frequency clock, and First change point of And based on the first control data Transition timing is controlled First clock generating means for generating a first clock, and the high-frequency clock; Second change point And the first clock based on the second control data Transition timing is controlled Main features include second clock generation means for generating a second clock, and clock selection means for selecting the first clock and the second clock according to the phase data and outputting them as a pixel clock.
[0012]
Also, the pixel clock and pulse modulation signal generation device of the present invention includes a high frequency clock generation means for generating a high frequency clock, and a high frequency clock output from the high frequency clock generation means and phase data indicating a phase shift amount of the pixel clock. A pixel clock generating means for generating a pixel clock based on the image data; a modulation data generating means for inputting image data and generating modulation data representing a desired bit pattern from the image data; and Synchronized with the pixel clock Serial modulation signal generation means for inputting and outputting a pulse modulation signal of a serial pulse train based on the high-frequency clock, and the pixel clock generation means indicates the phase data indicating the phase shift amount of the pixel clock and the state of the pixel clock. Control data generating means for generating first control data and second control data from the status signal shown, and the high-frequency clock The first change point of Based on the first control data Transition timing is controlled First clock generating means for generating a first clock; and The second change point and What is the first clock based on the second control data? Transition timing is controlled And a second clock generation unit configured to generate a second clock that transitions at different timings, and a clock selection unit that selects the first clock and the second clock according to the phase data and outputs the selected clock as a pixel clock. And
[0013]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a basic conceptual diagram of a pixel clock and pulse modulation signal generation apparatus of the present invention. In FIG. 1, a pixel clock and pulse modulation signal generation device includes a high-frequency clock generation circuit 10 that is high-frequency clock generation means, a pixel clock generation circuit 11 that is pixel clock generation means, and a modulation data generation circuit that is modulation data generation means. 12 and a serial modulation signal generation circuit 13 which is a serial modulation signal generation means. The high-frequency clock generation circuit 10 generates a high-frequency clock VCLK serving as a reference for the pixel clock PCLK, which is a basic period representing one dot. The pixel clock generator 11 is phase data that indicates the transition timing between the high-frequency clock VCLK and the pixel clock PCLK. (Indicates the phase shift amount of the pixel clock) and The pixel clock PCLK is generated based on the above. The cycle of the pixel clock PCLK changes based on the phase data. The modulation data generation circuit 12 generates modulation data representing a desired bit pattern (pulse pattern) based on image data given from outside such as an image processing unit (not shown). The phase data is also given to this modulation data generation circuit 12. The modulation data generation circuit 12 changes (corrects) the number of bits constituting the modulation data based on the phase data. The serial modulation signal generation circuit 13 receives the modulation data output from the modulation data generation unit 103, converts it into a serial pulse pattern sequence (pulse sequence) based on the high frequency clock VCLK, and outputs it as a pulse modulation signal PM. To do. The pixel clock PCLK output from the pixel clock generation circuit 11 is also supplied to the serial modulation signal generation circuit 13. The serial modulation signal generation circuit 13 inputs (loads) the modulation data output from the modulation data generation circuit 12 in synchronization with the pixel clock PCLK, thereby outputting a pulse modulation signal PM following the change in the period of the pixel clock. To do.
[0014]
If, for example, external modulation data is directly input to the serial modulation signal generation unit 104, the modulation data generation circuit 12 can be omitted.
[0015]
FIG. 2 shows a conceptual diagram of an output image of the pixel clock PCLK according to the present invention. Here, the case where the pixel clock PCLK is divided by 8 of the high frequency clock VCLK when the phase shift of the phase data is 0 is shown. As shown in FIG. 2, by providing phase data for each clock of the pixel clock PCLK, the cycle of the pixel clock PCLK changes in 1 or 1/2 clock steps of the high-frequency clock VCLK according to the value of the phase data. FIG. 2A shows an example in which the high frequency clock VCLK changes in one clock step, and FIG. 2B shows an example in which the high frequency clock VCLK changes in 1/2 clock step.
[0016]
FIG. 3 is a conceptual diagram of a pulse output (PM signal) image according to the present invention. Here, an image of outputting a pulse train corresponding to one dot is shown for easy understanding. As shown in FIG. 3, for example, when one dot is composed of 8 pulses, the pulse train can be serially output, so each of the 8 pulses is turned on (for example, black) and off (for example, black). By arbitrarily setting it to (white), it is possible to output a desired pulse at a desired position in one dot. Of course, it goes without saying that the present invention is not limited to one dot width.
[0017]
FIG. 4 is a conceptual diagram showing the relationship between the pixel clock PCLK and the pulse modulation signal PM according to the present invention. The serial modulation signal generation circuit 13 inputs (loads) modulation data at the rising edge of the pixel clock PCLK, converts it into a serial pulse train based on the high frequency clock, and outputs it as a pulse modulation signal PM. In the figure, black indicates 1 (ON) and white indicates 0 (OFF). FIG. 4A shows a case where the phase shift is 0, and the pixel clock PCLK is also divided by 8 of the high-frequency clock PCLK. Similarly, one dot (one pixel) is composed of eight pulse trains. FIG. 4B shows an example in which the phase shift is −1 and the pixel clock PCLK is divided by 7 (7/8), and the phase shift is +1 and the pixel clock PCLK is divided by 9 Indicates. As shown in FIG. 4B, the pulse train of the pulse modulation signal PM also changes in accordance with the change in the cycle of the pixel clock PCLK. In this case, the pulse output frequency in the pulse train is kept constant or the pulse output pattern in the pulse train is not changed as much as possible (in FIG. 4B, 4/8 → 3/7, 4/8 → 5/9). ). This is realized by making the bits constituting the modulation data variable according to the phase data.
[0018]
Hereinafter, a configuration example of each unit of the pixel clock and pulse modulation signal generation device of the present invention will be described in detail.
First, the pixel clock generation circuit 11 will be described. FIG. 5 shows a configuration diagram of a first embodiment of the pixel clock generation circuit. In FIG. 5, the pixel clock generation circuit 11 includes a counter 111, a comparison circuit 112, and a pixel clock control circuit 113. As described above, the high frequency clock generation circuit 10 generates the high frequency clock VCLK serving as a reference for the pixel clock PCLK. The counter 111 is a counter that operates at the rising edge of the high frequency clock VCKL and counts the VCKL. The comparison circuit 112 compares the counter value with a preset value and phase data indicating the phase shift amount as the transition timing of the pixel clock given from the outside, and outputs the control signal a and the control signal b based on the comparison result To do. The pixel clock control circuit 113 controls the transition timing of the pixel clock PCLK based on the control signals a and b.
[0019]
Here, the phase data is used to correct the scanning unevenness caused by the characteristics of the scanning lens, to correct the dot positional deviation due to the rotational irregularity of the polygon mirror, and to correct the dot positional deviation caused by the chromatic aberration of the laser beam. Data for indicating the amount of phase shift, and is generally given as a digital value of several bits. This will be described later.
[0020]
The operation of the pixel clock generation circuit of FIG. 5 will be described with reference to the timing chart of FIG. Here, the pixel clock PCLK is divided by 8 of the high-frequency clock VCLK, and the duty ratio is 50% as a standard. FIG. 6A shows how a standard pixel clock PCLK with a duty ratio of 50% corresponding to VCLK divided by 8 is generated, and FIG. 6B shows only 1/8 clock with respect to VCLK divided by 8 clock. FIG. 6C shows a state in which the PCLK with the advanced phase is generated, and FIG. 6C shows a state in which the PCLK clock whose phase is delayed by 1/8 clock with respect to the VCLK divided by 8 is generated. Phase data “7”, “8”, and “6” correspond to phase shifts “0”, “+1”, and “−1”, respectively.
[0021]
First, FIG. 6A will be described. Here, a value of “7” is given as the phase data. In the comparison circuit 112, “3” is set in advance. The counter 111 operates at the rising edge of the high frequency clock VCLK and performs counting. The comparison circuit 112 first outputs the control signal a when the value of the counter 111 reaches “3”. Since the control signal a is “H”, the pixel clock control circuit 113 changes the pixel clock PCLK from “H” to “L” at the timing of the clock (a). Next, the comparison circuit 112 compares the given phase data with the counter value, and outputs a control signal b if they match. In FIG. 6A, when the value of the counter 111 reaches “7”, the comparison circuit 112 outputs the control signal b. Since the control signal b is “H”, the pixel clock control circuit 113 changes the pixel clock PCLK from “L” to “H” at the timing of the clock (b). At this time, the comparison circuit 112 simultaneously resets the counter 111 and starts counting from 0 again. Thereby, as shown in FIG. 6A, the pixel clock PCLK having a duty ratio of 50% corresponding to the frequency division of the high frequency clock VCLK by 8 can be generated. Note that if the set value of the comparison circuit 112 is changed, the duty ratio changes.
[0022]
Next, FIG. 6B will be described. Here, it is assumed that “8” is given as the phase data. The counter 111 counts the high frequency clock VCLK. The comparison circuit 112 first outputs the control signal a when the value of the counter 111 reaches “3”. Since the control signal a is “H”, the pixel clock control circuit 113 changes the pixel clock PCLK from “H” to “L” at the timing of the clock (a). Next, the comparison circuit 112 outputs the control signal b when the value of the counter 111 coincides with the given phase data (here, 8). Since the control signal b is “H”, the pixel clock control circuit 113 changes the pixel clock PCLK from “L” to “H” at the timing of the clock (b). At this time, the comparison circuit 112 simultaneously resets the counter 111 and starts counting from 0 again. Thereby, as shown in FIG. 6B, it is possible to generate the pixel clock PCLK in which the phase is advanced by 1/8 clock with respect to the divide-by-8 clock of the high-frequency clock VCLK.
[0023]
Next, FIG. 6C will be described. Here, “6” is given as the phase data. The counter 111 counts the pixel clock VCLK. The comparison circuit 112 first outputs the control signal a when the value of the counter 111 reaches “3”. Since the control signal a is “H”, the pixel clock control circuit 113 changes the pixel clock PCLK from “H” to “L” at the timing of the clock (a). Next, the comparison circuit 112 outputs a control signal b when the value of the counter 111 coincides with the given phase data (here, 6). Since the control signal b is “H”, the pixel clock control circuit 113 changes the pixel clock PCLK from “L” to “H” at the timing of the clock (b). At this time, the counter 111 is reset at the same time to start counting from 0 again. As a result, as shown in FIG. 6C, it is possible to generate the pixel clock PCLK whose phase is delayed by 1/8 clock with respect to the divide-by-8 clock of the high-frequency clock VCLK.
[0024]
For example, by providing the phase data in synchronization with the rising edge of the pixel clock PCLK, the phase of the pixel clock PCLK can be changed for each clock. FIG. 7 is a timing chart showing this.
[0025]
According to the present embodiment, the phase of the pixel clock PCLK can be controlled in the ± direction in units of the clock width of the high frequency clock VCLK with a simple configuration. Further, by making the number of bits of the phase data the same as the number of count bits of the counter 111, the comparison circuit 112 has a simpler configuration.
[0026]
FIG. 8 shows a configuration diagram of the pixel clock generation circuit 11 according to the second embodiment. FIG. 8 is obtained by adding a phase data decoding circuit 114 to the configuration of FIG. Here, it is assumed that the phase data corresponds to the phase shift amount as shown in FIG. The phase data decoding circuit 114 obtains a counter value corresponding to the phase shift amount from the inputted phase data, and outputs it to the comparison circuit 112. In this way, the phase data does not need to have the bit width of the counter 111 as its bit width. For example, when the pixel clock generation circuit is incorporated in a chip, the number of pins can be reduced. The configuration of the comparison circuit 112 may be the same as that in FIG. The operation of FIG. 8 is the same as that of FIG.
[0027]
FIG. 10 shows a configuration diagram of the pixel clock generation circuit 11 according to the third embodiment. FIG. 10 is obtained by adding a phase data storage circuit 115 for storing a plurality of phase data in the configuration of FIG. In the phase data storage circuit 115, a plurality of phase data are set in advance from the outside, and one phase data is sequentially read out in synchronization with the pixel clock PCLK and supplied to the comparison circuit 112. Although omitted in FIG. 10, the phase data storage circuit 115 has a built-in address counter.
[0028]
Thus, for example, in the case of data that has the same phase data for each line, such as phase data for correcting scanning unevenness caused by the characteristics of the scanning lens, the phase data storage circuit 115 stores in advance one line worth of data. If the phase data is stored and the phase data is sequentially read from the head address of the phase data storage circuit 115 every time the line is scanned and supplied to the comparison circuit 112, the same phase data is output from the outside for each line. This is unnecessary, and the burden on the external control circuit can be reduced.
[0029]
FIG. 11 is a configuration diagram of the pixel clock generation circuit 11 according to the fourth embodiment. FIG. 11 is obtained by adding a phase data storage circuit 115 for storing a plurality of phase data before the phase data decoding circuit 114 in the configuration of FIG. That is, this embodiment is a combination of the second and third embodiments. A plurality of phase data is set in advance in the phase data storage circuit 115 in advance, and one phase data is sequentially read out in synchronization with the pixel clock PCLK. The phase data decoding circuit 114 receives the phase data read from the phase data storage circuit 115, obtains a counter value corresponding to the phase shift amount, and outputs it to the comparison circuit 112.
[0030]
Thus, for example, in the case of data that has the same phase data for each line, such as phase data for correcting scanning unevenness caused by the characteristics of the scanning lens, the phase data storage circuit 115 stores in advance one line worth of data. If the phase data is stored and the phase data is sequentially output from the head address of the phase data storage circuit 115 each time the line is scanned, it is not necessary to output the same phase data for each line from the outside. Less burden. Further, since the phase data and the output of the decoding circuit correspond to each other as shown in FIG. 9, for example, the bit width of the phase data is small and the storage capacity of the phase data storage circuit 115 is small, which is effective for chip size and cost. is there.
[0031]
FIG. 12 shows a configuration diagram of a fifth embodiment of the pixel clock generation circuit 11. FIG. 12 is obtained by adding a phase data synthesis circuit 116 to the configuration of FIG. A plurality of pieces of phase data (2) are set in the phase data storage circuit 115 in advance, and sequentially read out one by one in synchronization with the pixel clock VCLK as one input of the phase data synthesis circuit 116. As the other input of the phase data synthesizing circuit 116, for example, phase data (1) is given for each line from the outside. The phase data synthesis circuit 116 synthesizes phase data (1) given from the outside and phase data (2) output from the phase data storage circuit 115 and outputs the phase data to the comparison circuit 112. Here, the phase data synthesis circuit 17
Phase data = phase data (1) + phase data (2) -7
Perform calculations like
[0032]
In this way, for example, not only the same correction is always performed for each line that corrects the scanning unevenness caused by the characteristics of the scanning lens, but also the correction that changes for each line such as the rotational unevenness of the polygon mirror is supported. can do.
[0033]
FIG. 13 shows a configuration diagram of the pixel clock generation circuit 11 according to the sixth embodiment. FIG. 13 is obtained by adding a phase data decoding circuit 115 to the output side of the phase data synthesizing circuit 116 in the configuration of FIG. The phase data synthesizing circuit 116 synthesizes the phase data (1) given from the outside and the phase data (2) output from the phase data storage circuit 115 and outputs them to the phase data decoding circuit 114. In this case, the phase data synthesis circuit 116
Phase data = phase data (1) + phase data (2)
Perform calculations like The phase data decoding circuit 114 receives the phase data from the phase data synthesizing circuit 116, obtains a counter value corresponding to the phase shift amount, and outputs it to the comparison circuit 13, as shown in FIG.
[0034]
In this way, for example, not only the same correction is always performed for each line that corrects the scanning unevenness caused by the characteristics of the scanning lens, but also the correction that changes for each line such as the rotational unevenness of the polygon mirror is supported. can do. Further, since the phase data corresponds as shown in FIG. 5, for example, the bit width is small, the storage capacity of the phase data storage circuit 16 is small, and the chip size and cost are effective.
[0035]
As described above, in each embodiment, it has been described that the counter 111 operates at the rising edge of VCLK. However, the same can be realized by operating the counter 111 at the falling edge of VCLK.
[0036]
FIG. 14 shows a configuration diagram of a seventh embodiment of the pixel clock generation circuit 11. In all the embodiments so far, the pixel clock cycle is changed at one clock pitch of the high-frequency clock, but in this embodiment, the pixel clock cycle is changed at ½ clock pitch of the high-frequency clock.
[0037]
In FIG. 14, the pixel clock generation circuit 11 includes a transition detection circuit (1) 121, a control signal generation circuit (1) 122, a clock 1 generation circuit 123, a transition detection circuit (2) 124, and a control signal generation circuit (2) 125. , A clock 2 generation circuit 126, a multiplexer 127, a control data generation circuit 128, a status signal generation circuit 129, and a select signal generation circuit 130.
[0038]
The high frequency clock generation circuit 10 generates a high frequency clock VCLK serving as a reference for the pixel clock PCLK. The transition detection circuit (1) 121 operates at the rising edge of the high frequency clock VCLK, detects the rising edge of the clock 1 signal, and outputs a pulse signal having a width of 1 clock of the high frequency clock VCLK. The control signal generation circuit (1) 122 operates at the rising edge of the high-frequency clock VCLK. Based on the output signal of the transition detection circuit (1) 121 and the control data 1 output from the control data generation circuit 128, the control signal 1a and the control signal 1b is output. The clock 1 generation circuit 14 operates at the rising edge of the high-frequency clock VCLK, and generates the clock 1 based on the control signal 1a and the control signal 1b. The transition detection circuit (2) 124 operates at the falling edge of the high frequency clock VCLK, detects the rising edge of the clock 2 signal, and outputs a pulse signal having one clock width of the high frequency clock VCLK. The control signal generation circuit (2) 125 operates at the falling edge of the high-frequency clock VCLK. Based on the output signal of the transition detection circuit (2) 124 and the control data 2 output from the control data generation circuit 128, the control signal 2a and the control signal The signal 2b is output. The clock 2 generation circuit 126 operates at the falling edge of the high frequency clock VCLK and generates the clock 2 based on the control signal 2a and the control signal 2b. The multiplexer 127 selects the clock 1 and the clock 2 based on the select signal from the select signal generation circuit 130 and outputs it as the pixel clock PCLK.
[0039]
The control data generation circuit 128 outputs control data 1 and control data 2 based on phase data given from the outside and a status signal output from the status signal generation circuit 129. As described above, the phase data corrects the scanning unevenness caused by the characteristics of the scanning lens, corrects the dot positional deviation caused by the rotational irregularity of the polygon mirror, and corrects the dot positional deviation caused by the chromatic aberration of the laser beam. This is data for instructing the shift amount of the phase of the pixel clock for correction. Here, it has a 3-bit configuration, and the phase shift amount and the phase data are made to correspond as shown in FIG.
[0040]
When bit 0 of the phase data is 1, the status signal generation circuit 129 toggles the signal at the rising timing of the pixel clock PCLK and outputs it as a status signal. As a result, the status signal indicates the first state when the pixel clock PCLK rises when the high frequency clock VCLK rises, and the second state when the pixel clock PCLK falls when the high frequency clock VCLK falls. It becomes like this. Here, the status signal is “0” when the pixel clock PCLK is rising at the rising edge of the high frequency clock VCLK, and is “1” when the pixel clock PCLK is falling at the falling edge of the high frequency clock VCLK.
[0041]
When the bit 0 of the phase data is 1, the select signal generation circuit 130 toggles the signal at the falling timing of the pixel clock PCLK and outputs it as a select signal.
[0042]
15 and 16 show configuration examples of the clock 1 generation circuit 123 and the clock 2 generation circuit 126 in FIG. FIG. 15 includes a JK flip-flop (JK-FF), and the JK-FF 123a forming the clock 1 generation circuit 123 operates at the rising edge of the high frequency clock VCLK to form the clock 2 generation circuit 126. The JK-FF 126a operates at the falling edge of the high frequency clock VCLK. FIG. 16 is composed of a D-type Philip flop (D-FF) with a clock synchronous set reset, and the D-FF 123b forming the clock 1 generation circuit 123 operates at the rising edge of the high frequency clock VCLK to generate the clock 2 The D-FF 126b forming the circuit 126 operates at the falling edge of the high frequency clock VCLK.
[0043]
15 and 16 operate in the same manner. When the control signal 1a is "H" and the control signal 1b is "L", "L" is output to the clock 1 at the rising edge of the high-frequency clock VCLK. When the control signal 1a is "L" and the control signal 1b is "H", "H" is output to the clock 1 at the rising edge of the high frequency clock VCLK. When the control signal 2a is "H" and the control signal 2b is "L", "L" is output to the clock 2 at the falling edge of the high frequency clock VCLK. When the control signal 2a is "L" and the control signal 2b is "H", "H" is output to the clock 2 at the falling edge of the high frequency clock VCLK.
[0044]
FIG. 17 shows a configuration example of the control signal generation circuit (1) 122 and the control signal generation circuit (2) 125 in FIG. As shown in FIG. 17, the control signal generation circuit (1) 122 and the control signal generation circuit (2) 125 are constituted by a shift register and a multiplexer. However, the shift register (1) in the control signal generation circuit (1) 122 operates at the rising edge of the high frequency clock VCLK, and the shift register (2) in the control signal generation circuit (2) 125 operates at the falling edge of the high frequency clock VCLK. . The shift register (1) and the shift register (2) shift the input detection signal 1 and detection signal 2. Then, the register output S12 is output as the control signal 1a, and the register output S22 is output as the control signal 2a. The register outputs S13 to S19 are given to the multiplexer (1), and the register outputs S23 to S29 are given to the multiplexer (2). The multiplexer (1) selects one of the register outputs S13 to S19 according to the given control data 1 and outputs it as the control signal 1b. The multiplexer (2) selects one of the register outputs S13 to S19 according to the given control data 2 and outputs it as a control signal 2b. A truth table of the multiplexer (1) and the multiplexer (2) is shown in FIG.
[0045]
The control data generation circuit 128 in FIG. 14 decodes the phase data given from the outside and the status signal output from the status signal generation circuit 129 and outputs control data 1 and control data 2. The operation of the control data generation circuit 128 is related to the control signal generation circuit (1) 122 and the control signal generation circuit (2) 125. That is, the output of the control signal generation circuit (1) 122, the shift register (1) of the control signal generation circuit (2) 125, the output of the shift register (2) and the input of the multiplexer (1) and the multiplexer (2) shown in FIG. The decoding operation of the control data generation circuit 128 is determined by the order of
[0046]
FIG. 19 shows the correspondence between the phase shift amount and the phase data in this embodiment, and FIG. 20 shows the truth table of the control data generation circuit 128.
[0047]
Next, the operation of the configuration of FIG. 14 will be described using the timing chart of FIG. In FIG. 21, when the phase shift is 0, the pixel clock PCLK corresponding to the high-frequency clock VCLK divided by 8 is generated, and the pixel clock PCLK having the phase shifted by +1/16 PCLK and −1/16 PCLK is generated. It shows how it is.
[0048]
First, generation of a pixel clock PCLK with a phase shift of 0 will be described.
(Regarding generation of control data 1 and control data 2)
In synchronization with the pixel clock PCLK, phase data “000” indicating the phase shift 0 is given ((a) in FIG. 21). The phase data and the status signal (initially set to 0) are input to the control data generation circuit 128, and control data 1 (010) and control data 2 (010) are output according to the truth table of FIG.
[0049]
(Clock 1 generation)
In FIG. 21A, the rising edge of the clock 1 is detected by the transition detection circuit (1) 121, and as shown in FIG. 21, the detection signal 1 obtains a pulse signal of one clock width of the high frequency VCLK. This detection signal 1 is given to the shift register (1) of the control signal generation circuit (1) 122, and signals of register outputs S10 to S18 as shown in FIG. 21 are obtained. Since the control signal 1a is the register output S12 itself, it is “H” at the timing (B) in FIG. 21 and the control signal 1a is “H” at the clock timing (C) in FIG. The clock 1 generation circuit 123 shifts the clock 1 to “L” and outputs it. Since the control data 1 is “010”, the output of the register S16 appears in the control signal 1b and becomes “H” at the timing (d) in FIG. 21, and at the clock timing in (e) in FIG. Since the control signal 1b is “H”, the clock 1 generation circuit 123 shifts the clock 1 to “H” and outputs it.
[0050]
(Clock 2 generation)
In FIG. 21 (a) ′, the rising edge of the clock 2 is detected by the transition detection circuit (2) 124, and as shown in FIG. 21, the detection signal 2 obtains a pulse signal of one clock width of the high frequency VCLK. This detection signal 2 is applied to the shift register (2) of the control signal generation circuit (2) 125, and signals of register outputs S20 to S28 as shown in FIG. 21 are obtained. Since the control signal 2a is the register output S22 itself, it becomes “H” at the timing (B) ′ in FIG. 21, and the control signal 2a becomes “H” at the timing (C) ′ in FIG. Therefore, the clock 2 generation circuit 126 shifts the clock 2 to “L” and outputs it. Since the control data 2 is “010”, the output of the register S26 appears in the control signal 2b, and becomes “H” at the timing of (d) ′ in FIG. 21, and the clock signal of (e) ′ in FIG. Since the control signal 2b is “H” at the timing, the clock 2 generation circuit 126 shifts the clock 2 to “H” and outputs it.
[0051]
(Regarding generation of pixel clock PCLK)
Here, since the select signal is “L”, the clock 1 is output as the pixel clock PCLK.
[0052]
Next, the generation of the pixel clock PCLK having a phase shift of +1/16 PCLK will be described.
(Regarding generation of control data 1 and control data 2)
Phase shift in synchronization with pixel clock PCLK +1 Phase data “001” is given ((e) in FIG. 21). The status signal remains “0” without being toggled because bit0 of the previous phase data is “0”. The phase data and status signal are input to the control data generation circuit 128, and control data 1 (010) and control data 2 (001) are output according to the truth table of FIG.
[0053]
(Clock 1 generation)
In (e) of FIG. 21, the rising edge of clock 1 is detected by the transition detection circuit (1) 121, and as shown in FIG. 21, the detection signal 1 obtains a pulse signal of one clock width of the high frequency VCLK. This detection signal 1 is given to the shift register (1) of the control signal generation circuit (1) 122, and signals of register outputs S10 to S18 as shown in FIG. 21 are obtained. Since the control signal 1a is the register output S12 itself, it is “H” at the timing (f) in FIG. 21 and the control signal 1a is “H” at the clock timing (f) in FIG. The clock 1 generation circuit 123 shifts the clock 1 to “L” and outputs it. Since the control data 1 is “010”, the output of the register S16 appears in the control signal 1b and becomes “H” at the timing (H) in FIG. 21, and at the clock timing in (L) in FIG. Since the control signal 1b is “H”, the clock 1 generation circuit 123 shifts the clock 1 to “H” and outputs it.
[0054]
(Clock 2 generation)
In (e) ′ of FIG. 21, the rising edge of the clock 2 is detected by the transition detection circuit (2) 124, and as shown in FIG. 21, the detection signal 2 obtains a pulse signal of one clock width of the high frequency VCLK. This detection signal 2 is given to the shift register (2) of the control signal generation circuit (2) 125, and signals of register outputs S20 to S28 as shown in FIG. 21 are obtained. Since the control signal 2a is the register output S22 itself, it becomes “H” at the timing (f) ′ of FIG. 21, and the control signal 2a becomes “H” at the timing of the clock (g) ′ in FIG. Therefore, the clock 2 generation circuit 126 shifts the clock 2 to “L” and outputs it. Since the control data 2 is “001”, the output of the register S27 appears in the control signal 2b, and becomes “H” at the timing (H) ′ of FIG. 21, and the clock of (L) ′ of FIG. Since the control signal 2b is “H” at the timing, the clock 2 generation circuit 126 shifts the clock 2 to “H” and outputs it.
[0055]
(Regarding generation of pixel clock PCLK)
Here, since the bit 0 of the phase data is “1”, the select signal is toggled at the falling timing of the pixel clock PCLK in FIG. Therefore, at first, the clock 1 is output as the pixel clock PCLK (period (e) to (g) in FIG. 21), and after the select signal becomes “1” in (g) in FIG. It is output as the pixel clock PCLK (period (G) to (L) ′ in FIG. 21).
[0056]
Next, the generation of the pixel clock PCLK having a phase shift of −1/16 PCLK will be described.
(Regarding generation of control data 1 and control data 2)
In synchronization with the pixel clock PCLK, phase data “101” indicating phase shift −1 is given ((Li) ′ in FIG. 21). The status signal is toggled to “1” because bit 0 of the previous phase data is “1” ((re) ′ in FIG. 21). The phase data and status signal are input to the control data generation circuit 128, and control data 1 (010) and control data 2 (011) are output according to the truth table of FIG.
[0057]
(Clock 1 generation)
In FIG. 21 (i), the rising edge of the clock 1 is detected by the transition detection circuit (1) 121. As shown in FIG. 21, the detection signal 1 obtains a pulse signal of one clock width of the high frequency VCLK. This detection signal 1 is given to the shift register (1) of the control signal generation circuit (1) 122, and signals of register outputs S10 to S18 as shown in FIG. 21 are obtained. Since the control signal 1a is the register output S12 itself, it is “H” at the timing (n) in FIG. 21 and the control signal 1a is “H” at the clock timing (l) in FIG. The clock 1 generation circuit 123 shifts the clock 1 to “L” and outputs it. Since the control data 1 is “010”, the output of the register S16 appears in the control signal 1b, and becomes “H” at the timing of (e) in FIG. 21, and at the timing of the clock in (wa) in FIG. Since the control signal 1b is “H”, the clock 1 generation circuit 123 shifts the clock 1 to “H” and outputs it.
[0058]
(Clock 2 generation)
In (i) ′ of FIG. 21, the rising edge of the clock 2 is detected by the transition detection circuit (2) 124, and as shown in FIG. 21, the detection signal 2 obtains a pulse signal of one clock width of the high frequency VCLK. This detection signal 2 is given to the shift register (2) of the control signal generation circuit (2) 125, and signals of register outputs S20 to S28 as shown in FIG. 21 are obtained. Since the control signal 2a is the register output S22 itself, it becomes “H” at the timing of (nu) ′ in FIG. 21, and the control signal 2a becomes “H” at the timing of the clock in (lu) ′ of FIG. Therefore, the clock 2 generation circuit makes the clock 2 transition to “L” and outputs it. Since the control data 2 is “011”, the output of the register S25 appears in the control signal 2b, and becomes “H” at the timing of (e) ′ in FIG. 21, and the clock of the (wa) ′ in FIG. Since the control signal 2b is “H” at the timing, the clock 2 generation circuit 126 shifts the clock 2 to “H” and outputs it.
[0059]
(Regarding generation of pixel clock PCLK)
Here, since the bit 0 of the phase data is “1”, the select signal is toggled at the falling timing of the pixel clock PCLK in FIG. Therefore, at first, the clock 2 is output as the pixel clock PCLK (period (L) ′ to (L) ′ in FIG. 21), and after the select signal becomes “0” in (L) ′ in FIG. The clock 1 is output as the pixel clock PCLK (period (L) ′ to (W) in FIG. 21).
[0060]
Although only phase shifts 0, +1/16 PCLK, and −1/16 PCLK have been described here, +2/16 PCLK, +3/16 PCLK, −2/16 PCLK, and −3/16 PCLK can be similarly performed.
[0061]
As described above, according to the present embodiment, it is possible to obtain the pixel clock PCLK whose phase is shifted by ± 1/16 PCLK step by one clock, that is, by a half pitch step of the high frequency clock VCLK.
[0062]
In FIG. 14, if a clock obtained by inverting the high-frequency clock VCLK is given to the transition detection circuit (2) 124, the control signal generation circuit (2) 125, and the clock 2 generation circuit 126, these transition detection circuits (2 ) 124, the control signal generation circuit (2) 125, and the clock 2 generation circuit 126 can be configured with the same components as the transition detection circuit (1) 121, the control signal generation circuit (1) 122, and the clock 2 generation circuit 123. Cost is reduced.
[0063]
FIG. 22 shows a configuration diagram of an eighth embodiment of the pixel clock generation circuit 11. FIG. 22 is obtained by adding a phase data storage circuit 131 for storing a plurality of phase data in the configuration of FIG. In the phase data storage circuit 131, as described in the third embodiment (FIG. 10), a plurality of phase data are set in advance from the outside, and one phase data is sequentially sequentially synchronized with the pixel clock PCLK. Read and supply to the control data generation circuit 19. Although omitted in FIG. 22, the phase data storage circuit 131 has a built-in address counter.
[0064]
Thus, for example, in the case of data that has the same phase data for each line, such as phase data for correcting scanning unevenness caused by the characteristics of the scanning lens, the phase data storage circuit 131 stores in advance one line worth of data. If the phase data is stored and the phase data is sequentially read from the head address of the phase data storage circuit 131 each time the line is scanned and supplied to the control data generation circuit 128, the same phase data is externally given to each line. There is no need for output, and the burden on the external control circuit can be reduced.
[0065]
FIG. 23 shows a configuration diagram of the ninth embodiment of the pixel clock generation circuit 11. FIG. 23 is obtained by adding a phase data synthesis circuit 132 to the configuration of FIG. In the phase data storage circuit 132, as described in the fifth embodiment (FIG. 12), a plurality of phase data (2) is set in advance from the outside, and one phase data is sequentially stored in synchronization with the pixel clock PCLK. Each phase data is read out and used as one input of the phase data synthesis circuit 132. As the other input of the phase data synthesis circuit 132, for example, phase data (1) is given for each line from the outside. The phase data synthesis circuit 132 synthesizes phase data (1) given from the outside and phase data (2) output from the phase data storage circuit 131 and outputs the phase data to the control data generation circuit 128. Here, when the phase shift amount and the phase data correspond as shown in FIG. 19, the phase data synthesis circuit 132 performs the following calculation.
Phase data = phase data (1) + phase data (2)
In this way, for example, not only always the same correction is performed for each line that corrects the scanning unevenness caused by the characteristics of the scanning lens, but also the correction that changes for each line such as the rotational unevenness of the polygon mirror. Can respond.
[0066]
Next, the modulation data generation circuit 12 and the serial modulation signal generation circuit 13 in FIG. 1 will be described.
FIGS. 24 to 26 show examples of pulses generated by using a conventional pulse width modulation circuit when, for example, one dot is composed of eight pulses. Here, FIG. 24 shows an example of forming a pulse from the right, FIG. 25 shows an example of forming a pulse from the left, and FIG. 26 shows an example of forming a pulse from the inside. Thus, conventionally, it has been practically impossible to output a desired pulse at a desired position. Even if it was possible, a complicated configuration was required.
[0067]
FIG. 27 shows a specific example of a pulse output image according to the present invention. Here, since it becomes complicated as the number of pulses increases, an example of a pulse output in which one dot is constituted by 4 bits, that is, 4 pulses P1 to P4 is shown. As shown in FIG. 27, according to the modulation data generation circuit 12 and the serial modulation signal generation circuit 13 of the present invention, a pulse can be output at an arbitrary position of one dot. = 16 patterns of pulse trains can be output. Similarly, 25 = 32 outputs for 5 pulses, 26 = 64 outputs for 6 pulses, and so on are possible. Such an arbitrary pattern pulse train can be easily generated by using, for example, a look-up table (LUT).
[0068]
FIG. 28 shows an embodiment in which an LUT is used for the modulation data generation circuit 12 of FIG. FIG. 28 shows a configuration example when the 16 bits pattern of 4 bits shown in FIG. 27, that is, 4 pulses P1 to P4, is stored in the lookup table (LUT) 1221. In FIG. 28, the LUT 1221 is composed of a total of 64 bits, 4 bits in the horizontal direction and 16 columns in the vertical direction, and 16 addresses from 0000 to 1111 are given respectively. Therefore, by inputting image data as address data, it is possible to output bit strings (pulse strings) P1 to P4 having a desired pattern as modulation data. As can be seen from FIG. 27, the output of the image data “0000” and “1111” is inverted. Similarly, the output of the image data “0001” and “1110” is inverted. If a certain image data bit is an inverted signal, the LUT 1221 does not need 16 columns, and 8 columns are sufficient. In this way, by using the data inversion signal, it is possible to save the memory in half, and it is possible to reduce the size and cost. If a plurality of LUTs having different contents (bit patterns) for the same image data are prepared and selected by the value of the phase data, the number of bits (bits) of the modulation data can be easily determined based on the phase data. Pattern) can be changed.
[0069]
Here, the LUT may be configured using any memory such as ROM, DRAM, SRAM, etc. For example, when configured using DRAM, the LUT has a feature that can be reduced in size when the present invention is made into an ASIC. There is a feature that the speed can be increased regardless of whether it is an ASIC in the case of using an SRAM, and it may be selected according to the demand.
[0070]
The modulation data generation circuit 12 of FIG. 1 does not necessarily have to be configured by the LUT as described above, and can be configured by decoding of a logic gate array, for example.
FIG. 29 shows a conceptual diagram when the modulation data generating circuit 12 is configured by a decoder. FIG. 29 shows an image in which 8 pulse trains of 4 bits, that is, 4 pulses P1 to P4 are output with respect to 3 bits of image data. This assumes that the image data is given by D {2,1,0}
P1 = D2
P2 = D2B, D1, D0 + D2, D1B + D2, D1, D0B
P3 = D2B · D1 + D2 · D1B
P4 = D2B ・ D1B ・ D0 + D2B ・ D1 ・ D2 ・ D1B ・ D0B
(D0B, D1B, and D2B represent inversions of D0, D1, and D2, respectively)
This is possible by configuring the logic. This logic can be realized by a combination of AND and OR gates such as AND and OR, and can be configured without using the LUT described above.
[0071]
The serial modulation signal generation circuit 13 shown in FIG. 1 receives the modulation data output from the modulation data generation circuit 12 constituted by the LUT and the decoder as described above, and converts it into a serial pulse train. FIG. 30 shows a configuration example of the serial modulation signal generation circuit 13. In FIG. 30, the serial modulation signal generation circuit 13 is configured using a shift register. In the case of FIG. 30, the shift register 1310 includes four flip-flops (FF) or latches 1311. The modulation data P1 to P4 are input (loaded) in parallel, and the pulse train is serially input according to the high-frequency clock. The pulse modulation signal PM is obtained by outputting.
[0072]
31 and 32 show specific configuration examples of the shift register used in the serial modulation signal generation circuit 13. In FIG. 31, a shift register is configured using a set-reset type FF1321, and data loading is performed by setting or resetting. FIG. 32 shows a configuration example using an FF 1332 and a multiplexer (MUX) 1331, which determines whether to shift data to the next FF 1332 or to set (load data) in the MUX 1331 according to the LOAD signal.
[0073]
FIG. 33 shows an overall configuration diagram of an embodiment of the high-frequency clock generation circuit 10, the modulation data generation circuit 12, and the serial modulation signal generation circuit 13 shown in FIG.
In FIG. 33, the high frequency clock generation circuit 10 includes a phase comparator 101, a loop filter 102, a voltage controlled oscillator (VCO) 103, and a frequency divider 104. This is a so-called PLL circuit, which can generate a high-speed high-frequency clock VCLK that is phase-adjusted to a reference reference clock (for example, pixel clock) REFCLK and is N times the frequency of the clock REFCLK. It is. This VCLK has a duty of about 50%, for example. The high frequency clock generation circuit 10 is not limited to a PLL circuit, and may have any configuration as long as it can generate a high frequency clock. For example, a high frequency clock may be generated using a digital frequency synthesizer or the like. Further, the high-frequency clock generation circuit 10 generates a multiphase clock as necessary, as will be described later.
[0074]
The modulation data generation circuit 12 includes a register 1210, an LUT 1220, a decoder 1230, a selection circuit 1240, and the like. Image data input from the outside is latched in the register 121 at the timing of the pixel clock, and is input to both the LUT 1220 and the decoder 1230 at the timing of the load signal LOAD that is also synchronized with the pixel clock. The LUT 1220 and the decoder 1230 independently convert the image data into modulation data having a desired bit pattern (pulse pattern). The selection circuit 1240 selects either modulation data output from the LUT 1220 or modulation data output from the decoder 1230 based on the mode selection signal, and outputs the selected data to the serial modulation signal generation circuit 13.
[0075]
Thus, by using the LUT 1220 and the decoder 1230 properly according to the mode selection signal, the degree of freedom is greater, and various modulation data can be generated for the image data. Of course, only one of the LUT 1220 and the decoder 1230 may be used.
[0076]
In addition, as described with reference to FIG. 26, when the data inversion signal is input to the LUT 1220, the LUT memory can be configured in a small size. Further, as described above, if a plurality of LUTs are provided and the phase data value is selected, the number of bits of the modulation data can be changed (adjusted) according to the phase shift. Furthermore, if a configuration is used in which pulse trains are sequentially output from a plurality of LUTs using a high-resolution mode signal, a configuration capable of outputting a long pulse train while realizing a small LUT memory can be realized. This will be described later. Similarly, a plurality of decoders may be configured.
[0077]
The serial modulation signal generation circuit 13 includes the shift register 1300 as shown in FIGS. The shift register 1300 loads the modulation data output from the modulation data generation circuit 12 in parallel according to the load signal LOAD (pixel clock PCLK), and sequentially performs a shift operation in synchronization with the high frequency clock VCLK from the high frequency clock generation circuit 10. By doing so, a pulse modulation signal of a serial pulse train corresponding to the bit pattern of the modulation data is output. The shift register 1300 can have various configurations depending on the number of bits (number of pulses) of the modulation data.
[0078]
FIG. 34 shows a configuration example when the serial modulation signal generation circuit 13 is configured by a two-stage (column) shift register. In FIG. 34, the high frequency clock VCLK and the load signal LOAD1 are input to the upper shift register 1301, and the inverted clock VCLKB and the load signal LOAD2 of the VCLK are input to the lower shift register 1302, respectively. A pulse train is serially output via a multiplexer (MUX) 1309 according to a load signal synchronized with the high frequency clock. In this example, the modulation data is composed of 8-bit pulse trains P1 to P8, of which P1, P3, P5, and P7 are sequentially loaded into the upper row shift register 1301 at the timing of LOAD1, and the lower row shift register 1302 is loaded. P2, P4, P6, and P8 are loaded in order at the timing of LOAD2, are shifted by VCLK and VCLKB, and are sequentially switched and output by MUX 1309, so that P1, P2, P3, P4, P5, P6 , P7, and P8 in this order.
[0079]
In the case of the configuration as shown in FIG. 34, it is possible to serially output a pulse train at a speed twice that of the high-frequency clock VCLK, thereby realizing higher-speed or high-resolution pulse modulation signal generation. Alternatively, if VCLK is the original clock of the clock generation circuit, the high frequency clock can be expressed as a clock having a speed twice that of the original clock. The generation of the clock VCLK and its inverted clock VCLKB will be described later.
[0080]
FIG. 35 shows a configuration example in the case where the configuration of FIG. 34 is developed and the serial modulation signal generation circuit 13 is configured by a four-stage (column) shift register. Four-phase clocks VCLK1, VCLK2, VCLK3, and VCLK4 having different phases from the top are applied to the shift registers 1301 to 1304 in each column, and load signals LOAD1, LOAD2, LOAD3, and LOAD4 synchronized with the respective clocks are input. The In this example, the modulation data consists of 16-bit pulse trains P1 to P16, of which P1, P5, P9, P13 are in the first shift register 1301, and P2, P6 are in the second shift register 1302. P10, P14, P3, P7, P11, P15 are set in the third column shift register 1303, and the data of P4, P8, P12, P16 are set in the fourth column shift register 1304, respectively. 4 are sequentially selected, so that a pulse train is serially output in the order of P1, P2, P3... P15, P16.
[0081]
FIG. 37 shows an example of a four-phase clock. As shown in FIG. 37, if VCLK1, VCLK2, VCLK3, and VCLK4 having different phases every π / 2 (90 degrees) are used, even if a clock having a frequency four times that of VCLK is not generated, FIG. It is possible to selectively output pulse trains sequentially from the four shift registers 1301 to 1304 shown. Furthermore, if a multi-phase high-frequency clock having different phases for each of π / 4, π / 8,... Is used, a pulse train can be output from a larger number of shift registers. Therefore, even if the basic frequency of the high-frequency clock is low, it is possible to output many pulses serially with a simple configuration by selecting the data based on the high-frequency clock of multiple phases. Thus, it becomes possible to support high resolution. The generation of the multiphase clock will be described later.
[0082]
FIG. 36 shows another configuration example in the case where the serial modulation signal generation circuit 13 is configured by a four-stage (column) shift register. The basic operation principle of FIG. 36 is the same as that of FIG. 35. However, in the configuration of FIG. 36, all shift registers 1301 to 1304 are operated by one VCLK1 and a load signal LOAD1 synchronized with the clock. Based on VCLK1 to VCLK4, the phases of the outputs of the shift registers 1301 to 1304 are adjusted.
[0083]
As shown in FIG. 37, the data S1, S2, S3, S4 output from the shift registers 1301-1304 are output in synchronization with VCLK1. For this reason, for example, if the output S1 of the shift register 1301 is to output data at the rising edge of VCLK1 and the falling edge of VCLK2, the pulse cannot be latched because there is an indefinite part, but as shown in the figure, the phase adjustment In the circuit 1308, if S1 is latched by VCLK4 to S1 ′ and further latched by VCLK3 to S1 ″, a configuration in which data can be latched at the rising edge of VCLK1 and the falling edge of VCLK2 can be realized.
[0084]
The operation of the MUX unit 1309 is basically the same as the case of FIG. 35. As described above, by selecting and selecting a clock that can stably latch the output of the shift register, the configuration example of FIG. It is possible to convert the output of the shift register into a serial pulse train.
[0085]
In the configuration example of FIG. 36, a phase adjustment unit that adjusts the phase of the shift register output is required. However, the same clock and one load pulse LOAD1 synchronized with the clock are supplied to the four shift registers. A simple configuration can be realized. Here, only a configuration example of up to four shift registers is shown, but a serial pulse train can be generated from a plurality of shift registers with the same configuration. In the configuration example, the number of pulses per shift register is set to 4 for simplicity. However, the number of pulses may be any number, and the number of pulses is arbitrary depending on the resolution of one pulse, the method of generating a high-frequency clock, and the like. You just have to decide.
[0086]
FIG. 38 shows a configuration example of an LUT suitable for the above-described high resolution mode. This is a configuration example using two (two sides) LUTs 1221 having a 4-bit × 16-column configuration shown in FIG. Address data is given to each LUT (1) 1221 and LUT (2) 1222 in 5 bits, but the most significant bit is used to select LUT (1) 1221 and LUT (2) 1222, and the lower 4 bits. Are used to select the column of the LUT. Here, the above-described high resolution mode signal (see FIG. 21) is used for selection of the LUT (1) 1221 and the LUT (2) 1222.
[0087]
In the configuration example of FIG. 38, in the high resolution mode, the load signal is given, for example, twice in one dot. First, in synchronization with the first load signal, “0” is input for the high resolution mode and 4 bits are input for the image data. Address data is composed of a total of 5 bits of the high resolution mode signal and 4 bits of image data. Since the high resolution mode signal is “0”, LUT (1) 1221 is selected and the LUT (1) is selected. 4 bits of the desired column of 1221 are output. Subsequently, in synchronization with the second load signal, the high resolution mode signal becomes “1”, and similarly, 4 bits of image data are input. As a result, the LUT (2) 1222 is selected, and 4 bits of the desired column of the LUT (2) 1222 are output. As described above, in the high resolution mode, modulation data of a total of 8 bits can be generated using both the LUT (1) 1221 and the LUT (2) 1222. Each 4-bit data output from the LUT (1) 1221 and the LUT (2) 1222 is sequentially loaded into a shift register as shown in FIGS. 30 to 32, for example, and converted into a serial pulse train. Thereby, for example, a pulse modulation signal of 8 pulses per bit is output.
[0088]
In the normal mode, the load signal is, for example, one time per dot, the high resolution mode signal is “0”, and the image data is only 4 bits. As a result, LUT (1) 1221 is selected, and 4-bit data of the desired column is output. This is the same as the case of the LUT 1221 in FIG.
[0089]
If an LUT capable of outputting a total of 8 bits (8 pulses) as shown in FIG. 38 is to be configured by one, it is necessary to prepare 28 = 256 columns of LUTs. However, as in the configuration example of FIG. If two LUTs in a row (two sides) are prepared, 256 outputs can be configured with 32 rows of LUTs, and memory can be reduced in size and energy can be reduced. Also, the configuration of the shift register need not be changed basically between the normal mode and the high resolution mode.
[0090]
FIG. 39 shows another configuration example of the LUT suitable for the above-described high resolution mode. This is a configuration example in the case where it is desired to further change the number of pulses in addition to the high resolution mode. In FIG. 39, LUT (1) 1221 and LUT (2) 1222 with 14 bits × 216 columns, 14 bits × 214 columns It shows that a total of six LUTs are used, that is, LUT (3) 1223 and LUT (4) 1224 having a configuration, and LUT (5) 1225 and LUT (6) 1226 having a configuration of 18 bits × 218 columns. The address consists of 19 bits for LUT (1) 1221 and LUT (2) 1222, 17 bits for LUT (3) 1223 and LUT (4) 1224, and 21 bits for LUT (5) 1225 and LUT (6) 1226. The Of these addresses, the upper 3 bits are used to select the LUT (1) 1221 to LUT (6) 1226. Specifically, among the upper 3 bits of the address, the most significant bit and the 2nd bit are used to select a set of LUTs whose output bit number is 6 bits, 14 bits, or 18 bits. The bit is used to select either LUT in the set of LUTs. The above-described high resolution mode signal is used for the third bit, and in the high resolution mode, two LUTs of a set selected by the upper 2 bits can be used.
[0091]
In the configuration example of FIG. 39, output modulation data can be arbitrarily selected from six types of 14, 16, 18, 28, 32, and 36 bits by a combination of the high resolution mode signal and the upper 2 bits of the address. Become. LUT selection is easy, for example, by placing an address decoder in front of LUT (1) 1221 to LUT (6) 1226, decoding the upper 3 bits of the address with the address decoder, and selecting the LUT based on the decoding result. Is possible. Further, if the number of bits of the address used for selecting the LUT is increased, the combination of selecting the LUT is adjusted, and as a result, the combination of the number of bits of the output modulation data is also increased.
[0092]
In the configuration example of FIG. 39, the operation in the high resolution mode is basically the same as the configuration example of FIG. That is, the high resolution mode signal is “0” for the first load signal and “1” for the second load signal. The upper 2 bits of the address are set according to the required number of bits of modulation data. For example, when the upper 2 bits are “00”, LUT (1) 1221 is selected in the first load signal, 16-bit data in the desired column is output, and LUT (2) 1222 is output in the second load signal. Is selected, 16 bits of data in the desired column are output, and a total of 32 bits of modulated data are output. Similarly, when the upper 2 bits of the address are “01”, modulation data of a total of 28 bits is output by the first and second load signals.
[0093]
The configuration example of FIG. 39 shows the case where the LUT is used for the pulse train change accompanying the resolution mode switching. However, the configuration example can also be applied to the pulse train change according to the phase data. Further, it is obvious that the same thing can be carried out even if a decoder is used, and the decoder may be constituted by hardware or software. The pulse train can also be changed by adding a bit compression / expansion circuit between the LUT and the shift register, for example.
[0094]
FIG. 40 shows an embodiment of pulse train change by phase data or the like according to the present invention. FIG. 40 shows an example of converting an output pulse pattern having 16 pulses into an output pulse pattern having 14 pulses. As shown in FIG. 40, when an output pattern having 16 output pulses is output and the image forming apparatus or the like wants to obtain a desired density at a desired position, the last two pulses are left as they are. For example, in FIG. 40, since the density is 8/16 to 6/14 (considering the density with the number of pulses) in FIG. In such a case, if the data pattern change as shown by the arrow in FIG. 40 is performed using a memory or a decoder, the density will be 7/14, and in this example, the density will match. Further, even if the densities do not exactly match, by having a conversion unit that converts the density to the density closest to the density at the first 16 pulses, it is possible to minimize the density change caused by changing the number of pulses. It becomes possible.
[0095]
FIG. 41 shows another embodiment of the pulse train change according to the phase data or the like of the present invention. FIG. 41 shows an example of converting an output pulse pattern having 16 pulses into an output pulse pattern having 18 pulses. As in FIG. 40, a conversion unit for converting data is configured so that the densities in the pulse train are matched as much as possible. In this example, the conversion method from 8/16 to 9/18 is indicated by arrows. In this way, when changing the number of pulses constituting the pulse train, by having a data conversion unit according to the number of pulses, even if the number of pulses is changed, the high resolution without affecting the image density or the like. An image forming apparatus can be realized. In this example, the number of pulses is 16 as a reference for the sake of simplicity. However, since the data conversion unit can be configured with a finer pitch as the number of pulses constituting the pulse train is larger, it is possible to change the image density by changing the number of pulses. A configuration with little influence can be realized.
[0096]
FIG. 42 shows still another embodiment of the pulse train change according to the phase data or the like of the present invention. FIG. 42 shows a configuration example different from the concept of FIG. 40 and FIG. Consider the case where the number of output pulses is changed to 14, 16, and 18 as shown in the figure. The number of pulses to be output is changed to 14, 16, and 18, but only 14 pulses from the left can be actually output (white or black). In such a case, as shown in the figure, when the number of pulses is 16, the rightmost 2 pulses in the pulse train are always white, and when the number of pulses is 18, the rightmost 4 pulses in the pulse train are always white. Become. For example, in the case of a raster scanning image forming apparatus, even if the output is performed with a duty less than 100%, the light has a Gaussian distribution on the photoconductor, so that it is possible to output a solid black image. Therefore, as shown in FIG. 42, if the duty is 14 / 18≈77.8% and the number of pulses is changed without changing the data pattern, the data conversion unit may be omitted. Can be realized.
[0097]
Next, an example of a circuit that is appropriately used for the high-frequency clock generation circuit 10 in FIG. 1 will be described.
FIG. 43 shows an embodiment of the inverted clock generation circuit. This is because the output of the input clock ICLK input to the even-numbered inverter 1011 is CLK, the output input to the odd-numbered inverter 1012 is CLKB, and the π (180 degrees) phase is different by adjusting the delay amount of the inverter. It generates forward and inverted clocks. The normal and inverted clocks CLK and CLKB are used, for example, as the high frequency clocks VCLK and VCLKB of the shift register shown in FIG.
[0098]
FIG. 44 shows one embodiment of the multiphase clock generation circuit, and FIG. 45 shows an operation timing chart thereof. FIG. 44 shows a configuration example of the VCO 103 of FIG. 33, for example. In the present embodiment, the previous VCO 103 is composed of a four-stage differential ring oscillator 1030, and when the connections shown in the figure are made, the outputs FO1, FO2, FO3, and FO4 are π / It is possible to generate four-phase clocks having different phases every 2 (90 degrees). The clocks F01, F02, F03, and F04 are used for the high-frequency clocks VCLK1, VCLK2, VCLK3, and VCLK4 of the shift register shown in FIGS. As described above, in the differential ring oscillator, it is possible to easily generate a normal rotation and an inverted clock having different phases by π (180 degrees) without having an inverted clock generating unit as shown in FIG. Further, by taking out the intermediate phase of the ring oscillator as an even-stage configuration, it is possible to generate a different clock for each desired value having a phase.
[0099]
In the configuration example of FIG. 44, since the differential stage is taken out every two stages, four-phase clocks having different phases are output every π / 2 (90 degrees). It is also possible to output 8-phase clocks with different phases every / 4 (45 degrees). Similarly, with an odd-numbered stage, for example, a three-stage configuration, it is possible to generate 6-phase clocks having different phases every π / 3 (60 degrees), and a configuration for freely outputting the desired number of clock phases is possible. It is.
[0100]
FIG. 46 shows an embodiment of a delay control unit used in a circuit for generating a multiphase clock in which the phase is different and the phase difference is controlled in another embodiment. The clock X0 and its inverted clock X0B generated by the inverted clock generation unit or the like as shown in FIG. 43 are input to the delay unit 1041, and the delayed clocks X0D and XODB and the input clocks XO and XOB are input to the phase delay detection unit 1042. To enter. The phase difference between the clocks XO, XOB and the clocks X0D, XODB detected by the phase delay detection unit 1042 is compared with the reference signal in the error amplification unit 1043, and the output signal is fed back to the delay unit 1041 for delay. Control the amount.
[0101]
FIG. 47 shows an operation timing chart of the delay amount control unit of FIG. First, the clocks X0 and X0B are delayed by the time ΔT by the delay unit 1041 to become X0D and X0DB. The logic of the phase delay detection unit 1042 is expressed by C = X0 · X0DB + X0B · X0D, where C is the output. The reason why the logic of the phase delay detection unit 1042 is set in this way is to allow the phase delay amount to be detected accurately even if the duty of the input pulses X0 and X0B is not 50%. In this case, the output signal C of the phase delay detection unit 1042 has a waveform in which a pulse with a delay time ΔT as shown in FIG. 47 appears in a T / 2 cycle. Here, the output signal C of the phase lag detection unit 1042 is a current output, and the current value is N × Iref.
[0102]
The error amplifying unit 1043 compares the current output C of the phase delay detecting unit 1042 with the reference current Iref serving as a reference signal, and generates a current Idelay that determines the delay amount of the delay unit 18. In this case, for example, if N = 4, the integrated value of the integrated waveform of C becomes Iref when the delay time ΔT = T / 8, so that the delay unit 1142 has the delay time ΔT = T / 8. The amount of delay is controlled. Generally, it can be expressed as delay time ΔT = T / 2N. That is, by freely setting N, a pulse signal with a controlled delay time ΔT can be freely obtained with a delay within the range of the period T / 2 which is half of the input signals X0 and X0.
[0103]
FIG. 48 shows a specific circuit example in which the delay amount control unit of FIG. 46 is composed of bipolar transistors. A current Idelay that determines the delay amount of the delay amount generation unit 1041 is generated by the current source 1050 including the transistors Q16 and Q18 and the resistor R0. The input pulse signals X0 and X0B are connected to a diode load circuit 1053 composed of transistors Q1 and Q2 and an emitter follower composed of transistors Q19 and Q20 via a differential circuit 1052 composed of transistors Q21 and Q22. Delayed by circuit 1054.
[0104]
Since the output of the diode load circuit 1053 composed of the transistors Q1 and Q2 has a very small amplitude, the output signal of the emitter follower circuit 1054 composed of the transistors Q19 and Q20 is composed of transistors Q3 and Q4 and resistors R3 and R4. The swing is adjusted by being output through the binarization circuit 1055. When the output of the ECL logic circuit 1056 composed of the transistors Q5 to Q10 is C, the input signals X0D and X0DB from the binarization circuit 1055 are used.
C = X0B · X0D + X0 · X0DB
The output current Ic is inverted by a current mirror circuit 1057 including transistors Q11 and Q12 and compared with a reference current Iref generated by the transistor Q14 and the resistor R1. The collector of the transistor Q14 which is the comparison unit 1058 is high impedance, and the capacitor C1 is connected to the ground GND, so that Ic and Iref are compared, and the comparison output is the transistor Q15 and the resistor R0. Current generated by the current source 1059.
[0105]
Here, the current sources 1050 and 1059 including the transistors Q15 to Q18 and the resistor R0 are current mirror circuits in which the currents flowing through the current sources 1050 and 1059 are the same because the emitter resistors are the resistors R0. That is, the current generated by the transistor Q15 and the resistor R0 becomes Idelay, and the output current of the current mirror circuit configured by the transistors Q15 to Q18 and the resistor R0 so that the delay amount of the delay amount generation unit 1041 becomes a desired delay amount. Idelay is controlled by the output of transistor Q15 and resistor R0.
[0106]
Here, assuming that the current of the current source 1060 formed of the transistor Q13 and the resistor R2 is N times Iref, as described above.
Delay time ΔT = T / 2N
The delayed pulse signals X0D and X0DB can be obtained. For example, if N = 4,
R1: R2 = 4: 1
Area factor (emitter area) of transistor Q13: Area factor (emitter area) of transistor Q14 = 4: 1
Is set so that a current of 4 × Iref can be accurately supplied to the current source 1060 including the transistor Q13 and the resistor R2, so that the delay time ΔT = T / 8, that is, the phase delay amount Can generate delayed pulse signals X0D and X0DB with Δθ = π / 4.
[0107]
FIG. 49 shows a configuration example of a multiphase clock generation circuit using the delay amount control unit. For example, the clock VCO1 generated from the output of the VCO 103 in FIG. 33 and its inverted signal VCO1B are input to the delay control unit 1071 and the delay clock generation unit 1072 of the multiphase clock generation circuit 1070. The delay amount control unit 1071 includes a delay amount generation unit, a phase delay detection unit, and an error amplification unit as shown in FIGS. 46 and 48, and an output is a control current Idelay for controlling the delay amount. The delay clock generation unit 1072 may be the same as the delay amount generation unit 1041 of FIG. 48, and outputs clocks DVCO1 and DVCO1B whose delay amounts are controlled based on the control current Idelay. FIG. 50 shows an example in which a four-phase clock having a different phase is generated every 90 degrees from a two-phase clock (forward rotation, inverted clock).
[0108]
FIG. 51 shows a configuration example of a different multiphase clock generation circuit. In this configuration example, by providing three delay clock generation units 1082, 1083, and 1084, different 8-phase clocks can be generated every 45 degrees of phase. Similarly, it is possible to generate a clock in which the phase difference is controlled with respect to the reference VCO clock and the phase difference can be freely set.
[0109]
FIG. 52 shows an overall configuration diagram of an embodiment of a semiconductor laser modulation device, an optical scanning device, and an image forming device to which the pixel clock and pulse modulation signal generation device according to the present invention is applied. In FIG. 52, reference numeral 200 denotes a laser scanning optical system, and in this embodiment, a single beam scanning optical system. Reference numerals 211 and 212 denote photodetectors (sensors), 220 denotes a dot misregistration detection / control unit, 230 denotes a high-frequency clock generation unit, 240 denotes a pixel clock generation unit, 250 denotes an image processing unit, 260 denotes a laser drive signal generation unit, and 270. Is a laser driver. Here, the high-frequency clock generation unit 230 corresponds to the high-frequency clock generation circuit 10 described in the embodiment, and the pixel clock generation unit 240 also corresponds to the pixel clock generation circuit 11. The laser drive signal generation unit 260 corresponds to the modulation data generation circuit 12 and the serial modulation signal generation circuit 13 and constitutes a pulse modulation signal generation unit.
[0110]
Laser light from the semiconductor laser 201 passes through the collimator lens 202 and the cylinder lens 203, is scanned (scanned) by the polygon mirror 204, passes through the fo lens 205 and the toroidal lens 206, is reflected by the mirror 208, and enters the photosensitive member 208. By doing so, an image (electrostatic latent image) is formed on the photoreceptor 208. The start point and end point of the scanning laser light are detected by the photosensors 211 and 212 and input to the dot position deviation detection / control unit 220. The dot position deviation detection / control unit 220 measures the time during which the laser beam is scanned between the photosensors 211 and 212, obtains the deviation amount by comparing it with a reference time, and corrects the deviation amount. And output to the pixel clock generation unit 240 and the laser drive signal generation unit 260. Note that the output signal of the photosensor 211 is also provided to the image processing unit 250 as a line synchronization signal. When the modulation data is generated from the image data by the image processing unit 250, the phase data may be supplied to the image processing unit 250 and the output to the laser drive signal generation unit 260 may be omitted.
[0111]
If the pixel clock generation unit 240 does not include a phase data storage circuit, the dot position deviation detection / control unit 220 outputs phase data to the pixel clock generation unit 240 for each line. In the case where the circuit is provided, the phase data is obtained in advance, for example, to the pixel clock generator 240 in advance. In addition, the dot position deviation detection / control unit 220 not only uses phase data (first phase data) for always performing the same correction for each line that corrects scanning unevenness caused by the characteristics of the scanning lens, but also the polygon mirror. When phase data (second phase data) corresponding to correction such as rotation unevenness that changes for each line is also generated, and the pixel clock generation unit 240 includes a phase data synthesis circuit, the phase data Data is also output to the pixel clock generator 240.
[0112]
As described in the embodiment, the pixel clock generation unit 240 generates a pixel clock based on the high-frequency clock output from the high-frequency clock generation unit 230 and the phase data from the dot position deviation detection / control unit 220, and performs image processing. To the unit 250 and the laser drive signal generation unit 260.
[0113]
The image processing unit 250 inputs an image read by an image input device such as a scanner (not shown), and generates image data synchronized with a horizontal synchronization signal and a pixel clock. This image data is generally generated in consideration of the photosensitive characteristics of the photoreceptor. In addition to the image data, the image processing unit 250 generates a high resolution mode signal, a data inversion signal, a mode selection signal, a load signal, and the like as shown in FIG. Is transferred to the laser drive signal generator 260.
[0114]
As described above, the laser drive signal generation unit 260 generates modulation data from image data, and converts the modulation data into a serial string, thereby outputting a pulse modulation signal PM synchronized with the pixel clock. . This pulse modulation signal PM is input to the laser drive unit 270, and the laser drive unit 270 modulates the light of the semiconductor laser 201 according to the pulse modulation signal PM, and forms an image without positional deviation on the photoconductor 208. be able to.
[0115]
Note that the image processing unit 250 may generate modulation data from the image data and transfer it to the laser drive signal generation unit 260. In this case, the laser drive signal generation unit 260 directly converts this modulation data into a serial pulse train.
[0116]
When a multi-beam scanning device described later is used, for example, a plurality of pixel clock generation units 240 and laser drive signal generation units 260 (modulation data generation unit and serial modulation signal generation unit) are prepared, and the photo sensor 211 is further prepared. , 212, a plurality of sets of phase data for a plurality of lines are simultaneously generated, each phase data is supplied to each pixel clock generation unit, and each pixel clock is generated. The transferred image data for a plurality of scanning lines may be processed by the respective laser drive data generation units so as to output a plurality of pulse modulation signals.
[0117]
FIG. 53 shows a basic conceptual diagram thereof. 53, the pixel clock and pulse modulation signal generation circuit of FIG. 1 is prepared for n scanning lines (n is an integer of 2 or more), and each pixel clock and pulse modulation signal generation circuit 1000-1 to 1000-n has a high frequency. The high-frequency clock generated by the clock generation circuit 10 is shared.
[0118]
FIG. 54 shows a configuration diagram of an embodiment of a multi-beam scanning device (multi-beam optical system). In this embodiment, as shown in FIG. 55, n = 2 semiconductor laser arrays 300 in which two light emitting sources are monolithically arranged at a distance ds = 25 μm are used, and the optical axis C of the collimating lens 305 is symmetric. Arranged in the scanning direction.
[0119]
In FIG. 54, the semiconductor laser arrays 301 and 302 are laid out so that the optical axes of the collimating lenses 303 and 304 coincide with each other, have an emission angle symmetrical in the main scanning direction, and the emission axes intersect at the reflection point of the polygon mirror 307. Has been. A plurality of beams emitted from the respective semiconductor laser arrays 301 and 302 are collectively scanned by a polygon mirror 307 through a cylinder lens 308 and imaged on a photoconductor 313 by an fθ lens 310, a toroidal lens 311 and a mirror 312. . For example, print data (image data) for one line is stored for each light source in the buffer memory in the image processing unit 250 shown in FIG. 52, and is read out for each surface of the polygon mirror. Through the generation unit 260 and the laser driving unit 270, recording is performed simultaneously for every four lines.
[0120]
FIG. 56 shows a configuration diagram of the light source unit. The semiconductor laser arrays 403 and 404 are individually connected to mating holes 405-1 and 405-2 (not shown) formed on the back side of the base member 405 inclined at a predetermined angle in the main scanning direction, in the embodiment, about 1.5 °. The cylindrical heat sink portions 403-1 and 404-1 are mated, the protrusions 406-1 and 407-1 of the holding members 406 and 407 are aligned with the notches of the heat sink portion, and the arrangement direction of the light emitting sources is aligned, and the rear side To be fixed with screws 412. Further, the collimating lenses 408 and 409 are adjusted in the optical axis direction so that the outer circumference thereof is aligned with the semicircular mounting guide surfaces 405-4 and 405-5 of the base member 405. It is positioned and glued so that it becomes a parallel light beam.
[0121]
In the embodiment, as described above, since the light beams from the respective semiconductor laser arrays are set to intersect within the main scanning plane, the mating holes 405-1 and 405-2 and semicircular shapes are formed along the light beams. The mounting guide surfaces 405-4 and 405-5 are inclined.
[0122]
The base member 405 is engaged with the holder member 410 by the cylindrical engagement portion 405-3, and the screw 413 is screwed into the screw holes 405-6 and 405-7 through the through holes 410-2 and fixed. Configure.
[0123]
In the light source unit, the cylindrical portion 410-1 of the holder member is engaged with the reference hole 411-1 provided in the mounting wall 411 of the optical housing, and the spring 611 is inserted from the front side to insert the stopper member 612 into the cylindrical protrusion 410-3. The holder member 410 is held in close contact with the back side of the mounting wall 411 by engaging with. At this time, one end of the spring is hooked on the protrusion 411-2 to generate a rotational force with the center of the cylindrical portion as the rotational axis, and an adjustment screw 613 provided to lock the rotational force causes the rotation around the optical axis to be θ. The entire unit is rotated and adjusted so that each beam spot row is shifted by one line and arranged alternately as shown in FIG.
[0124]
The aperture 415 is provided with a slit for each semiconductor laser array, and is attached to the optical housing to define the emission diameter of the light beam.
[0125]
FIG. 57 shows another embodiment of the light source unit, and shows an example in which light beams from two semiconductor laser arrays are combined using beam combining means. Similarly to the embodiment of FIG. 56, the semiconductor laser arrays 603 and 613 and the collimating lenses 605 and 606 are supported by the base members 601 and 602, respectively, and constitute the first and second light source sections. The first base member 601 and the second base member 602 are fixed by screws by engaging cylindrical engagement portions in holes 607-1 and 607-2 provided in the common flange member 607. An adjusting screw 606 is screwed onto the second base member 602, and by adjusting the amount of protrusion from the back side, both arms 602-1 are twisted so that only the holding portion of the semiconductor laser array and the collimating lens is sub-scanned. Can be tilted in the direction β. Thereby, the arrangement of each beam spot is shifted by one line and adjusted so as to be the arrangement shown in FIG.
[0126]
A prism 608 composed of a parallelogram prism portion and a triangular prism portion reflects each beam of the second light source portion on the inclined surface 608-1, reflects on the beam splitter surface 608-2, and directly passes through the first light source. Injected close to each beam of the part. The plurality of adjacent beams are scanned at once by a polygon mirror, and each beam spot is imaged on the photosensitive member. The aperture 615 is similarly supported on the optical housing. In the embodiment, since the light beams from the respective semiconductor laser arrays are almost overlapped, a common slit 615 is provided. The flange member 607 is held by the holder member 609, and the cylindrical portion 609? 1 of the holder member is engaged with the reference hole 610-1 provided in the mounting wall 610 to the optical housing, as in the above embodiment, and the entire unit is rotated. By doing so, the inclination of the array of each beam spot can be corrected.
[0127]
FIG. 59 shows a configuration example of a multi-beam scanning device in the case of using a 4-channel semiconductor laser array 801 as shown in FIG. Since the configuration is the same as in FIGS. 56 and 57, description thereof is omitted here.
[0128]
FIG. 61 shows a state in which the light source unit shown in FIG. 56 is mounted on the optical housing 804 to constitute a multi-beam scanning device. A printed circuit board 802 on which a drive circuit for controlling the semiconductor laser is formed is mounted on the back surface of the light source unit 801. The printed circuit board 802 is brought into contact with the wall surface of the optical housing perpendicular to the optical axis by the spring, and is adjusted by an adjusting screw 803. The posture is maintained by adjusting the tilt. The adjusting screw 803 is screwed into a protrusion formed on the wall surface of the housing. Inside the optical housing, the cylinder lens 805, the polygon motor 808 that rotates the polygon mirror, the fθ lens 806, the toroidal lens, and the folding mirror 807 are positioned and supported, and the printed circuit board 809 on which the synchronization detection sensor is mounted. Is mounted on the wall of the housing from the outside in the same manner as the light source unit. The upper portion of the optical housing is sealed with a cover 811 and fixed to the frame member of the image forming apparatus main body with a plurality of mounting portions 810 protruding from the wall surface.
[0129]
FIG. 62 shows an example of an image forming apparatus equipped with the optical scanning device. Around the photosensitive drum 901 that is the surface to be scanned, a charging charger 902 that charges the photosensitive member to a high voltage, and a developing roller that attaches the charged toner to the electrostatic latent image recorded by the optical scanning device 900 and visualizes it. 903, a toner cartridge 904 for supplying toner to the developing roller, and a cleaning case 905 for scraping and storing toner remaining on the drum. As described above, a plurality of lines are simultaneously recorded on the photosensitive drum for each surface. The recording paper is supplied from the paper supply tray 906 by the paper supply roller 907 and is sent out by the registration roller pair 908 in accordance with the recording start timing in the sub-scanning direction, and the toner is transferred by the transfer charger 906 when passing through the photosensitive drum. The image is transferred, fixed by the fixing roller 909, and discharged to the paper discharge tray 910 by the paper discharge roller 912.
[0130]
【The invention's effect】
The main operations and effects of the pixel clock and pulse modulation signal generating apparatus, the optical scanning apparatus and the image forming apparatus including the pixel clock according to the present invention are listed as follows.
(1) A pixel clock capable of phase shifting can be generated with a simple configuration, and a pulse modulation signal corresponding to the pixel clock can be generated with a simple configuration even if the phase of the pixel clock is shifted.
(2) The pixel clock cycle can be controlled with a simple configuration, and a pulse modulation signal corresponding to a change in the pixel clock cycle can be generated with a simple configuration.
(3) The pixel clock cycle can be finely controlled with a simple configuration, and an arbitrary pulse modulation signal can be generated. Furthermore, a pulse modulation signal that does not affect the image can be obtained.
(4) In pixel clock generation, the same phase shift amount data is stored at the same pixel position for at least one line, and the same phase shift amount data is output at the same pixel position of each line, thereby reducing the load on the external circuit. can do. Furthermore, by giving different phase data for each line from the outside, the phase shift can be controlled flexibly.
(5) For example, the same correction can always be performed for each line so as to correct the scanning unevenness caused by the characteristics of the scanning lens. Furthermore, it is possible to cope with corrections that change for each line such as uneven rotation of the polygon mirror.
(6) A pixel clock is generated with a simple configuration, and similarly, a pulse modulation signal that follows the pixel clock at high speed is generated with a simple configuration to modulate the light output of a laser light source or the like.
[Brief description of the drawings]
FIG. 1 is a basic configuration diagram of a pixel clock and pulse modulation signal generation device of the present invention.
FIG. 2 is a conceptual diagram of an output image of a pixel clock according to the present invention.
FIG. 3 is a conceptual diagram of an output image of a pulse modulation signal according to the present invention.
FIG. 4 is a conceptual diagram of a relationship between a pixel clock and a pulse modulation signal according to the present invention.
FIG. 5 is a configuration diagram of a pixel clock generation circuit according to a first embodiment of the present invention.
FIG. 6 is a timing diagram for explaining the operation of FIG. 5;
FIG. 7 is another timing diagram for explaining the operation of FIG. 5;
FIG. 8 is a configuration diagram of a pixel clock generation circuit according to a second embodiment of the present invention.
9 is a diagram showing an input / output correspondence relationship of the phase data decoding circuit of FIG. 8;
FIG. 10 is a configuration diagram of a pixel clock generation circuit according to a third embodiment of the present invention.
FIG. 11 is a configuration diagram of a pixel clock generation circuit according to a fourth embodiment of the present invention.
FIG. 12 is a configuration diagram of a pixel clock generation circuit according to a fifth embodiment of the present invention.
FIG. 13 is a configuration diagram of a pixel clock generating circuit according to a sixth embodiment of the present invention.
FIG. 14 is a configuration diagram of a pixel clock generation circuit according to a seventh embodiment of the present invention.
15 is a diagram illustrating a configuration example of a clock generation circuit in FIG. 14;
16 is a diagram illustrating another configuration example of the clock generation circuit in FIG. 14;
17 is a diagram illustrating a configuration example of a control signal generation circuit in FIG. 14;
18 is a truth table of the multiplexer of FIG.
FIG. 19 is a correspondence table between phase shift amounts and phase data in the seventh embodiment shown in FIG. 14;
20 is a truth table of the control data generation circuit of FIG.
FIG. 21 is a timing chart for explaining the operation of FIG. 14;
FIG. 22 is a configuration diagram of a pixel clock generation circuit according to an eighth embodiment of the present invention.
FIG. 23 is a configuration diagram of Embodiment 9 of the pixel clock generating circuit according to the invention.
FIG. 24 is a diagram showing a dot image of a conventional pulse width modulation signal.
FIG. 25 is a diagram showing a dot image of a conventional pulse width modulation signal.
FIG. 26 is a diagram similarly showing a dot image of a conventional pulse width modulation signal.
FIG. 27 is a diagram showing a specific example of a dot image of a pulse modulation signal according to the present invention.
FIG. 28 is a diagram showing an example of a look-up table (LUT) used in the modulation data generation circuit of the present invention.
FIG. 29 is a diagram illustrating a configuration example of a decoder used in the modulation data generation circuit of the present invention.
FIG. 30 is a diagram showing an embodiment of a shift register used in the serial modulation signal generation circuit of the present invention.
FIG. 31 is a diagram illustrating a specific configuration example of a shift register.
FIG. 32 is a diagram illustrating another specific configuration example of the shift register.
FIG. 33 is an overall configuration diagram of an embodiment of a high-frequency clock generation circuit, a modulation data generation circuit, and a serial modulation signal generation circuit according to the present invention.
FIG. 34 is a diagram illustrating an example of a multi-stage shift register configuration used in a serial modulation signal generation circuit.
FIG. 35 is a diagram showing another embodiment of a multi-stage shift register configuration.
FIG. 36 is a diagram showing still another embodiment of a multi-stage shift register configuration.
FIG. 37 is a timing chart for explaining the operation of FIG. 36;
FIG. 38 is a diagram showing an embodiment using a plurality of lookup tables used in a modulation data generation circuit.
FIG. 39 is a diagram illustrating another embodiment using multiple look-up tables.
FIG. 40 is a diagram illustrating an example of changing an output pulse train.
FIG. 41 is a diagram illustrating another embodiment of changing the output pulse train.
FIG. 42 is a diagram illustrating still another embodiment of changing the output pulse train.
FIG. 43 is a diagram illustrating a configuration example of an inversion clock generation circuit used in the high-frequency clock generation circuit.
FIG. 44 is a diagram showing a specific configuration example of a multiphase clock generation circuit used in the high frequency clock generation circuit.
FIG. 45 is a timing chart for explaining the operation of FIG. 44;
FIG. 46 is a diagram illustrating an example of a delay amount control unit used in another multiphase clock generation circuit.
47 is a timing chart for explaining the operation of FIG. 46. FIG.
48 is a diagram illustrating a specific configuration example of a delay amount control unit in FIG. 46;
49 is a diagram illustrating an example of a multi-phase clock generation circuit using the delay amount control unit of FIG. 46. FIG.
FIG. 50 is a timing chart for explaining the operation of FIG. 49;
FIG. 51 is a diagram showing another embodiment of a multiphase clock generation circuit.
FIG. 52 is an overall configuration diagram of an embodiment of a semiconductor laser modulation device, an optical scanning device, and an image forming device to which the pixel clock and pulse modulation signal generation device of the present invention is applied.
FIG. 53 is a conceptual diagram of one embodiment of a pulse modulation signal generation circuit used for multi-beam scanning.
FIG. 54 is an overall configuration diagram of a multi-beam scanning device used in the image forming apparatus according to the present invention.
FIG. 55 is a configuration diagram of a two-channel semiconductor laser array.
FIG. 56 is an exploded configuration diagram of a light source unit of the multi-beam scanning device.
FIG. 57 is an exploded configuration diagram of another light source unit of the multi-beam scanning device.
58 is a diagram showing a beam spot arrangement in the light source unit of FIGS. 56 and 57. FIG.
FIG. 59 is an exploded configuration diagram of still another light source unit of the multi-beam scanning device.
FIG. 60 is a block diagram of a 4-channel semiconductor laser array.
FIG. 61 is a diagram showing a state in which the multi-beam scanning device is mounted on an optical housing.
FIG. 62 is a diagram illustrating an example of an image forming apparatus equipped with an optical scanning device.
FIG. 63 is a diagram illustrating a general configuration of a conventional image forming apparatus.
[Explanation of symbols]
10 High-frequency clock generation circuit
11 Pixel clock generation circuit
12 Modulation data generation circuit
13 Serial modulation signal generation circuit
111 counter
112 Comparison circuit
113 Pixel clock control circuit
114 Phase data decoding circuit
115 Phase data storage circuit
116 Phase data synthesis circuit
112, 124 transition detection circuit
122, 125 Control signal generation circuit
123, 126 Clock generation circuit
127 multiplexer
128 Control data generation circuit
129 Status signal generation circuit
130 Select signal generation circuit
131 Phase data storage circuit
132 Phase data synthesis circuit
1210 registers
1220 Look-up table
1230 decoder
1240 Selection circuit
1300 Shift register
200 Laser optical system
211,212 Sensor
220 dot misalignment detection / control unit
230 High-frequency clock generator
240 pixel clock generator
250 Image processing unit
260 Laser drive signal generator
270 Laser drive unit

Claims (33)

High-frequency clock generation means for generating a high-frequency clock;
Pixel clock generation means for changing the period of the pixel clock based on the high frequency clock output from the high frequency clock generation means and phase data indicating the phase shift amount of the pixel clock;
Serial modulation signal generation means for inputting modulation data representing a desired bit pattern corresponding to image data in synchronization with the pixel clock, and outputting a pulse modulation signal of a serial pulse train based on the high frequency clock,
The pixel clock generation means includes
Control data generating means for generating first control data and second control data from phase data indicating the phase shift amount of the pixel clock and a state signal indicating the state of the pixel clock;
First clock generation means for generating a first clock whose transition timing is controlled based on the first change point of the high-frequency clock and the first control data;
Second clock generating means for generating a second clock in which a transition timing different from the first clock is controlled based on the second change point of the high-frequency clock and the second control data;
Clock selection means for selecting the first clock and the second clock according to the phase data and outputting as a pixel clock;
A device for generating a pixel clock and pulse modulation signal, comprising: High-frequency clock generation means for generating a high-frequency clock;
Pixel clock generation means for changing the period of the pixel clock based on the high frequency clock output from the high frequency clock generation means and phase data indicating the phase shift amount of the pixel clock;
Modulation data generation means for inputting image data and generating modulation data representing a desired bit pattern from the image data;
Serial modulation signal generation means for inputting the modulation data in synchronization with the pixel clock and outputting a pulse modulation signal of a serial pulse train based on the high frequency clock,
The pixel clock generation means includes
Control data generating means for generating first control data and second control data from phase data indicating the phase shift amount of the pixel clock and a state signal indicating the state of the pixel clock;
First clock generation means for generating a first clock whose transition timing is controlled based on the first change point of the high-frequency clock and the first control data;
Second clock generating means for generating a second clock in which a transition timing different from the first clock is controlled based on the second change point of the high-frequency clock and the second control data;
Clock selection means for selecting the first clock and the second clock according to the phase data and outputting as a pixel clock;
A device for generating a pixel clock and pulse modulation signal, comprising: The pixel clock and pulse modulation signal generation device according to claim 1 or 2,
The pixel clock transition timing is synchronized with the high-frequency clock transition timing. The pixel clock and pulse modulation signal generation device according to claim 1 or 2,
The pixel clock generation means changes the period of the pixel clock in a 1/2 clock step of the high-frequency clock. The pixel clock and pulse modulation signal generation device according to claim 2,
The pixel clock and pulse modulation signal generation device, wherein the modulation data generation means makes the number of bits constituting the modulation data variable. The pixel clock and pulse modulation signal generation device according to claim 2,
The transition timing of the pixel clock is synchronized with the transition of the high frequency clock,
The modulation data generating means makes the number of bits constituting the modulation data variable;
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generation device according to claim 2,
The pixel clock generation means changes the period of the pixel clock in a half clock step of the high frequency clock,
The modulation data generating means makes the number of bits constituting the modulation data variable;
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generation device according to any one of claims 5 to 7,
The pixel clock and pulse modulation signal generation device, wherein the modulation data generation means varies the number of bits constituting the modulation data based on phase data indicating a phase shift amount of the pixel clock. In the pixel clock and pulse modulation signal generating device according to any one of claims 1 to 8,
The first clock generation means generates a first control signal based on a first detection means for detecting a transition of the first clock, an output from the first detection means and the first control data. A signal generation unit; and a first signal transition unit configured to perform a signal transition at a first change point timing of a high-frequency clock based on the first control signal and output the signal as a first clock.
A device for generating a pixel clock and a pulse modulation signal. In the pixel clock and pulse modulation signal generating device according to any one of claims 1 to 8,
The second clock generation means generates second control signals based on second detection means for detecting a transition of the second clock, output from the second detection means and the second control data. A signal generating means; and a second signal transition means for making a signal transition at a second change point timing of the high-frequency clock based on the second control signal and outputting as a second clock.
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generation device according to claim 9,
The first control signal generation means includes a shift register that shifts data at a first change point of a high-frequency clock, and a multiplexer that selects data based on the first control data.
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generation device according to claim 10,
The second control signal generation means includes a shift register that shifts data at a second change point of the high-frequency clock, and a multiplexer that selects data based on the second control data.
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generation device according to any one of claims 1 to 12,
The pixel clock generation unit has a phase data storage unit that stores a plurality of phase data, sequentially reads out in synchronization with the pixel clock, and supplies the phase data to the control data generation unit.
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generation device according to any one of claims 1 to 12,
The pixel clock generation means stores a plurality of first phase data, sequentially reads out in synchronization with the pixel clock, second phase data, and first phase read out from the phase data storage means. Having phase data synthesizing means for synthesizing data and giving it to the control data generating means;
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generation device according to claim 13 or 14,
The phase data storage means stores phase data for one line in advance, and sequentially reads out in synchronization with the pixel clock every time the line is scanned.
A device for generating a pixel clock and a pulse modulation signal . The pixel clock and pulse modulation signal generation device according to claim 14,
The phase data storage means stores the first phase data for one line in advance, and sequentially reads out in synchronization with the pixel clock every time the line is scanned. Combining the second phase data and the first phase data sequentially read from the phase data storage means each time the line is scanned.
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generation device according to any one of claims 2 to 16,
The modulation data generation means is configured by a lookup table that stores modulation data corresponding to image data, and reads the corresponding modulation data from the lookup table based on the input image data.
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generation device according to claim 17,
The look-up table is composed of a plurality, and the modulation data is read by switching the look-up table based on the input image data.
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generation device according to claim 18,
Multiple look-up tables have different bit lengths of modulated data,
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generation device according to claim 18,
The plurality of look-up tables are composed of a first set composed of a plurality of look-up tables each having a different bit length of modulation data, and a plurality of look-up tables having the same configuration corresponding to the first set. Consisting of the second set,
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generation device according to any one of claims 2 to 16,
The modulation data generation means is composed of a decoder that decodes image data to generate modulation data.
A device for generating a pixel clock and a pulse modulation signal. In the pixel clock and pulse modulation signal generating device according to any one of claims 1 to 21,
The serial modulation signal generating means is composed of a shift register, loads input modulation data, and converts it into a serial pulse train based on a high frequency clock.
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generation device according to claim 22,
The serial modulation signal generating means includes a plurality of stages of shift registers and a multiplexer that selects the outputs of the plurality of stages of shift registers.
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generation device according to claim 23,
The multistage shift register operates based on a single high-frequency clock.
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generating device according to claim 24,
The serial modulation signal generating means includes a phase adjustment unit that adjusts the phase of output pulses of a plurality of shift registers based on a high-frequency clock.
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generation device according to claim 23,
The multi-stage shift register operates based on a high-frequency clock having a plurality of phases.
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generation device according to any one of claims 1 to 26,
The high-frequency clock generation means is composed of a PLL circuit composed of a differential ring oscillator, and the high-frequency clock is composed of a plurality of clocks having different phases by outputting a plurality of phases of the differential ring oscillator.
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generation device according to any one of claims 1 to 26,
The high-frequency clock generation means includes a delay unit that delays a basic clock, and the high-frequency clock includes a plurality of clocks having different phases output from the delay unit.
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generating device according to claim 28,
The high-frequency clock generation unit includes a delay amount control unit that controls a delay amount in the delay unit.
A device for generating a pixel clock and a pulse modulation signal. The pixel clock and pulse modulation signal generation device according to claim 29,
The delay amount control unit includes a phase difference detection unit and an error amplification unit that detect a clock delay amount.
A device for generating a pixel clock and a pulse modulation signal. In an optical scanning device having a light source and a scanning optical system that scans a light beam output from the light source,
A pixel clock and a pulse modulation signal generation device according to any one of claims 1 to 30, wherein the light beam output from the light source is modulated based on a pulse modulation signal output therefrom.
An optical scanning device characterized by that. In an image forming apparatus having a light source, a scanning optical system that scans a light beam output from the light source, and an image forming unit that forms an image according to the scanning light beam,
A pixel clock and a pulse modulation signal generation device according to any one of claims 1 to 30, wherein the light beam output from the light source is modulated based on a pulse modulation signal output therefrom.
An image forming apparatus. In an image forming apparatus having a plurality of light sources, a scanning optical system that scans a light beam output from each light source, and an image forming unit that forms an image according to each scanning light beam,
31. A pixel clock and pulse modulation signal generation device according to claim 1, comprising at least a serial modulation signal generation means or a combination of modulation data generation means and serial modulation signal generation means corresponding to the light source. And a plurality of components, and modulate the light flux output from each light source based on the pulse modulation signal output from each serial modulation signal generation means,
An image forming apparatus.

Images