JP4694782B2 - Semiconductor device, manufacturing method thereof, and semiconductor surface processing method - Google Patents

Description

  The present invention relates to a semiconductor device having improved characteristics such as mobility, a manufacturing method thereof, and a semiconductor surface processing method.

  In general, this type of semiconductor device includes a field effect transistor in which a source region, a drain region, and a channel region are formed along a semiconductor surface such as silicon. Further, this field effect transistor has a gate insulating film formed on the channel region and a gate electrode on the gate insulating film. As is well known, field effect transistors include n-type field effect transistors (n-type transistors) and p-type field effect transistors (p-type transistors). An LSI including these n-type and p-type transistors is used. When forming, silicon having (100) plane on the surface (hereinafter referred to as (100) silicon) is usually used. As a description of the plane orientation in this specification, for example, (100) is a collective representation of all planes (100), (010), (001), etc. equivalent to the (100) plane. To do.

  Thus, when an n-type transistor and a p-type transistor are formed using (100) silicon, the driving capability, for example, mobility of the p-type transistor is as low as about 0.3 times that of the n-type transistor. It is known that For this reason, generally, a method of designing the size of the p-type transistor larger than the size of the n-type transistor is adopted. However, designing the size of the p-type transistor larger than the size of the n-type transistor is one of the factors that hinder miniaturization.

  Here, with reference to FIG. 1, a conventional method for manufacturing a semiconductor device will be described by taking an example of forming an integrated circuit by forming an n-type transistor in a semiconductor region. In this example, an n-type transistor having an LDD (Lightly Doped Drain) structure is shown.

  First, as shown in FIG. 1A, element isolation is performed on the surface of p-type (100) silicon 101 by, for example, STI (Shallow Trench Isolation) to form an element region 102. Here, as described above, the plane orientation (100) of silicon includes planes (100), (010), and (001) equivalent to the (100) plane. In this case, The silicon having the surface may be a semiconductor substrate or a semiconductor layer formed on the semiconductor substrate.

Next, the device region 102 is subjected to RCA cleaning using NH ₄ OH—H ₂ O ₂ —H ₂ O (SC1) and HCl—H ₂ O ₂ —H ₂ O (SC2) (FIG. 1). (B)). As a result of the RCA cleaning, organic substances, particles, and metal impurities are removed from the entire surface, and then a gate insulating film (SiO ₂ ) 103 is formed (FIG. 1C).

  Further, as shown in FIG. 1D, boron is ion-implanted over the entire surface of the silicon 101 in order to control the threshold voltage. After the ion implantation, a polycrystalline silicon film is deposited on the entire surface of the silicon 101. By patterning the polycrystalline silicon film, the polycrystalline silicon electrode 105 is formed on the gate insulating film 103 in the element region 102 as shown in FIG. Formed.

Subsequently, as shown in FIG. 1 (f), n-source and n-drain regions 106 for relaxing a high electric field are formed by ion implantation of phosphorus at a low concentration. Next, a silicon oxide film (SiO ₂ ) is deposited on the entire surface of the silicon 101 so as to cover the gate electrode 105 by a CVD method or the like, and anisotropic etching is performed so that the side wall of the gate electrode 105 is insulated. A film 107 is formed (FIG. 1G). Thereafter, n + source and drain regions 108 are formed by ion implantation of n-type impurities such as arsenic at a high concentration (FIG. 1 (h)).

  An n-type transistor is fabricated by the illustrated method using (100) silicon. Similarly, a p-type transistor fabricated on (100) silicon is compared with an n-type transistor as described above. There is a disadvantage that the mobility is low.

  On the other hand, in order to increase the driving capability of the p-type transistor, it has been proposed to use (110) silicon having a (110) plane on the surface. In fact, it has been reported that when (110) silicon is used, the driving capability of the p-type transistor is about 2.5 times higher than when (100) silicon is used. However, when (110) silicon is used, on the contrary, the driving capability of the n-type transistor is about 0.6 times that when (100) silicon is used. Therefore, (110) silicon is a very useful material if a decrease in driving capability of the n-type transistor can be suppressed. However, the actual situation is that a method for preventing a decrease in driving capability of an n-type transistor using (110) silicon has not been proposed yet.

  Further, an apparatus and a method that can be applied to (110) silicon are disclosed in Japanese Patent Application No. 9-15790 (Japanese Patent Application Laid-Open No. 10-33362) (Patent Document 1) and Japanese Patent Application Laid-Open No. 11-57636 (Patent Document). Each of them is disclosed in Document 2). However, Patent Literature 1 is performed using only (100) silicon, and (110) silicon has not been tested. Similarly, Patent Document 2 is an experimental result when (100) silicon is used, and no experiment has been performed on (110) silicon.

On the other hand, Japanese Patent Application Laid-Open No. 9-51097 (Patent Document 3) discloses a method of manufacturing a field effect transistor that can avoid deterioration of interface mobility due to electron scattering at the interface between silicon and an oxide film. However, Patent Document 3 only discloses that the electron traveling direction and the step direction in (001) silicon are parallel, and (110) silicon is not studied.
Japanese National Patent Publication No. 10-33362 JP-A-11-57636 Japanese Patent Laid-Open No. 9-51097

  According to the observations of the present inventors, when a field effect transistor is manufactured by the method shown in FIG. 1, the surface of the element region is unavoidable during alkali treatment in RCA cleaning, pure water rinsing, and the like. Was found to be rough.

  On the other hand, the carrier mobility in a field effect transistor is one of the indexes indicating the driving capability of the transistor, and holes are used as carriers in p-type field effect transistors and electrons are used as carriers in n-type field effect transistors. In general, in order to improve the driving ability of a field effect transistor, it is necessary to reduce the roughness of the surface of the element region and increase the mobility of carriers.

More specifically, when normal RCA cleaning is used, the surface roughness of silicon in the element region, when expressed by the centerline average roughness Ra, causes a roughness of Ra = 0.5 to 1.5 nm. The present inventors have confirmed that a gate insulating film is formed thereon. For forming a gate insulating film, a SiO ₂ film formed using dry O ₂ is generally used. However, in the case of oxidation using dry O ₂ , an oxidizing species enters from the (111) facet surface, and thus preferentially. It was considered that oxidation progressed, and as a result, it was observed that the roughness of the silicon surface and the gate SiO ₂ film interface was further increased.

  When a field effect transistor is manufactured using silicon having minute roughness due to RCA cleaning, not only the driving ability of the field effect transistor is lowered, but also when a voltage is actually applied to the gate electrode, an electric field is applied to the protrusion. Concentration occurs, leading to dielectric breakdown. In particular, when silicon having a substantially (110) plane orientation on its surface is used, the roughening during the alkali treatment becomes severe, and this uses silicon having the substantial (110) plane orientation on its surface. It has also been found that this causes a decrease in mobility.

  Although the n-type field effect transistor has been described above as an example, the same applies to semiconductor elements such as TFT, CCD, and IGBT.

  The present invention has been made under such circumstances, and an object of the present invention is to provide a semiconductor device having improved performance by reducing the roughness of the silicon surface.

  Another object of the present invention is to provide a semiconductor device having high surface flatness and improved characteristics using silicon having a substantially (110) plane orientation on its surface.

  Another object of the present invention is to provide a manufacturing method for manufacturing an n-type transistor having a high driving capability by using silicon having a substantially (110) plane orientation on the surface thereof.

  Still another object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing the roughness of the surface of the semiconductor region.

  Another object of the present invention is to provide a method for treating a semiconductor surface that can maintain or planarize the roughness of the surface of the semiconductor region caused by cleaning.

  According to the present invention, the surface roughness of silicon having substantially (110) plane orientation on the surface thereof is set to Ra = 0.15 nm or less with a center line average roughness Ra, whereby carrier electrons are scattered in the semiconductor device. It is characterized by being kept low and improving the carrier electron driving capability of the semiconductor device. The carrier electron mobility of a semiconductor device has a close relationship with the roughness of the surface of the semiconductor region. In particular, in silicon having a substantially (110) plane orientation on the surface, the mobility of carrier electrons increases as Ra is reduced. Can be improved.

  Here, the substantial (110) plane orientation refers to a plane facing a direction substantially equivalent to the (110) plane orientation from the crystallographic viewpoint, and is a (551) plane, (311) plane, ( 221) plane, (553) plane, (335) plane, (112) plane, (113) plane, (115) plane, (117) plane, and the like.

  According to Kazuo Sato et al., FIG. Of a paper published in “Sensors and Actuators 73 (1999)” (P122-130). 2 shows that when the (110) plane is subjected to an alkali etching treatment, a surface shape in which a line runs in the <−110> direction is obtained. Thus, as a region where a surface shape similar to the (110) plane is obtained, a plane turned off to 0 to 12 ° in the <100> direction, for example, a (551) plane off by 8 ° is applicable. A similar surface shape can be obtained up to a surface that is turned off by 1 ° in the <−110> direction. Therefore, FIG. The plane orientation showing the same surface roughness behavior as the (110) plane shown in 2 is substantially included in the (110) plane orientation.

  Further, T.W. Sato et al., Phys. Rev. , B4, 1950 (1971), a surface on which carrier electron mobility similar to that of the (110) surface can be obtained is reported. According to this report, when electrons are flowed in the <−110> direction, the surface is turned off by 0 to 35 ° in the <−110> direction, such as the (331) plane, the (221) plane, the (332) plane, ( Even if the (111) plane is used, the same electron movement behavior as that of the (110) plane can be obtained. Further, even when a plane off by 0 to 12 ° in the <110> direction, for example, the (320) plane is used, the same behavior as the (110) plane can be obtained. Therefore, the above-described surface and its vicinity surface are also included in the substantial (110) surface referred to in this specification.

  Based on the above points, the features of the present invention are listed below. First, the semiconductor device according to the present invention is a semiconductor device in which a semiconductor element is formed on silicon having a substantially (110) plane orientation on its surface, and its surface roughness is expressed as 0. centerline average roughness Ra. It is characterized by being 15 nm or less, preferably 0.11 nm or less. Further, the Ra is preferably 0.09 nm or less, and more preferably 0.07 nm or less. In this case, the semiconductor device may be a field effect transistor characterized by a MOS transistor. The gate insulating film of the field effect transistor may be a film including any one or more of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In the gate insulating film of the field effect transistor, It may contain a rare gas element.

In the gate insulating film of the field effect transistor,
A metal silicide combining one or any element of Hf, Zr, Ta, Ti, La, Co, Y and Al,
Selected from Si, Hf, Zr, Ta, Ti, Y, Nb, Na, Co, Al, Zn, Pb, Mg, Bi, La, Ce, Pr, Sm, Eu, Gd, Dy, Er, Sr and Ba Metal oxides combining one or any of the elements,
Selected from Si, Hf, Zr, Ta, Ti, Y, Nb, Na, Co, Al, Zn, Pb, Mg, Bi, La, Ce, Pr, Sm, Eu, Gd, Dy, Er, Sr and Ba A metal nitride combining one or any of the elements,
Or
One from Si, Hf, Zr, Ta, Ti, Y, Nb, Na, Co, Al, Zn, Pb, Mg, Bi, La, Ce, Pr, Sm, Eu, Gd, Dy, Er, Sr and Ba Alternatively, a high dielectric film containing a metal oxynitride in which any element is combined may be formed.

  The gate insulating film of the field effect transistor may have a structure in which a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a high dielectric film, or any of these films are combined.

  According to one aspect of the present invention, the step of cleaning the silicon surface using an RCA SC-1 cleaning solution with a reduced OH concentration, and oxidizing the cleaned silicon surface in an atmosphere containing oxygen radicals, And a step of forming an oxide film on the cleaned silicon surface, thereby obtaining a method for manufacturing a semiconductor device, wherein the silicon surface is planarized. In this case, the oxide film may be used as a gate insulating film.

  Furthermore, according to another aspect of the present invention, a sacrificial oxide film is formed on the surface of the semiconductor region in a step of cleaning the silicon surface using an RCA SC-1 cleaning solution with a reduced OH concentration and in an atmosphere containing oxygen radicals. A manufacturing method is obtained for a semiconductor device that includes a step of forming and a step of peeling the sacrificial oxide film, whereby the surface flatness of the semiconductor region can be improved. The atmosphere containing radical oxygen may be realized using a mixed gas plasma of a rare gas and oxygen gas generated by microwave excitation.

  In the method of manufacturing a field effect transistor according to another aspect of the present invention, when forming a channel region, a sacrificial oxide film is formed on the semiconductor surface in an atmosphere containing oxygen radicals in order to improve the flatness of the semiconductor surface of the channel region. And a step of removing the sacrificial oxide film, and a step of forming a gate insulating film on the semiconductor surface of the channel region. The atmosphere containing radical oxygen may be realized using a mixed gas plasma of a rare gas and oxygen gas generated by microwave excitation. The rare gas may be one or more of krypton, argon, or xenon. The gate insulating film may be formed by including any one of an oxidation treatment and a nitridation treatment or a simultaneous parallel treatment on the semiconductor surface in an atmosphere containing at least one of radical oxygen and radical nitrogen. The gate insulating film may be formed using a mixed gas plasma of a rare gas and an insulating film forming gas generated by microwave excitation.

  The rare gas may be krypton or argon, and the insulating film forming gas may be ammonia, nitrogen, oxygen, or a mixed gas thereof.

  A method for manufacturing a semiconductor device or a method for treating a semiconductor surface according to another aspect of the present invention includes a first step of performing an oxidation treatment using a wet gas on a silicon surface, and 10A to 1000A without peeling off the oxide film. It is characterized in that the silicon surface is flattened by removing the oxide film with an aqueous solution containing HF by repeating the desired number of steps of the second step of etching back and then the first step and the second step. .

  A semiconductor device manufacturing method or a semiconductor surface treatment method according to another aspect of the present invention includes treating a semiconductor or cleaning a semiconductor surface only with a non-alkaline liquid having a pH of 7 or less.

  In the cleaning method, ultrasonic cleaning may be performed while suppressing generation of OH.

The generation of OH may be suppressed by adding H ₂ .

A method for manufacturing a semiconductor device or a method for treating a semiconductor surface according to another aspect of the present invention includes a first step of cleaning with pure water containing ozone, HF and deaeration while applying vibrations having a frequency of 500 kHz or higher. The second step of cleaning with a cleaning solution containing H ₂ O and a surfactant, the third step of performing a battlefield with H ₂ O containing ozone, HF and degassed H to remove the oxide film _The cleaning method includes a fourth step of cleaning with a cleaning solution containing ₂ O and a fifth step of cleaning with H ₂ O to which hydrogen is added.

The second, degassed of H _{2 O} the fourth step, may be used of H _{2 O} was added hydrogen was degassed of H 2 _O.

  In the cleaning method, the processing chemical solution and the semiconductor device may not be exposed to air from the start to the end of cleaning.

According to still another aspect of the present invention, there is provided a method for manufacturing a semiconductor device or a method for treating a semiconductor surface, wherein a silicon oxide film, silicon nitridation is performed using a cleaning liquid containing HF and H ₂ O having a dissolved oxygen concentration of 100 ppb or less. The film and the silicon oxynitride film are peeled off.

  In the peeling treatment, the treatment chemical solution and the semiconductor device may not come into contact with air from the start to the end of the peeling.

A method for manufacturing a semiconductor device or a method for treating a semiconductor surface according to another aspect of the present invention adds H to HF and H ₂ O having a dissolved oxygen concentration of 100 ppb or less while applying vibration at a frequency of 500 kHz or more. The semiconductor surface is cleaned with the cleaning solution.

  From the start to the end of cleaning, the cleaning chemical solution and the semiconductor device may not be exposed to air.

  Although the above description has been given for a silicon surface having a substantially (110) plane orientation, the method for planarizing a silicon surface according to the present invention is not limited to a silicon surface having a substantially (110) plane orientation. Even when applied to a silicon surface having a substantially (100) plane orientation, the silicon surface can be flattened to a centerline average roughness Ra of 0.09 nm or less.

  According to the present invention, the flatness of the silicon surface is reduced by reducing the surface roughness (Ra) of about 1.0 nm obtained by conventional RCA cleaning to 0.05 nm by performing the flattening process in an atmosphere containing radical oxygen. It was possible to make it even 0.02 nm. As a result, in the silicon having the (110) plane orientation on the surface, the carrier electron mobility can be improved by 1.6 times compared to the prior art, and is equal to or higher than the mobility in the (100) plane orientation. Can be made. Further, since the interface between the silicon surface and the gate insulating film is atomically flat, the reliability of the gate clean film is improved. If the planarization method according to the present invention is used, the center line average roughness Ra of the (100) plane orientation silicon surface can be made 0.09 nm or less. The characteristics of the formed semiconductor device can also be improved.

Principle of the invention :
Below, the case where a field effect transistor is comprised using (110) silicon is demonstrated. First, the factor (rate-limiting factor) that determines the mobility of carrier electrons on the (110) silicon surface will be described. Usually, (1) impurity scattering μ _co and (2) phonon scattering μ _ph are the rate-limiting factors of mobility. (3) Three factors of surface roughness scattering μ _sr are mentioned. Furthermore, the observed mobility μ is an addition of three factors, is given by Matterson's law, and is known to be expressed by the following equation.

Among the three rate-determining factors described above, it has been found that electron carriers on the (110) plane are greatly affected by the roughness of the silicon surface (ie, surface roughness scattering μ _sr ). Actually, when investigating the relationship between mobility and effective electric field at extremely low temperatures, impurity scattering μ _co and phonon scattering μ _ph can be substantially ignored, and only the influence of surface roughness scattering μ _sr is extracted. I can do it. Therefore, as a result of investigating the relationship between the mobility and the effective electric field at 77k, it was found that the influence of the interface roughness on the mobility is greater in the (110) plane than in the (100) plane.

  Furthermore, referring to FIG. 2, the result of examining the relationship between the centerline average group Ra and the interface roughness spectrum by simulation is shown. Considering that Ra that can actually be realized using the conventional method is about 0.4 nm, the relationship between the centerline average group Ra and the interface roughness spectrum shown in FIG. 2 is smaller than the limit of the conventional method. It can be seen that the relationship is in the Ra region. Here, the interface roughness spectrum is not the roughness physically obtained by measurement or the like, but the roughness actually felt by the carrier, and is defined as the following equation.

  Here, Δ is the center line average roughness Ra of the interface roughness, Λ is the average period of the interface roughness, and q is the difference between the incident wave vector k to the carrier interface and the reflected wave vector k ′. (Ie q = k−k ′).

  As shown in FIG. 2, in the (100) plane, the change in the interface spectrum is negligibly small with respect to the change in Ra. On the other hand, in the case of the (110) plane, it can be seen that the roughness spectrum decreases and the carrier mobility increases as Ra decreases. Further, as is apparent from FIG. 2, it can be estimated by simulation that the mobility in (110) silicon is improved to Ra and the level equivalent to the electron mobility in (100) silicon by setting the Ra to 0.07 nm or less. .

  Accordingly, the gist of the present invention is that the Ra of the (110) silicon surface can be flattened to 0.4 nm or less, particularly 0.15 nm or less, preferably 0.07 nm or less, which is the conventional limit, and flattened silicon. The object is to obtain a semiconductor device formed by using the above.

First embodiment :
With reference to FIG. 3, the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention is demonstrated.

First, as shown in FIG. 3A, p-type (110) silicon 301 is prepared, and element isolation is performed on the surface thereof by, for example, STI (Shallow Trench Isolation) method, thereby including an element region including a source / drain region and a channel region. 302 is formed.

  Next, RCA cleaning is performed on the element region 302 in order to remove organic matter, particles, and metal contamination (FIG. 3B). Further, as in the present invention, in a roughness region where fine roughness (roughness) is a problem, it is necessary to consider an increase in roughness during SC1 cleaning, which is one step of RCA cleaning. I understood. In fact, during SC1 cleaning, which is one step of RCA cleaning, it was confirmed that the silicon surface was etched by the OH concentration, and the roughness increased by the etching.

Considering this, in this embodiment, the SC1 cleaning process having a low OH concentration is performed. In a typical conventional SC1 process, a chemical solution of NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 1: 5 is used. However, in the first embodiment of the present invention, NH ₄ OH: H ₂ O ₂ : H ₂ O = 0.05: 1: 5, which is lower than the conventional SC1 treatment.

  In addition, when the defect density such as COP (Crystal Originated Particle) is high in the silicon crystal, it was also observed that the increase in surface roughness was accelerated during the SC1 treatment. Further, it has been found that micropits are formed on the surface after SC1 treatment due to defects, and also induces deterioration of the oxide film breakdown voltage. In particular, when a CZ wafer is used, it is known that the COP density is high.

  Therefore, in order to suppress an increase in surface roughness during the SC1 cleaning, it is preferable that the silicon surface is subjected to a hydrogen annealing process or an argon annealing process to reduce the residual oxygen level to about 5E16 / cm 3. It is preferable to use a silicon wafer having a surface subjected to Si epitaxial growth. In the present embodiment, a silicon wafer having Si epitaxial growth on the surface is used.

  Thus, when the low OH concentration SC1 process was used, the silicon surface had a center line average roughness Ra of about 0.15 nm. When an n-type transistor is manufactured using silicon having such a surface roughness, an n-type transistor having improved mobility as compared with a conventional n-type transistor can be obtained. However, as is clear from FIG. 2, when (110) silicon is used, such a degree of Ra cannot achieve the same mobility as when (100) silicon is used.

  Therefore, in this embodiment, in order to further planarize the surface roughness, as shown in FIG. 3C, the surface of the device region is planarized in an atmosphere containing radical oxygen as a planarization treatment of the silicon surface of the device region. Then, an oxide film 303 is formed. It was confirmed that by forming the oxide film 303 in this radical oxygen atmosphere, the surface of the oxide film 303 is flattened as compared to before the oxide film 303 is formed. It has also been found that isotropic oxidation is performed in the oxidation in a radical oxygen atmosphere.

  Here, the radical oxidation used in FIG. 3C will be described in detail with reference to FIG.

  FIG. 4 shows an example of an apparatus using a radial line slot antenna used for performing the radical oxidation treatment of the present invention. The illustrated apparatus has substantially the same configuration as the plasma apparatus disclosed in Japanese Patent Application No. 9-133422 (see Japanese Patent Application Laid-Open No. 10-33362). The film is formed as follows.

In FIG. 4, the vacuum chamber 401 is first brought to a vacuum state, and then Kr gas and O ₂ gas are introduced from the shower plate 402 to set the pressure in the processing chamber to about 1 Torr. On the other hand, silicon (403) oriented in the (110) plane is placed on a sample stage 404 having a heating mechanism, and the temperature of the sample is set to about 400 ° C. Even if this temperature setting is changed within the range of 200 to 550 ° C., the result almost similar to the result described below can be obtained.

  A microwave of 2.45 GHz is supplied from the coaxial waveguide 405 to the processing nitrogen through the radial line slot antenna 406 and the dielectric plate 407, and high-density plasma is generated in the processing chamber. If the frequency of the supplied microwave is in the range of 900 MHz to 10 GHz, the results described below are almost the same. In this embodiment, the distance between the shower plate 402 and the silicon 403 is 6 cm. A narrower interval enables faster oxidation. In the present embodiment, an example of oxidation using a plasma apparatus using a radial line slot antenna is shown, but microwaves may be introduced into the processing chamber using other methods.

When oxidizing the silicon surface in an atmosphere containing radical oxygen, the effect of high adhesion of oxidized species to the protrusions on the silicon surface, and further, when the radicals hit the protrusions, the protrusions are negatively charged, It is presumed that the effect of easily attracting oxygen ions such as O + and O ₂ + is synergistic and the protrusions are preferentially oxidized, and as a result, a flattened silicon oxide film is formed on the silicon surface. The

  FIG. 5 shows how the surface flatness changes before and after oxidation when dry oxidation is performed on the silicon surface and when oxidation is performed in an atmosphere containing radical oxygen. Here, the initial shows the centerline average roughness Ra after performing the SC1 step of the low OH concentration. As is apparent from the figure, Ra is in the range of 0.14 to 0.16. .

  When a silicon oxide film is formed on such a silicon surface by dry oxidation, Ra changes between 0.17 and 0.19 nm. On the other hand, when a silicon oxide film is formed by radical oxidation as in the present invention, Ra on the surface thereof is smaller than 0.07 nm. Thus, in the case of dry oxidation, the roughness is increased by the oxidation, but it is understood that the flatness is improved by performing radical oxidation. That is, it was found that the surface of the silicon oxide film formed by radical oxidation and the silicon surface after peeling the silicon oxide film were flattened compared to the silicon surface before radical oxidation. In this way, when an oxide film (silicon oxide film) is formed by radical oxidation on the silicon surface cleaned by the RCA SC1 cleaning process at a low OH concentration, the silicon oxide film has a center line average roughness as is apparent from FIG. The thickness Ra can be flattened to 0.06 nm. In other words, the surface of the silicon oxide film can be planarized by performing isotropic oxidation such as radical oxidation. Therefore, the planarized oxide film can be used as it is as a part of the gate insulating film or the gate insulating film without being removed and peeled off.

  The roughness after oxidation shown in FIG. 5 is obtained after the oxide film is immersed in a mixed solution of HF and HCl (volume ratio, HF: HCl = 1.19) for 1 minute and peeled off. In addition, the reason why the mixed liquid of HF and HCI is used for the etching is to suppress the etching of the silicon surface when the insulating film is peeled off by using a chemical solution having a low OH ion concentration as much as possible, and the situation of the interface between the silicon and the gate insulating film is controlled. This is to grasp accurately. Before measuring the roughness after oxidation, (110) silicon was immersed in a mixed solution of HF and HCl for 10 minutes or more, and the change in Ra before and after immersion was examined. As a result, it was confirmed that no change in Ra was observed in (110) silicon before and after the immersion, and no etching of silicon occurred. This confirmed the validity of this evaluation method. Thereafter, the roughness value of the silicon surface under the insulating film is a value evaluated after the insulating film is peeled off by immersing in the mixed solution of HF and HCl for 1 minute.

  As described above, when radical oxidation is performed, the surface flatness can be improved. The planarization of the silicon surface using this radical oxidation treatment is a technique that can be applied to other semiconductor elements without being limited to the silicon plane orientation and the applicable semiconductor elements.

  As shown in FIG. 3D, after the oxide film 303 is formed (FIG. 3C), the oxide film 303 is peeled off. In the present embodiment, the oxide film 303 is peeled off using a chemical solution having a pH of 1 or less mixed at a volume ratio of HF: HCl = 1: 19.

Next, as shown in FIG. 3E, the silicon surface of the element region is oxidized in an atmosphere containing radical oxygen to form a 5 nm gate insulating film (SiO ₂ ) 304. In this state, silicon is mixed in a volume ratio of HF: HCI = 1: 19 and immersed in a chemical solution having a pH of 1 or less for 1 minute to remove the gate insulating film, and the interface between the silicon surface and the gate green eye. When the roughness was evaluated, the center line average roughness Ra was 0.06 nm. As described above, even if the oxide film 303 is left as it is and the oxide film 303 is used as the gate oxide film 304, the gate insulating film 304 having a center line average roughness Ra of 0.06 nm or less is formed similarly. Can do.

  The silicon oxide film formed in the present invention only needs to be present at least in a portion in contact with silicon, and an oxide, nitride, or the like using a different material, an alkaline earth metal, a rare earth metal, or a transition metal on the upper layer. An insulating film in which one or more layers of oxynitride, silicate, and the like are stacked may be used. Further, instead of the silicon oxide film formed in the present invention, a single layer or a laminated structure such as an oxide, nitride, oxynitride, silicate, or the like using an alkaline earth metal, a rare earth metal, or a transition metal may be used. good. Furthermore, a film including any one or more of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film may be used. Here, as an example of a material constituting a high dielectric film that can be used as a gate insulating film in the present invention, a metal in which one or any element of Hf, Zr, Ta, Ti, La, Co, Y, and Al is combined. From silicate, Si, Hf, Zr, Ta, Ti, Y, Nb, Na, Co, Al, Zn, Pb, Mg, Bi, La, Ce, Pr, Sm, Eu, Gd, Dy, Er, Sr and Ba Metal oxide, Si, Hf, Zr, Ta, Ti, Y, Nb, Na, Co, Al, Zn, Pb, Mg, Bi, La, Ce, Pr, a combination of one or any selected elements Metal nitride combining one or any element selected from Sm, Eu, Gd, Dy, Er, Sr and Ba, or Si, Hf, Zr, Ta, Ti, Y, Nb, Na, Co, Al, Zn, Pb, M , Bi, La, Ce, Pr, Sm, Eu, Gd, Dy, Er, include metal oxynitride in combination with one or any one element of Sr and Ba.

  Returning to FIG. 3F, boron is ion-implanted over the entire surface of the silicon 301 in order to control the threshold voltage. After the boron ion implantation, a polycrystalline silicon film is deposited on the entire surface of the silicon 301 and patterned to form a polycrystalline silicon electrode (gate electrode) 305 on the gate insulating film 304 in the element region 302 (FIG. 3 (g)).

  Next, phosphorus is ion-implanted at a low concentration to form n-source and n-drain regions 306 that relax the high electric field (FIG. 3H).

Next, a silicon oxide film (SiO ₂ ) is deposited on the entire surface of the silicon 301 so as to cover the gate electrode 305 by CVD or the like, and then anisotropic etching is performed on the side wall of the gate electrode 305. Sidewall insulating films 307 are formed (FIG. 3I).

  Thereafter, n-type impurities such as ions were implanted at a high concentration to form n + source and n + drain regions 308, and an n-type transistor was obtained (FIG. 3 (j)).

  Next, the relationship between Ra and mobility after RCA cleaning shown in FIG. Here, by changing the ammonia concentration during SC1 cleaning in the RCA cleaning step, the center line average roughness Ra of the silicon surface is changed from 0.05 to 0.18 nm, and the roughness scattering component of mobility at that time I examined the changes.

  FIG. 6 shows the result in FIG. FIG. 6 shows that the mobility increases as Ra decreases. When the SC1 process having the low OH concentration described above is used, Ra is about 0.15 nm, which can be said to be a flat limit that can be achieved by cleaning. On the other hand, as in the first embodiment of the present invention, the formation of an oxide film by radical oxidation and the step of removing it were performed, and thereby Ra could be flattened to 0.05 nm.

  As is clear from the relationship between the Ra and mobility of (110) silicon shown in FIG. 6, the improvement phenomenon of electron mobility could be confirmed by setting Ra to 0.15 nm or less. Moreover, when Ra was 0.09 nm or less, it turned out that a mobility increases rapidly. It can be said that 0.09 nm is an inflection point at which a rapid increase in mobility starts to occur. Further, by flattening Ra to 0.07 nm, mobility equivalent to the carrier electron mobility obtained on the (100) surface can be obtained, and it can be predicted that the mobility is improved to 0.05 nm or less.

  The above is the knowledge that can be obtained for the first time because a very flat surface can be obtained by performing the radical oxidation after washing.

  As is clear from FIG. 6, in the first embodiment, Ra = 0.05 nm can be achieved, and the mobility of the n-type transistor can be improved 1.6 times compared to the prior art. It was.

Furthermore, since the interface between the silicon surface and the gate insulating film is flatter than in the prior art, the reliability of the gate insulating film can also be improved.

  The above improvement in carrier electron mobility on the (110) silicon surface can be easily applied not only to field effect transistors but also to semiconductor elements such as TFTs, CCDs, and IGBTs.

Second embodiment :
Next, with reference to FIG. 7, a method for manufacturing a semiconductor device according to the second embodiment will be described.

  In the first embodiment, the (110) silicon surface subjected to Si epitaxial growth treatment on the surface is used. However, in the second embodiment, the (110) silicon surface subjected to Si epitaxial growth treatment on the surface is < A case where a silicon surface which is turned off by 8 ° in the 100> direction is used and a silicon oxynitride film is further used will be described. The above-mentioned plane turned off by 8 ° can be rephrased as a (551) silicon surface, and the (551) silicon surface is substantially included in the (110) silicon surface.

  As shown in FIG. 7A, element isolation is performed on the surface of p-type (551) silicon 701 by, for example, STI (Shallow Trench Isolation), thereby forming an element region 702 including a source / drain and a channel region. The

Next, as shown in FIG. 7B, the element region 702 is subjected to RCA cleaning in order to remove organic matter, particles, and metal contamination. As in the first embodiment, NH ₄ OH: H ₂ O ₂ : H ₂ O = 0.05: 1: 5, a chemical solution with a reduced OH concentration, is used to suppress an increase in roughness during SC1. It was used.

  Thereafter, as shown in FIGS. 7C and 7D, a sacrificial oxide film 703 is formed on the surface of the element region in an atmosphere containing radical oxygen at 300 ° C. to 500 ° C. as a planarization process of the silicon surface of the element region. Further, the sacrificial oxide film is peeled off. In the present embodiment, a chemical solution having a pH of 1 or less mixed at a volume ratio of HF: HCl = 1: 19 was used for removing the sacrificial oxide film. When the surface condition at that time is observed, as shown in FIG. 8, a step shape is formed in a self-aligning manner by a step along the <−110> direction and a terrace with the (110) plane appearing on the surface. appear. The step height is preferably about 0.17 to 0.35 nm, and the center line average roughness Ra is preferably about 0.04 nm. As described above, the sacrificial oxide film does not necessarily have to be peeled off.

  Next, as shown in FIG. 7E, the silicon surface of the element region is oxidized in an atmosphere containing radical oxygen to form a gate insulating film (oxynitride film) 704. In this state, the gate insulating film was immersed and peeled off in a chemical solution having a pH ratio of 1 or less mixed at a volume ratio of HF: HCl = 1: 19, and the interface roughness between the silicon surface and the gate insulating film was evaluated. A line average roughness Ra of 0.05 nm was achieved. For comparison, the centerline average roughness Ra of the silicon surface that was not subjected to radical sacrificial oxidation treatment was 0.15 nm.

The gate silicon oxynitride film of the field effect transistor of the present invention can be formed by using a microwave-excited plasma treatment (FIG. 4) using a radial line slot antenna, as in the first embodiment. Specifically, the silicon oxynitride film is formed as follows. First, the inside of the vacuum chamber 401 shown in FIG. 4 is evacuated, Kr gas, O ₂ gas, and NH ₃ gas are introduced from the shower plate 402, and the pressure in the processing chamber is set to about 1 Torr. On the other hand, on a sample stage 404 having a heating mechanism, silicon (403) oriented in the (110) plane is placed, and the temperature of the sample is set to about 400 ° C. This temperature setting is in the range of 200 to 550 ° C., and the results described below are almost the same.

  In this state, a 2.45 GHz microwave is supplied from the coaxial waveguide 405 through the radial line slot antenna 406 and the dielectric plate 407 into the processing chamber, and high-density plasma is generated in the processing chamber. The distance between the shower plate 402 and the silicon 403 is 6 cm in this embodiment. In the description of the present embodiment, an example in which oxidation is performed using a plasma apparatus using a radial line slot antenna is shown, but microwaves may be introduced into the processing chamber using other methods.

In the formation of the silicon oxynitride film of the present invention, the presence of hydrogen is one important requirement. Due to the presence of hydrogen in the plasma, dangling bonds in the silicon oxynitride film and at the interface are terminated by forming Si—H and N—H bonds, and as a result, electron traps at the silicon oxynitride film and the interface are generated. Disappear. The presence of Si—H bonds and N—H bonds in the oxynitride film of the present invention has been confirmed by measuring F11R and XPS, respectively. The presence of hydrogen eliminates the hysteresis of the CV characteristics, and the interface density between silicon and the silicon oxynitride film can be suppressed to a low level of 3 × 10 ¹⁰ cm ⁻² . When a silicon oxynitride film is formed using a mixed gas of a rare gas (Ar or Kr) and O ₂ , N ₂ , H ₂ , the partial pressure of hydrogen gas is set to 0.5% or more, It was found that the traps of electrons and holes in the film decreased rapidly.

In the present invention, the silicon nitride film can be formed by using, for example, Kr gas or NH ₃ gas as the gas introduced into the microwave-excited plasma processing chamber.

  Furthermore, the silicon oxynitride film or silicon nitride film formed in the present invention may be present at least in a portion in contact with silicon, and an oxidation using a different material, alkaline earth metal, rare earth metal, or transition metal on the upper layer. An insulating film in which one or more layers of nitride, nitride, oxynitride, silicate, or the like are stacked may be used. Further, instead of the silicon oxynitride film formed in the present invention, a single layer or a laminated structure such as an oxide, nitride, oxynitride, silicate, or the like using an alkaline earth metal, a rare earth metal, or a transition metal may be used. good.

  Returning to FIG. 7, after the gate insulating film is formed, boron is ion-implanted over the entire surface of the silicon 701 to control the threshold voltage (FIG. 7F).

  Subsequently, a polycrystalline silicon film is deposited on the entire surface of the silicon 701 and patterned to form a polycrystalline silicon electrode 705 on the gate insulating film 703 in the element region 702 as shown in FIG. Are formed as gate electrodes. Next, as shown in FIG. 7H, phosphorus is ion-implanted at a low concentration to form n-source and drain regions 706 that relax the high electric field.

Further, a silicon oxide film (SiO ₂ ) is deposited on the entire surface of the silicon 701 so as to cover the gate electrode 4 by a CVD method or the like, and then anisotropic etching is performed, as shown in FIG. As described above, a sidewall insulating film 707 is formed on the sidewall of the gate electrode 705.

  Thereafter, an n-type impurity such as arsenic was ion-implanted at a high concentration to form n + source and drain regions 708, whereby an n-type transistor was obtained (FIG. 7 (j)).

  As a result of evaluating the carrier electron mobility of the field effect transistor manufactured by the manufacturing method according to the second embodiment of the present invention described above, the mobility can be improved by 1.6 times compared to the conventional technique. It was.

  Furthermore, since the interface between the silicon surface and the gate insulating film is flatter than in the prior art, the reliability of the gate insulating film can also be improved.

  As described above, the embodiment in which the silicon surface is planarized by radical sacrificial oxidation treatment has been described. However, flatness can be maintained or improved even by using a technique other than radical sacrificial oxidation treatment.

Third embodiment :
First, an embodiment for improving flatness using wet oxidation will be described as a third embodiment.

(110) silicon having a surface having a relatively large roughness is prepared, and the silicon surface is wet-oxidized under the conditions of 1000 ° C., H ₂ = 1 slm, O ₂ = 1 slm to form a silicon oxide film 3000A ( First step). Next, etch back the silicon oxide film with a H ₂ O chemical solution containing HF until the remaining film thickness becomes 0 to 2500 A (second step), and then repeat the first step and the second step twice. Finally, the silicon oxide film was completely removed using a chemical solution having a pH of 1 or less mixed at a volume ratio of HF: HCl = 1: 19.

  The result is shown in FIG. The horizontal axis in FIG. 9 indicates the amount (thickness) of the remaining silicon oxide film in the second step, and the vertical axis indicates the centerline average roughness Ra. As a reference, a silicon oxide film of 9000 A formed at a time and the silicon oxide film peeled off using a chemical solution having a pH of 1 or less mixed at a volume ratio of HF: HCl = 1: 19 is shown.

  As a result, it is found that Ra decreases as the remaining film thickness at the time of etch back in the second process is reduced, and is almost saturated at the remaining film thickness of 1000A. However, if the remaining film 0, that is, the silicon oxide film is completely peeled off, the planarization effect is lost.

  This is presumed to be due to the fact that, when the silicon surface is exposed by the chemical treatment, the factors that obstruct the planarization such as attack of the silicon surface and adhesion of metal contamination due to the chemical itself increase. Further, if the remaining film amount in the second process is set to an appropriate value, for example, the remaining film 100A, the process in which the first process and the second process are repeated rather than forming and peeling the 9000A silicon oxide film at a time. It was confirmed that the effect of flattening was higher.

  The mechanism of the planarization effect due to oxidation and etchback is unknown, but if the remaining film is thinned by etchback, the oxidized species during wet oxidation can easily reach the vicinity of the interface between silicon and silicon oxide. It is guessed.

  Further, the relationship between the number of repetitions of the first step and the second step and the flatness is examined, and the result is shown in FIG. In FIG. 10, the horizontal axis represents the number of repetitions, and the vertical axis represents the centerline average roughness Ra. As is clear from FIG. 10, when the number of repetitions exceeds 3, the tendency of saturation is almost observed, and it has been confirmed that the number of repetitions has an appropriate value.

  As described above, oxidation using wet gas is performed (first step), etch back is performed from 10 A to 1000 A without peeling the oxide film (second step), and then the first step and the second step are desired. The silicon surface can be flattened as compared with the initial wafer also by peeling the oxide film several times and finally with an aqueous solution containing HF.

Fourth embodiment :
Next, a method for maintaining and improving flatness using chemical processing will be described as a fourth embodiment of the present invention. As described above, the RCA cleaning is frequently used for cleaning the silicon surface. However, the SC1 cleaning in the RCA cleaning step (silicon in the ammonia, hydrogen peroxide solution and pure water solution heated to about 80 ° C. is used. It is known that a portion having a weak Si—Si bond is attacked by OH ions during the cleaning of the Si surface and the Si surface is roughened. In the SC1 treatment, oxidation of the silicon surface with hydrogen peroxide, Si—O etching with OH ions, and etch back by Si—Si etching are simultaneously performed. Although it has the feature that the effect of particle removal and organic substance contamination removal is high, there exists a side effect of roughening the Si surface. In order not to roughen the silicon surface as much as possible, a cleaning method that eliminates alkali cleaning is required. JP-A-11-057636 discloses a cleaning method using five steps as a cleaning method that eliminates alkali cleaning treatment and has particle removal, organic contamination removal, and metal contamination removal capability equal to or higher than those of RCA. ing.

The cleaning method disclosed in the publication is a first step of cleaning with pure water containing ozone, and cleaning with a cleaning liquid containing HF, H ₂ O, and a surfactant while applying vibration at a frequency of 500 kHz or higher. A second step of performing cleaning, a third step of cleaning with pure water containing ozone, a fourth step of cleaning with a cleaning solution containing HF and H ₂ O for removing the silicon oxide film, and cleaning with pure water It consists of the 5th process to perform.

  Since the cleaning method disclosed in Japanese Patent Application Laid-Open No. 11-057636 does not include alkali treatment as described above, it is estimated that cleaning can be performed without impairing the flatness of the Si surface. Shows an example in which the surface before or after cleaning is maintained at 0.11 nm in Ra. However, this publication does not point out the fact that the surface roughness (Ra) becomes rough when RCA cleaning is performed. Further, this publication shows experimental results by a part of the present inventors and the like, and is experimental results conducted only on silicon having (100) plane orientation on the surface thereof. In the case of silicon having (110) plane orientation on its surface, an initial wafer having a thickness of 0.15 nm or less cannot be obtained, and Ra of 0.15 nm or less cannot be obtained using this method. Japanese Patent Application Laid-Open No. 11-057636 does not disclose a method of setting the centerline average roughness Ra of (100) plane orientation to (0.09) nm or less.

The present inventors flatten the surface by degassing H ₂ O used in the second step and the fourth step among the first to fifth steps described above to reduce the amount of dissolved oxygen. It was found that sex can be maintained. Here, this method will be described as a fourth embodiment of the present invention. In the second step of the fourth embodiment, the silicon oxide film formed in the first step is removed, particles are removed, Similarly, in the fourth step, the silicon oxide film formed in the third step is removed to remove metal contamination.

  In the second and fourth steps, when dissolved oxygen is present in the chemical solution, a weak part of the Si-Si bond is selectively reoxidized on the Si surface removed by HF and further removed by HF. Proceed simultaneously, resulting in an increase in surface roughness. Therefore, in the fourth embodiment, the amount of dissolved oxygen in the second and fourth steps is lowered from the conventional ppm order to 100 ppb or less (preferably 10 ppb or less), and the chemical treatment is performed. As a result, surface roughness (Ra) It was found that can be maintained.

More specifically, (110) cleaning with pure water containing 5 ppm of ozone is performed for 5 minutes (first step), and 0.5% HF water deaerated while giving vibration at a frequency of 950 kHz, Cleaning with a cleaning solution containing degassed H ₂ O and 50 ppm of surfactant was performed for 5 minutes (second step). Next, cleaning with pure water containing 5 ppm of ozone is performed for 5 minutes (third step), and cleaning with a cleaning solution containing degassed 0.5% HF and degassed H ₂ O to remove the oxide film is performed. Was performed for 1 minute (fourth step), and cleaning with ultrapure water in which 0.1 to 50 ppm of H was added to degassed H ₂ O was performed for ten minutes (fifth step).

  The cleaning was performed by immersing silicon in the cleaning solution. FIG. 11 shows the result of comparing the roughness of the cleaned silicon surface with a conventional RCA. As is clear from FIG. 11, when the conventional RCA cleaning is performed on the silicon surface with Ra of 0.08 nm before the cleaning, the surface becomes rough to 0.13 nm. However, in the embodiment of the present invention, the surface is rough as 0.10 nm. Can be seen to ease.

As in the present invention, when the silicon oxide film is peeled off, the surface roughness of the silicon surface can be alleviated by using a cleaning solution containing HF and H ₂ O having a dissolved oxygen concentration of 100 ppb or less. The technology that can be applied is applicable not only to silicon having a substantially (110) plane orientation but also to other plane orientations (for example, (100) plane orientation). Furthermore, the present invention can also be used when any one of a silicon nitride film and a silicon oxynitride film is peeled off.

In addition, by degassing H ₂ O used in the second step and the fourth step, and then adding 0.1 to 50 ppm of hydrogen, in addition to the effect of lowering the amount of dissolved oxygen, an attempt is made to lower the OH ion concentration. FIG. 11 also shows the result of comparison with RCA. As a result, it can be seen that Ra is reduced by about 0.01 nm compared to 0.08 nm of the initial wafer, but the level is reduced. In particular, in the second step, the conventional technique has a problem that H ₂ O is dissociated into H and OH and the OH concentration is increased when the treatment is performed while applying vibrations having a frequency of 500 kHz or more. In the present invention, Ra is substantially removed by performing cleaning with a cleaning solution containing 50 ppm of H ₂ O added with 50 ppm of H after degassing and reducing dissolved oxygen to 100 ppb or less. Can be maintained. This means that ultrasonic cleaning with suppressed generation of OH is performed in the second step. The dissolved oxygen is preferably 10 ppb or less.

Furthermore, H ₂ O used in the second step and the fourth step is degassed, and then, in addition to using a chemical solution to which 0.1 to 50 ppm of hydrogen is added, the cleaning process starts and ends when the five processes are performed. Until now, both the cleaning chemical and the silicon surface were treated in an apparatus that was not exposed to air, thereby preventing oxygen from dissolving into the chemical from the air. The result compared with the conventional RCA is also shown in FIG. As is clear from the figure, it can be seen that the surface roughness (Ra) can be maintained without causing roughness as compared with 0.08 nm of the initial wafer.

The semiconductor treatment or cleaning described above may be performed only with a non-alkaline liquid having a pH of 7 or less. In this case, ultrasonic cleaning may be performed while suppressing generation of OH, and suppression of generation of OH may be performed by adding H ₂ .

  In any case, in the embodiment shown in FIG. 11, the silicon surface having a center line average roughness Ra of 0.11 nm or less can be obtained by cleaning silicon with (110) orientation in five steps. did it. Further, when applied to silicon having a (100) plane orientation, a center line average roughness of 0.09 nm or less could be obtained.

  Referring to FIGS. 12A and 12B, each of the pMOS and nMOS transistors in the case where the pMOS and nMOS transistors are actually formed on the silicon surface having the (110) plane orientation flattened by the method of the present invention described above. The mobility of pMOS and nMOS transistors is shown. As is well known, the mobility of the pMOS and nMOS transistors is evaluated by the hole mobility and the electron mobility, respectively. As is clear from FIG. 12A, the pMOS according to the present invention has a large mobility (110) compared to the mobility (100) of the pMOS formed on the conventional (100) silicon surface. You can see that Referring to FIG. 12 (b), the nMOS according to the present invention shown in (110) shows slightly lower electron mobility than the nMOS formed on the (100) plane silicon surface. The electron mobility improved compared with the conventional nMOS formed on the (110) plane.

  In any case, the pMOS and nMOS according to the present invention exhibit hole mobility and electron mobility improved by about 20% compared to the pMOS and nMOS formed on (110) silicon by the conventional method. There was found.

  Next, referring to FIG. 13, the measurement results of (1 / f) noise in the conventional nMOS formed on the (100) plane and the pMOS and nMOS of the present invention formed on the flattened (110) plane are shown. It is shown. As is apparent from FIG. 13, the pMOS and nMOS according to the present invention can improve the (1 / f) noise characteristics by about one digit compared with the conventional nMOS formed in (100) silicon.

It is process drawing explaining the manufacturing process of the field effect transistor in a prior art. It is a graph which shows the simulation result which investigated the relationship between the centerline average roughness Ra of a silicon surface, and an interface roughness spectrum. It is process drawing which shows the manufacturing process of the field effect transistor which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows schematic structure of the apparatus used at the manufacturing process of FIG. It is a graph explaining the effect by the manufacturing method concerning a 1st embodiment of the present invention, and shows the dependence of the oxidation method to the planarization of the silicon surface here. It is a graph explaining the relationship between the centerline average group Ra on the silicon surface and the electron mobility. It is process drawing explaining the manufacturing method of the field effect transistor which concerns on the 2nd Embodiment of this invention. It is a schematic diagram of the atomic step in the (551) plane used with the manufacturing method shown by FIG. It is a graph which shows the relationship between the etch-back residual film quantity of the silicon oxide film in the 2nd process of the manufacturing method which concerns on the 3rd Embodiment of this invention, and Ra. It is a figure which shows the relationship between Ra and the frequency | count of repetition of the 1st process performed in the 3rd Embodiment of this invention, and a 2nd process. It is a graph which shows the effect of the surface flatness maintenance technique concerning a 4th embodiment of the present invention. (A) And (b) is a graph explaining the mobility of pMOS and nMOS concerning the present invention, respectively. It is a graph explaining the (1 / f) noise characteristic of pMOS and nMOS concerning the present invention compared with conventional nMOS.

Explanation of symbols

301, 701 p-type (110) silicon 302, 702 element region 303, 703 oxide film 304, 704 gate insulating film 305, 705 gate electrode 306, 706 n-source, drain region 307, 707 sidewall insulating film 308, 708 n + source , Drain region

Claims (59)

In a semiconductor device formed using a (110) plane or a (551) plane oriented silicon surface,
A semiconductor device characterized in that the surface roughness is 0.15 nm or less in terms of centerline average roughness Ra. 2. The semiconductor device according to claim 1 , wherein the silicon surface has a center line average roughness Ra of 0.11 nm or less. 3. The semiconductor device according to claim 2 , wherein the silicon surface has a center line average roughness Ra of 0.09 nm or less. 4. The semiconductor device according to claim 3 , wherein the silicon surface has a center line average roughness Ra of 0.07 nm or less. 5. The semiconductor device according to claim 4 , wherein the silicon surface has a center line average roughness Ra of 0.02 nm or more. In a field effect transistor having a source region, a drain region, a channel region, a gate insulating film formed on the channel region, and a gate electrode on the gate insulating film, the channel region has a (110) plane or (551) A semiconductor device formed on a silicon surface having a plane orientation, wherein the silicon surface has a center line average roughness Ra of 0.09 nm or less. In a field effect transistor having a source region, a drain region, a channel region, a gate insulating film formed on the channel region, and a gate electrode on the gate insulating film, the channel region has a (110) plane or (551) A semiconductor device formed on a silicon surface having a plane orientation, wherein the silicon surface has a center line average roughness Ra of 0.15 nm or less. 8. The semiconductor device according to claim 7 , wherein the center line average roughness Ra is 0.11 nm or less. 8. The semiconductor device according to claim 7 , wherein the center line average roughness Ra is 0.07 nm or less. 8. The semiconductor device according to claim 6 , wherein the gate insulating film of the field effect transistor includes one or more of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. 8. The semiconductor device according to claim 6 , wherein the gate insulating film contains a rare gas element. 8. The semiconductor device according to claim 6 , wherein the gate insulating film of the field effect transistor includes a dielectric film having a high relative dielectric constant. 13. The semiconductor device according to claim 12 , wherein the dielectric film includes at least one selected from the group consisting of metal silicide, metal oxide, and metal nitride. 14. The metal silicide according to claim 13 , wherein the metal silicide includes at least one selected from the group consisting of Hf, Zr, Ta, Ti, La, Co, Y, and Al together with silicon. Semiconductor device. 14. The metal oxide according to claim 13 , wherein the metal oxide is Si, Hf, Zr, Ta, Ti, Y, Nb, Na, Co, Al, Zn, Pb, Mg, Bi, La, Ce, Pr, Sm, Eu, Gd. A semiconductor device comprising at least one selected from Dy, Er, Sr and Ba. 14. The metal nitride according to claim 13 , wherein the metal nitride, together with N, is Si, Hf, Zr, Ta, Ti, Y, Nb, Na, Co, Al, Zn, Pb, Mg, Bi, La, Ce, Pr, Sm, A semiconductor device comprising at least one selected from Eu, Gd, Dy, Er, Sr and Ba. 8. The gate insulating film according to claim 6 , wherein the gate insulating film has a structure in which a film selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a dielectric film having a high relative dielectric constant is combined. A featured semiconductor device. A method of manufacturing a semiconductor device includes a step of planarizing a silicon semiconductor surface having a (110) plane or a (551) plane orientation so as to have a center line average roughness Ra of 0.09 nm or less. A method for manufacturing a semiconductor device. In a method for manufacturing a semiconductor device, a silicon surface having a (110) plane or (551) plane orientation is prepared, and the silicon surface is flattened so as to have a predetermined centerline average roughness Ra of 0.15 nm or less. The manufacturing method of the semiconductor device characterized by including the formation process. 20. The silicon surface according to claim 18 , wherein the planarization step cleans the silicon surface using at least a RCA SC-1 cleaning solution in which NH ₄ OH: H ₂ O ₂ : H ₂ O = 0.05: 1: 5. And a step of forming an oxide film on the cleaned silicon surface by oxidizing the cleaned silicon surface in an atmosphere containing oxygen radicals. 21. The method of manufacturing a semiconductor device according to claim 20 , wherein the oxide film is used as a gate insulating film or a part of the gate insulating film, and includes a step of forming a gate electrode on the gate insulating film. In the method for manufacturing a semiconductor device, a silicon surface having a (110) plane or a (551) plane orientation is prepared, and a first oxide film is formed by oxidizing the silicon surface by an isotropic oxidation process . 1. A method for manufacturing a semiconductor device , comprising the step of removing one oxide film, whereby the silicon surface is planarized to 0.15 nm or less in terms of centerline average roughness Ra .
23. The semiconductor device according to claim 22 , wherein the isotropic oxidation step and the removal step are repeated a plurality of times until a surface roughness of 0.15 nm or less is obtained in terms of the centerline average roughness Ra. Production method. 23. The method of manufacturing a semiconductor device according to claim 22 , further comprising a step of forming a gate insulating film on the planarized silicon surface and a step of forming a gate electrode on the gate insulating film. 23. The method of manufacturing a semiconductor device according to claim 22 , wherein the isotropic oxidation step includes radical oxidation of the silicon surface at a temperature of 550 [deg.] C. or less. Including a step of forming a sacrificial oxide film on a silicon surface having a (110) plane or (551) plane orientation of a semiconductor region in an atmosphere containing oxygen radicals, and a step of removing the sacrificial oxide film. When the flatness of the silicon surface in the region is expressed by the center line average roughness Ra, the surface roughness is improved to 0.15 nm or less . A method of manufacturing a semiconductor device including a channel region and a gate insulating film, in an atmosphere containing oxygen radicals, forming a sacrificial oxide film on a silicon semiconductor surface having a (110) plane or (551) plane orientation, the sacrificial By the step of removing the oxide film, the flatness of the silicon semiconductor surface of the channel region is improved to a surface roughness of 0.15 nm or less when expressed by the centerline average roughness Ra, and the channel region having the improved flatness is improved. A method of manufacturing a semiconductor device, wherein a gate insulating film is formed on a silicon semiconductor surface. 20. The method for manufacturing a semiconductor device according to claim 18 , wherein the planarization step is performed without exposing the silicon surface to the atmosphere. 28. The process of forming an oxide film according to claim 20 , wherein the oxide film is generated by microwave excitation in a mixed gas of a rare gas containing at least one of Ar, Kr, and Xe and an oxygen gas. A method for manufacturing a semiconductor device, which is performed using gas plasma. 21. The silicon surface according to claim 18 , wherein the planarization step uses a gas plasma generated by microwave excitation in a mixed gas of a rare gas containing at least one of Ar, Kr, and Xe and oxygen gas. The manufacturing method of the semiconductor device characterized by including the process of oxidizing. 20. The method of manufacturing a semiconductor device according to claim 19 , wherein the predetermined center line average roughness Ra is 0.09 nm or less. 20. The method according to claim 18 , further comprising a step of forming a gate insulating film on the silicon surface, wherein the step of forming the gate insulating film includes a step of oxidizing the silicon surface in an atmosphere containing oxygen radicals, and a nitrogen radical. Alternatively, a method for manufacturing a semiconductor device, comprising at least one of a step of nitriding a silicon surface in an atmosphere containing NH radicals or a simultaneous parallel processing step. 33. The process of claim 32 , wherein the step of forming the gate insulating film comprises: Ar, Kr. Preparing a mixed gas of a rare gas selected from at least one of Xe and an insulating film forming gas selected from at least one of ammonia, nitrogen, oxygen, NO, and N ₂ O;
And a step of generating plasma by microwave excitation in the mixed gas. The planarization step according to claim 19 , wherein the planarization step includes a first step of forming an oxide film on the silicon surface by performing an oxidation treatment using water vapor.
A second step of partially removing the oxide film in a thickness direction, and leaving an oxide film having a thickness of 10 to 1000 angstroms on the silicon surface, wherein the first and second steps are at least And a third step of completely removing the oxide film with an aqueous solution containing HF after being performed once. 20. The method for manufacturing a semiconductor device according to claim 18 , further comprising a cleaning step of cleaning the silicon surface. 36. The cleaning step according to claim 35 , wherein the cleaning step includes a step of cleaning the silicon surface by an RCA cleaning process using a solution of NH ₄ OH: H ₂ O ₂ : H ₂ O = 0.05: 1: 5. A method for manufacturing a semiconductor device. 36. The method of manufacturing a semiconductor device according to claim 35 , wherein the cleaning step includes a step of cleaning the silicon surface with a cleaning liquid having a pH of 7 or less. 36. The cleaning process according to claim 35 , wherein the cleaning step includes a first step of rinsing the silicon surface using ultrapure water containing ozone, HF, H ₂ O in which dissolved oxygen is reduced, and a surfactant. A second step of cleaning the silicon surface while applying a vibration having a frequency of 500 kHz or higher using a cleaning liquid; and a third step of rinsing the silicon surface using H ₂ O containing ozone. , Using a cleaning solution containing HF and H ₂ O with reduced dissolved oxygen, cleaning the silicon surface to remove the oxide film, and using H ₂ O added with hydrogen, And a fifth step of rinsing the silicon surface. 39. The method of manufacturing a semiconductor device according to claim 38 , wherein hydrogen is added to the cleaning liquid in at least one of the second and fourth steps. 36. The method of manufacturing a semiconductor device according to claim 35 , further comprising a step of treating the silicon surface with a cleaning solution containing HF and H ₂ O containing dissolved oxygen of 100 ppb or less. Having in claim 35, wherein the cleaning step and HF, the following dissolved oxygen 100 ppb, providing a cleaning liquid containing a _{H 2} O containing hydrogen 0.1Ppm～1.6Ppm, a 500kHz or more frequencies in the cleaning solution A method for manufacturing a semiconductor device, wherein cleaning is performed by applying vibration. 36. The method of manufacturing a semiconductor device according to claim 35 , wherein the cleaning step is performed without exposing the silicon surface to air. 36. The method of manufacturing a semiconductor device according to claim 35 , wherein the cleaning step is performed by bringing the silicon surface into contact with a cleaning solution and applying ultrasonic waves to the cleaning solution while suppressing generation of OH in the cleaning solution. Method. 36. The cleaning process according to claim 35 , wherein the cleaning step includes a first step of cleaning the silicon surface using H ₂ O containing ozone, and a cleaning liquid containing HF, H ₂ O, and a surfactant with a high frequency of 500 kHz or more. Cleaning is performed to remove the oxide film using a second step of cleaning while applying vibration, a third step of cleaning with H ₂ O containing ozone, and a cleaning solution containing HF and H ₂ O. a fourth step of performing, using H _{2 O} was added hydrogen or deuterium, while giving vibration of frequencies above 500 kHz, was washed, fifth to terminate the silicon surface with hydrogen or deuterium A method for manufacturing a semiconductor device comprising the steps of: 45. The method for manufacturing a semiconductor device according to claim 44, wherein oxygen is removed from H ₂ O in the second and fourth steps and hydrogen is added. 45. The method of manufacturing a semiconductor device according to claim 44 , wherein the first to fifth steps are performed without exposing the silicon surface to air. A first step of forming an oxide film by performing an oxidation treatment using a wet gas on a silicon surface having a (110) plane or a (551) plane orientation ;
A second step of etching back to a thickness of 10 A or more and 1000 A or less without peeling off the oxide film;
Thereafter, the first step and the second step are repeated as many times as desired.
Finally, an oxide film is peeled off with an aqueous solution containing HF, whereby the silicon surface is planarized to 0.15 nm or less in terms of the center line average roughness Ra . In a method for manufacturing a semiconductor device including a step of flattening a silicon semiconductor surface having a (110) plane or a (551) plane orientation to a center line average roughness Ra of 0.15 nm or less,
A first step of cleaning with pure water containing ozone, a second step of cleaning with a cleaning liquid containing HF, degassed H ₂ O, and a surfactant while applying vibration at a frequency of 500 kHz or higher. A third step of cleaning with ozone-containing H ₂ O, a fourth step of cleaning with a cleaning liquid containing HF and degassed H ₂ O to remove the oxide film, and hydrogen-added H ₂ A method for manufacturing a semiconductor device, comprising: a cleaning method including a fifth step of cleaning with O. The method of manufacturing a semiconductor device according to claim 48, degassed of H _{2 O} said second and fourth step, H ₂ O formed by adding hydrogen after degassing of H 2 _O A method for manufacturing a semiconductor device, wherein: In a method for manufacturing a semiconductor device including a step of flattening a silicon semiconductor surface having a (110) plane or a (551) plane orientation to a center line average roughness Ra of 0.15 nm or less,
A method of manufacturing a semiconductor device, wherein at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film is stripped with a cleaning liquid containing HF and H ₂ O having a dissolved oxygen concentration of 100 ppb or less. . In a method for manufacturing a semiconductor device including a step of flattening a silicon semiconductor surface having a (110) plane or a (551) plane orientation to a center line average roughness Ra of 0.15 nm or less,
A method of manufacturing a semiconductor device, comprising: cleaning a semiconductor surface with a cleaning liquid obtained by adding H to HF and H ₂ O having a dissolved oxygen concentration of 100 ppb or less while applying vibration having a frequency of 500 kHz or more. 52. The method of manufacturing a semiconductor device according to claim 48 , wherein the processing is performed in an apparatus in which the processing chemical solution and the semiconductor device are not exposed to air from the start to the end of cleaning of the semiconductor device. A method for manufacturing a semiconductor device. In a method for treating a semiconductor surface which is a silicon surface having a (110) plane or a (551) plane orientation,
Cleaning the semiconductor surface;
And a step of planarizing the cleaned semiconductor surface with a centerline average roughness (Ra) smaller than 0.15 nm . In the method for treating a semiconductor surface, the surface roughness of a silicon semiconductor surface having a (110) plane or a (551) plane orientation is expressed by a center line average roughness Ra to be flattened to 0.15 nm or less .
A first step of oxidizing the semiconductor surface by wet oxidation to form an oxide film;
A second step of etching back the oxide film to a predetermined thickness,
The method further includes the step of peeling the remaining film left in the second step after repeating the first and second steps at least twice, thereby planarizing the semiconductor surface. Semiconductor surface treatment method. In the semiconductor surface processing method of maintaining the surface roughness of 0.15 nm or less when the flatness of the silicon semiconductor surface having the (110) plane or (551) plane orientation is expressed by the centerline average roughness Ra ,
A first step of cleaning the semiconductor surface with pure water containing ozone, and cleaning with a cleaning liquid containing HF, degassed H ₂ O, and a surfactant while applying vibration of a frequency of 500 kHz or more. A second step, a third step of cleaning with H ₂ O containing ozone, a fourth step of cleaning with a cleaning solution containing HF and degassed H ₂ O to remove the oxide film, and hydrogen is added And a fifth step of cleaning with H ₂ O, thereby maintaining the flatness of the surface of the semiconductor surface. In the processing method of the described semiconductor surface to claim 55, degassed of H _{2 O} said second and fourth step, H ₂ O formed by adding hydrogen after degassing of H 2 _O A method for treating a semiconductor surface, wherein: In a method for treating a semiconductor surface including a step of flattening a silicon semiconductor surface having a (110) plane or (551) plane orientation to a center line average roughness Ra of 0.15 nm or less,
A semiconductor surface treatment characterized by stripping any one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film with a cleaning liquid containing HF and H ₂ O having a dissolved oxygen concentration of 100 ppb or less Method. In a method for treating a semiconductor surface including a step of flattening a silicon semiconductor surface having a (110) plane or (551) plane orientation to a center line average roughness Ra of 0.15 nm or less,
A method for treating a semiconductor surface, comprising washing a semiconductor surface with a cleaning liquid obtained by adding H to HF and H ₂ O having a dissolved oxygen concentration of 100 ppb or less while applying vibration having a frequency of 500 kHz or more. 59. The semiconductor surface processing method according to claim 55 , wherein the processing is performed in an apparatus in which the processing chemical solution and the semiconductor surface are not exposed to air from the start to the end of cleaning of the semiconductor surface. A method for treating a semiconductor surface.

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