JP4685834B2 - 集積回路デバイス - Google Patents
集積回路デバイス Download PDFInfo
- Publication number
- JP4685834B2 JP4685834B2 JP2007138865A JP2007138865A JP4685834B2 JP 4685834 B2 JP4685834 B2 JP 4685834B2 JP 2007138865 A JP2007138865 A JP 2007138865A JP 2007138865 A JP2007138865 A JP 2007138865A JP 4685834 B2 JP4685834 B2 JP 4685834B2
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- layer
- integrated circuit
- chip
- substrate
- circuit device
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Junction Field-Effect Transistors (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Combinations Of Printed Boards (AREA)
Description
Sn 5 63 95
Pb 95 37 0
Sb 0 0 5
12 ゲート接続用ランナー
13 ソース領域接続用ランナー
14 ドレイン接点
15 空気絶縁型クロスオーバー領域
21 ポリイミド層
22 ホトレジスト層
23 金属層
32 第1ホトレジスト層
41 キャップ層
42 ドレイン接点ウインドウ
43 アンダーバンプ金属化領域(UBM)
44 第1層
45 第2層
46 第3層
47 第4層
51 相互接続用基板
52 酸化物層
53 タンタル製キャパシタ列
54 アルミ製インダクタ列
55 層
56 メッキボール
57 空隙スペース
58 アンダーバンプ金属化領域
59 誘電体層
61 相互接続用ランナー
62 フリップチップ組立体
63 酸化物層(相互接続用基板)
64 アンダーバンプ金属化層
65 ヒートシンク
Claims (7)
- 集積回路デバイスであって、前記デバイスは、
集積回路(IC)チップ(11)と、
前記集積回路チップ(11)上の複数のドレイン接点(14)と、
前記複数のドレイン接点上に配置された複数の第1のアンダーバンプ金属化領域(43)と、
前記集積回路チップ(11)上に、互いに電気的に孤立する前記複数のドレイン接点(14)の各々の間に位置するソース接点(12)及びゲート接点(13)であって、前記ソース接点(12)及びゲート接点(13)は、前記ソース接点およびゲート接点上並びにそれらの間に配置されたキャップ層(41)によって互いに孤立して配置される、ソース接点(12)及びゲート接点(13)と、
前記集積回路チップ(11)と対向し、酸化物層(52)及び前記酸化物層上の相互接続用ランナー(61)を含む相互接続用基板(51)と、
前記相互接続用ランナー(61)上に、前記複数のドレイン接点(14)と対向する位置に配置された複数の第2のアンダーバンプ金属化領域(58)と、
前記複数のドレイン接点(14)上の第1のアンダーバンプ金属化領域(43)と前記複数のアンダーバンプ金属化領域(58)の間に配置された複数のハンダバンプ(56)、を含み、
前記ドレイン接点(14)は、前記相互接続用ランナー(61)により互いに電気的に接続されていることを特徴とする集積回路デバイス。
- 前記相互接続用基板(51)が、シリコン製基板を含むことを特徴とする請求項1記載の集積回路デバイス。
- 前記相互接続用基板(51)が前記集積回路チップへ結合されたフリップチップであり、前記集積回路チップが第2の相互接続基板に結合されることを特徴とする請求項1記載の集積回路デバイス。
- 前記酸化物層が絶縁層であり、前記相互接続用ランナーが導電金属パターンであることを特徴とする請求項2記載の集積回路デバイス。
- 前記第1及び第2のアンダーバンプ金属化層が、第1層にクロム層、第2層にクロム/銅の遷移層、第3層に銅層、及び第4層に金層を含む多層構造金属化層であることを特徴とする請求項1記載の集積回路デバイス。
- 前記シリコン製基板へ接合されたヒートシンク手段を更に含むことを特徴とする請求項2記載の集積回路デバイス。
- 前記ソース接点、ゲート接点及びドレイン接点がGaAsパワートランジスタを構成することを特徴とする請求項1記載の集積回路デバイス。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/946,693 US6683384B1 (en) | 1997-10-08 | 1997-10-08 | Air isolated crossovers |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10284522A Division JPH11204646A (ja) | 1997-10-08 | 1998-10-06 | 集積回路デバイス |
Publications (2)
Publication Number | Publication Date |
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JP2007274004A JP2007274004A (ja) | 2007-10-18 |
JP4685834B2 true JP4685834B2 (ja) | 2011-05-18 |
Family
ID=25484824
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10284522A Pending JPH11204646A (ja) | 1997-10-08 | 1998-10-06 | 集積回路デバイス |
JP2007138865A Expired - Fee Related JP4685834B2 (ja) | 1997-10-08 | 2007-05-25 | 集積回路デバイス |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10284522A Pending JPH11204646A (ja) | 1997-10-08 | 1998-10-06 | 集積回路デバイス |
Country Status (4)
Country | Link |
---|---|
US (1) | US6683384B1 (ja) |
EP (1) | EP0908951B1 (ja) |
JP (2) | JPH11204646A (ja) |
DE (1) | DE69836944T2 (ja) |
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DE19734509C2 (de) * | 1997-08-08 | 2002-11-07 | Infineon Technologies Ag | Leistungstransistorzelle |
US6683384B1 (en) * | 1997-10-08 | 2004-01-27 | Agere Systems Inc | Air isolated crossovers |
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EP1219565A1 (en) | 2000-12-29 | 2002-07-03 | STMicroelectronics S.r.l. | Process for manufacturing integrated devices having connections on separate wafers and stacking the same |
KR100481216B1 (ko) * | 2002-06-07 | 2005-04-08 | 엘지전자 주식회사 | 볼 그리드 어레이 패키지 및 그의 제조 방법 |
US7145248B2 (en) * | 2002-06-28 | 2006-12-05 | Lucent Technologies Inc. | Common connection method for flip-chip assembled devices |
US20040075170A1 (en) * | 2002-10-21 | 2004-04-22 | Yinon Degani | High frequency integrated circuits |
DE10313047B3 (de) * | 2003-03-24 | 2004-08-12 | Infineon Technologies Ag | Verfahren zur Herstellung von Chipstapeln |
US7262508B2 (en) * | 2003-10-03 | 2007-08-28 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Integrated circuit incorporating flip chip and wire bonding |
US6884661B1 (en) * | 2003-11-04 | 2005-04-26 | Rf Micro Devices, Inc. | Method of fabricating posts over integrated heat sink metallization to enable flip chip packaging of GaAs devices |
JP3880600B2 (ja) * | 2004-02-10 | 2007-02-14 | 松下電器産業株式会社 | 半導体装置およびその製造方法 |
US7135766B1 (en) | 2004-11-30 | 2006-11-14 | Rf Micro Devices, Inc. | Integrated power devices and signal isolation structure |
US20080162855A1 (en) * | 2006-12-29 | 2008-07-03 | Tessil Thomas | Memory Command Issue Rate Controller |
US7872350B2 (en) * | 2007-04-10 | 2011-01-18 | Qimonda Ag | Multi-chip module |
TW201011878A (en) * | 2008-09-03 | 2010-03-16 | Phoenix Prec Technology Corp | Package structure having substrate and fabrication thereof |
WO2010117987A1 (en) * | 2009-04-08 | 2010-10-14 | Efficient Power Conversion Corporation | Bumped, self-isolated gan transistor chip with electrically isolated back surface |
JP5578012B2 (ja) * | 2010-10-15 | 2014-08-27 | 三菱電機株式会社 | エアブリッジの製造方法 |
WO2012174732A1 (en) | 2011-06-24 | 2012-12-27 | Acm Research (Shanghai) Inc. | Methods and apparatus for uniformly metallization on substrates |
US20150049443A1 (en) * | 2013-08-13 | 2015-02-19 | Infineon Technologies Ag | Chip arrangement |
CN113764261B (zh) * | 2020-10-15 | 2023-08-22 | 腾讯科技(深圳)有限公司 | 空桥结构及其制作方法、超导量子芯片及其制作方法 |
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Also Published As
Publication number | Publication date |
---|---|
EP0908951A3 (en) | 2000-07-19 |
JP2007274004A (ja) | 2007-10-18 |
DE69836944T2 (de) | 2007-10-25 |
US6683384B1 (en) | 2004-01-27 |
JPH11204646A (ja) | 1999-07-30 |
DE69836944D1 (de) | 2007-03-15 |
EP0908951B1 (en) | 2007-01-24 |
EP0908951A2 (en) | 1999-04-14 |
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