JP4678270B2 - Solid-state image sensor - Google Patents

Description

  The present invention relates to a solid-state image sensor, and more particularly to a solid-state image sensor that captures a subject image.

  Among solid-state imaging devices that capture a subject image, a solid-state imaging device that simultaneously starts and ends the accumulation of all pixels is known (for example, see Patent Document 1). FIG. 5 shows an equivalent circuit diagram for one pixel of this type of conventional solid-state imaging device. The pixel 1 of the conventional solid-state imaging device shown in FIG. 5 has an N-channel MOS type through a transfer transistor 3 that is a P-channel MOS field effect transistor that simultaneously accumulates charges accumulated in a photodiode 2 that photoelectrically converts subject light. The data is transferred to the well diffusion layer 15 of the amplification transistor 5 which is a field effect transistor. Since the potential of the well diffusion layer 15 changes according to the transferred charge amount, a pixel signal is taken out from the source of the amplification transistor 5 to the pixel signal output line 16 as a change in threshold voltage or a change in on-resistance.

  Next, a method for driving the solid-state imaging device of FIG. 5 will be described with reference to the timing chart of FIG. Here, as a characteristic of each MOS type field effect transistor, the transfer transistor 3 is turned off when the potential of the gate wiring 13 is high level (High) and turned on when the potential is low level (Low), and is a P channel MOS type field effect transistor. The reset transistor 4 is turned on when the potential of the gate wiring 12 is low, and is turned off when the potential is the middle level (Middle) and high level (High). The amplification transistor 5 that is an N-channel MOS field effect transistor is the potential of the gate wiring 12. It is assumed that the threshold voltage is set so that it is off when is Low and Middle, and is on when High.

  Both gates of the reset transistor 4 and the amplification transistor 5 are commonly connected to the gate wiring 12, and the source of the amplification transistor 5 is connected to the pixel signal output line 16. The transfer transistor 3 has a gate connected to the gate wiring 13 and a source connected to the well diffusion layer 15 constituting the drain of the reset transistor 4 and the back gate of the amplification transistor 5. A load 10 is connected to the pixel signal output line 16. The load 10 includes a first series circuit including a switch 6 and a capacitor 7, and a second series circuit including a switch 8 and a capacitor 9. Are connected in parallel. As a result, the load voltages at the time of optical signal output and reset signal output can be stored in the capacitors 7 and 9.

  First, as shown in FIGS. 6A and 6B, the potentials of the gate wirings 13 and 12 of all the pixels are set to Low, the transfer transistor 3 and the reset transistor 4 are turned on, and the photodiode 2 and the well diffusion are turned on. Both charges of layer 15 are discharged to the substrate and reset. After that, as shown in FIG. 6A, the potentials of the gate wirings 13 of all the pixels are High, and as shown in FIG. 6B, the potentials of the gate wirings 12 of all the pixels become Middle, so that the transfer transistor 3 and the reset transistor 4 Are turned off, and accumulation of optical signal charges by the photodiodes 2 is started for all the pixels simultaneously.

  After the predetermined accumulation time, as shown in FIG. 6A, the potentials of the gate wirings 13 of all the pixels become Low, and the optical signal charges of the photodiodes 2 pass through the transfer transistors 3 turned on in all the pixels. Then, after the transfer is completed, the potential of the gate wiring 13 becomes High, and the transfer transistor 3 is turned off. Thereafter, the readout process is sequentially performed for every row from all pixels.

  In this row sequential reading, first, as shown in FIG. 6B, when the potential of the gate wiring 12 is set to High, the amplification transistor 5 is turned on, and the output corresponding to the optical signal charge of the well diffusion layer 15 is turned on. Is output to the pixel signal output line 16 through the amplifying transistor 5 and stored in the capacitor 7 through the switch 6 which is turned on as schematically shown in FIG. 6D (at this time, the switch 8 is off). is there.). Subsequently, as shown in FIG. 6B, the potential of the gate wiring 12 becomes Low, the amplification transistor 5 is turned off, the reset transistor 4 is turned on, and the optical signal charge in the well diffusion layer 15 is transferred to the substrate through the reset transistor 4. (Reset).

  Subsequently, as shown in FIG. 6B again, when the potential of the gate wiring 12 is set to High, the amplification transistor 5 is turned on, the reset transistor 4 is turned off, and the signal output at the time of reset is amplified to the pixel signal output line 16. The signal output is output through the transistor 5, and the signal output is stored in the capacitor 9 through the switch 8 which is turned on as schematically shown in FIG. 6C (at this time, the switch 6 is off). . This completes the readout process from the pixels, and subtracts the signals stored in the capacitors 7 and 9 using a subtracting means (not shown), and outputs it to the outside of the sensor.

  FIG. 7 is an element cross-sectional view corresponding to the photodiode 2, the transfer transistor (PMOSFET) 3, and the amplification transistor (NMOSFET) 5 in FIG. In FIG. 7, a P-type diffusion region 21 is formed on an N-type substrate 20, and these constitute the photodiode 2 of FIG. Further, a P-type diffusion region 24 is formed at a position close to the P-type diffusion region 21 on the substrate 20, and an N-type diffusion region 25 is formed in the P-type diffusion region 24. The P-type diffusion regions 21 and 24 are used as a drain diffusion layer and a source diffusion layer, and the transfer transistor 3 in FIG.

  Further, the N-type diffusion region 26 formed on the N-type diffusion region 25 and the substrate 20 is used as a source diffusion layer and a drain diffusion layer, and the gate electrode 23 formed above them is used in FIG. An amplification transistor 5 is configured. The P-type diffusion region 24 corresponds to the well diffusion layer 15 in FIG. The pixel signal output line 16 of FIG. 5 is connected to the N-type diffusion region 25, and the power supply line 11 of FIG. 5 is connected to the N-type diffusion region 26.

  Here, a potential pocket 30 exists in the P-type diffusion region 24 (well diffusion layer 15), and this is the same P-type impurity concentration as the well diffusion layer in the vicinity of the source. It becomes lower and it becomes easier to collect holes here. Therefore, since the influence of the threshold fluctuation is greater than when there is no potential pocket 30, the signal conversion efficiency is improved.

Japanese Patent Laid-Open No. 2003-17677

  However, since the conventional solid-state imaging device uses three transistors per pixel (transfer transistor 3, reset transistor 4, and amplification transistor 5), the area used for the transistor increases and the aperture ratio decreases. There are challenges.

  Further, since the potential pocket 30 shown in FIG. 7 has a higher concentration in principle than the P-type diffusion region 24, the impurity concentration adjustment range is limited accordingly. On the other hand, if the potential pocket 30 is omitted, the transferred holes spread over the entire lower surface of the gate electrode 23, so that the conversion efficiency is lowered.

  The present invention has been made in view of the above points, and can improve the aperture ratio and localize holes transferred from the photodiode in the vicinity of the source without forming a high-concentration region such as a potential pocket. An object is to provide a solid-state imaging device.

To achieve the above object, the present invention provides an amplifying transistor that outputs the amount of input charge as a change in threshold value, a photoelectric conversion region that converts light into charge, and a photoelectric conversion region. A solid-state imaging device in which a plurality of unit pixels including a charge transfer means for transferring accumulated charges to an amplification transistor are regularly arranged. The amplification transistor is formed on a gate electrode on the substrate and the substrate. The source region and the drain region of the first conductivity type and the high-concentration impurity, and the source vicinity region of the second conductivity type provided in the vicinity of the source region. together are separated in the lower position, except a position below the gate electrode are separated by a source region near the vicinity of the source region is in contact with the drain region under the gate electrode And yet not, charge transfer means is characterized by transferring the charge accumulated in the photoelectric conversion region to the vicinity of the source region.

  In the present invention, the charge accumulated in the photoelectric conversion region can be transferred to the source vicinity region and discharged from the source vicinity region to the substrate at the time of resetting. Therefore, the pixel does not have a conventionally required reset transistor. In addition, since the second conductivity type source vicinity region is created only in the vicinity of the first conductivity type and high concentration source region, the high concentration region such as the potential pocket is formed. Creation can be made unnecessary.

  According to the present invention, since the pixel does not have a conventionally required reset transistor in the pixel, the aperture ratio can be increased as compared with the conventional one by reducing the number of transistors in the pixel by one.

  In addition, according to the present invention, a high-concentration region such as a potential pocket can be created by creating a second-conductivity-type source vicinity region only in the vicinity of the first-conduction type high-concentration source region. Since it is not necessary, holes transferred from the charge storage means can be localized in the source vicinity region, and the concentration in the source vicinity region can be freely set.

Next, embodiments of the present invention will be described with reference to the drawings. 1A is a top view of a first embodiment of a solid-state imaging device according to the present invention, and FIG. 1B is a longitudinal sectional view taken along line XX ′ of FIG. As shown in FIGS. 1A and 1B, in the solid-state imaging device of the present embodiment, a p ⁻ type epitaxial layer 42 is grown on a p ⁺ type substrate 41. An n-well 43 is present in the epitaxial layer 42. On the n-well 43, a gate electrode 45 having a U-shaped planar shape is formed as a first gate electrode with a gate oxide film 44 interposed therebetween, as shown in FIG.

The gate electrode 45 has an n ⁺ -type drain region 48 on one end of the top view and the other has an n ⁺ -type source region 46. A p-type source vicinity region (source vicinity p-type region) 47 is provided adjacent to the n ⁺ -type source region 46 so as to surround the source region 46. The source vicinity p-type region 47 does not reach the drain region 48 at the other end of the gate electrode 45 in at least all the gate width directions. The source vicinity p-type region 47 is in contact with the drain region 48 on the same side as the source region 46, which is one end of the gate electrode 45, and separates the source region 46 and the drain region 48.

There is a buried p ⁻ type region 49 in the n well 43 below the n ⁺ type drain region 48 formed at a position separated from the source region 46 and the p-type region 47 near the source. The buried p ⁻ type region 49 and the n-well 43 constitute the buried photodiode 50 shown in FIG.

  Between the embedded photodiode 50 and the gate electrode 45, there is a transfer gate electrode 51 which is a second gate electrode. A drain electrode wiring 52, a source electrode wiring (output line) 54, and a transfer gate electrode wiring 55, which are metal wirings, are connected to the drain region 48, the gate electrode 45, the source region 46, and the transfer gate electrode 51, respectively. Further, as shown in FIG. 1B, a light shielding film 56 is formed above each of the above components, and an opening 57 is formed at a position corresponding to the embedded photodiode 50 in the light shielding film 56. Has been. The light shielding film 56 is formed of a metal or an organic film. The light reaches the embedded photodiode 50 through the opening 57 and is photoelectrically converted.

In the first embodiment, the amplifying MOSFET comprising the gate electrode 45, the n ⁺ -type source region 46 and drain region 48, which are high-concentration impurities, and the p-type region 47 in the vicinity of the source has a p-type in the vicinity of the source. The region 47 is not in contact with the drain region 48 at the substrate position below the gate electrode 45, and the source region 46 and the drain region 48 are separated from each other by a portion below the gate electrode 45 of the n well 43 (gate electrode 45). 45) and a source vicinity p-type region 47.

  Therefore, in the first embodiment, since element isolation is not used for the separation of the source region 46 and the drain region 48, there is a feature that noise due to defects generated in the element isolation region does not occur. .

Next, the structure of the second embodiment of the solid-state imaging device of the present invention will be described. 2A is a top view of the second embodiment of the solid-state imaging device according to the present invention, and FIG. 2B is a longitudinal sectional view taken along line YY ′ of FIG. As shown in FIGS. 2A and 2B, in the solid-state imaging device of this embodiment, a p ⁻ type epitaxial layer 42 is grown on a p ⁺ type substrate 41. An n-well 43 is present in the epitaxial layer 42. A gate electrode 45 having a U-shaped planar shape is formed as a first gate electrode on the n-well 43 with a gate oxide film 44 interposed therebetween, as shown in FIG.

The gate electrode 45 has an n ⁺ -type drain region 48 on one end of the top view and the other has an n ⁺ -type source region 46. Adjacent to the n ⁺ -type source region 46 is a p-type source vicinity region (source vicinity p-type region) 47. The source vicinity p-type region 47 does not reach the drain region 48 at the other end of the gate electrode 45 in at least all the gate width directions. The above structure is the same as that of the first embodiment shown in FIG. 1, but in this embodiment, between the drain region 48 on the same side as the source region 46, FIG. As shown in FIG. 5B, there is a feature in that the insulating isolation region 60 exists, and the source region 46, the source vicinity p-type region 47 and the drain region 48 are isolated by this insulating isolation region 60. The insulating isolation region 60 is formed of a field oxide film or STI (Sallow Trench Isolation).

As in the first embodiment, in the n well 43 below the n ⁺ type drain region 48 formed at a position spaced outside the source region 46 and the p-type region 47 near the source, There is a buried p ⁻ type region 49, and the buried p ⁻ type region 49 and the drain region 48 thereabove constitute a buried photodiode 50 shown in FIG.

  Between the embedded photodiode 50 and the gate electrode 45, there is a transfer gate electrode 51 which is a second gate electrode. A drain electrode wiring 52, a source electrode wiring (output line) 54, and a transfer gate electrode wiring 55, which are metal wirings, are connected to the drain region 48, the source region 46, and the transfer gate electrode 51, respectively. Further, similarly to the first embodiment, a light shielding film 56 is formed above each of the above components as shown in FIG. 2B, and corresponds to the embedded photodiode 50 of the light shielding film 56. An opening 57 is formed at the position.

In the second embodiment, the amplifying MOSFET comprising the gate electrode 45, the n ⁺ -type source region 46 and drain region 48, which are high-concentration impurities, and the p-type region 47 in the vicinity of the source has a p-type in the vicinity of the source. The region 47 is not in contact with the drain region 48 at the substrate position below the gate electrode 45, and the source region 46 and the drain region 48 are separated from each other by a portion below the gate electrode 45 of the n well 43 (gate electrode 45). 45) and the insulating isolation region 60.

  Therefore, in the second embodiment, since the isolation region 60 is used for the separation of the source region 46 and the drain region 48, as compared with the first embodiment in which the isolation region is not used. It has the feature of being able to perform electrically stable separation. Although not shown in FIGS. 1 and 2, a gate electrode wiring is connected to the gate electrode 45.

  Next, the pixel structure of the solid-state image sensor according to the present invention and the structure of the entire image sensor will be described with reference to FIG. In the figure, pixels are arranged in a pixel spread area 61 in m rows and n columns. In FIG. 3, one pixel 62 of s rows and t columns among these m rows and n columns pixels is represented by an equivalent circuit. The pixel 62 includes an amplification MOSFET 63, a photodiode 64, and a transfer gate MOSFET 65. The drain of the amplification MOSFET 63 corresponds to the n-side terminal of the photodiode 64 and the drain electrode wiring 66 (52 in FIGS. 1 and 2). ), The source of the transfer gate MOSFET 65 is connected to the p-side terminal of the photodiode 64, and the drain is connected to the back gate of the amplification MOSFET 63 (p-type region 47 near the source in FIGS. 1 and 2).

In FIG. 1B and FIG. 2B, the amplifying MOSFET 63 has an n ⁺ -type source region 46 and an n ⁺ -type drain as a gate region that is a p-type region 47 near the source immediately below the gate electrode 45. This is an n-channel MOSFET having a region 48. 1B and 2B, the n-well 43 just below the transfer gate electrode 51 is the gate region, the p ⁻ type region 49 embedded with the photodiode 50 is the source region, and the source This is a p-channel MOSFET having the neighboring p-type region 47 as a drain.

  In FIG. 3, in order to read a signal for one frame from each pixel of m rows and n columns, there is a circuit 67 for generating a frame start signal for giving a signal to start reading. The frame start signal may be given from outside the image sensor. This frame start signal is supplied to the vertical shift register 68. The vertical shift register 68 outputs a signal instructing which row of pixels in each pixel of m rows and n columns is to be read.

  The gate potential control circuit 70 in the s row is connected to the gate electrode (corresponding to 45 in FIGS. 1 and 2) of the amplification MOSFET 63 in each pixel in the s row through the amplification gate electrode wiring 69, and the s row. The transfer gate potential control circuit 72 is connected to the gate electrode of the transfer gate MOSFET 65 (corresponding to 51 in FIGS. 1 and 2) through the transfer gate electrode wiring 71 (corresponding to 55 in FIGS. 1 and 2), and the s-th row The drain potential control circuit 73 is connected to the drain of the amplifying MOSFET 63 and the n-side terminal of the photodiode 64 through the drain electrode wiring 66 (corresponding to 52 in FIGS. 1 and 2).

  The gate potential control circuit 70 receives a signal from the vertical shift register 68, the transfer gate potential control circuit 72 receives a signal from the frame start signal generation circuit 67, and the drain potential control circuit 73 performs a vertical shift with the frame start signal generation circuit 67. A signal is received from the register 68 and processed to control each potential of the gate electrode wiring 69, the transfer gate electrode wiring 71, and the drain electrode wiring 66.

  Since the gate electrode of the amplification MOSFET 63 is controlled for each row, the gate electrode wiring 69 is wired in the horizontal direction. Since the gate electrodes of the transfer gate MOSFET 65 are controlled all at once, wiring in the vertical direction may be used, but here it is expressed in the horizontal direction. The drain potential control may be performed for all the pixels at the same time or may be controlled for each row, and the drain electrode wiring 66 is expressed in the horizontal direction here.

  A source electrode wiring 74 (corresponding to 54 in FIGS. 1 and 2) connected to the source electrode of the amplification MOSFET 63 of the pixel 62 is wired in the vertical direction, and one of the wirings is connected to the source potential control circuit 75 through the switch SW1. The other is connected to the signal readout circuit 76 via the switch SW2. When reading the signal, SW1 is turned off and SW2 is turned on. When the source potential is controlled, SW1 is turned on and SW2 is turned off.

  The signal readout circuit 76 has a load 77, and is connected to the source electrode of the amplifying MOSFET 63 through the source electrode wiring 74 to form a source follower circuit. The load 77 is a current source, for example. One end of a load (current source) 77 is grounded, and the other end is connected to one ends of capacitors C1 and C2 via switches sc1 and sc2. The other ends of the capacitors C1 and C2 are grounded, and one end thereof is connected to the inverting input terminal and the non-inverting input terminal of the differential amplifier 78, respectively, so as to output the potential difference between C1 and C2.

  Such a signal readout circuit 76 is called a CDS circuit, and various circuits other than those described here are disclosed, and the present invention is not limited to this circuit. The signal output from the signal readout circuit 76 is output via the switch swt controlled by the horizontal shift register 79.

Next, a method for driving the equivalent circuit shown in FIG. 3 will be described with reference to the timing chart of FIG. As a representative, attention is paid to the pixel 62 in s rows and t columns. First, in the period shown in FIG. 4A, light is incident on the embedded photodiode 64 (50 in FIGS. 1A and 2A), and an electron-hole pair is generated by the photoelectric conversion effect. Holes are accumulated in the buried p ⁻ -type region (49 in FIGS. 1 and 2) of the photodiode 64. At this time, the potential of the transfer gate electrode wiring 71 is the same as the drain potential Vdd, and the transfer gate MOSFET 65 is in the off state. These accumulations are performed at the same time as the previous frame read operation is being performed.

  When the reading of the previous frame is completed, a pulse is output from the frame start signal generation circuit 67 as shown in FIG. Subsequently, in the period (2) shown in FIG. 4, the charges are transferred simultaneously from all the pixels to the back gate of the amplification MOSFET 63 from the photodiode 64 as shown in FIG. 4B. The control signal potential of the gate potential control circuit 72 falls from Vdd to Low2, and the transfer gate MOSFET 65 is turned on.

  At this time, the potential of the gate electrode wiring 69 controlled by the gate potential control circuit 70 changes from Low to Low1 as shown in FIG. 4C, but Low2 is larger than Low1. Low1 may be the same as Low. Most simply, Low1 = Low = 0 (V) is set.

  On the other hand, the source potential of all the pixels including the source potential supplied from the source potential control circuit 75 to the source of the amplifying MOSFET 63 from the source electrode wiring 74 via the switch SW1 is the potential as shown in FIG. Set to S1. S1> Low1, which keeps the amplification MOSFET 63 off and prevents current from flowing. As a result, the charges (holes) accumulated in the photodiodes of all the pixels are transferred all at once under the gate electrodes of the amplification MOSFETs of the corresponding pixels.

  In the region below the gate electrode 45 shown in FIG. 1B and FIG. 2B, the p-type region 47 near the source has the lowest potential, so the holes accumulated in the photodiode 64 It reaches the back gate (p-type region 47 near the source) and is accumulated there. As a result of the accumulation of holes, the potential of the p-type region 47 near the source rises.

Subsequently, in the period shown in FIG. 4 (3), as shown in FIG. 4 (B), the transfer gate electrode becomes Vdd again, and the transfer gate MOSFET 65 is turned off. As a result, electron-hole pairs are generated again in the photodiode 64 due to the photoelectric conversion effect, and holes start to accumulate in the buried p ⁻ -type region 49 of the photodiode 64. This accumulation operation is continued until the next charge transfer.

  On the other hand, since the read operation is performed in units of rows, the potential of the gate electrode of the amplification MOSFET 63 is as shown in FIG. 4C in the period (3) in which the first to (s-1) th rows are read. In the low state, a standby state is entered while holes are accumulated in the back gate (source-side p-type region 47). The source potential can take various values depending on the value of the signal from the pixel while the signal is read from another row. The gate electrode potential of the amplifying MOSFET 63 can take various values for each row, but is set to Low in the sth row, and the amplifying MOSFET 63 is off.

  In the subsequent period shown in FIGS. 4 (4) to (6), signal readout from the pixel 62 in the s row and t column is performed. First, with the amplification MOSFET 63 accumulating holes in the back gate (p-type region 47 near the source), the output signal of the vertical shift register 68 shown in FIG. 4 (E) is low as shown in FIG. In the period (4) which is a level, the potential of the gate electrode 45 of the amplification MOSFET 63 is changed from Low to Vg1 by a control signal output from the gate potential control circuit 70 to the gate electrode wiring 69 as shown in FIG. Raise to.

Here, the potential Vg1 is between the potentials Low, Low1, and Vdd described above.
Low ≦ Low1 ≦ Vg1 ≦ Vdd (where Low <Vdd)
Is an electric potential that holds the inequality. In the period (4), the switch SW1 is turned off as shown in FIG. 4I, the switch SW2 is turned on as shown in FIG. 4J, and the switch sc1 is turned on as shown in FIG. The switch sc2 is turned off as shown in FIG. As a result, the source follower circuit connected to the source of the amplifying MOSFET 63 works, and the source potential of the amplifying MOSFET 63 is S2 (= Vg1−Vth1) in the period (4) as shown in FIG. Here, Vth1 is the threshold voltage of the amplifying MOSFET 63 in a state where there is a hole in the back gate (p-type region 47 near the source). The source potential S2 is stored in the capacitor C1 through the switch sc1 that is turned on.

  In the subsequent period shown in FIG. 4 (5), the potential of the gate electrode of the amplifying MOSFET 63 is raised to High1 as shown in FIG. 4 (K) by the control signal output from the gate potential control circuit 70 to the gate electrode wiring 69. At the same time, the switch SW1 is turned on and the switch SW2 is turned off as shown in (I) and (J) of the figure, and the source potential output from the source potential control circuit 75 is shown in (L) of the figure. Raise to Highs. Here, High1 and Highs> Low1.

  The values of the potentials High1 and Highs may be the same or different, but High1 and Highs ≦ Vdd are desirable for simplicity of design. In a simple setting, High1 = Highs = Vdd. It is desirable to set the potential so that the amplification MOSFET 63 is turned on and no current flows. As a result, the potential of the p-type region 47 near the source rises, and holes are discharged to the epitaxial layer 42 beyond the barrier of the n-well 43 (reset).

  In the subsequent period shown in FIG. 4 (6), the same signal readout state as in the period (4) is set again. However, unlike the period (4), as shown in FIGS. 4M and 4N, the switch sc1 is turned off and the switch sc2 is turned on. The ring-shaped gate electrode is set to Vg1 which is the same as that in the period (4) as shown in FIG. However, in this period (6), holes are discharged to the substrate in the immediately preceding period (5), and no holes are present in the p-type region 47 near the source. Therefore, the source potential of the amplification MOSFET 63 is as shown in FIG. ), The period is S0 (= Vg1−Vth0) in the period (6). Here, Vth0 is a threshold voltage of the amplifying MOSFET 63 in a state where there is no hole in the back gate (p-type region 47 near the source). The source potential S0 is stored in the capacitor C2 through the switch sc2 that is turned on.

  The differential amplifier 78 shown in FIG. 3 outputs the potential difference between the capacitors C1 and C2. That is, the differential amplifier 78 outputs (Vth0−Vth1). This output value (Vth0-Vth1) is a change in threshold value due to hole charge. Thereafter, among the pulses shown in FIG. 4F output from the horizontal shift register 79, the output switch swt in FIG. 3 is turned on based on the output pulse in the t-th column shown in FIG. During the ON period, as schematically shown by hatching in FIG. 4 (P), the threshold value change due to the Hall charge from the differential amplifier 78 is output to the outside of the sensor as the output signal Vout of the pixel 62.

  Subsequently, in the period indicated by (7) in FIG. 4, the potential of the ring-shaped gate electrode 45 is set to low again as shown in FIG. It waits until the signal processing of the next row is completed (until the readout of pixels of the s + 1 row to the nth row is completed). During these readout periods, the photodiode 64 is accumulating holes due to the photoelectric conversion effect. Thereafter, the process returns to the period (1) and repeats from the hole transfer. As a result, the output signal shown in FIG. 4G is read from each pixel. When signals are read from all pixels, the next frame is started again.

  As described above, in the first and second embodiments of the solid-state imaging device of the present invention shown in FIGS. 1 and 2, the transistor in the pixel 52 is connected to the amplification MOSFET 63 and the transfer as shown in FIG. The gate MOSFET 65 has two structures, and the charge accumulated in the photodiode 64 is discharged to the epitaxial layer 42 as a substrate and reset to have a structure without a reset transistor. The aperture ratio can be increased by the reduced amount.

  In the first and second embodiments of the solid-state imaging device of the present invention shown in FIGS. 1 and 2, the p-type semiconductor diffusion layer is formed as the source vicinity p-type region 47 only in the vicinity of the source region 46. As a result, holes transferred from the photodiode 64 can be localized in the vicinity of the source region 46 without forming a high-concentration region like the potential pocket 30 of FIG. The density of the mold region 47 can be set freely.

  Note that there is a method other than the supply of the potential of the source electrode wiring 74 from the source potential control circuit 75 at the time of resetting in the period (5) of FIG. In the period (5), both the switches SW1 and SW2 are turned off, and the source electrode wiring 74 is brought into a floating state. Here, when the potential of the gate electrode wiring 69 is set to High1, the amplification MOSFET 63 is turned on, current is supplied from the drain to the source electrode, and the source electrode potential rises. As a result, the potential of the p-type region 47 in the vicinity of the source is raised, and holes are discharged to the p-type epitaxial layer 42 beyond the barrier of the n-well 43 (reset). The source electrode potential of the amplifying MOSFET 63 when the holes are completely discharged becomes High1-Vth0. This method can reduce the number of transistors that supply Highs in the source potential control circuit 75 and can reduce the chip area.

  Note that the circuit configuration of the pixel 62 in FIG. 3 is simplified. Strictly speaking, the circuit of the pixel 62 is configured such that a switch linked to each potential of the gate electrode wiring 69 and the transfer gate electrode wiring 71 is provided between the source of the amplification MOSFET 65 and the back gate of the amplification MOSFET 63. . This switch is turned on when there is a relationship of Low1 ≦ Low2 between the potential Low1 of the gate electrode wiring 69 and the potential Low2 of the transfer gate electrode wiring 71, and is turned off when there is a relationship of Low1> Low2. become.

  By providing this switch, the substrate potential below the gate electrode 45 (potential Low1) is higher than the substrate potential below the transfer gate electrode 61 (potential Low2), and below the gate electrode 45 (potential Low1). The phenomenon that the substrate potential acts as a barrier and holes cannot reach the p-type region 47 near the source can be expressed in a circuit form. However, at the time of transfer, the above condition of Low1 ≦ Low2 is always satisfied by the potential control circuits 70, 72, etc., and therefore this switch is omitted in FIG.

1 is a top view of an element structure for one pixel according to a first embodiment of a solid-state image sensor of the present invention and a longitudinal sectional view taken along line X-X ′. It is the top view of the element structure for 1 pixel of 2nd Embodiment of the solid-state image sensor of this invention, and the longitudinal cross-sectional view accompanying the YY 'line | wire. It is an electrical equivalent circuit diagram for one pixel of one embodiment of the solid-state image sensor of the present invention. It is a timing chart explaining operation | movement of the solid-state image sensor of FIG. It is an equivalent circuit diagram of an example for 1 pixel of the conventional solid-state image sensor. 6 is a timing chart for explaining a driving method of the pixel in FIG. 5. FIG. 6 is an element cross-sectional view of an example corresponding to the photodiode, transfer transistor (PMOSFET), and amplification transistor (NMOSFET) of the pixel of FIG. 5.

Explanation of symbols

43 n well 45 gate electrode 46 n ⁺ type source region 47 near source p type region 48 n ⁺ type drain region 49 buried p ⁻ type region 50, 64 photodiode 51 transfer gate electrode 52, 66 drain electrode wiring 54, 74 source electrode Wiring (output line)
55, 71 Transfer gate electrode wiring 60 Insulation isolation region 61 Pixel covering region 62 Pixel 63 Amplifying MOSFET
65 Transfer gate MOSFET

Claims (2)

An amplification transistor that outputs the amount of input charge as a change in threshold value, a photoelectric conversion region that converts light into charge and accumulates, and the charge accumulated in the photoelectric conversion region to the amplification transistor A solid-state imaging device in which a plurality of unit pixels including a charge transfer means for transferring are regularly arranged,
The amplifying transistor includes a gate electrode on a substrate, a source region and a drain region of high-concentration impurities of a first conductivity type formed on the substrate, and a second conductivity type provided in the vicinity of the source region. And a source neighborhood region of
The source region and the drain region are separated at a position below the gate electrode, and are separated by the source vicinity region except at a position below the gate electrode,
The source vicinity region is not in contact with the drain region under the gate electrode, and the charge transfer means transfers the charge accumulated in the photoelectric conversion region to the source vicinity region. Solid-state image sensor. The solid-state imaging device according to claim 1, wherein the charges are transferred from the photoelectric conversion region to the source vicinity region all at once.

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