JP4674443B2 - Flat display device - Google Patents

Description

  The present invention relates to a flat display device, and can be applied to, for example, a display device using an organic EL (Electro Luminescence) element. The present invention generates black level and white level original reference voltages according to black level and white level original reference voltage setting data, respectively, and resistances of the black level and white level original reference voltages. A reference voltage for digital-analog conversion is generated by voltage division, and the original reference voltage setting data for black level and white level is modulated according to the correction data, and spatial and temporal integration in the display unit is performed. By using the effect to set the original reference voltage for black level and white level with the resolution below the resolution of these original reference voltage setting data, it is possible to cope with product variations in light emission characteristics, etc., and simple configuration Therefore, the color can be adjusted with high accuracy.

  Conventionally, in a liquid crystal display device which is one of flat display devices, as disclosed in, for example, Japanese Patent Laid-Open No. 10-333648, gamma characteristics are switched by setting a reference voltage used for digital-analog conversion processing. Has been made.

  That is, as shown in FIG. 8, in the liquid crystal display device 1, each pixel (P) 3R, 3G, 3B is formed by the liquid crystal cell, the switching element of the liquid crystal cell, and the storage capacitor. The display unit 2 is formed in a matrix form. In the liquid crystal display device 1, each pixel 3R, 3G, 3B of the display unit 2 is connected to a horizontal drive circuit 4 and a vertical drive circuit 5 via a signal line (column line) SIG and a gate line (row line) G, respectively. The pixels 3R, 3G, and 3B are sequentially selected by the vertical drive circuit 5, and the gradation of each pixel 3R, 3G, and 3B is set by the drive signal from the horizontal drive circuit 4, thereby displaying a desired image. Has been made. A color image can be displayed by sequentially and sequentially arranging pixels 3R, 3G, and 3B provided with red, green, and blue color filters, respectively.

  Therefore, in the liquid crystal display device 1, red, green, and blue image data DR, DG, and DB for display from the device body 6 are simultaneously input to the controller 7 and synchronized with the image data DR, DG, and DB. The vertical drive circuit 5 drives the gate line G of the display unit 2 in accordance with the timing signal. The image data DR, DG, and DB are time-division multiplexed to correspond to the driving of the signal line SIG by the horizontal drive circuit 4 to generate one system of image data D1, and the horizontal drive circuit 4 is generated from the image data D1. To drive the signal line SIG.

  FIG. 9 is a block diagram showing the horizontal drive circuit 4 and the controller 7 in detail. The controller 7 supports the driving of the signal line SIG by the horizontal drive circuit 4 by sequentially storing and outputting the image data DR, DG, DB output from the apparatus main body 6 to the memory 10 under the control of the memory control circuit 9. As described above, the image data DR, DG, and DB are time-division multiplexed and output by one system so that the image data relating to the same color is continuous in line units in units of horizontal scanning periods. Specifically, in this example, for the red, green, and blue pixels 3R, 3G, and 3B, the horizontal drive circuit 4 sequentially drives the red pixel 3R, the green pixel 3G, and the blue pixel 3B in line units. Thus, as shown in FIG. 10B, the controller 7 sequentially repeats the red image data DR, the green image data DG, and the blue image data DB in units of lines. This image data D1 is output.

  Further, the controller 7 generates various timing signals synchronized with the image data D1 by the timing generator (TG) 11 and outputs them to the horizontal drive circuit 4 and the vertical drive circuit 5. Here, in this timing signal, for example, the clock CK of the image data D1 (FIG. 10A), the start pulse indicating the start and end timing of the image data DR, DG, DB of each color in the image data D1. ST (FIG. 10C), strobe pulse (FIG. 10D), and the like.

  In addition, the controller 7 generates the original reference voltages VRT, VB to VG, VRB, which are the generation references of the reference voltage used for the digital / analog conversion processing, by the original reference voltage generation circuit 12 and outputs the generated voltage to the horizontal drive circuit 4.

  The horizontal driving circuit 4 inputs the image data D1 output from the controller 7 to the shift register 13, and sequentially distributes and outputs the image data D1 to the signal line system of the display unit 2. The reference voltage generation circuit 14 generates reference voltages V1 to V64 corresponding to the gradations of the image data D1 from the original reference voltages VRT, VB to VG, and VRB input from the controller 7, and outputs them.

  Each of the digital / analog conversion circuits (D / A) 15A to 15N performs digital / analog conversion processing on the output data of the shift register 13, and in this example, in this example, the drive signals of the adjacent three signal lines SIG are time-division multiplexed. A drive signal is output. The digital / analog conversion circuits 15A to 15N select and output the reference voltages V1 to V64 generated by the reference voltage generation circuit 14 according to the output data of the shift register 13, thereby outputting the image data output from the shift register 13. Is converted from digital to analog.

  The amplifier circuits 16A to 16N amplify the output signals of the digital / analog converter circuits 15A to 15N, respectively, and output the amplified signals to the display unit 2. In the display unit 2, the selectors 17A to 17N output the outputs of the amplifier circuits 16A to 16N. The signals are sequentially and cyclically output to the signal lines SIG related to the red, green, and blue pixels 3R, 3G, and 3B, respectively.

  In this way, the reference voltages V1 to V64 generated from the original reference voltages VRT, VB to VG, and VRB are selected to generate the drive signals for the respective signal lines SIG. It is a block diagram which shows the structure of the reference | standard voltage generation circuit 12 used for the production | generation of VB-VG, VRB, and the reference voltage generation circuit 14 used for the production | generation of reference voltage V1-V64.

  The original reference voltage generating circuit 12 is provided with a voltage dividing circuit 21 in which a predetermined number of resistors are connected in series, and the voltage dividing circuit 21 divides the reference voltage generating voltage VCOM to provide original reference voltages VRT, VB to VG, VRB. Is generated. As a result, the original reference voltage generation circuit 12 generates the original reference voltages VRT, VB to VG, and VRB by resistance voltage division and outputs them through the amplifier circuits 24A to 24H, respectively. In the case of a liquid crystal display device, the original reference voltage generation circuit 12 is configured so that the voltage applied to the voltage dividing circuit 21 can be switched by the selection circuit 22 and the inverting amplification circuit 23, whereby line inversion or frame inversion is performed. It is made to be able to cope with. Accordingly, FIG. 10F shows the potential of the signal line SIG in the case of line inversion.

  On the other hand, the reference voltage generation circuit 14 forms a resistor series circuit 26 by further connecting in series the voltage dividing circuits R1 to R7 in which a predetermined number of resistors having the same resistance value are connected in series. One end of a circuit 26, connection points of voltage dividing circuits R1 to R7 constituting the resistor series circuit 26, and the other end of the resistor series circuit 26 are respectively supplied to original reference voltages VRT, VB to VG through amplifier circuits 27A to 27H. VRB is input. As a result, the reference voltage generation circuit 14 further divides each potential difference by the original reference voltages VRT, VB to VG and VRB generated by the original reference voltage generation circuit 12 by the voltage dividing circuits R1 to R7, respectively. The reference voltages V1 to V64 are generated in the range of VRB.

  In this way, the reference voltages V1 to V64 are generated from the original reference voltages VRT, VB to VG, and VRB, so that the reference voltage generation circuit 14 has a predetermined number of resistors constituting the voltage dividing circuits R1 to R7. As a result, the original reference voltages VRT, VB to VG and VRB are divided to output a plurality of reference voltages V1 to V64 corresponding to the gradation of the image data D1.

  In the original reference voltage generation circuit 12, the resistors constituting the voltage dividing circuit 21 are displayed so that an image having a desired gamma characteristic is displayed by the reference voltages V1 to V64 corresponding to the gradation of the image data D1. Value is set. As a result, an example in which the voltage VCOM is set to 5 [V] can secure a desired gamma characteristic by polygonal line approximation by setting the original reference voltages VRT, VB to VG, and VRB, as indicated by reference numeral L1 in FIG. ing. In the original reference voltage generation circuit 12, the original reference voltages VRT, VB to VG, VRB output from the voltage dividing circuit 21 can be switched by changing the wiring pattern, whereby the characteristic indicated by reference numeral L1. As shown by reference numeral L2 in comparison with the above, for example, with the original reference voltages VRT and VRB that are potentials at both ends being fixed, the remaining original reference voltages VB to VG are varied within the range indicated by the arrows, and various gamma characteristics are obtained. Can be made variable.

  In this way, the gamma characteristic can be switched by the setting of the original reference voltage generation circuit 12 that generates the original reference voltages VRT, VB to VG, VRB. The controller 7 is formed by a control IC, whereas the horizontal drive circuit 4 is formed by a driver IC. As a result, in the conventional liquid crystal display device 1, it is possible to manufacture products with different gamma characteristics by changing only the control IC. It is made so that it can be shortened. Symbols CA to CH are stray capacitances between these ICs.

  By the way, in such a flat display device, there is a display device using an organic EL element, and the display unit of the display device using such an organic EL element is driven by a signal line SIG as in the display unit of the liquid crystal display device. A method for setting the gradation of each organic EL element has been proposed. Accordingly, it is considered that the display device of the organic EL element according to such a method can be configured using a control IC or the like related to the liquid crystal display device.

  However, in the organic EL element, it is necessary to change the setting of the reference voltages V1 to V64 corresponding to each color because the light emission characteristics are different for each product and the light emission characteristics change with time. become. As a result, there is a problem that the display device cannot actually be configured depending on the drive circuit related to the liquid crystal display device described above with reference to FIG. Specifically, the organic EL element needs to adjust the black level and the dynamic range for each color and for each product. It has been found that no adjustment is required for the gamma characteristic itself in the organic EL element. Thus, when the original reference voltage generation circuit 12 shown in FIG. 11 is applied, it is necessary to adjust the voltage across the voltage dividing circuit 21 for each color, for each product, and in response to changes over time.

  As one method for solving this problem, for example, it is conceivable to configure the original reference voltage generation circuit 30 as shown in FIG. In the original reference voltage generation circuit 30, original reference voltages VRT, VB to VG, and VRB are generated by digital / analog conversion circuits (D / A) 31A to 31H according to the original reference voltage setting data DV, respectively.

  Here, among the digital / analog conversion circuits 31A to 31H, the digital / analog conversion circuits 31A and 31H relating to the generation of the original reference voltages VRT and VRB set to the voltages at both ends are used for generating the reference voltage by the voltage dividing circuits 32A and 32H, respectively. The voltage VCOM is divided to generate a plurality of original reference voltage candidate voltages. Here, the voltage dividing circuits 32A and 32H are constituted by a series circuit of a plurality of resistors having the same resistance value, and the reference voltage generation voltage VCOM is converted into the black level and white level original reference voltage setting data DV (DVVRT, DVVRB) (hereinafter appropriately referred to as black level original reference voltage setting data DVVRT, white level original reference voltage setting data DVVRB) and divided and output.

  The selectors 33A and 33H select a plurality of types of candidate voltages output from the voltage dividing circuits 32A and 32H according to the black level original reference voltage setting data DVVRT and the white level original reference voltage setting data DVVRB, respectively. Thus, the original reference voltages VRT and VRB are generated according to the original reference voltage setting data DV and output from the amplifier circuits 34A and 34H.

  On the other hand, the digital analog conversion circuits 31B to 31G other than the digital analog conversion circuits 31A and 31H are respectively the original reference by the divided voltages by the voltage dividing circuits 32B to 32G, similarly to the digital analog conversion circuits 31A and 31H. A plurality of types of candidate voltages VB to VG are generated, and the plurality of types of candidate voltages are selected by the selectors 33B to 33G according to the original reference voltage setting data DV (DVVB to DVVG), respectively, and the original reference voltages VB to VG are selected. Generate. The digital-analog conversion circuits 31B to 31G output these original reference voltages VB to VG by the amplifier circuits 34B to 34G. In the digital-analog conversion circuits 31B to 31G, voltage-dividing circuits 32B to 32G used for generating candidate voltages for the original reference voltages VB to VG are connected in series between the digital-analog conversion circuits 31B to 31G. It is connected to the original reference voltages VRT and VRB by 31A and 31H.

  The decoder 35 sequentially takes in the original reference voltage setting data DV output from the controller 7 or the like, and distributes and outputs the original reference voltage setting data DV to the digital / analog conversion circuits 31A to 31H at the timing corresponding to the switching of the contacts in the selectors 17A to 17N. The reference voltage generation circuit 39 divides the original reference voltages VRT, VB to VG, VRB output from the original reference voltage generation circuit 30 in this way by the voltage dividing circuits R1 to R7 to generate the reference voltages V1 to V64. . In the example shown in FIG. 13, the original reference voltage generation circuit 30 and the reference voltage generation circuit 39 are integrally formed in an integrated circuit related to the horizontal drive circuit, so that the reference voltage generation circuit 39 has the original reference voltage VRT, An amplifier circuit used for inputting VB to VG and VRB is omitted.

  In this way, the original reference voltage setting data DV can be set for each color, so that different light emission characteristics can be accommodated for each color. In addition, the original reference voltage setting data DV can be set for each product to correct the variation in the light emission characteristics depending on the product. Further, it is possible to cope with a change in light emission characteristics over time.

  As shown in FIG. 14, among these original reference voltages VRT, VB to VG, VRB, the original reference voltages VB to VG excluding the potentials at both ends are output from voltage dividing circuits 32B to 32G connected in series, respectively. When it becomes difficult to vary the voltage only within the range of the candidate voltage to be generated, as shown in FIG. 15 by comparison with FIG. 14, when the original reference voltage setting data DV is set erroneously due to noise mixing Even in this case, it is possible to prevent the output of the drive signal due to the extreme gamma characteristic, and it is possible to prevent significant image quality deterioration due to noise.

  Further, both ends of the voltage dividing circuits 32B to 32G connected in series in this way are connected to the original reference voltages VRT and VRB which are the first and second original reference voltages, thereby correcting the light emission characteristics. When these original reference voltages VRT and VRB are varied by black level adjustment and dynamic range adjustment, as shown in FIG. 16 in comparison with FIG. 14, the resistance components by the voltage dividing circuits 32B to 32G formed in series are connected. Depending on the pressure ratio, the original reference voltages VB to VG also change following the changes in the original reference voltages VRT and VRB. That is, without any change in the gamma characteristics, the black level adjustment and the dynamic range adjustment can be performed to correct the variation in the light emission characteristics related to the organic EL element, thereby simplifying the adjustment work.

  The present invention can also be applied to a liquid crystal display device by changing the setting of each original reference voltage setting data DV, and further by switching line units and frame units.

  However, in the configuration shown in FIG. 13, there is a problem that the dynamic range and the black level cannot be adjusted with high accuracy, which may cause a color shift in the display.

  That is, in the example of FIG. 13, for example, when the original reference voltage setting data DV is formed by 6 bits and the reference voltage generation voltage VCOM is set to 5 [V], the resolution is about 80 mV [5 [V] / 64]. Thus, the original reference voltages VRT and VRB at both ends can be generated. In this case, for example, as shown in FIG. 14, when the black level or the like is adjusted with a large dynamic range, the resolution is practically sufficient. However, when the black level or the like is adjusted with a small dynamic range as shown in FIG. 16, the resolution becomes rough, which ultimately makes it difficult to accurately adjust the dynamic range and the black level.

  That is, in this case, when the potential difference between the original reference voltages VRT and VRB is set to 5 [V], the resolution with respect to the emission luminance is 1.6 [%] (80 mV / 5000 [mV]), for example, When the potential difference between the original reference voltages VRT and VRB is set to 2 [V] by suppressing the dynamic range, the resolution with respect to the light emission luminance is 4.0 [%] (80 mV / 2000 [mV]). Adjustment accuracy is lowered, and color misregistration is caused by these.

In this case, there can be considered a method of partially improving the resolution of the original reference voltages VRT and VRB output from the selectors 33A and 33H by changing the resistance values of the voltage dividing circuits 32A and 32H. In this case, it becomes difficult to set the original reference voltages VRT, VB to VG, VRB in various ways. Further, it may be possible to create the reference voltages VRT and VRB by providing the digital analog conversion circuits 31A and 31H with the same configuration as that of the digital analog conversion circuits 31B to 31G, respectively, but this makes the configuration extremely complicated. . In addition, while increasing the number of bits of the original reference voltage setting data DV related to these original reference voltages VRT and VRB, a method of increasing the resolution of the configuration of the voltage dividing circuits 32A and 32H and the selectors 33A and 33H can be considered. In this case, if the dynamic range further decreases, the integrated circuit must be recreated.
JP-A-10-333648

  The present invention has been made in consideration of the above points, and is intended to propose a flat display device capable of accurately adjusting the color with a simple configuration so as to be able to cope with product variations in light emission characteristics and the like. is there.

  In order to solve such a problem, according to the first aspect of the present invention, the horizontal drive circuit is applied to a flat display device that displays an image based on image data, and the horizontal driving circuit is adapted to black level original reference voltage setting data. A black-level digital-analog conversion circuit for generating a reference voltage, a white-level digital-analog conversion circuit for generating a white-level original reference voltage according to white-level original reference voltage setting data, and the black-level original A plurality of original reference voltage generation circuits including a plurality of digital-to-analog conversion circuits that generate a plurality of original reference voltages based on the reference voltage and the original reference voltage for white level, and a plurality of voltage dividing circuits including a plurality of resistors connected in series Are connected in series, and the black level original reference voltage and the white level original reference voltage are inputted to both ends, respectively, A reference voltage generation circuit that inputs the original reference voltage by the digital analog conversion circuit and outputs a plurality of reference voltages by the divided voltages by the plurality of voltage dividing circuits; A plurality of selection circuits for outputting the drive signal and the black level original reference voltage setting data and / or the white level original reference voltage setting data are modulated by selecting and outputting in accordance with the image data relating to the signal line. A modulation circuit that performs black level correction data whose value changes in units of lines and frames in accordance with the value of the fine adjustment data for black level and / or the fine adjustment data for white level, and / or A correction data generation circuit for generating white level correction data, and the black level correction data and / or white level correction data are set to the black level original reference voltage setting. Data and / or an addition circuit for adding to the original reference voltage setting data for white level, and the correction data generation circuit is a number of values that can be taken by the fine adjustment data for black level and / or fine adjustment data for white level When the continuous frames and lines are divided by the above, the average value of the black level correction data and / or white level correction data set in the continuous frames is equal for each line and the black level correction data The average value of the correction data for black level and the correction data for white level set in the continuous line so as to correspond to the value of fine adjustment data and / or fine adjustment data for white level is equal in each frame, The black level is equal to the average value of the black level correction data and / or white level correction data set in the continuous frames. Correction data and / or white level correction data are generated.

  According to the configuration of the first aspect, the modulation circuit has black level correction data and / or white whose values change in units of lines and frames according to the values of the fine adjustment data for black level and / or the fine adjustment data for white level. A correction data generation circuit that generates level correction data, and the black level correction data and / or white level correction data are added to the black level original reference voltage setting data and / or white level original reference voltage setting data. The black level fine adjustment data and / or the black level correction data generated according to the white level fine adjustment data and / or the white level correction data. Alternatively, the white level original reference voltage setting data can be modulated. Further, when the black level fine adjustment data and / or the white level fine adjustment data can be taken to divide continuous frames and lines, the black level correction set in the continuous frames is seen. The average value of the data and / or white level correction data is set to the continuous lines so that the average value is the same for each line and corresponds to the value of the black level fine adjustment data and / or the white level fine adjustment data. The average value of the black level correction data and / or the white level correction data is equal in each frame, and is equal to the average value of the black level correction data and / or white level correction data set in the continuous frame. As described above, if the black level correction data and / or white level correction data are generated, the time-axis modulation is performed by successive frames. In addition, the black level original reference voltage setting data and / or the white level original reference voltage setting data are modulated according to the black level fine adjustment data and / or the white level fine adjustment data by spatial modulation using continuous lines. As a result, the corresponding black level original reference voltage and / or white level original reference voltage can be modulated. As a result, the integration effect in the time axis direction by continuous frames and the spatial integration effect by continuous lines enable high accuracy below the resolution of the black level original reference voltage setting data and white level original reference voltage setting data. The black level original reference voltage and / or the white level original reference voltage can be set. As a result, color variations can be accurately adjusted with a simple configuration so as to cope with variations in the product of the light emission characteristics.

  ADVANTAGE OF THE INVENTION According to this invention, the flat display apparatus which can be color-adjusted with a simple structure accurately can be provided so that it can respond to the product variation of a light emission characteristic, etc.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.

(1) Configuration of Embodiment FIG. 2 is a block diagram showing PDA (Personal Digital Assistants) according to an embodiment of the present invention. In the apparatus main body 42, the PDA 41 displays various images on the display unit 44 by executing predetermined processing procedures with the controller 43, which is arithmetic processing means, in response to the operation of the operator. In this PDA 41, the same configurations as those described above with reference to FIGS. 9, 13 and the like are denoted by the corresponding reference numerals, and redundant description is omitted.

  Here, in the PDA 41, the display unit 44 is a color image display panel in which pixels of organic EL elements are arranged in a matrix, and is lined by a vertical drive circuit (not shown) using gate lines connected to the pixels. A pixel is selected in units, and the gray level of each pixel is set by the horizontal drive circuit 45 by switching the contacts of the selectors 17A to 17N corresponding to the selection of the pixel by the vertical drive circuit.

  For this reason, the horizontal drive circuit 45 is constituted by an integrated circuit, and after the image data D1 output from the controller 52 is distributed to each set of red, green, and blue pixels continuous in the horizontal direction by the shift register 13, Digital / analog conversion processing is performed by the digital / analog conversion circuits 15A to 15N by the selector. Further, the drive signals resulting from the digital-analog conversion processing result are amplified by the amplification circuits 16A to 16N and output to the display unit 44.

  In the horizontal drive circuit 45, the reference voltages V1 to V64 used for the digital analog conversion processing of the digital analog conversion circuits 15A to 15N are generated by the original reference voltage generation circuit 30 and the reference voltage generation circuit 39 described above with reference to FIG. . That is, the original reference voltage generation circuit 30 generates and outputs the original reference voltages VRT, VB to VG, VRB according to the original reference voltage setting data DV (DVVRT, DVVB to DVVG, DVVRB), and outputs the reference voltage generation circuit 39. Generates a reference voltage V1 to V64 by resistance-dividing these original reference voltages VRT, VB to VG, and VRB. The horizontal drive circuit 45 is configured such that original reference voltage setting data DV (DVVRT, DVVB to DVVG, DVVRB) instructing the setting of the original reference voltages VRT, VB to VG, VRB is input by 6 bits each. The reference voltage generation voltage VCOM by 5 [V] is divided by the resolution corresponding to 6 bits to generate the original reference voltages VRT and VRB, and thereby the original reference voltages VRT and VRB are about 80 [mV]. ] (= 5 [V] / 64).

  With respect to such original reference voltage setting data DV (DVVRT, DVVB to DVVG, DVVRB), the PDA 41 measures the light emission characteristics of each color for the display unit 44 by the organic EL element at the time of shipment from the factory. On the basis of this, the original reference voltage setting data DV (DVVRT, DVVB to DVVG, DVVRB) is recorded in the memory 50, whereby the emission characteristics of each color and the light emission between products using the original reference voltage setting data DV are recorded. Variations in characteristics can be corrected, whereby a display image can be displayed with correct white balance and color reproducibility. Further, with respect to the original reference voltages VRT and VRB, fine adjustment data D3 (D3VRT and D3VRB) each having 2 bits for setting the corresponding original reference voltage setting data DVVRT and DVVRB in more detail is recorded in the memory 50. Has been made.

  In this embodiment, among these original reference voltages VRT, VB to VG, VRB, the original reference voltage VRT having the highest voltage and the original reference voltage VRB having the lowest voltage are the levels of the black level and the white level, respectively. Accordingly, in the following description, these two original reference voltages VRT and VRB will be appropriately referred to as a black level original reference voltage VRT and a white level original reference voltage VRB, respectively. Correspondingly, the original reference voltage setting data DV corresponding to the black level original reference voltage VRT and the white level original reference voltage VRB is appropriately set to the black level original reference voltage setting data DVVRT and the white level original reference voltage VRB. This is called voltage setting data DVVRB. As a result, the memory 50 stores the black level original reference voltage setting data DVVRT, the white level original reference voltage setting data DVVRB, the other original reference voltage setting data DVVB to DVVG, and the black level original reference voltage setting data DVVRT. The adjustment data D3VRT and the fine adjustment data D3VRB related to the white level original reference voltage setting data DVVRB are held.

  The PDA 41 can adjust a white balance, a black level, and a white level in the display unit 44 by executing a predetermined processing procedure by the controller 43 so as to be able to cope with a change in light emission characteristics with time according to user's preference. The adjustment result is recorded and held in the memory 51, and the display of the display unit 44 is set based on the adjustment result. This PDA 41 includes original reference voltage setting data DVVRT, white level original data among the original reference voltage setting data DVVRT, DVVB to DVVG, DVVRB, fine adjustment data D3VRT, D3VRB recorded in the memory 50 at the time of factory shipment. The correction data D2 of the reference voltage setting data DVVRB is recorded and held in the memory 51 for each color in the format of difference data ΔDVVRT and ΔDVRVR corresponding to the original reference voltage setting data DVVRT and DVVRB, and recorded in the memory 51. The correction data D2 is output to the controller 52 at a timing according to the processing of the controller 52. Accordingly, the PDA 41 records and holds the adjustment result such as the white balance adjustment, and further sets the display of the display unit 44 based on the adjustment result.

  The controller 52 is configured by an integrated circuit, and time-division multiplexes the image data DR, DG, DB of each color output from the apparatus main body 42 in units of lines, and outputs image data D1 of one system. Further, after correcting the original reference voltage setting data DV by the correction data D2 output from the controller 43 of the apparatus main body 42, it is further corrected by the fine adjustment data D3 and output to the horizontal drive circuit 45.

  That is, in the controller 52, the timing generator (TG) 53 generates and outputs various timing signals synchronized with the image data D1, DR to DB. The memory control circuit 54 controls the operation of the memory 55 based on this timing signal. The memory 55 sequentially stores and outputs the image data DR to DB output from the apparatus main body 42, thereby outputting the image data DR. , DG and DB are time-division multiplexed in line units to output image data D1.

  The memory control circuit 56 controls the operation of the memory 50 to read the original reference voltage setting data DV and fine adjustment data D3 from the memory 50 and output them to the original reference voltage setting circuit 59 in the horizontal scanning cycle.

  The original reference voltage setting circuit 59 corrects the original reference voltage setting data DV output from the memory control circuit 56 with the correction data D2 output from the controller 43 of the apparatus main body 42, and further corrects it with the fine adjustment data D3. Output. That is, as shown in FIG. 3, the original reference voltage setting circuit 59 includes the original reference voltage for black level of the original reference voltage setting data DV (DVVRT, DVVB to DVVG, DVVRB) input via the memory control circuit 56. The setting data DVVRT and the white level original reference voltage setting data DVVRB are input to the adder circuit 59A, and the corresponding correction data D2 (ΔDVVRT, ΔDVVRB) output from the apparatus main body 42 is added here, and thereby, for these black levels. The original reference voltage setting data DVVRT and the white level original reference voltage setting data DVVRB are corrected. Further, the black level original reference voltage setting data DVVRT and the white level original reference voltage setting data DVVRB are input to the encoder 59C via the adding circuit 59B, and the remaining original reference voltage setting data DVVB to DVVG are corrected. Is input to the encoder 59C via the selector (SEL) 59D, where the original reference voltage setting data DVVRT, DVVB to DVVG, DVVRB are converted into serial data and output. In the original reference voltage setting circuit 59, an original reference voltage setting separately output from the apparatus main body 42 is used in place of the original reference voltage setting data DVVB to DVVG output from the memory control circuit 56 in this manner by setting of the selector 59D. Data can be output.

  As a result, the PDA 41 can set various original reference voltages VRT, VB to VG, VRB based on the original reference voltage setting data DVVRT, DVVB to DVVG, DVVRB recorded in the memory 50. The original reference voltage setting data DVVRT In addition, various gamma characteristics can be secured by setting DVVB to DVVG and DVVRB, and further, by setting original reference voltage setting data DVVRT and DVVRB, it is possible to cope with variations in colors and products in the display unit 44. Has been made. Further, the correction data D2 recorded in the memory 51 can be set so as to cope with a change with time of the display unit 44.

  In this series of processing, the original reference voltage setting circuit 59 generates and outputs original reference voltage setting data DV corresponding to the driving of the signal line SIG in the horizontal drive circuit 45. In this embodiment, the display unit 44 sets red, green, and blue pixels that are continuous in the horizontal direction as one set, and drives the one set of pixels in a time-division manner using a single drive signal. The reference voltage setting circuit 59 is configured to switch and output the original reference voltage setting data DV for red, green, and blue image data DR, DG, and DB, respectively, during one horizontal scanning period.

  In this way, the original reference voltage setting circuit 59 outputs the original reference voltage setting data DVVRT, DVVB to DVVG, DVVRB to the horizontal drive circuit 45 by correcting the original reference voltage setting data DVVRT, DVVB to DVVG, DVVRB in this way. Of the reference voltage setting data DVVRT, DVVB to DVVG, DVVRB, the original reference voltage setting data DVVRT and DVVRB relating to the black level and the white level are corrected by the fine adjustment data D3VRT and D3VRB relating to the black level and the white level, respectively, and output. .

  That is, in the original reference voltage setting circuit 59, the correction data generation circuit 59E counts the number of lines and the number of frames using, for example, a 2-bit counter, and determines the count result of each counter based on the fine adjustment data D3VRT and D3VRB for each color. Thus, 1-bit correction data D4VRT and D4VRB whose values change in units of lines and frames, respectively, are generated according to the fine adjustment data D3VRT and D3VRB. Specifically, as shown in FIGS. 4 to 7, when the continuous frames and lines are divided by the number of values that can be taken by the fine adjustment data D3VRT and D3VRB, the correction data The average value of D4VRT and D4VRB is equal in each line and corresponds to the value of fine adjustment data D3VRT and D3VRB. In the continuous line, the average value of correction data D4VRT and D4VRB is equal in each frame, and The correction data D4VRT and D4VRB are generated so as to be equal to the average value in each line related to consecutive frames.

  As a result, in this embodiment, the fine adjustment data D3VRT and D3VRB are formed by 2 bits, and the fine adjustment data D3VRT and D3VRB take four types of values, so that the correction data generation circuit 59E has a time axis in each line. When the correction data D4 for four consecutive frames in the direction is averaged for each line, the correction data D4 is generated so that the average value changes according to the fine adjustment data D3.

  In this case, the correction data generation circuit 59E sets the correction data D4 to the value 0 in any frame when the fine adjustment data D3 has a value 0 for the four consecutive frames (see FIG. 4) When the fine adjustment data D3 has a value of 1, the correction data D4 is set to a value of −1 in one of these four consecutive frames (FIG. 5). When the fine adjustment data D3 has a value of 2, the correction data D4 is set to a value of -1 in two of these four consecutive frames (FIG. 6), whereas the fine adjustment data D3 has a value of 3. In this case, the correction data D4 is set to a value −1 in three of the four consecutive frames (FIG. 7).

  Further, when setting the value of the correction data D4 in the four consecutive frames in this way, the correction data D4 is generated so that the correction data D4 with the same logical value is not continuous in the continuous frames as much as possible. When the fine adjustment data D3 has a value of 2 and the correction data D4 is set to a value of -1 in two of these four consecutive frames (FIG. 6), a frame of logic -1 and a frame of logic 0 The correction data D4 is generated so that are continuously alternated. The generation of the correction data D4 in units of 4 frames is repeated cyclically in successive frames.

  In the original reference voltage setting circuit 59, the correction data D4VRT and D4VRB generated in this way are added to the corresponding original reference voltage setting data DVVRT and DVVRB by the adding circuit 59B, and as shown in FIG. With the minimum resolution based on the reference voltage setting data DVVRT and DVVRB, the voltages of the original reference voltages VRT and VRB are temporarily lowered according to the fine adjustment data D3VRT and D3VRB in successive frames F1, F2, F3, F4,. Has been made. In the example shown in FIG. 1, the lines L1, L2,... Are blacked out and the original reference voltages VRT and VRB are thus lowered.

  As a result, in the PDA 41, the original reference voltages VRT and VRB are set in detail with an integration effect in the time axis direction, with a resolution lower than that of the original reference voltage setting data DVVRT and DVVRB. That is, when the correction data D4 is not set to a value of -1 in four consecutive frames in this way, the original reference voltages VRT and VRB averaged in the four consecutive frames are set as the original reference voltage setting output from the adder circuit 59A. It is generated by the voltage based on the data DVVRT and DVVRB, and is output with a resolution of about 80 [mV] with respect to a change of one digit in the original reference voltage setting data DVVRT and DVVRB output from the adding circuit 59A. Accordingly, in this case, for example, when the original reference voltage setting data DVVRT has a value of 10d (001010b (b: binary)), the original reference voltage VRT corresponding to the value 10d is output.

  On the other hand, when the correction data D4 is set to the value -1 for only one frame in the four consecutive frames, the original reference voltage VRT corresponding to the value 9d is output in the frame set to the value -1, and the remaining In three frames, the original reference voltage VRT corresponding to the value 10d is output, and as a result, in the average of these four frames, the original reference voltage VRT corresponding to the value 9.75d is output. When the correction data D4 is set to a value of -1 for only two frames in four consecutive frames, the average of the four frames outputs the original reference voltage VRT corresponding to the value 9.5d, whereas When the correction data D4 is set to the value −1 for only 3 frames in the 4 frames, the original reference voltage VRT corresponding to the value 9.25d is output in the average of the 4 frames. Accordingly, in this embodiment, the basic reference voltage setting data DVVRT and DVVRB output to the original reference voltage setting circuit 59 are simply corrected, and the number of bits of the original reference voltage setting data DVVRT and DVVRB is supported. The original reference voltages VRT and VRB are accurately set with a resolution equal to or lower than the resolution to be adjusted so that the color can be accurately adjusted with a simple configuration.

  Further, in this way, correction data D4 is generated so that correction data D4 with the same logical value does not continue in consecutive frames as much as possible, and thus, the original reference voltage setting data DVVRT and DVVRB are temporarily raised. The lowering is made inconspicuous.

  The correction data generation circuit 59E sequentially shifts the setting of the correction data D4 in the four consecutive frames by one frame in the line direction, thereby correcting the four consecutive lines as described above. The correction data D4VRT and D4VRB are generated so that the average value of the data D4VRT and D4VRB is equal in each frame and equal to the average value in each line related to four consecutive frames, thereby effectively avoiding the occurrence of flicker. To do.

  As a result, the correction data generation circuit 59E also sets the correction data D4 to 0 for any line when the fine adjustment data D3 is 0 as shown in FIG. When the fine adjustment data D3 has the value 1, the correction data D4 is set to the value −1 in one of the four consecutive lines (FIG. 5). When the fine adjustment data D3 has a value of 2, the correction data D4 is set to a value of -1 for two of these four consecutive lines (FIG. 6), whereas the fine adjustment data D3 has a value of 3. In this case, the correction data D4 is set to a value −1 on three of these four consecutive lines (FIG. 7).

  Further, when setting the value of the correction data D4 with four continuous lines in this way, the correction data D4 is generated so that the correction data D4 with the same logical value is not continuous with the continuous lines as much as possible. When the fine adjustment data D3 has a value of 2 and the correction data D4 is set to a value of -1 in two of these four continuous lines, the lines of logic -1 and the lines of logic 0 are alternately continuous. As described above, the correction data D4 is generated. Further, the generation of the correction data D4 in units of four lines is cyclically repeated sequentially with continuous lines.

  Accordingly, as shown in FIG. 1, the original reference voltage setting circuit 59 temporarily fine-tunes the voltages of the original reference voltages VRT and VRB in the line direction with the minimum resolution based on the original reference voltage setting data DVVRT and DVVRB. In accordance with the simple configuration in which the original reference voltage setting data DVVRT and DVVRB output to the original reference voltage generation circuit 30 are simply corrected in accordance with D3VRT and D3VRB, the original reference is also spatially included in each frame. The original reference voltages VRT and VRB are accurately set with a resolution equal to or lower than the resolution corresponding to the number of bits of the voltage setting data DVVRT and DVVRB, and the color can be adjusted with high accuracy by a simple configuration. .

  Thus, in this embodiment, the correction data generation circuit 59E and the addition circuit 59B modulate the black level original reference voltage setting data DVVRT and the white level original reference voltage setting data DVVRB with fine adjustment data D3VRT and D3VRB, respectively. It is made to constitute.

(2) Operation of Embodiment In the above configuration, in this PDA 41 (FIG. 2), image data DR to DB for display is input from the apparatus main body 42 to the controller 52, and here, in line units via the memory 55 Time-division multiplexing processing is performed so that image data relating to the same color is continuous, and image data D 1 as a result of the processing is input to the horizontal drive circuit 45. In the horizontal drive circuit 45, the image data D1 is taken into the shift register 13, and the image data for the same color is input to the digital / analog conversion circuits 15A to 15N in parallel in units of lines. The digital-analog conversion circuits 15A to 15N convert the signals into drive signals, and the drive signals are input to the display unit 44 through the amplifier circuits 16A to 16N, respectively. The signals are output to the signal lines SIG by 17A to 17N. As a result, the image data D1 is a combination of the red, green, and blue pixels with respect to the pixels by the organic EL elements that are cyclically repeated in the horizontal direction in the order of red, green, and blue in the display unit 44. After being distributed, the signal is converted into a drive signal, and this drive signal is distributed to the signal lines SIG related to the red, green, and blue pixels by the selectors 17A to 17N. Thus, in the PDA 41, the image data DR to DB The gradation is set and a desired image is displayed.

  In the original reference voltage generating circuit 30 (FIGS. 1 and 13), a plurality of original reference voltages VRT, VB to VG, VRB are generated, and a plurality of voltage dividing circuits R1 formed by connecting a predetermined number of resistors in series. In a reference voltage generating circuit 39 by a resistor series circuit formed by further connecting in series to R7, these original reference voltages VRT, VB to VG, VRB are divided to form reference voltages V1 to V64, and the digital-analog conversion circuit 15A .About.15N, the selection of the reference voltages V1 to V64 converts the image data D1 from digital to analog to generate a drive signal, whereby a gamma characteristic based on a broken line approximation set by the original reference voltages VRT, VB to VG, VRB. As a result, a drive signal is generated and an image is displayed.

  Thus, in the organic EL element, although the gamma characteristic itself does not vary, the light emission characteristic differs for each color and for each product, and the light emission characteristic changes with time. On the other hand, the PDA 41 divides the black level original reference voltage VRT and the white level original reference voltage VRB by the voltage dividing circuits 32B to 32G to generate the original reference voltages VB to VG. Reference voltages V1 to V64 are generated by dividing VB to VG and VRB by voltage dividing circuits R1 to R7. Thus, the image data DR to DB are digital-analog converted to generate a drive signal, and the black level original reference voltage VRT and the white level original reference voltage VRB are set for each color and each product. Therefore, it is necessary to correct so as to cope with the change with time.

  For this reason, the PDA 41 measures the light emission characteristics for each color and for each product, and based on the measurement results, the original reference voltages for instructing the settings of the original reference voltages VRT, VB to VG, VRB can be secured. The setting data DV is recorded and held in the memory 50 together with the fine adjustment data D3VRT and D3VRB (FIG. 2). Of these original reference voltages VRT, VB to VG, VRB, correction data D2 for correcting the original reference voltage VRT for black level and the original reference voltage VRB for white level is held in the memory 51. In the PDA 41, after the original reference voltage setting data DV is corrected by the correction data D2 in the original reference voltage setting circuit 59, it is sequentially input to the horizontal drive circuit 45 in correspondence with the time division multiplexing of the image data D1. The

  In the horizontal drive circuit 45 (FIG. 13), the original reference voltage setting data DV is divided into original reference voltages VRT, VB to VG, VRB by the decoder 35, and the original reference voltage setting data DV is digital analog. The conversion circuits 31A to 31H perform digital / analog conversion processing to generate original reference voltages VRT, VB to VG, and VRB.

  Thus, in this embodiment, by setting the original reference voltage setting data DV, various light emission characteristics can be dealt with, and various display panels can be dealt with easily and quickly. That is, the dynamic range adjustment, black level adjustment, and gamma characteristics can be changed simply by changing the data, so that the development period can be greatly shortened compared to the conventional case, and the effort required for development can also be reduced.

  This also makes it possible to flexibly deal with variations in emission characteristics from color to color and from product to product, and changes in light emission characteristics due to changes over time. Such variations in characteristics, deviations in white balance due to changes over time, and color reproducibility. It is possible to provide a high-quality display image by effectively avoiding deterioration of the image.

  In this way, the original reference voltages VRT, VB to VG, VRB are set by the original reference voltage setting data DV so that the light emission characteristics can be variously corrected. In this PDA 41, the black level original reference voltage VRT, the white level In the digital-analog conversion circuits 31A and 31H related to the original reference voltage VRB, a plurality of candidate voltages for the original reference voltages VRT and VRB are generated by dividing the reference voltage generating voltage VCOM by the voltage dividing circuits 32A and 32H, respectively. Are selected by the original reference voltage setting data DV, and the original reference voltages VRT and VRB are generated. Thereby, in these original reference voltages VRT and VRB, various voltages can be set between the reference voltage generating voltage VCOM and the ground potential.

  On the other hand, in the digital / analog conversion circuits 31B to 31G related to the remaining original reference voltages VB to VG, the voltage dividing circuits 32B to 32G are connected in series, and both ends are supplied with the black level original reference voltage VRT and the white level original. In a state of being connected to the reference voltage VRB, a plurality of candidate voltages of the original reference voltages VB to VG are generated by dividing by the voltage dividing circuits 32B to 32G, respectively, and the plurality of candidate voltages are selected by the original reference voltage setting data DV. Thus, the original reference voltages VB to VG are generated.

  As a result, the original reference voltages VB to VG are held so that the voltage changes only within the range of the candidate voltages output from the voltage dividing circuits 32B to 32G connected in series. Even when the original reference voltage setting data DV is erroneously set due to mixing, it is possible to prevent the output of a drive signal due to extreme gamma characteristics and to prevent significant image quality degradation due to noise.

  Further, both ends of the voltage dividing circuits 32B to 32G connected in series in this way are connected to the black level original reference voltage VRT and the white level original reference voltage VRB, thereby enabling dynamic range adjustment and black level adjustment. When the original reference voltages VRT and VRB are varied when correcting variations in light emission characteristics and changes over time, the original reference voltages VRT are determined by the resistance voltage dividing ratios of the voltage dividing circuits 32B to 32G connected in series. The original reference voltages VB to VG also change following the change of VRB. As a result, the process of resetting these original reference voltages VB to VG can be omitted, so that the PDA 41 can omit the calculation processes related to the remaining digital-analog conversion circuits 31B to 31G and perform the adjustment work. It is made so that it can be simplified.

  Further, in this way, the original reference voltages VRT, VB to VG, VRB are set by the original reference voltage setting data DV, and the original reference voltage setting corresponding to the time division multiplexing processing related to the transmission of the image data D1. By switching the data DV, one system of the original reference voltage generation circuit can be shared for the processing of the image data of each color, whereby the overall configuration can be simplified.

  As a result, the PDA 41 eventually switches the gamma characteristic by outputting the original reference voltage setting data DV three times in one line. As a result, even if the gamma characteristic is erroneously set due to noise mixing, the erroneous gamma setting due to the influence of noise can be stopped in one line, thereby reducing image quality degradation due to noise.

  Thus, in the PDA 41, the original reference voltages VRT, VB to VG, VRB are set by the original reference voltage setting data DV in this way, and the original reference voltages VRT, VB to VG, VRB are generated. By providing the circuit on the reference voltage generation circuit side and integrating it into an integrated circuit, the capacitances in the transmission paths of the original reference voltages VRT, VB to VG, VRB can be remarkably reduced. In the generation circuit 39, an amplifier circuit used to input the original reference voltages VRT, VB to VG, VRB can be omitted. Thereby, the configuration can be simplified and power consumption can be reduced accordingly. Further, since the amplifier circuit is unnecessary, the accuracy of the original reference voltages VRT, VB to VG and VRB input to the reference voltage generation circuit can be improved correspondingly, thereby setting the reference voltages V1 to V64. Accuracy can be improved and productivity can be improved.

  In this way, the original reference voltages VRT, VB to VG, and VRB are set by the original reference voltage setting data DVVRT, DVVB to DVVG, and DVVRB. In the PDA 41, the correction data generation circuit 59E (FIG. 3) and the memory 50 In accordance with the values of the fine adjustment data D3VRT and D3VRB held in the correction data D4, correction data D4 whose logical value changes from a value of 0 to a value of 1 in units of lines and frames is generated for each color (FIGS. 4 to 5). 7) The black level original reference voltage setting data DVVRT and the white level original reference voltage setting data DVVRB output to the original reference voltage generation circuit 30 are corrected by the correction data D4. Thereby, in the PDA 41, the voltages of the original reference voltages VRT and VRB temporarily correspond to the fine adjustment data D3VRT and D3VRB according to the value of the fine adjustment data D3VRT and D3VRB with the minimum resolution by the original reference voltage setting data DVVRT and DVVRB. (Fig. 1).

  In the PDA 41, when the continuous frames and lines are divided by the number of values that the fine adjustment data D3VRT and D3VRB can take, the average values of the correction data D4VRT and D4VRB are equal in each line in the continuous frames. In addition, so as to correspond to the values of the fine adjustment data D3VRT and D3VRB, and in the continuous line, the average value of the correction data D4VRT and D4VRB is equal in each frame and is equal to the average value in each line related to the continuous frame. Thus, the correction data D4VRT and D4VRB are generated, and the black level and white level original reference voltages VRT and VRB, which are the generation references of the reference voltages V1 to V64, are continuously generated in the time axis direction by successive frames. Integration effect in the time axis direction, spatially modulated by the line Spatial by integration effect original reference voltage setting data DVVRT, original reference voltages VRT for these black level and for the white level by the following resolution minimum resolution by DVVRB, VRB is set. As a result, the PDA 41 can adjust the black level and the white level with high accuracy with a simple configuration, and perform color adjustment with high accuracy.

  In this embodiment, however, the temporary fall of the original reference voltages VRT and VRB by the fine adjustment data D3 is performed in accordance with 2-bit fine adjustment data in units of four consecutive lines and four frames. As a result, the original reference voltage setting data DVVRT and DVVRB relating to the black level and the white level are created by 8 bits (6 bits + 2 bits), and the original reference voltage setting data DVVRT and DVVRB are related. The original reference voltages VRT and VRB relating to the black level and the white level can be set with the same resolution as when the digital-analog conversion circuits 31A and 31H are configured with 8 bits. As a result, in this embodiment, the color misregistration can be adjusted with high accuracy by a simple configuration.

  In this way, when the original reference voltages VRT and VRB are modulated temporally and spatially related to the display of the display unit 44, the PDA 41 prevents the correction data D4 having the same logical value from continuing in continuous frames as much as possible. Then, the correction data D4 is generated, thereby making the temporary fall of the original reference voltages VRT and VRB inconspicuous. For the line direction, the setting of the correction data D4 in the four consecutive frames is sequentially shifted by one frame at a time, so that the temporary fall of the original reference voltages VRT and VRB is also noticeable in the line direction. Further, the occurrence of flicker is effectively avoided.

(3) Effects of the Embodiment According to the above configuration, the black level and white level original reference voltages are generated according to the black level and white level original reference voltage setting data, respectively. In addition, the reference voltage for digital-analog conversion is generated by the resistance voltage division of the original reference voltage for white level and the original reference voltage setting data for black level and white level according to the correction data. Modulating in time, and using these spatial and temporal integration effects, setting the original reference voltage for black level and white level with the resolution below the resolution of the original reference voltage setting data, The color can be adjusted with high accuracy with a simple configuration so as to cope with product variations and the like.

  In the above-described embodiment, the case where the adjustment accuracy is improved for both the black level and the white level has been described. Only one of the white level and the white level may be modulated by fine adjustment data.

  Further, in the above-described embodiment, only the black level original reference voltage setting data and the white level original reference voltage setting data are corrected by the correction data output from the apparatus main body. Although the case where the change is not corrected has been described, the present invention is not limited to this, and correction data corresponding to the fine adjustment data is provided in the apparatus main body so that the fine adjustment data can also correspond to the temporal change in the light emission characteristics. May be.

  In the above-described embodiments, the case where the present invention is applied to a PDA has been described. However, the present invention is not limited to this and can be widely applied to various video devices.

  The present invention relates to a flat display device and can be applied to, for example, a display device using an organic EL element.

It is a basic diagram with which it uses for description of the setting of the black level original reference voltage in the PDA which concerns on Example 1 of this invention, and a white level original reference voltage. It is a block diagram which shows PDA which concerns on Example 1 of this invention. FIG. 2 is a block diagram illustrating an original reference voltage setting circuit in FIG. 1. 10 is a chart for explaining generation of correction data when fine adjustment data is a value [00]. 10 is a chart for explaining generation of correction data when fine adjustment data is a value [01]. It is a table | surface used for description of the production | generation of correction | amendment data in case fine adjustment data is a value [10]. 10 is a chart for explaining generation of correction data when fine adjustment data is a value [11]. It is a block diagram which shows the conventional liquid crystal display device. It is a block diagram which shows the horizontal drive circuit in a liquid crystal display device of FIG. 8 with a periphery structure. 10 is a time chart for explaining FIG. 9. FIG. 10 is a block diagram illustrating an original reference voltage generation circuit and a reference voltage generation circuit in the horizontal drive circuit and controller of FIG. 9. It is a characteristic curve figure with which it uses for description of the gamma characteristic in the liquid crystal display device of FIG. It is a block diagram which shows the example of a setting of the original reference voltage by original reference voltage setting data. It is a characteristic curve figure with which it uses for description of the gamma characteristic by the structure of FIG. It is a characteristic curve figure with which it uses for description of the influence of the noise in the gamma characteristic by the structure of FIG. It is a characteristic curve figure with which it uses for description of the dynamic range adjustment in the gamma characteristic by the structure of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device, 2, 44 ... Display part, 3R, 3G, 3B ... Pixel, 4, 45 ... Horizontal drive circuit, 6, 42 ... Device main body, 7, 43, 52 ... Controller, 9, 54, 56 ... Memory control circuit, 10, 50, 51, 55 ... Memory, 12, 30 ... Original reference voltage generation circuit, 13 ... Shift register, 14, 39 ... Reference voltage generation circuit, 15A -15N, 31A-31H: Digital-analog conversion circuit, 17A-17N, 33A-33H ... Selector, 21, 32A-32H, R1-R7 ... Voltage divider, 26 ... Resistor series circuit, 35 ... Decoder , 41... PDA, 59... Original reference voltage setting circuit, 59 A, 59 B... Adder circuit, 59 E.

Claims (3)

In a flat display device that displays an image based on image data,
A display unit in which pixels are arranged in a matrix;
A horizontal drive circuit that outputs a drive signal of the display unit,
The horizontal drive circuit includes:
The black level original reference voltage setting data is modulated to generate the modulated black level original reference voltage setting data and / or the white level original reference voltage setting data is modulated to generate the modulated white level original reference voltage setting data. A modulation circuit to be generated;
A digital-to-analog converter for black level to generate a black level YoHara reference voltage in response to the modulated black level YoHara reference voltage setting data, for the white level in response to the modulated white level YoHara reference voltage setting data a digital-to-analog conversion circuit for the white level to generate the original reference voltage, based on the original reference voltage setting data except for the black level YoHara reference voltage and a white level YoHara reference voltage black level for the white level with respect to the An original reference voltage generation circuit including a plurality of digital-analog conversion circuits excluding a black level and a white level for generating an original reference voltage except for a black level and a white level ;
A plurality of voltage dividing circuits having a plurality of resistors connected in series are further connected in series, and the black level original reference voltage and the white level original reference voltage are respectively input to both ends, and the plurality of resistors are connected between the voltage dividing circuits. A reference voltage generation circuit that inputs the original reference voltage by a digital-to-analog converter circuit and outputs a plurality of reference voltages by the divided voltages by the plurality of voltage dividing circuits;
A plurality of selection circuits for outputting the drive signal by inputting the plurality of reference voltages and selectively outputting according to the image data relating to the corresponding signal lines ;
Have,
The modulation circuit includes:
Generate black level correction data whose value changes in line units and frame units according to the black level fine adjustment data values and / or line units and frame units in accordance with the white level fine adjustment data values a correction data generation circuit for generating a white level correction data that will change the value,
Wherein the black level correction data black level YoHara reference voltage setting said modulated black level by adding the data YoHara reference voltage to generate the configuration data and or the white level correction data before xylo level YoHara reference An adder circuit that adds to the voltage setting data to generate the modulated white level original reference voltage setting data ;
The correction data generation circuit includes:
When the continuous frames and lines are divided by the number of values that can be taken by the fine adjustment data for the black level,
The average value of the black level correction data set in the continuous frame is equal in each line and corresponds to the value of the black level fine adjustment data.
The average value of the black level correction data set in the continuous line is equal in each frame, and is equal to the average value of the black level correction data set in the continuous frame.
Generating the black level correction data;
And / or when continuous frames and lines are divided by the number of values that the white level fine adjustment data can take,
As the average value of the white level correction data set in the frame in which the consecutive, equally on each line, and corresponds to the value before the fine adjustment data xylo level,
So that the average value of xylo-level correction data before being set in the line which the consecutive, equal in each frame, and equal to the average of the previous correction data xylose level set in the frame of the continuous,
Before flat display device that generates a xylo-level correction data. The black level digital-to-analog converter circuit is:
A plurality of black level original reference voltage candidate voltages are generated by a voltage dividing circuit for generating an original reference voltage and selectively output according to the modulated black level original reference voltage setting data. Generate voltage,
The white level digital-to-analog conversion circuit is:
A plurality of candidate voltages for the white level original reference voltage are generated by a voltage dividing circuit for generating an original reference voltage and selectively output according to the modulated white level original reference voltage setting data. Generate voltage,
A plurality of digital-analog conversion circuits excluding the black level and the white level are:
A plurality of original reference voltage candidate voltages are respectively generated by a voltage dividing circuit for generating an original reference voltage and selectively output according to original reference voltage setting data except for the black level and the white level. the flat display apparatus as claimed in 請 Motomeko 1 that generates a voltage. A time-division multiplexing circuit that time-division-multiplexes the image data relating to the pixels of each color and supplies the image data to the horizontal drive circuit so that the image data relating to the pixels of the same color is continuous in line units;
The original reference voltage generation circuit includes:
By switching between the modulated black level original reference voltage setting data and the modulated white level original reference voltage setting data in response to the color switching in the time division multiplexing circuit, an original corresponding to each color in the image data is obtained. the flat display apparatus as claimed in 請 Motomeko 1 or claim 2 sequentially generates a reference voltage.

Images