JP4507395B2 - Method for manufacturing element substrate for electro-optical device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an SOI substrate including a single crystal silicon layer on one surface of a support substrate, an element substrate including the SOI substrate, an electro-optical device and an electronic apparatus including the element substrate, and a method for manufacturing the SOI substrate The present invention relates to a method for manufacturing an element substrate.
[0002]
[Prior art]
A semiconductor technology in which a single crystal silicon thin film is formed on an insulating substrate and a semiconductor device is formed using the single crystal silicon thin film is called SOI (Silicon On Insulator) technology. It is widely used because it has advantages such as integration.
[0003]
As one of the SOI techniques, there is a technique for manufacturing an SOI substrate by bonding a single crystal silicon substrate. A conventional SOI substrate manufacturing method and structure will be briefly described with reference to FIG.
[0004]
First, as illustrated in FIG. 18A, a single crystal silicon substrate 1003 in which a silicon oxide film 1002 is formed by previously oxidizing a surface on a bonding side is bonded to a surface of a support substrate 1001 using a hydrogen bonding force. Then, after increasing the bonding strength by heat treatment, the single crystal silicon substrate 1003 is thinned by grinding, polishing, etching or the like to form a single crystal silicon thin film 1004 as shown in FIG. An SOI substrate having a structure in which a silicon oxide film 1002 and a single crystal silicon layer 1004 are sequentially stacked on the surface of the substrate 1001 is manufactured.
[0005]
According to the above method for manufacturing an SOI substrate, since the single crystal silicon thin film 1004 having excellent crystallinity can be formed to reduce the thickness of the single crystal silicon substrate 1003, a high-performance device can be manufactured. .
[0006]
An SOI substrate based on such a bonding method is used for manufacturing various devices in the same way as an ordinary bulk semiconductor substrate (semiconductor integrated circuit). However, as a feature different from a bulk substrate, various materials can be used as a supporting substrate. The point which can use a board | substrate can be mentioned.
[0007]
That is, as a supporting substrate, a normal silicon substrate, a transparent (light transmissive) quartz substrate, a glass substrate, or the like can be used. Therefore, for example, by forming a single crystal silicon thin film on a light-transmitting substrate, single crystal silicon having excellent crystallinity even in a device requiring light transmittance, such as a transmissive liquid crystal display device Using a thin film, a transistor element such as a high-performance liquid crystal driving MOSFET can be formed.
[0008]
[Problems to be solved by the invention]
When an SOI substrate is manufactured using a quartz substrate or a glass substrate as a support substrate and a transistor element is formed on the surface, impurities contained in the support substrate permeate the silicon oxide film and diffuse to the transistor element side. There is a risk of deteriorating the characteristics of the.
[0009]
In addition, regardless of the type of the support substrate, when the support substrate and the single crystal silicon substrate are bonded together in the manufacturing process of the SOI substrate, Na from the atmosphere. ⁺ , K ⁺ , Cl ^- In this case, the obtained SOI substrate is obtained by sandwiching the impurity between the supporting substrate and the silicon oxide film.
[0010]
When a transistor element is formed on the surface of an SOI substrate having such a structure, impurities sandwiched between the support substrate and the silicon oxide film permeate the silicon oxide film and diffuse to the transistor element side. There is a risk of deteriorating the characteristics of the element.
[0011]
Conventionally, when attaching a support substrate and a single crystal silicon substrate, a dustproof filter has been used to prevent impurities from adsorbing to the support substrate from the atmosphere. However, the present situation is that it is impossible to completely prevent impurities from adsorbing to the bonding surface from the atmosphere.
[0012]
Therefore, the present invention has been made to solve the above problems, and impurities contained in the support substrate, or impurities adsorbed on the bonding surface of the support substrate and the single crystal silicon substrate, are on the single crystal silicon layer side. It is an object of the present invention to provide an SOI substrate and a method for manufacturing the same that can be completely prevented from diffusing.
[0013]
Also provided are an element substrate and a method for manufacturing the element substrate that can completely prevent the transistor element from being affected by impurities contained in the support substrate or impurities adsorbed on the bonding surface of the support substrate and the single crystal silicon substrate. The purpose is that.
[0014]
Further, it is an object of the present invention to provide an electro-optical device and an electronic apparatus which are provided with this element substrate and can prevent deterioration of characteristics of the transistor element and have excellent performance.
[0015]
[Means for Solving the Problems]
In order to solve the above problems, the present inventor has made various studies, and as a result, the silicon nitride film or the silicon nitride oxide film is contained in the support substrate and the bonded surface between the support substrate and the single crystal silicon substrate. The inventors have found that the adsorbed impurities are not permeated, and have focused on this point to complete the present invention.
[0016]
The SOI substrate of the present invention is an SOI substrate having a single crystal silicon layer on one surface of a support substrate, and a single layer or a laminated structure of an insulating film between the support substrate and the single crystal silicon layer. An insulating portion is provided, and the insulating portion includes at least a silicon nitride film or a silicon nitride oxide film.
[0017]
In this manner, by providing the insulating portion including at least a silicon nitride film or a silicon nitride oxide film between the supporting substrate and the single crystal silicon layer, impurities contained in the supporting substrate can be converted into a silicon nitride film or Since the silicon nitride oxide film is not transmitted, it is possible to completely prevent the impurities contained in the supporting substrate from diffusing to the single crystal silicon layer side.
[0018]
Note that in the SOI substrate of the present invention, as the insulating film other than the silicon nitride film or the silicon nitride oxide film constituting the insulating portion, a silicon oxide film can be specifically mentioned.
[0019]
The SOI substrate of the present invention having the above structure includes a step of forming a silicon nitride film or a silicon nitride oxide film on one surface of a single crystal silicon substrate or a support substrate, and the silicon nitride film or silicon nitride oxide film. Forming a silicon oxide film on the surface, bonding the single crystal silicon substrate and the support substrate with the surface of the silicon oxide film as a bonding surface, and the single crystal bonded to the support substrate And a process for forming a single crystal silicon layer by thinning the silicon substrate.
[0020]
Further, in this way, after forming a silicon nitride film or a silicon nitride oxide film on one surface of either the single crystal silicon substrate or the support substrate, and further forming a silicon oxide film on the surface, the silicon oxide film Adhesion between the single crystal silicon substrate and the support substrate can be improved by bonding the single crystal silicon substrate and the support substrate with the surface as a bonding surface. Note that any of the silicon nitride film, the silicon nitride oxide film, and the silicon oxide film may be formed first.
[0021]
In the method for manufacturing an SOI substrate of the present invention, it is desirable to form a silicon nitride film or a silicon nitride oxide film on the surface of the single crystal silicon substrate, and a single crystal silicon substrate on which a silicon nitride film or a silicon nitride oxide film is formed; By attaching the support substrate, the silicon nitride film or the silicon nitride oxide film can be positioned closer to the single crystal silicon layer side than the bonding surface of the support substrate and the single crystal silicon substrate. It is possible to completely prevent not only the impurities but also the impurities adsorbed on the bonding surface from diffusing to the single crystal silicon layer side.
[0022]
In addition, a silicon nitride film, a silicon nitride oxide film, or a silicon oxide film may be formed on the surface of the single crystal silicon substrate or the support substrate by a CVD method or the like, but the manufacturing process is simplified and the film thickness is uniform. A flat silicon nitride film, a silicon nitride oxide film, or a silicon oxide film can be formed, and further, the adhesion between the single crystal silicon substrate and the silicon nitride film or silicon nitride oxide film can be improved. After forming the silicon oxide film by thermally oxidizing the surface, the surface of the single crystal silicon substrate on which the silicon oxide film is formed is nitrided or oxynitrided with dinitrogen monoxide or nitric oxide, thereby forming the silicon oxide film A silicon nitride film or silicon nitride oxide film is formed on the single crystal silicon substrate side, and if necessary, Then, the surface of the single crystal silicon substrate on which the silicon nitride film or the silicon nitride oxide film is formed is re-thermally oxidized to form a second silicon oxide film on the single crystal silicon substrate side of the silicon nitride film or the silicon nitride oxide film. It is desirable to do.
[0023]
That is, the SOI substrate manufacturing method of the present invention in this case includes a step of forming a silicon oxide film on the surface of a single crystal silicon substrate, and a silicon nitride film or a silicon nitride oxide oxide on the single crystal silicon substrate side of the silicon oxide film. Forming a film; using the surface of the silicon oxide film as a bonding surface; bonding the single crystal silicon substrate and the support substrate; and thinning the single crystal silicon substrate bonded to the support substrate. And a process.
[0024]
In addition, the method for manufacturing an SOI substrate of the present invention in the case where the second silicon oxide film is formed on the surface of the single crystal silicon substrate on which the silicon nitride film or the silicon nitride oxide film is formed has the first crystal structure on the surface of the single crystal silicon substrate. Forming a silicon oxide film, forming a silicon nitride film or a silicon nitride oxide film on the single crystal silicon substrate side of the first silicon oxide film, and forming the silicon nitride film or the silicon nitride oxide film A step of forming a second silicon oxide film on the single crystal silicon substrate side, a step of bonding the single crystal silicon substrate and a support substrate with the surface of the first silicon oxide film as a bonding surface, and the support And a step of thinning the single crystal silicon substrate bonded to the substrate.
[0025]
By forming a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film in this way and forming a flat film with a uniform thickness, voids are generated on the bonding surface of the support substrate and the single crystal silicon substrate. Since the bonding strength can be improved and the silicon nitride film or the silicon nitride oxide film has an effect of reducing the stress of bonding, a transistor element or the like is formed using an SOI substrate. In this case, it is possible to prevent film peeling or the like from occurring, so that the yield of products can be improved.
[0026]
In addition, according to the manufacturing method, the insulating portion has a stacked structure of the silicon nitride film or the silicon nitride oxide film and the silicon oxide film formed on the upper surface or the lower surface of the silicon nitride film or the silicon nitride oxide film. An SOI substrate can be provided, and this SOI substrate completely diffuses impurities contained in the support substrate and impurities adsorbed on the bonding surface of the support substrate and the single crystal silicon substrate to the single crystal silicon layer side. In addition to being able to prevent, the bonding strength between the support substrate and the single crystal silicon substrate is high and the reliability becomes high.
[0027]
In addition, when the support substrate is formed of a light-transmitting substrate such as a quartz substrate or a glass substrate, the SOI substrate can be applied to a device that transmits light, such as a transmissive liquid crystal device. In this case, the thickness of the silicon nitride film or the silicon nitride oxide film constituting the insulating portion is set to 100 nm in order to prevent the light transmittance from being lowered due to the presence of the silicon nitride film or the silicon nitride oxide film. It is desirable to set the following.
[0028]
An element substrate can be manufactured using the above SOI substrate of the present invention. The element substrate manufacturing method of the present invention includes a step of using a SOI substrate manufactured by the SOI substrate manufacturing method of the present invention and forming a semiconductor layer constituting a transistor element by the single crystal silicon layer of the SOI substrate. It is characterized by that.
[0029]
Further, this element substrate manufacturing method can provide an element substrate having a transistor element including a semiconductor layer made of a single crystal silicon layer of an SOI substrate of the present invention.
[0030]
The element substrate of the present invention can completely prevent the impurities contained in the support substrate and the impurities adsorbed on the bonding surface of the support substrate and the single crystal silicon substrate from diffusing to the transistor element side. It is possible to prevent the deterioration of the characteristics of the transistor element.
[0031]
The element substrate of the present invention, another substrate disposed so as to face the surface of the element substrate on which the transistor element is formed, and an electro-optic material layer sandwiched between the two substrates An electro-optical device including the electronic optical device including the electro-optical device according to the invention can be provided. In the electro-optical device according to the aspect of the invention, it is preferable that a light shielding film is formed on the lower surface of the silicon nitride film or the silicon nitride oxide film via an insulating film made of a silicon oxide film.
[0032]
The electro-optical device and the electronic apparatus provided with the element substrate of the present invention can prevent deterioration of the characteristics of the transistor element and have excellent performance.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments according to the present invention will be described in detail.
[0034]
[SOI substrate]
First, FIG. 1 shows a cross-sectional structure of an SOI substrate according to an embodiment of the present invention, and the structure of this SOI substrate 200 will be described.
[0035]
As shown in FIG. 1, the SOI substrate 200 of the present embodiment includes a support substrate 201 made of silicon, quartz, glass, or the like and a single crystal silicon layer 202, and between the support substrate 201 and the single crystal silicon layer 202. Is formed with an insulating portion 205 having a laminated structure of a plurality of insulating films. In this embodiment, the insulating portion 205 is formed by sequentially laminating a first silicon oxide film 203B, a silicon nitride film or silicon nitride oxide film 204, and a second silicon oxide film 203A from the support substrate 201 side.
[0036]
Next, as a method for manufacturing the SOI substrate according to this embodiment, a method for manufacturing the SOI substrate 200 having the above structure will be described with reference to FIGS. 2A to 2E and 3A to 3C are cross-sectional views. In addition, the manufacturing method described below is an example, and the present invention is not limited to the following.
[0037]
First, as shown in FIG. 2A, a single crystal silicon substrate 202A having a film thickness of, for example, about 300 to 900 μm is prepared, and as shown in FIG. 2B, one surface of the single crystal silicon substrate 202A is prepared. O ₂ Or H ₂ By performing thermal oxidation at 700 to 1150 ° C. in an O atmosphere, a first silicon oxide film 203B having a thickness of, for example, about 5 to 400 nm is formed on one surface of the single crystal silicon substrate 202A.
[0038]
Next, as shown in FIG. 2C, the surface of the single crystal silicon substrate 202A on which the first silicon oxide film 203B is formed is nitrided or oxidized at 800 to 1150 ° C. in a dinitrogen monoxide or nitrogen monoxide atmosphere. By nitriding, a silicon nitride film or a silicon nitride oxide film 204 is formed on the single crystal silicon substrate 202A side of the first silicon oxide film 203B.
[0039]
When the support substrate 201 is made of a light-transmitting substrate such as a quartz substrate or a glass substrate, and the SOI substrate 200 is applied to a device that transmits light, such as a transmissive liquid crystal device, a silicon nitride film Alternatively, the thickness of the silicon nitride film or the silicon nitride oxide film 204 is preferably 100 nm or less in order to prevent the light transmittance from being lowered due to the presence of the silicon nitride oxide film 204.
[0040]
Next, as shown in FIG. 2D, the surface of the single crystal silicon substrate 202A on which the silicon nitride film or the silicon nitride oxide film 204 is formed is O ₂ Or H ₂ By performing thermal oxidation at 700 to 1150 ° C. in an O atmosphere, a second silicon oxide film 203A having a thickness of, for example, about 5 to 400 nm is formed on the single crystal silicon substrate 202A side of the silicon nitride film or the silicon nitride oxide film 204. Form. As described above, the insulating portion 205 including the first silicon oxide film 203B, the silicon nitride film or the silicon nitride oxide film 204, and the second silicon oxide film 203A is formed on the surface of the single crystal silicon substrate 202A.
[0041]
Next, as shown in FIG. 2E, the surface of the single crystal silicon substrate 202A having the insulating portion 205 formed on the surface thereof on the insulating portion 205 side has hydrogen ions (H ⁺ ), For example, with an acceleration voltage of 100 keV and a dose of 10 × 10 ¹⁶ / Cm ² Inject. By this treatment, a high concentration layer 206 of hydrogen ions is formed in the single crystal silicon substrate 202A.
[0042]
Next, as shown in FIG. 3A, the surface of the insulating portion 205 (the surface of the first silicon oxide film 203B) is used as a bonding surface, and a single crystal silicon substrate 202A and a support substrate made of silicon, quartz, glass, or the like. Bonding with 201 is performed. For the bonding step, for example, a method of directly bonding two substrates by heat treatment at 300 ° C. for 2 hours can be employed. In order to further increase the bonding strength, it is necessary to further increase the heat treatment temperature to about 450 ° C., but there is a large difference in the thermal expansion coefficient between the support substrate 201 made of quartz and the single crystal silicon substrate 202A. Therefore, if heated as it is, defects such as cracks are generated in the single crystal silicon layer, and the quality of the manufactured SOI substrate 200 may be deteriorated.
[0043]
Therefore, in order to suppress the occurrence of defects such as cracks, the single crystal silicon substrate 202A once subjected to heat treatment for bonding at 300 ° C. is subjected to wet etching or CMP (chemical mechanical polishing). It is desirable to perform heat treatment at a higher temperature after thinning to about 100 to 150 μm. For example, using an aqueous KOH solution at 80 ° C., etching is performed so that the thickness of the single crystal silicon substrate 202A is 150 μm, and then bonding to the support substrate 201 is performed, and heat treatment is performed again at 450 ° C. to increase the bonding strength. It is desirable to increase.
[0044]
Next, as shown in FIG. 3B, most of the single crystal silicon substrates are formed by heat-treating the two bonded substrates, leaving a thin single crystal silicon layer 202 on the surface of the support substrate 201. 202A is peeled off. This substrate peeling phenomenon occurs because silicon bonds are broken by hydrogen ions introduced into the single crystal silicon substrate 202A. That is, in the single crystal silicon substrate 202A, the single crystal silicon substrate 202A can be divided at a portion near the boundary between the high concentration layer 206 of hydrogen ions and the portion where hydrogen ions are not implanted.
[0045]
The heat treatment for peeling the single crystal silicon substrate 202A can be performed, for example, by heating the two bonded substrates to 600 ° C. at a temperature increase rate of 20 ° C. per minute. By this heat treatment, most of the bonded single crystal silicon substrate 202A is separated from the support substrate 201, and a single crystal silicon layer 202 having a thickness of about 200 nm ± 5 nm is formed on the surface of the support substrate 201, for example. The Note that the single crystal silicon layer 202 can be formed to have an arbitrary thickness from 50 nm to 3000 nm by changing the acceleration voltage of hydrogen ion implantation performed on the single crystal silicon substrate 202A described above.
[0046]
As described above, the SOI substrate 200 is manufactured as shown in FIG.
[0047]
Note that the method for forming the single crystal silicon layer 202 by thinning the single crystal silicon substrate 202A after bonding the single crystal silicon substrate 202A and the support substrate 201 is not limited to the above-described method using hydrogen ions. The thin single crystal silicon layer 202 is formed by bonding the single crystal silicon substrate and the support substrate, polishing the surface of the single crystal silicon substrate to a thickness of 3 to 5 μm, and then further adding PACE (Plasma). On the supporting substrate, the epitaxial silicon layer formed on the porous silicon layer is bonded by selective etching of the porous silicon layer by etching the film thickness to about 0.05 to 0.8 μm by the Assisted Chemical Etching method. Transcribed into ELTRAN (Epitaxial Layer T It can also be obtained by Ansfer) method.
[0048]
According to the method for manufacturing an SOI substrate of this embodiment, a single crystal silicon substrate 202A having a silicon nitride film or a silicon nitride oxide film 204 formed on the surface is bonded to a support substrate 201, whereby a silicon nitride film or a silicon nitride oxide is bonded. Since the film 204 can be positioned closer to the single crystal silicon layer 202 than the bonding surface of the support substrate 201 and the single crystal silicon substrate 202A, impurities contained in the support substrate 201, and the support substrate 201 and the single crystal silicon It is possible to completely prevent the impurities adsorbed on the bonding surface with the substrate 202A from diffusing to the single crystal silicon layer 202 side.
[0049]
Further, a second silicon oxide film 203A, a silicon nitride film or a silicon nitride oxide film 204, and a first silicon oxide film 203B are sequentially stacked on the surface of the single crystal silicon substrate 202A by using a CVD method or the like. Also good. However, in this case, the manufacturing process is complicated, and the thickness of the second silicon oxide film 203A, the silicon nitride film or the silicon nitride oxide film 204, and the first silicon oxide film 203B may be nonuniform. is there.
[0050]
However, in this embodiment, after the surface of the single crystal silicon substrate 202A is thermally oxidized to form the first silicon oxide film 203B, the surface of the single crystal silicon substrate 202A on which the first silicon oxide film 203B is formed is nitrided or By oxynitriding, a silicon nitride film or a silicon nitride oxide film 204 is formed on the single crystal silicon substrate 202A side of the first silicon oxide film 203B, and a silicon nitride film or a silicon nitride oxide film 204 is further formed. Since the method of forming the second silicon oxide film 203A on the single crystal silicon substrate 202A side of the silicon nitride film or the silicon nitride oxide film 204 by thermally oxidizing the surface of the substrate 202A is adopted, a flat film having a uniform film thickness is adopted. First silicon oxide film 203B, silicon nitride film Ku can be formed a silicon nitride oxide film 204, the second silicon oxide film 203A.
[0051]
By forming these films having a uniform thickness in this manner, voids can be prevented from being generated on the bonding surface between the support substrate 201 and the single crystal silicon substrate 202A, and the bonding strength can be improved. In addition, when a transistor element or the like is formed using the SOI substrate 200, film peeling or the like can be prevented, so that the yield of products can be improved.
[0052]
Further, according to this method, the first silicon oxide film 203B, the silicon nitride film or the silicon nitride oxide film 204, and the second silicon oxide film 203A can be formed integrally with the single crystal silicon substrate 202A. The SOI substrate 200 in which the first silicon oxide film 203B, the silicon nitride film or the silicon nitride oxide film 204, the second silicon oxide film 203A, and the single crystal silicon layer 202 have high adhesion can be manufactured.
[0053]
In addition, according to the present embodiment, the first silicon oxide film 203B is formed on the surface of the silicon nitride film or the silicon nitride oxide film 204, and the surface of the first silicon oxide film 203B is used as the bonding surface. The first silicon oxide film 203B is not formed on the surface of the silicon film or the silicon nitride oxide film 204, and the supporting substrate 201 and the single crystal silicon are used rather than the case where the surface of the silicon nitride film or the silicon nitride oxide film 204 is used as a bonding surface. Adhesion with the substrate 202A can be improved, and the bonding strength can be improved.
[0054]
Note that the first silicon oxide film 203B, the silicon nitride film or the silicon nitride oxide film 204, and the second silicon oxide film 203A may be formed by a CVD method or the like without being integrally formed with the single crystal silicon substrate 202A. In the case where a flat film can be formed, a method for forming the first silicon oxide film 203B, the silicon nitride film or the silicon nitride oxide film 204, and the second silicon oxide film 203A other than those described in the above manufacturing method and A pattern of bonding between the crystalline silicon substrate 202A and the support substrate 201 can be illustrated.
[0055]
In this embodiment, the second silicon oxide film 203A is formed after the silicon nitride film or the silicon nitride oxide film 204. This is because the silicon nitride film or the silicon nitride oxide film is formed on the single crystal silicon substrate 202A. This is only when lattice defects are formed when 204 is formed directly. In particular, when a silicon nitride oxide film is formed, lattice defects are hardly formed, and thus the second silicon oxide film 203A may not be formed.
[0056]
Based on FIGS. 4A to 4D, a method for forming the first silicon oxide film 203B, the silicon nitride film or silicon nitride oxide film 204, and the second silicon oxide film 203A other than the above, and a bonding pattern are described. Briefly described. 4A to 4D show a combination of the supporting substrate 201 and the single crystal silicon substrate 202A to be bonded together.
[0057]
As shown in FIG. 4A, a second silicon oxide film 203A, a silicon nitride film or a silicon nitride oxide film 204, and a first silicon oxide film 203B are sequentially formed on the surface of the single crystal silicon substrate 202A by a CVD method. After the formation, the single crystal silicon substrate 202A and the support substrate 201 may be bonded to each other.
[0058]
Further, after the second silicon oxide film 203A is formed by thermally oxidizing the surface of the single crystal silicon substrate 202A, a silicon nitride film or a silicon nitride oxide film 204 and a first silicon oxide film 203B are sequentially formed by a CVD method. For example, the method described above and the CVD method may be combined.
[0059]
When a silicon oxide film and a silicon nitride film or a silicon nitride oxide film are formed on the surface of the single crystal silicon substrate 202A using a CVD method, as shown in FIG. 4B, the surface of the single crystal silicon substrate 202A is formed. A silicon nitride film or a silicon nitride oxide film 204 may be formed directly without providing the second silicon oxide film 203A thereon.
[0060]
Even with such a structure, the silicon nitride film or the silicon nitride oxide film 204 can be positioned closer to the single crystal silicon layer 202 than the bonding surface of the support substrate 201 and the single crystal silicon substrate 202A. It is also possible to completely prevent the impurities contained in and the impurities adsorbed on the bonding surface of the supporting substrate 201 and the single crystal silicon substrate 202A from diffusing to the single crystal silicon layer 202 side.
[0061]
4A and 4B, the case where bonding is performed after a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film is formed on the single crystal silicon substrate 202A side has been described. It is not limited to. Hereinafter, a case where bonding is performed after a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film is formed on the supporting substrate 201 side will be described with reference to FIGS.
[0062]
As shown in FIG. 4C, after the first silicon oxide film 203B, the silicon nitride film or silicon nitride oxide film 204, and the second silicon oxide film 203A are sequentially formed on the surface of the support substrate 201 by the CVD method. The support substrate 201 and the single crystal silicon substrate 202A may be bonded together.
[0063]
In this case, it is desirable to previously form a silicon oxide film 203C on the surface of the single crystal silicon substrate 202A by thermal oxidation or a CVD method. Thus, any one of the support substrate 201 and the single crystal silicon substrate 202A is formed. With regard to the above, by making the outermost surface on the bonding side a silicon oxide film, the adhesion between the two substrates after bonding can be improved.
[0064]
In the case where the support substrate 201 is made of a quartz substrate or a glass substrate, the main component of the support substrate 201 is silicon oxide. Therefore, as shown in FIG. The silicon oxide film 203B may not be formed. After the silicon nitride film or the silicon nitride oxide film 204 and the second silicon oxide film 203A are sequentially formed on the support substrate 201 side by using a CVD method, the support substrate 201 and A single crystal silicon substrate 202A over which a silicon oxide film 203C is formed may be attached.
[0065]
Note that in the bonding pattern illustrated in FIGS. 4C and 4D, the silicon nitride film or the silicon nitride oxide film 204 is formed on the supporting substrate 201 side with respect to the bonding surface; Although it is possible to prevent the formed impurities from diffusing to the single crystal silicon layer 202 side, it is not possible to prevent the impurities adsorbed on the bonding surface from diffusing to the single crystal silicon layer 202 side. That is, the bonding pattern shown in FIGS. 4C and 4D is effective when a substrate containing impurities such as a quartz substrate or a glass substrate is used as the support substrate 201.
[0066]
[Element substrate]
Next, the structure of the element substrate 210 according to the embodiment of the present invention manufactured using the SOI substrate 200 having the above structure will be described with reference to FIG. An element substrate 210 shown in FIG. 5 is manufactured by forming a single crystal silicon layer 202 of an SOI substrate 200 in a predetermined pattern and then forming a TFT (transistor element) using the single crystal silicon layer. is there.
[0067]
5, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. In FIG. 5, reference numeral 220 denotes a TFT, and reference numeral 208 denotes a semiconductor layer formed from the single crystal silicon layer 202 of the SOI substrate 200 and constituting the TFT. Further, in FIG. 5, a support substrate 201, an insulating portion 205 including a first silicon oxide film 203 B and a silicon nitride film or a silicon nitride oxide film 204 and a second silicon oxide film 203 A, and a single crystal silicon layer 202 are formed. The formed semiconductor layer 208 is an SOI substrate.
[0068]
As shown in FIG. 5, a TFT 220 including a semiconductor layer 208, a gate insulating film 209, a gate electrode 211, a source electrode 215, a drain electrode 216, and an interlayer insulating film 212 is formed on the surface of the insulating portion 205.
[0069]
More specifically, a gate insulating film 209 is formed on the surface of the support substrate 201 on which the semiconductor layer 208 is formed, and a gate electrode 211 is formed on the surface of the gate insulating film 209. Further, an interlayer insulating film 212 is provided on the surface of the support substrate 201 on which the gate electrode 211 is formed.
[0070]
Contact holes 217 and 218 are formed in the interlayer insulating film 212 and the gate insulating film 209, respectively, which lead to a source region and a drain region (both not shown) formed in the semiconductor layer 208. An electrode 216 is formed so as to be electrically connected to a source region and a drain region of the semiconductor layer 208 through contact holes 217 and 218, respectively.
[0071]
Since the element substrate 210 of the present embodiment is formed using the SOI substrate 200 described above, impurities contained in the support substrate 201 and a bonding surface between the support substrate 201 and the single crystal silicon substrate 202A are formed. Since it is possible to completely prevent the adsorbed impurities from diffusing to the semiconductor layer 208 (TFT 220) side, deterioration of the characteristics of the TFT 220 can be prevented.
[0072]
[Electro-optical device]
Next, as an example of an electro-optical device according to an embodiment of the present invention, an active matrix liquid crystal device using a TFT (transistor element) as a switching element, which is preferably used in a projection display device such as a projector, is taken up. explain.
[0073]
Note that the liquid crystal device of this embodiment includes an element substrate manufactured using the SOI substrate of the present invention. That is, the basic structure of the element substrate constituting the electro-optical device according to the present embodiment is the first silicon oxide film, silicon nitride film, or oxynitride film on the surface of the substrate body corresponding to the support substrate, as described above. An insulating portion formed of a silicon film and a second silicon oxide film is provided, and a TFT including a semiconductor layer formed of a single crystal silicon layer is formed on the insulating portion.
[0074]
In a projection display device, light is usually incident from the substrate side (the surface of the liquid crystal device) that faces the element substrate, out of the two substrates that constitute the liquid crystal device. In order to prevent light leakage current from entering the channel region of the TFT formed on the surface, a structure in which a light shielding layer is provided on the side on which the TFT light is incident is generally used.
[0075]
However, even if a light-shielding layer is provided on the side on which the TFT light is incident, the light incident on the liquid crystal device may be reflected at the interface on the back surface of the element substrate and enter the channel portion of the TFT as incident light. This return light is a small percentage of the amount of light incident from the surface of the liquid crystal device, but in a device using a very powerful light source such as a projector, a light leakage current can be sufficiently generated. That is, the return light from the back surface of the element substrate affects the switching characteristics of the TFT and degrades the characteristics of the device.
[0076]
Therefore, in this embodiment, in order to prevent the deterioration of the TFT characteristics due to such return light, a light shielding film is provided in correspondence with each TFT (transistor element) immediately above the substrate body corresponding to the support substrate, Further, a first interlayer insulating film for electrically insulating a light shielding film made of metal or the like and a semiconductor layer constituting the TFT is provided. On the surface of the first interlayer insulating film, a first silicon oxide film, nitride An insulating portion formed of a silicon film, a silicon nitride oxide film, or a second silicon oxide film is provided.
[0077]
(Structure of electro-optical device)
First, the structure of an electro-optical device according to an embodiment of the present invention will be described by taking up a liquid crystal device.
[0078]
FIG. 6 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix that constitutes a pixel portion (display region) of the liquid crystal device. FIG. 7 is an enlarged plan view showing a plurality of pixel groups adjacent to each other on the element substrate on which data lines, scanning lines, pixel electrodes, light shielding films, and the like are formed. FIG. 8 is a cross-sectional view taken along the line AA ′ of FIG.
[0079]
6 to 8, reference numeral 30 denotes a TFT (transistor element), and reference numeral 1a denotes a semiconductor layer formed of a single crystal silicon layer and constituting the TFT. Moreover, in FIGS. 6-8, the same referential mark is attached | subjected about the same component as FIG. 1, FIG. 5, and description is abbreviate | omitted. 6 to 8, the scales are different for each layer and each member so that each layer and each member can be recognized on the drawings.
[0080]
In FIG. 6, a plurality of pixels formed in a matrix that forms a pixel portion of the liquid crystal device includes a plurality of pixel electrodes 9 a formed in a matrix and TFTs 30 for controlling the pixel electrodes 9 a, and an image signal is The supplied data line 6 a is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn to be written to the data line 6a may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. . Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the scanning line 3a in a pulse-sequential manner in this order at a predetermined timing. It is configured.
[0081]
The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,..., Sn supplied from the data line 6a is obtained by closing the switch of the TFT 30 as a switching element for a certain period. Write at a predetermined timing. Image signals S1, S2,..., Sn written to the liquid crystal via the pixel electrode 9a are held for a certain period with a counter electrode described later formed on a counter substrate described later.
[0082]
The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gradation display. In the normally white mode, incident light cannot pass through the liquid crystal part according to the applied voltage. In the normally black mode, incident light passes through the liquid crystal part according to the applied voltage. Light that has a contrast corresponding to the image signal is emitted from the liquid crystal device as a whole.
[0083]
Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. For example, the voltage of the pixel electrode 9a is held by the storage capacitor 70 for a time that is three orders of magnitude longer than the time when the voltage is applied to the data line. Thereby, the holding characteristics are further improved, and a liquid crystal device having a high contrast ratio can be realized. In the present embodiment, in particular, in order to form such a storage capacitor 70, a capacitor line 3b having a low resistance using the same layer as the scanning line or a conductive light-shielding film is provided as will be described later.
[0084]
Next, a planar structure in the pixel portion (display area) of the element substrate will be described in detail with reference to FIG. As shown in FIG. 7, a plurality of transparent pixel electrodes 9a (outlined by dotted line portions 9a ') are provided in a matrix in the pixel portion on the element substrate of the liquid crystal device. A data line 6a, a scanning line 3a, and a capacitor line 3b are provided along the vertical and horizontal boundaries of 9a. The data line 6a is electrically connected to a source region to be described later in the semiconductor layer 1a of the single crystal silicon layer through the contact hole 5, and the pixel electrode 9a is connected to the source layer in the semiconductor layer 1a through the contact hole 8. It is electrically connected to a drain region described later. Further, the scanning line 3a is arranged so as to face the channel region (the hatched region in the upper right in the drawing) of the semiconductor layer 1a, and the scanning line 3a functions as a gate electrode.
[0085]
The capacitance line 3b is formed from a main line portion (that is, a first region formed along the scanning line 3a in a plan view) extending substantially linearly along the scanning line 3a and a portion intersecting the data line 6a. And a protruding portion (that is, a second region extending along the data line 6 a when viewed in a plan view) that protrudes forward (upward in the drawing) along the data line 6 a.
[0086]
A plurality of first light-shielding films 11a are provided in a region indicated by oblique lines rising to the right in the drawing. More specifically, each of the first light-shielding films 11a is provided at a position where the TFT including the channel region of the semiconductor layer 1a is covered in the pixel portion as viewed from the substrate body side to be described later of the element substrate. A main line portion extending linearly along the scanning line 3a opposite to the main line portion 3b, and protruding from the portion intersecting the data line 6a to the adjacent step side (that is, downward in the figure) along the data line 6a And a protrusion. The tip of the downward projecting portion in each stage (pixel row) of the first light shielding film 11a overlaps the tip of the upward projecting portion of the capacitor line 3b in the next stage under the data line 6a. A contact hole 13 for electrically connecting the first light shielding film 11a and the capacitor line 3b to each other is provided at the overlapping portion. In other words, in the present embodiment, the first light shielding film 11a is electrically connected to the upstream or downstream capacitor line 3b through the contact hole 13.
[0087]
Next, a cross-sectional structure in the pixel portion of the liquid crystal device will be described with reference to FIG. As shown in FIG. 8, in the liquid crystal device, a liquid crystal layer (electro-optic material layer) 50 is sandwiched between an element substrate 10 and a counter substrate 20 disposed to face the element substrate 10.
[0088]
The element substrate 10 includes a substrate body (supporting substrate) 10A made of a light-transmitting substrate such as silicon, quartz, and glass, a pixel electrode 9a formed on the surface of the liquid crystal layer 50, and a pixel switching TFT (transistor element) 30. The counter substrate 20 is composed mainly of an alignment film 16, and the counter substrate 20 is a substrate body 20 A made of a transparent substrate such as transparent glass or quartz, and a counter electrode (common electrode) formed on the liquid crystal layer 50 side surface. 21 and the alignment film 22 are mainly constituted.
[0089]
A pixel electrode 9a is provided on the surface of the substrate body 10A of the element substrate 10 on the liquid crystal layer 50 side. On the liquid crystal layer 50 side, an alignment film 16 subjected to a predetermined alignment process such as a rubbing process is provided. A pixel switching TFT 30 for switching control of each pixel electrode 9a is provided at a position adjacent to each pixel electrode 9a. The pixel electrode 9a is made of a transparent conductive thin film such as ITO (indium tin oxide), and the alignment film 16 is made of an organic thin film such as polyimide.
[0090]
A first light shielding film 11 a is provided immediately above the substrate body 10 </ b> A of the element substrate 10 (on the surface on the liquid crystal layer 50 side) at a position corresponding to each pixel switching TFT 30. The first light shielding film 11a is preferably made of a simple metal, an alloy, a metal silicide, or the like containing at least one of Ti, Cr, W, Ta, Mo, and Pd, which are preferably opaque high melting point metals.
[0091]
In the present embodiment, since the first light shielding film 11a is formed on the element substrate 10 in this way, return light or the like from the element substrate 10 side is caused by the channel region 1a ′ or the LDD regions 1b, 1c of the pixel switching TFT 30. Can be prevented, and the characteristics of the pixel switching TFT 30 as a transistor element can be prevented from deteriorating due to generation of a photocurrent.
[0092]
In addition, the semiconductor layer 1a constituting the pixel switching TFT 30 is electrically insulated from the first light shielding film 11a over the entire surface of the substrate body 10A on the surface of the first light shielding film 11a. In order to flatten the surface of the substrate body 10A on which the light-shielding film 11a is formed, NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), etc. A first interlayer insulating film 12 made of a silicate glass film, a silicon nitride film, a silicon oxide film or the like is provided. On the surface of the first interlayer insulating film 12, a first silicon oxide film 203B, a silicon nitride film or An insulating portion 205 made of the silicon nitride oxide film 204 and the second silicon oxide film 203A is provided, and the insulating portion 20 Pixel switching TFT30 is provided on the surface. The TFT 30 is provided on the surface of the insulating portion 205 and includes a semiconductor layer 1a formed of a single crystal silicon layer. In this embodiment, the thickness of the silicon nitride film or the silicon nitride oxide film 204 is 100 nm or less in order to prevent the light transmittance from being lowered due to the presence of the silicon nitride film or the silicon nitride oxide film 204. It is desirable to be set to. The structure of the insulating portion 205 is the same as the structure of the insulating portion 205 of the SOI substrate 200 and the element substrate 210 except that the contact hole 13 is opened, and thus the description thereof is omitted.
[0093]
On the other hand, a counter electrode (common electrode) 21 is provided over the entire surface of the substrate body 20A of the counter substrate 20 on the liquid crystal layer 50 side, and a predetermined rubbing process or the like is provided on the liquid crystal layer 50 side. An alignment film 22 having been subjected to the alignment process is provided. The counter electrode 21 is made of a transparent conductive thin film such as ITO, and the alignment film 22 is made of an organic thin film such as polyimide.
[0094]
Further, as shown in FIG. 8, a second light-shielding film 23 is provided on the surface of the substrate body 20A on the liquid crystal layer 50 side in a region other than the opening region of each pixel portion. By providing the second light-shielding film 23 on the counter substrate 20 side in this way, incident light from the counter substrate 20 side causes the channel region 1a ′ of the semiconductor layer 1a of the pixel switching TFT 30 and the LDD (Lightly Doped Drain) regions 1b and 1c. Intrusion into the image can be prevented and contrast can be improved.
[0095]
Between the element substrate 10 and the counter substrate 20 that are configured in this manner and are arranged so that the pixel electrode 9a and the counter electrode 21 face each other, a sealant (not shown) formed between the peripheral portions of both substrates. The liquid crystal (electro-optical material) is enclosed in the space surrounded by () to form a liquid crystal layer (electro-optical material layer) 50.
[0096]
The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state by the alignment films 16 and 22 in a state where an electric field from the pixel electrode 9a is not applied.
[0097]
Further, the sealing material is made of an adhesive such as a photo-curing adhesive or a thermosetting adhesive for bonding the element substrate 10 and the counter substrate 20 at their peripheral portions, and the inside thereof is between the two substrates. A spacer such as glass fiber or glass bead is mixed in to set the distance to a predetermined value.
[0098]
In the present embodiment, the gate insulating film 2 is extended from a position facing the scanning line 3a and used as a dielectric film, the semiconductor film 1a is extended to form the first storage capacitor electrode 1f, and further opposed thereto. The storage capacitor 70 is configured by using a part of the capacitor line 3b to be a second storage capacitor electrode.
[0099]
More specifically, the high-concentration drain region 1e of the semiconductor layer 1a extends below the data line 6a and the scanning line 3a, and an insulating film is formed on the capacitor line 3b that extends along the data line 6a and the scanning line 3a. The first storage capacitor electrode (semiconductor layer) 1f is disposed so as to be opposed to each other. In particular, since the insulating film 2 as a dielectric of the storage capacitor 70 is nothing but the gate insulating film 2 of the TFT 30 formed on the single crystal silicon layer by high-temperature oxidation, it can be a thin and high withstand voltage insulating film. The storage capacitor 70 can be configured as a large storage capacitor with a relatively small area.
[0100]
Further, in the storage capacitor 70, as can be seen from FIGS. 7 and 8, the first light shielding film 11a is connected to the first storage capacitor electrode 1f on the opposite side of the capacitor line 3b as the second storage capacitor electrode. A storage capacitor is further provided by arranging it as a third storage capacitor electrode through the film 12 (see the storage capacitor 70 on the right side of FIG. 8). That is, in the present embodiment, a double storage capacitor structure in which storage capacitors are provided on both sides across the first storage capacitor electrode 1f is constructed, and the storage capacitor is further increased. By adopting such a structure, it is possible to improve a function of the liquid crystal device of the present embodiment that prevents flicker and burn-in in a display image.
[0101]
As a result, the space outside the opening area, that is, the area under the data line 6a and the area where the liquid crystal disclination occurs along the scanning line 3a (that is, the area where the capacitor line 3b is formed) is effectively used. Thus, the storage capacity of the pixel electrode 9a can be increased.
[0102]
In the present embodiment, the first light shielding film 11a (and the capacitor line 3b electrically connected thereto) is electrically connected to a constant potential source, and the first light shielding film 11a and the capacitor line 3b are Constant potential. Therefore, the potential fluctuation of the first light shielding film 11a does not adversely affect the pixel switching TFT 30 disposed opposite to the first light shielding film 11a. Further, the capacitor line 3 b can function well as the second storage capacitor electrode of the storage capacitor 70.
[0103]
Further, as shown in FIGS. 7 and 8, in the present embodiment, in addition to providing the first light shielding film 11a on the element substrate 10, the first light shielding film 11a is provided at the front stage or the rear stage via the contact hole 13. The capacitor line 3b is electrically connected. In the case of such a configuration, the data lines 6a are arranged along the edge of the opening region of the pixel portion as compared with the case where each first light shielding film 11a is electrically connected to the capacitor line of its own stage. There are few steps with respect to the other region where the capacitor line 3b and the first light shielding film 11a are formed. In this way, when there are few steps along the edge of the opening area of the pixel portion, the liquid crystal disclination (alignment failure) caused by the step can be reduced, so that the opening area of the pixel portion can be widened. Become.
[0104]
Further, in the first light shielding film 11a, the contact hole 13 is opened at the protruding portion protruding from the main line portion extending linearly as described above. Here, as the location of the contact hole 13 is closer to the edge, cracks are less likely to occur due to the fact that stress is more easily released from the edge. Therefore, the stress applied to the first light-shielding film 11a during the manufacturing process depends on how close to the tip of the protruding portion the contact hole 13 is opened (preferably, depending on how close the tip is to the tip of the margin). Is mitigated, cracks can be prevented more effectively, and the yield can be improved.
[0105]
The capacitor line 3b and the scanning line 3a are made of the same polysilicon film, the dielectric film of the storage capacitor 70 and the gate insulating film 2 of the TFT 30 are made of the same high-temperature oxide film, and the first storage capacitor electrode 1f and the channel formation region 1a, the source region 1d, the drain region 1e, and the like of the TFT 30 are made of the same semiconductor layer 1a. For this reason, the laminated structure formed on the surface of the substrate body 10A of the element substrate 10 can be simplified. Further, in the manufacturing method of the liquid crystal device described later, the capacitor line 3b and the scanning line 3a are simultaneously formed in the same thin film forming step. The dielectric film of the storage capacitor 70 and the gate insulating film 2 can be formed at the same time.
[0106]
The capacitor line 3b and the first light-shielding film 11a are electrically connected to each other reliably and with high reliability through the contact hole 13 opened in the first interlayer insulating film 12, Such a contact hole 13 may be opened for each pixel, or may be opened for each pixel group including a plurality of pixels.
[0107]
The contact hole 13 provided for each pixel or each pixel group is opened under the data line 6a when viewed from the counter substrate 20 side. For this reason, the contact hole 13 is out of the opening region of the pixel portion, and is provided in the portion of the first interlayer insulating film 12 where the TFT 30 and the first storage capacitor electrode 1f are not formed. Defects of the TFT 30 and other wirings due to the formation of the contact hole 13 can be prevented while effectively utilizing.
[0108]
In FIG. 3, the pixel switching TFT 30 has an LDD (Lightly Doped Drain) structure, and a channel region 1a ′ of a semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a and the scanning line 3a. Gate insulating film 2 that insulates scan line 3a from semiconductor layer 1a, data line 6a, low concentration source region (source side LDD region) 1b and low concentration drain region (drain side LDD region) 1c of semiconductor layer 1a, semiconductor layer 1a of high concentration source region 1d and high concentration drain region 1e.
[0109]
A corresponding one of the plurality of pixel electrodes 9a is connected to the high concentration drain region 1e. As will be described later, the source regions 1b and 1d and the drain regions 1c and 1e are doped with an N-type or P-type dopant having a predetermined concentration depending on whether an N-type or P-type channel is formed in the semiconductor layer 1a. It is formed by doping. N-channel TFTs have the advantage of high operating speed and are often used as pixel switching TFTs 30 that are pixel switching elements.
[0110]
The data line 6a is composed of a light-shielding thin film such as a metal film such as Al or an alloy film such as metal silicide. A second contact hole 5 leading to the high concentration source region 1d and a contact hole 8 leading to the high concentration drain region 1e are formed on the scanning line 3a, the gate insulating film 2 and the first interlayer insulating film 12, respectively. An interlayer insulating film 4 is formed. The data line 6a is electrically connected to the high concentration source region 1d through the contact hole 5 to the source region 1b.
[0111]
Furthermore, on the data line 6a and the second interlayer insulating film 4, a third interlayer insulating film 7 in which a contact hole 8 to the high concentration drain region 1e is formed is formed. The pixel electrode 9a is electrically connected to the high concentration drain region 1e through the contact hole 8 to the high concentration drain region 1e. The above-described pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 thus configured. The pixel electrode 9a and the high-concentration drain region 1e may be electrically connected by relaying the same Al film as the data line 6a or the same polysilicon film as the scanning line 3b.
[0112]
The pixel switching TFT 30 preferably has an LDD structure as described above, but may have an offset structure in which impurity ions are not implanted into the low concentration source region 1b and the low concentration drain region 1c. It may be a self-aligned TFT in which impurity ions are implanted at a high concentration using the (scanning line 3a) as a mask and high concentration source and drain regions are formed in a self-aligning manner.
[0113]
In addition, although a single gate structure in which only one gate electrode (scanning line 3a) of the pixel switching TFT 30 is arranged between the source-drain regions 1b and 1e is used, two or more gate electrodes are arranged between them. Also good. At this time, the same signal is applied to each gate electrode. If the TFT is configured with a double gate or a triple gate or more in this way, leakage current at the junction between the channel and the source-drain region can be prevented, and the current at the time of off can be reduced. If at least one of these gate electrodes has an LDD structure or an offset structure, the off-current can be further reduced and a stable switching element can be obtained.
[0114]
Here, in general, the single crystal silicon layer constituting the channel region 1a ′, the low concentration source region 1b, the low concentration drain region 1c, and the like of the semiconductor layer 1a has a photoelectric current due to the photoelectric conversion effect of silicon when light enters. However, in this embodiment, since the data line 6a is formed from a light-shielding metal thin film such as Al so as to cover the scanning line 3a from above, at least, the transistor characteristics of the pixel switching TFT 30 are deteriorated. Incident light can be prevented from entering the channel region 1a ′ and the LDD regions 1b and 1c of the semiconductor layer 1a.
[0115]
Further, as described above, since the first light shielding film 11a is provided below the pixel switching TFT 30 (on the substrate body 10A side), at least the channel region 1a ′ and the LDD regions 1b, 1c of the semiconductor layer 1a. It is possible to prevent the return light from entering.
[0116]
In the present embodiment, since the capacitor line 3b provided in the adjacent upstream or downstream pixel is connected to the first light shielding film 11a, the first light shielding is applied to the uppermost or lowermost pixel. The capacitor line 3b for supplying a constant potential to the film 11a is required. Therefore, it is preferable to provide one extra capacity line 3b with respect to the number of vertical pixels.
[0117]
(Method for manufacturing electro-optical device)
Next, a method for manufacturing a liquid crystal device having the above structure will be described.
First, a method for manufacturing the element substrate 10 will be described as a method for manufacturing the element substrate according to the embodiment of the present invention with reference to FIGS. 9 to 14 are process diagrams showing a part of the element substrate in each process in correspondence with the AA ′ cross section of FIG. 7, as in FIG. 10 to 14, the illustration of the insulating portion 205 is omitted to simplify the drawings.
[0118]
First, a substrate body (supporting substrate) 10A such as a silicon substrate, a quartz substrate, or a glass substrate is prepared. Where preferably N ₂ In an inert gas atmosphere such as (nitrogen), annealing is performed at a high temperature of about 850 to 1300 ° C., more preferably 1000 ° C., and pre-processing is performed so as to reduce distortion generated in the substrate body 10A in a high-temperature process performed later. Keep it. That is, the substrate main body 10A is heat-treated in advance at the same temperature or higher in accordance with the maximum temperature processed in the manufacturing process.
[0119]
As shown in FIG. 9A, a metal alloy film such as a metal such as Ti, Cr, W, Ta, Mo and Pd or a metal silicide is sputtered on the entire surface of the substrate body 10A thus processed. Thus, the light shielding layer 11 having a thickness of about 100 to 500 nm, preferably about 200 nm is formed.
[0120]
Next, as shown in FIG. 9B, a photoresist 207 corresponding to the pattern of the first light-shielding film 11a (see FIG. 7) is formed by photolithography.
[0121]
Next, as shown in FIG. 9C, the light shielding layer 11 is etched through the photoresist 207 to form the first light shielding film 11a having the pattern as shown in FIG.
[0122]
Next, as shown in FIG. 9D, on the first light shielding film 11a, TEOS (tetraethylorthosilicate) gas, TEB (tetraethylethyl First interlayer insulating film made of silicate glass film such as NSG, PSG, BSG, BPSG, silicon nitride film, silicon oxide film, etc. using boat rate) gas, TMOP (tetra-methyl-oxy-phosphate) gas, etc. 12 is formed. The film thickness of the first interlayer insulating film 12 is, for example, about 400 to 1000 nm, more preferably about 800 nm.
[0123]
Next, as shown in FIG. 9E, the entire surface of the first interlayer insulating film 12 is polished and planarized by a CMP (Chemical Mechanical Polishing) method or the like.
[0124]
Next, as shown in FIG. 9F, the substrate body 10A shown in FIG. 9E in which the first interlayer insulating film 12 having a flattened surface is formed, and the first silicon oxide film 203B on the surface. Bonding is performed with the single crystal silicon substrate 202A over which the insulating portion 205 including the silicon nitride film or the silicon nitride oxide film 204 and the second silicon oxide film 203A is formed. Next, as shown in FIG. 9G, most of the single crystal silicon substrate 202A is peeled off, leaving the thin single crystal silicon layer 202 on the surface of the substrate body 10A.
[0125]
Note that a method of forming the insulating portion 205 on the surface of the single crystal silicon substrate 202A, a method of bonding the single crystal silicon substrate 202A having the insulating portion 205 formed on the surface and the substrate body 10A, and a method of peeling the single crystal silicon substrate 202A Since the above has been described in detail in the method for manufacturing the SOI substrate 200, the description thereof will be omitted.
[0126]
Next, as shown in FIG. 9H, the single crystal silicon layer 202 is formed in a predetermined pattern through a photolithography process, an etching process, etc., so that the semiconductor layer 1a having a predetermined pattern as shown in FIG. Form. That is, in particular, in a region where the capacitor line 3b is formed under the data line 6a and a region where the capacitor line 3b is formed along the scanning line 3a, the first layer extending from the semiconductor layer 1a constituting the pixel switching TFT 30 is provided. One storage capacitor electrode 1f is formed.
[0127]
Next, as shown in FIG. 9I, the first storage capacitor electrode 1f together with the semiconductor layer 1a constituting the pixel switching TFT 30 is placed at a temperature of about 850 to 1300 ° C., preferably about 1000 ° C. for about 72 minutes. By thermal oxidation, a relatively thin thermal silicon oxide film having a thickness of about 60 nm is formed, and the gate insulating film 2 for forming a capacitor is formed together with the gate insulating film 2 of the pixel switching TFT 30. As a result, the thickness of the semiconductor layer 1a and the first storage capacitor electrode 1f is about 30 to 170 nm, and the thickness of the gate insulating film 2 is about 60 nm.
[0128]
Next, as shown in FIG. 10A, a resist film 301 is formed at a position corresponding to the N-channel semiconductor layer 1a, and a dopant 302 of a V-group element such as P is added to the P-channel semiconductor layer 1a at a low concentration. (For example, P ions are accelerated by 70 keV, 2 × 10 ¹¹ / Cm ² Dope).
[0129]
Next, as shown in FIG. 10B, a resist film is formed at a position corresponding to a P-channel semiconductor layer 1a (not shown), and a group 303 element dopant 303 such as B is formed on the N-channel semiconductor layer 1a. At a low concentration (for example, an acceleration voltage of 35 keV for B ions, 1 × 10 ¹² / Cm ² Dope).
[0130]
Next, as shown in FIG. 10C, a resist film 305 is formed on the surface of the substrate 10 excluding the end of the channel region 1a ′ of each semiconductor layer 1a for each P channel and N channel. About 1 to 10 times the dose shown in FIG. 10A, the dose of about 1 to 10 times that of the step shown in FIG. A dopant 306 of a group III element such as B is doped.
[0131]
Next, as shown in FIG. 10D, in order to reduce the resistance of the first storage capacitor electrode 1f formed by extending the semiconductor layer 1a, it corresponds to the scanning line 3a (gate electrode) on the surface of the substrate body 10A. A resist film 307 (wider than the scanning line 3a) is formed on the portion to be formed, and this is used as a mask to form a V group element dopant 308 such as P at a low concentration (for example, P ions at an acceleration voltage of 70 keV). 3 × 10 ¹⁴ / Cm ² Dope).
[0132]
Next, as shown in FIG. 11A, the contact hole 13 reaching the first light shielding film 11a is formed in the first interlayer insulating film 12 and the insulating portion 205 (not shown) by reactive etching, reactive ion beam etching, or the like. It is formed by dry etching or wet etching. At this time, opening the contact hole 13 or the like by anisotropic etching such as reactive etching or reactive ion beam etching has an advantage that the opening shape can be made substantially the same as the mask shape. However, if a hole is formed by combining dry etching and wet etching, these contact holes 13 and the like can be tapered, so that an advantage of preventing disconnection at the time of wiring connection can be obtained.
[0133]
Next, as shown in FIG. 11B, after depositing a polysilicon layer 3 with a thickness of about 350 nm by a low pressure CVD method or the like, phosphorus (P) is thermally diffused to make the polysilicon film 3 conductive. . Alternatively, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film 3 may be used. Thereby, the conductivity of the polysilicon layer 3 can be increased.
[0134]
Next, as shown in FIG. 11C, the capacitor line 3b is formed together with the scanning line 3a having a predetermined pattern as shown in FIG. 7 by a photolithography process, an etching process, etc. using a resist mask. Thereafter, the polysilicon remaining on the back surface of the substrate body 10A is removed by etching with the surface of the substrate body 10A covered with a resist film.
[0135]
Next, as shown in FIG. 11D, in order to form a P-channel LDD region in the semiconductor layer 1a, the position corresponding to the N-channel semiconductor layer 1a is covered with a resist film 309, and the scanning line 3a (gate First, a dopant 310 of a group III element such as B is used at a low concentration (for example, BF ₂ Ions are accelerated at 90 keV, 3 × 10 ¹³ / Cm ² The lightly doped source region 1b and the lightly doped drain region 1c of the P channel are formed.
[0136]
Subsequently, as shown in FIG. 11E, in order to form a P-channel high concentration source region 1d and a high concentration drain region 1e in the semiconductor layer 1a, a position corresponding to the N-channel semiconductor layer 1a is formed in a resist film. 309 and a state in which a resist layer is formed on the scanning line 3a corresponding to the P channel with a mask wider than the scanning line 3a (not shown), but also of a group III element such as B High concentration of dopant 311 (eg, BF ₂ Ions are accelerated at 90 keV, 2 × 10 ¹⁵ / Cm ² Dope).
[0137]
Next, as shown in FIG. 12A, in order to form an N-channel LDD region in the semiconductor layer 1a, a position corresponding to the P-channel semiconductor layer 1a is covered with a resist film (not shown) and scanned. Using the line 3a (gate electrode) as a diffusion mask, a dopant 60 of a group V element such as P is used at a low concentration (for example, P ions are accelerated by 70 keV, 6 × 10 6 ¹² / Cm ² N-channel lightly doped source region 1b and lightly doped drain region 1c are formed.
[0138]
Subsequently, as shown in FIG. 12B, in order to form the N channel high concentration source region 1d and the high concentration drain region 1e in the semiconductor layer 1a, a resist 62 is formed with a mask wider than the scanning line 3a. After forming on the scanning line 3a corresponding to the N channel, the dopant 61 of a V group element such as P is also used at a high concentration (for example, P ions are accelerated at a voltage of 70 keV, 4 × 10 4 ¹⁵ / Cm ² Dope).
[0139]
Next, as shown in FIG. 12C, for example, using a normal pressure or reduced pressure CVD method or TEOS gas so as to cover the capacitor line 3 b and the scan line 3 a together with the scan line 3 a in the pixel switching TFT 30, A second interlayer insulating film 4 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, or a silicon oxide film is formed. The film thickness of the second interlayer insulating film 4 is preferably about 500 to 1500 nm, and more preferably 800 nm.
[0140]
Thereafter, an annealing process at about 850 ° C. is performed for about 20 minutes in order to activate the high concentration source region 1d and the high concentration drain region 1e.
[0141]
Next, as shown in FIG. 12D, the contact hole 5 for the data line 31 is formed by dry etching such as reactive etching or reactive ion beam etching or by wet etching. Further, contact holes for connecting the scanning lines 3 a and the capacitor lines 3 b to wirings (not shown) are also formed in the second interlayer insulating film 4 by the same process as the contact holes 5.
[0142]
Next, as shown in FIG. 13A, a light-shielding low-resistance metal such as Al, metal silicide, or the like is formed on the second interlayer insulating film 4 as a metal film 6 by sputtering or the like. The film is deposited to a thickness of 700 nm, preferably about 350 nm. Further, as shown in FIG. 13B, the data line 6a is formed by a photolithography process, an etching process, or the like.
[0143]
Next, as shown in FIG. 13C, a silicate glass film such as NSG, PSG, BSG, or BPSG is used to cover the data line 6a by using, for example, normal pressure or low pressure CVD or TEOS gas. Then, a third interlayer insulating film 7 made of a silicon nitride film, a silicon oxide film or the like is formed. The film thickness of the third interlayer insulating film 7 is preferably about 500 to 1500 nm, and more preferably 800 nm.
[0144]
Next, as shown in FIG. 14A, in the pixel switching TFT 30, the contact hole 8 for electrically connecting the pixel electrode 9a and the high concentration drain region 1e is formed by reactive etching, reactive ion beam. It is formed by dry etching such as etching.
[0145]
Next, as shown in FIG. 14B, a transparent conductive thin film 9 such as ITO is deposited on the third interlayer insulating film 7 to a thickness of about 50 to 200 nm by sputtering or the like. As shown in FIG. 14C, the pixel electrode 9a is formed by a photolithography process, an etching process, or the like. In the case where the liquid crystal device of the present embodiment is a reflective liquid crystal device, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.
[0146]
Subsequently, after a polyimide alignment film coating solution is applied onto the pixel electrode 9a, the alignment film 16 (see FIG. 8) is formed by performing a rubbing process in a predetermined direction so as to have a predetermined pretilt angle. ) Is formed.
[0147]
The element substrate 10 is manufactured as described above.
[0148]
According to the element substrate manufacturing method of the present embodiment, a silicon nitride film or silicon nitride oxide is obtained by bonding a single crystal silicon substrate 202A having a silicon nitride film or silicon nitride oxide film 204 formed on the surface thereof and the substrate body 10A. Since the film 204 can be positioned closer to the semiconductor layer 1a (TFT 30) than the bonding surface of the substrate body 10A and the single crystal silicon substrate 202A, impurities contained in the substrate body 10A, and the substrate body 10A and the single crystal It is possible to completely prevent the impurities adsorbed on the bonding surface with the silicon substrate 202A from diffusing to the semiconductor layer 1a (TFT 30) side.
[0149]
In addition, the element substrate 10 manufactured by the element substrate manufacturing method of the present embodiment has impurities contained in the substrate body 10A and impurities adsorbed on the bonding surface of the substrate body 10A and the single crystal silicon substrate 202A as a semiconductor. Since the diffusion to the layer 1a (TFT 30) side can be completely prevented, the deterioration of the characteristics of the TFT 30 can be prevented.
[0150]
Next, a method for manufacturing the counter substrate 20 and a method for manufacturing a liquid crystal device from the element substrate 10 and the counter substrate 20 will be described.
[0151]
For the counter substrate 20 shown in FIG. 8, a light transmissive substrate such as a glass substrate is prepared as the substrate body 20A, and the second light shielding film 23 and a second light shielding as a peripheral parting described later are formed on the surface of the substrate body 20A. A film is formed. The second light-shielding film 23 and the second light-shielding film as a peripheral parting described later are formed through a photolithography process and an etching process after sputtering a metal material such as Cr, Ni, and Al. These second light-shielding films may be formed of a material such as resin black in which carbon, Ti, or the like is dispersed in a photoresist in addition to the above metal material.
[0152]
Thereafter, a counter electrode 21 is formed by depositing a transparent conductive thin film such as ITO on the entire surface of the substrate main body 20A to a thickness of about 50 to 200 nm by sputtering or the like. Further, after an alignment film coating solution such as polyimide is applied to the entire surface of the counter electrode 21, the alignment film 22 (see FIG. 5) is applied by rubbing in a predetermined direction so as to have a predetermined pretilt angle. 3). The counter substrate 20 is manufactured as described above.
[0153]
Finally, the element substrate 10 and the counter substrate 20 manufactured as described above are bonded to each other with a sealing material so that the alignment films 16 and 22 face each other, and a method such as a vacuum suction method is used. A liquid crystal device having the above-described structure is manufactured by sucking, for example, liquid crystal formed by mixing a plurality of types of nematic liquid crystals into the space to form a liquid crystal layer 50 having a predetermined thickness.
[0154]
(Overall configuration of liquid crystal device)
The overall configuration of the liquid crystal device of the present embodiment configured as described above will be described with reference to FIGS. 15 and 16. 15 is a plan view of the element substrate 10 viewed from the counter substrate 20 side, and FIG. 16 is a cross-sectional view taken along the line HH ′ of FIG. 15 including the counter substrate 20.
[0155]
In FIG. 15, a sealing material 52 is provided on the surface of the element substrate 10 along the edge thereof. As shown in FIG. 16, the counter substrate has substantially the same outline as the sealing material 52 shown in FIG. 20 is fixed to the element substrate 10 by the sealing material 52.
[0156]
As shown in FIG. 15, on the surface of the counter substrate 20, a second light shielding film 53 as a peripheral parting made of the same or different material as the second light shielding film 23 is provided in parallel with the inside of the sealing material 52. ing.
[0157]
In the element substrate 10, a data line driving circuit 101 and a mounting terminal 102 are provided along one side of the element substrate 10 in a region outside the sealing material 52, and the scanning line driving circuit 104 is provided on this one side. It is provided along two adjacent sides. Needless to say, when the delay of the scanning signal supplied to the scanning line 3a is not a problem, the scanning line driving circuit 104 may be provided on only one side.
[0158]
In addition, the data line driving circuit 101 may be arranged on both sides along the side of the display region (pixel portion). For example, the odd-numbered data lines 6a are supplied with image signals from the data line driving circuit arranged along one side of the display area, and the even-numbered data lines 6a are arranged along the opposite side of the display area. An image signal may be supplied from the provided data line driving circuit. If the data lines 6a are driven in a comb-like shape in this way, the area occupied by the data line driving circuit can be expanded, so that a complicated circuit can be configured.
[0159]
Further, a plurality of wirings 105 are provided on the remaining side of the element substrate 10 to connect between the scanning line driving circuits 104 provided on both sides of the display area. Further, the second light shielding film 53 as a part of the periphery is provided. A precharge circuit may be provided hidden underneath. In addition, at least one corner portion between the element substrate 10 and the counter substrate 20 is provided with a conductive material 106 for electrical conduction between the element substrate 10 and the counter substrate 20.
[0160]
Further, on the surface of the element substrate 10, an inspection circuit for inspecting the quality, defects, etc. of the liquid crystal device during the manufacturing or at the time of shipment may be formed. Further, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the surface of the element substrate 10, for example, a peripheral area of the element substrate 10 is mounted on a driving LSI mounted on a TAB (tape automated bonding substrate). You may make it connect electrically and mechanically through the anisotropic conductive film provided in this.
[0161]
Further, for example, the TN (twisted nematic) mode, the STN (super TN) mode, and the D-STN (dual scan-STN) are respectively provided on the side on which the light of the counter substrate 20 enters and the side on which the light of the element substrate 10 exits. A polarizing film, a retardation film, a polarizing means, and the like are arranged in a predetermined direction according to an operation mode such as a mode, and a normally white mode / normally black mode.
[0162]
When the liquid crystal device of this embodiment is applied to a color liquid crystal projector (projection display device), three liquid crystal devices are used as RGB light valves, and each panel is for RGB color separation. Each color light separated through the dichroic mirror is incident as projection light. Therefore, in that case, as shown in the above embodiment, the counter substrate 20 is not provided with a color filter.
[0163]
However, even if an RGB color filter is formed together with the protective film in a predetermined region facing the pixel electrode 9a on which the second light shielding film 23 is not formed on the surface of the counter substrate 20 on the liquid crystal layer 50 side of the substrate body 20A. Good. With such a configuration, the liquid crystal device of the above embodiment can be applied to a color liquid crystal device such as a direct-view type or a reflective type color liquid crystal television other than the liquid crystal projector.
[0164]
Furthermore, a micro lens may be formed on the surface of the counter substrate 20 so as to correspond to one pixel. In this way, a bright liquid crystal device can be realized by improving the collection efficiency of incident light. Furthermore, a dichroic filter that creates RGB colors using light interference may be formed by depositing multiple layers of interference layers having different refractive indexes on the surface of the counter substrate 20. According to this counter substrate with a dichroic filter, a brighter color liquid crystal device can be realized.
[0165]
In the liquid crystal device according to the present embodiment, incident light is incident from the counter substrate 20 side. However, since the first light shielding film 11a is provided on the element substrate 10, incident light is incident from the element substrate 10 side. Then, the light may be emitted from the counter substrate 20 side. That is, even when the liquid crystal device is attached to the liquid crystal projector in this way, it is possible to prevent light from entering the channel region 1a ′ and the LDD regions 1b and 1c of the semiconductor layer 1a and display a high-quality image. Is possible.
[0166]
Further, since the liquid crystal device of the present embodiment includes the element substrate 10 manufactured by the element substrate manufacturing method of the present embodiment, impurities contained in the substrate body 10A, and the substrate body 10A and the single crystal Impurities adsorbed on the bonding surface with the silicon substrate 202A can be completely prevented from diffusing to the semiconductor layer 1a (TFT 30) side, so that deterioration of the characteristics of the TFT (transistor element) 30 can be prevented. , The performance will be excellent.
[0167]
(Electronics)
As an example of an electronic apparatus using the liquid crystal device (electro-optical device) of the above embodiment, a configuration of a projection display device will be described with reference to FIG.
[0168]
In FIG. 17, a projection type display device 1100 is provided with three liquid crystal devices of the above-described embodiment, and is a schematic configuration diagram of an optical system of a projection type liquid crystal device used as RGB liquid crystal devices 962R, 962G, and 962B, respectively. Show.
[0169]
A light source device 920 and a uniform illumination optical system 923 are employed in the optical system of the projection display device of this example. The projection display device includes a color separation optical system 924 as color separation means for separating the light beam W emitted from the uniform illumination optical system 923 into red (R), green (G), and blue (B); The three light valves 925R, 925G, and 925B as modulation means for modulating the color light beams R, G, and B, and the color synthesis prism 910 as color synthesis means for recombining the modulated color light beams are combined. A projection lens unit 906 is provided as projection means for enlarging and projecting the light beam onto the surface of the projection surface 100. Further, a light guide system 927 for guiding the blue light beam B to the corresponding light valve 925B is also provided.
[0170]
The uniform illumination optical system 923 includes two lens plates 921 and 922 and a reflection mirror 931, and the two lens plates 921 and 922 are arranged to be orthogonal to each other with the reflection mirror 931 interposed therebetween. The two lens plates 921 and 922 of the uniform illumination optical system 923 each include a plurality of rectangular lenses arranged in a matrix. The light beam emitted from the light source device 920 is divided into a plurality of partial light beams by the rectangular lens of the first lens plate 921. These partial light beams are superimposed in the vicinity of the three light valves 925R, 925G, and 925B by the rectangular lens of the second lens plate 922. Therefore, by using the uniform illumination optical system 923, even when the light source device 920 has a non-uniform illuminance distribution within the cross section of the emitted light beam, the three light valves 925R, 925G, and 925B can be uniformly illuminated. It can be illuminated.
[0171]
Each color separation optical system 924 includes a blue-green reflecting dichroic mirror 941, a green reflecting dichroic mirror 942, and a reflecting mirror 943. First, in the blue-green reflecting dichroic mirror 941, the blue light beam B and the green light beam G included in the light beam W are reflected at right angles and travel toward the green reflecting dichroic mirror 942. The red light beam R passes through the mirror 941, is reflected at a right angle by the rear reflecting mirror 943, and is emitted from the emission unit 944 of the red light beam R to the prism unit 910 side.
[0172]
Next, in the green reflection dichroic mirror 942, only the green light beam G out of the blue and green light beams B and G reflected by the blue-green reflection dichroic mirror 941 is reflected at right angles, and the green light beam G is emitted from the emitting portion 945. The light is emitted to the side of the combining optical system.
[0173]
The blue light beam B that has passed through the green reflecting dichroic mirror 942 is emitted from the emission part 946 of the blue light beam B to the light guide system 927 side. In this example, the distances from the light beam W emission part of the uniform illumination optical element to the color light emission parts 944, 945, and 946 in the color separation optical system 924 are set to be substantially equal.
[0174]
Condensing lenses 951 and 952 are disposed on the emission side of the emission portions 944 and 945 for the red and green light beams R and G of the color separation optical system 924, respectively. Therefore, the red and green light beams R and G emitted from the respective emission portions are incident on these condenser lenses 951 and 952 and are collimated.
[0175]
The collimated red and green light beams R and G are incident on the light valves 925R and 925G and modulated, and image information corresponding to each color light is added. That is, these liquid crystal devices are subjected to switching control according to image information by a driving unit (not shown), thereby modulating each color light passing therethrough. On the other hand, the blue light beam B is guided to the corresponding light valve 925B via the light guide system 927, where it is similarly modulated according to the image information. The light valves 925R, 925G, and 925B in this example further include incident-side polarization means 960R, 960G, and 960B, emission-side polarization means 961R, 961G, and 961B, and liquid crystal devices 962R and 962G disposed therebetween. , 962B.
[0176]
The light guide system 927 includes a condensing lens 954 arranged on the emission side of the emission part 946 of the blue light beam B, an incident-side reflection mirror 971, an emission-side reflection mirror 972, and an intermediate lens arranged between these reflection mirrors. 973 and a condenser lens 953 disposed on the front side of the light valve 925B. The blue light beam B emitted from the condenser lens 946 is guided to the liquid crystal device 962B via the light guide system 927 and modulated. The optical path length of each color light beam, that is, the distance from the emission part of the light beam W to each liquid crystal device 962R, 962G, 962B is the longest for the blue light beam B, and therefore, the light amount loss of the blue light beam is the largest. However, the light loss can be suppressed by interposing the light guide system 927.
[0177]
The color light beams R, G, and B modulated through the light valves 925R, 925G, and 925B are incident on the color synthesis prism 910 and synthesized there. Then, the light synthesized by the color synthesis prism 910 is enlarged and projected onto the surface of the projection surface 100 at a predetermined position via the projection lens unit 906.
[0178]
Since the projection display device 1100 having the above-described structure includes the liquid crystal device according to the above-described embodiment, it is possible to prevent deterioration of characteristics of the TFT (transistor element) and to have excellent performance.
[0179]
【The invention's effect】
As described above, according to the present invention, since the insulating portion including at least the silicon nitride film or the silicon nitride oxide film is provided between the support substrate and the single crystal silicon layer, it is contained in the support substrate. An SOI substrate capable of completely preventing impurities from diffusing to the single crystal silicon layer side can be provided.
[0180]
In addition, by forming a silicon nitride film or a silicon nitride oxide film on the single crystal silicon substrate side, the single crystal silicon substrate and the support substrate are bonded to each other, whereby impurities contained in the support substrate, and the support substrate and the single crystal It is possible to provide an SOI substrate manufacturing method capable of completely preventing impurities adsorbed on a bonding surface with a silicon substrate from diffusing to the single crystal silicon layer side.
[0181]
In addition, an element substrate can be manufactured using the SOI substrate of the present invention, and the element substrate of the present invention is adsorbed on the impurities contained in the support substrate or the bonding surface of the support substrate and the single crystal silicon substrate. The influence of the impurities on the transistor element can be prevented, and the deterioration of the characteristics of the transistor element can be prevented.
[0182]
In addition, by including the element substrate of the present invention, it is possible to prevent deterioration of characteristics of the transistor element, and it is possible to provide an electro-optical device and an electronic apparatus with excellent performance.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing the structure of an SOI substrate according to an embodiment of the present invention.
FIGS. 2A to 2E are process diagrams showing a method for manufacturing an SOI substrate according to an embodiment of the present invention.
FIGS. 3A to 3C are process diagrams showing a method for manufacturing an SOI substrate according to an embodiment of the present invention.
FIGS. 4A to 4D are diagrams showing a bonding pattern of a support substrate and a single crystal silicon substrate in an SOI substrate manufacturing method according to an embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a structure of an element substrate according to an embodiment of the present invention.
FIG. 6 is an equivalent circuit diagram of various elements, wirings, and the like constituting the pixel unit in the electro-optical device according to the embodiment of the invention.
FIG. 7 is a plan view of a plurality of pixel groups adjacent to each other in the element substrate in the electro-optical device according to the embodiment of the invention.
FIG. 8 is a cross-sectional view taken along the line AA ′ in FIG.
FIGS. 9A to 9I are process diagrams showing a method for manufacturing an element substrate according to an embodiment of the present invention.
FIGS. 10A to 10D are process diagrams showing a method for manufacturing an element substrate according to an embodiment of the present invention.
FIGS. 11A to 11E are process diagrams showing a method for manufacturing an element substrate according to an embodiment of the present invention.
FIGS. 12A to 12D are process diagrams showing a method for manufacturing an element substrate according to an embodiment of the present invention.
13A to 13C are process diagrams showing a method for manufacturing an element substrate according to an embodiment of the present invention.
FIGS. 14A to 14C are process diagrams showing a method for manufacturing an element substrate according to an embodiment of the present invention.
FIG. 15 is a plan view of an element substrate of an electro-optical device according to an embodiment of the present invention, as viewed from the counter substrate side, together with each component formed thereon.
FIG. 16 is a cross-sectional view taken along the line HH ′ of FIG.
FIG. 17 is a configuration diagram of a projection display device that is an example of an electronic apparatus using the electro-optical device according to the embodiment of the invention.
18A and 18B are process diagrams showing a conventional method for manufacturing an SOI substrate.
[Explanation of symbols]
200 ... SOI substrate
201 ... support substrate
202 ... single crystal silicon layer
202A ... single crystal silicon substrate
203B ... first silicon oxide film
203A ... Second silicon oxide film
204... Silicon nitride film or silicon nitride oxide film
205 ... Insulating part
210: Element substrate
220 ... TFT (transistor element)
208 ... Semiconductor layer
1a ... Semiconductor layer
1a '... channel region
1b: low concentration source region (source side LDD region)
1c: Low concentration drain region (drain side LDD region)
1d ... High concentration source region
1e ... High concentration drain region
10: Element substrate
10A ... Substrate body (support substrate)
20 ... Counter substrate
20A ... Board body
11a ... 1st light shielding film
12 ... 1st interlayer insulation film
30 ... TFT for pixel switching (transistor element)
50 ... Liquid crystal layer (electro-optic material layer)

Claims (2)

Forming a silicon oxide film on the surface of the single crystal silicon substrate by thermally oxidizing the surface of the single crystal silicon substrate;
The surface of the single crystal silicon substrate on which the silicon oxide film is formed is nitrided or oxynitrided with dinitrogen monoxide or nitric oxide, so that a silicon nitride film or nitride is formed on the single crystal silicon substrate side of the silicon oxide film. Forming a silicon oxide film;
Forming a light shielding film at a position corresponding to a transistor element to be formed later on the surface of the support substrate;
Forming a second silicon oxide film on the surface of the support substrate including the light shielding film;
Planarizing the surface of the second silicon oxide film;
Using the interface between the surface of the silicon oxide film formed on the single crystal silicon substrate and the surface of the second silicon oxide film formed on the support substrate and planarized as a bonding surface, the single crystal silicon substrate And a step of bonding the support substrate and
Thinning the single crystal silicon substrate bonded to the support substrate ;
Forming a semiconductor layer constituting a transistor element by a single crystal silicon layer comprising the thin single crystal silicon substrate;
A method for manufacturing an element substrate for an electro-optical device. Forming a first silicon oxide film on the surface of the single crystal silicon substrate by thermally oxidizing the surface of the single crystal silicon substrate;
The surface of the single crystal silicon substrate on which the first silicon oxide film is formed is nitrided or oxynitrided with dinitrogen monoxide or nitric oxide, whereby the first silicon oxide film is on the single crystal silicon substrate side. Forming a silicon nitride film or a silicon nitride oxide film on the substrate;
By thermally oxidizing the surface of the single crystal silicon substrate on which the silicon nitride film or the silicon nitride oxide film is formed, a second silicon oxide film is formed on the single crystal silicon substrate side of the silicon nitride film or the silicon nitride oxide film. Forming, and
Forming a light shielding film at a position corresponding to a transistor element to be formed later on the surface of the support substrate;
Forming a third silicon oxide film on the surface of the support substrate including the light shielding film;
Planarizing the surface of the third silicon oxide film;
The interface between the surface of the first silicon oxide film formed on the single crystal silicon substrate and the surface of the third silicon oxide film formed flat on the support substrate is used as a bonding surface. Bonding the crystalline silicon substrate and the support substrate;
Thinning the single crystal silicon substrate bonded to the support substrate ;
Forming a semiconductor layer constituting a transistor element by a single crystal silicon layer comprising the thin single crystal silicon substrate;
A method for manufacturing an element substrate for an electro-optical device.

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