JP2002170942A - Soi substrate, manufacturing method thereof, element substrate, manufacturing method thereof, electrooptical device, electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an SOI substrate and its manufacturing method which perfectly prevents impurities contained in a support substrate or adsorbed to a cladding surface of the substrate support with a single crystal silicon substrate from diffusing to a single crystal silicon layer. SOLUTION: The SOI substrate 200 is manufactured by steps of thermally oxidating a single crystal silicon substrate 202A surface to form a first silicon oxide film 203B, nitriding or oxynitriding the single crystal silicon substrate 202A surface to form a silicon nitride film or a silicon oxynitride film 204, thermally oxidating the single crystal silicon substrate 202A surface to form a second silicon oxide film 203A, cladding the support substrate 201 with the single crystal silicon substrate 202A through a cladding surface using the first silicon oxide film 203B surface, and finally thinning the single crystal silicon substrate 202A clad to the support substrate 201 to form a single crystal silicon layer 202.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SOI substrate having a single crystal silicon layer on one surface of a supporting substrate,
The present invention relates to an element substrate provided with an OI substrate, an electro-optical device and an electronic device provided with the element substrate, a method for manufacturing an SOI substrate, and a method for manufacturing an element substrate.

[0002]

2. Description of the Related Art Semiconductor technology in which a single-crystal silicon thin film is formed on an insulating substrate and a semiconductor device is formed using the single-crystal silicon thin film is known as SOI (Silicon On).
Insulator technology is widely used because of its advantages such as higher speed, lower power consumption, and higher integration of devices.

As one of the SOI techniques, there is a technique for manufacturing an SOI substrate by bonding a single crystal silicon substrate. Based on FIG. 18, a conventional method and structure for manufacturing an SOI substrate will be briefly described.

First, as shown in FIG. 18A, a single crystal silicon substrate 1003 having a silicon oxide film 1002 formed by oxidizing a surface on a bonding side in advance on a surface of a support substrate 1001 is formed by utilizing a hydrogen bonding force. After increasing the bonding strength by heat treatment, FIG.
As shown in (b), the single-crystal silicon substrate 1003 is thinned by grinding, polishing, etching or the like to form a single-crystal silicon thin film 1004.
An SOI substrate having a structure in which a silicon oxide film 1002 and a single crystal silicon layer 1004 are sequentially formed on the surface of the substrate 1 is manufactured.

According to the above-described method for manufacturing an SOI substrate, a single-crystal silicon thin film 1004 having excellent crystallinity can be formed in order to make the single-crystal silicon substrate 1003 thin, so that a high-performance device is manufactured. be able to.

[0006] The SOI substrate formed by such a bonding method is used for fabricating various devices similarly to a normal bulk semiconductor substrate (semiconductor integrated circuit). It is possible to use a substrate made of any material.

That is, a transparent (light-transmitting) quartz substrate, a glass substrate, or the like can be used as a support substrate in addition to an ordinary silicon substrate. Therefore, for example, by forming a single-crystal silicon thin film on a substrate having light transmittance, a single-crystal silicon film having excellent crystallinity can be used in a device requiring light transmittance, such as a transmission type liquid crystal display device. Using the thin film, a high-performance transistor element such as a MOSFET for driving a liquid crystal can be formed.

[0008]

When an SOI substrate is manufactured using a quartz substrate or a glass substrate as a supporting substrate and a transistor element is formed on the surface thereof, impurities contained in the supporting substrate are transmitted through the silicon oxide film. However, there is a possibility that the diffusion may occur to the transistor element side and deteriorate the characteristics of the element.

Further, regardless of the type of the supporting substrate, the SOI
In the substrate manufacturing process, when the supporting substrate and the single crystal silicon substrate are bonded to each other, Na ⁺ , K ⁺ , C
l ^- may be adsorbed to impurities adhered surface, such as, in this case, SOI substrate obtained has a supporting substrate as the above impurities are sandwiched between the silicon oxide film.

When a transistor element is formed on the surface of an SOI substrate having such a structure, the impurities sandwiched between the supporting substrate and the silicon oxide film pass through the silicon oxide film, and the , And may degrade the characteristics of the device.

Conventionally, when a supporting substrate and a single crystal silicon substrate are bonded to each other, a dust filter is used to prevent impurities from adsorbing to the supporting substrate from the atmosphere. Even in such a case, at present, it is not possible to completely prevent impurities from adsorbing to the bonding surface from the atmosphere.

Accordingly, the present invention has been made to solve the above-mentioned problems, and has been made in consideration of an impurity contained in a support substrate.
Alternatively, it is an object to provide an SOI substrate capable of completely preventing impurities adsorbed on a bonding surface of a supporting substrate and a single crystal silicon substrate from diffusing to the single crystal silicon layer side, and a method for manufacturing the SOI substrate.

An element substrate capable of completely preventing an impurity contained in a support substrate or an impurity adsorbed on a bonding surface between a support substrate and a single crystal silicon substrate from affecting a transistor element, and a method of manufacturing the same. It is intended to provide.

It is still another object of the present invention to provide an electro-optical device and an electronic apparatus having the element substrate, capable of preventing deterioration of the characteristics of the transistor element, and having excellent performance.

[0015]

Means for Solving the Problems In order to solve the above problems, the present inventors have made various studies and as a result, have found that a silicon nitride film or a silicon oxynitride film can be used simply as an impurity or a support substrate contained in a support substrate. The inventor found that impurities adsorbed on the surface bonded to the crystalline silicon substrate were not transmitted, and focused on this point, and completed the present invention.

An SOI substrate according to the present invention is an SOI substrate having a single-crystal silicon layer on one surface of a support substrate, wherein a single-layer insulating film is provided between the support substrate and the single-crystal silicon layer. Alternatively, an insulating portion having a stacked structure is provided, and the insulating portion includes at least a silicon nitride film or a silicon nitride oxide film.

As described above, by providing an insulating portion having at least a silicon nitride film or a silicon nitride oxide film between the supporting substrate and the single crystal silicon layer, impurities contained in the supporting substrate can be nitrided. Since it does not pass through the silicon film or the silicon nitride oxide film, it is possible to completely prevent impurities contained in the supporting substrate from diffusing to the single crystal silicon layer side.

In the SOI substrate of the present invention, a specific example of the insulating film other than the silicon nitride film or the silicon nitride oxide film forming the insulating portion is a silicon oxide film.

The SOI substrate having the above structure according to the present invention includes a step of forming a silicon nitride film or a silicon nitride oxide film on one surface of either a single crystal silicon substrate or a supporting substrate; Forming a silicon oxide film on the surface of the silicon oxide film;
Bonding the single crystal silicon substrate and the support substrate with the surface of the silicon oxide film as a bonding surface; forming a single crystal silicon layer by thinning the single crystal silicon substrate bonded to the support substrate And a method of manufacturing an SOI substrate according to the present invention.

Further, as described above, a silicon nitride film or a silicon nitride oxide film is formed on one surface of either the single crystal silicon substrate or the support substrate, and a silicon oxide film is further formed on the surface, and then the oxide film is formed. By bonding the single crystal silicon substrate and the supporting substrate with the surface of the silicon film as a bonding surface, adhesion between the single crystal silicon substrate and the supporting substrate can be improved. Note that the order of forming the silicon nitride film, the silicon nitride oxide film, and the silicon oxide film may be any order.

In the method for manufacturing an SOI substrate according to the present invention, it is preferable that a silicon nitride film or a silicon nitride oxide film is formed on the surface of the single crystal silicon substrate, and the single crystal silicon nitride film or the silicon nitride oxide film is formed. By bonding the silicon substrate and the supporting substrate, the silicon nitride film or the silicon nitride oxide film can be positioned closer to the single crystal silicon layer than the bonding surface between the supporting substrate and the single crystal silicon substrate. It is possible to completely prevent not only the contained impurities but also the impurities adsorbed on the bonding surface from diffusing to the single crystal silicon layer side.

A silicon nitride film, a silicon nitride oxide film, or a silicon oxide film may be formed on the surface of the single crystal silicon substrate or the support substrate by a CVD method or the like. Since a silicon nitride film, a silicon nitride oxide film, or a silicon oxide film having a uniform thickness can be formed and the adhesion between the single crystal silicon substrate and the silicon nitride film or the silicon nitride oxide film can be improved, After a silicon oxide film is formed by thermally oxidizing the surface of the silicon substrate, the surface of the single crystal silicon substrate on which the silicon oxide film is formed is nitrided or oxynitrided with nitrous oxide or nitric oxide. A silicon nitride film or a silicon nitride oxide film is formed on the silicon oxide film on the side of the single crystal silicon substrate. Then, the surface of the single crystal silicon substrate on which the silicon nitride film or the silicon nitride oxide film is formed is reheat-oxidized, so that the second silicon oxide film is formed on the silicon nitride film or the silicon nitride oxide film on the single crystal silicon substrate side. It is desirable to form a film.

In other words, in this case, the method of manufacturing an SOI substrate according to the present invention includes a step of forming a silicon oxide film on the surface of a single crystal silicon substrate, and a step of forming a silicon nitride film or A step of forming a silicon nitride oxide film, a step of bonding the single crystal silicon substrate to a support substrate with the surface of the silicon oxide film as a bonding surface, and a step of bonding the single crystal silicon substrate bonded to the support substrate. And forming a thin film.

In the case where a second silicon oxide film is formed on the surface of a single crystal silicon substrate on which a silicon nitride film or a silicon nitride oxide film is formed, the method for manufacturing an SOI substrate according to the present invention comprises: Forming a first silicon oxide film on the first silicon oxide film, forming a silicon nitride film or a silicon nitride oxide film on the single crystal silicon substrate side of the first silicon oxide film, Forming a second silicon oxide film on the single crystal silicon substrate side of a film, and bonding the single crystal silicon substrate and the support substrate with the surface of the first silicon oxide film as a bonding surface; Thinning the single-crystal silicon substrate bonded to the support substrate.

By forming a silicon oxide film, a silicon nitride film, or a silicon oxynitride film as described above and forming a flat film having a uniform thickness, voids are formed on the bonding surface between the supporting substrate and the single crystal silicon substrate. Generation can be prevented, the bonding strength can be improved, and the silicon nitride film or the silicon oxynitride film has an effect of reducing the stress of bonding. In the case of forming, since it is possible to prevent the occurrence of film peeling and the like,
Product yield can be improved.

Further, according to the above-described manufacturing method, the insulating portion is formed by laminating the silicon nitride film or the silicon nitride oxide film and the silicon oxide film formed on the upper or lower surface of the silicon nitride film or the silicon nitride oxide film. An SOI substrate having a structure can be provided.
The OI substrate can completely prevent diffusion of impurities contained in the support substrate and impurities adsorbed on the bonding surface of the support substrate and the single crystal silicon substrate to the single crystal silicon layer side, The bonding strength between the supporting substrate and the single crystal silicon substrate is high, and the reliability is high.

Further, by forming the supporting substrate from a substrate having optical transparency such as a quartz substrate or a glass substrate,
The OI substrate can be applied to a device that transmits light, such as a transmissive liquid crystal device. In this case, the thickness of the silicon nitride film or the silicon nitride oxide film forming the insulating portion is set to 100 nm in order to prevent the light transmittance from being reduced due to the presence of the silicon nitride film or the silicon nitride oxide film. It is desirable to set the following.

An element substrate can be manufactured using the above-described SOI substrate of the present invention. The method for manufacturing an element substrate according to the present invention includes a step of using a SOI substrate manufactured by the method for manufacturing an SOI substrate according to the present invention, and forming a semiconductor layer forming a transistor element from the single-crystal silicon layer of the SOI substrate. It is characterized by the following.

Further, according to the method for manufacturing an element substrate, it is possible to provide an element substrate having a transistor element having a semiconductor layer made of a single crystal silicon layer of the SOI substrate of the present invention.

The element substrate of the present invention can completely prevent the impurities contained in the support substrate and the impurities adsorbed on the bonding surface between the support substrate and the single crystal silicon substrate from diffusing to the transistor element side. Therefore, deterioration of the characteristics of the transistor element can be prevented.

Further, the element substrate of the present invention, another substrate arranged to face the surface of the element substrate on which the transistor elements are formed, and an electro-optical material sandwiched between these two substrates And an electronic apparatus provided with the electro-optical device of the present invention. In the electro-optical device according to the present invention, it is preferable that a light-shielding film is formed on the lower surface of the silicon nitride film or the silicon nitride oxide film via an insulating film made of a silicon oxide film.

The electro-optical device and the electronic apparatus provided with the element substrate according to the present invention can prevent deterioration of the characteristics of the transistor element and have excellent performance.

[0033]

Embodiments of the present invention will be described below in detail.

[SOI Substrate] First, FIG. 1 shows a sectional structure of an SOI substrate according to an embodiment of the present invention.
The structure of the I substrate 200 will be described.

As shown in FIG. 1, the SOI substrate 200 of the present embodiment includes a support substrate 201 made of silicon, quartz, glass, or the like, and a single-crystal silicon layer 202. An insulating portion 205 having a laminated structure of a plurality of insulating films is formed between the insulating portions 205 and. In the present embodiment, the insulating section 205 is
From the first side, a first silicon oxide film 203B, a silicon nitride film or a silicon nitride oxide film 204, and a second silicon oxide film 203A are sequentially stacked.

Next, based on FIGS. 2 and 3, as a method of manufacturing the SOI substrate of the present embodiment, an SOI substrate having the above-described structure will be described.
A method for manufacturing the I substrate 200 will be described. FIG. 2 (a)
3 (e) and FIGS. 3 (a) to 3 (c) are cross-sectional views.
The manufacturing method described below is an example, and the present invention is not limited to the following method.

First, as shown in FIG. 2A, a single-crystal silicon substrate 202A having a thickness of, for example, about 300 to 900 μm is prepared, and as shown in FIG. A first silicon oxide film having a thickness of, for example, about 5 to 400 nm is formed on one surface of the single crystal silicon substrate 202A by thermally oxidizing one surface in an O ₂ or H ₂ O atmosphere at 700 to 1150 ° C. Form 203B.

Next, as shown in FIG. 2C, the single-crystal silicon substrate 2 on which the first silicon oxide film 203B is formed
02A is nitrided or oxynitrided at 800 to 1150 ° C. in an atmosphere of dinitrogen monoxide or nitrogen monoxide to form a silicon nitride film or silicon nitride oxide on the side of the first silicon oxide film 203B on the side of the single crystal silicon substrate 202A. A film 204 is formed.

When the support substrate 201 is formed of a substrate having light transmittance such as a quartz substrate or a glass substrate, and the SOI substrate 200 is applied to a device that transmits light, such as a transmission type liquid crystal device, In order to prevent a decrease in light transmittance due to the presence of the silicon nitride film or the silicon nitride oxide film 204, the thickness of the silicon nitride film or the silicon nitride oxide film 204 is preferably 100 nm or less.

Next, as shown in FIG. 2D, the surface of the single crystal silicon substrate 202A on which the silicon nitride film or the silicon nitride oxide film 204 has been formed is heated at 700 to 1150 ° C. in an O ₂ or H ₂ O atmosphere. By thermal oxidation,
On the side of the single crystal silicon substrate 202A of the silicon nitride film or the silicon nitride oxide film 204, for example, 5 to 400 nm
A second silicon oxide film 203A having a film thickness of about the same is formed. As described above, the single crystal silicon substrate 202
On the surface A, an insulating portion 205 including a first silicon oxide film 203B, a silicon nitride film or a silicon nitride oxide film 204, and a second silicon oxide film 203A is formed.

Next, as shown in FIG. 2E, hydrogen ions (H ⁺ ) are applied to the surface of the single crystal silicon substrate 202A having the insulating portion 205 formed on the insulating portion 205 side, for example, at an acceleration voltage of 100 keV and at a dose. The injection is performed at a dose of 10 × 10 ¹⁶ / cm ² . By this processing, the single crystal silicon substrate 20
A high concentration layer 206 of hydrogen ions is formed in 2A.

Next, as shown in FIG.
With the surface 05 (the surface of the first silicon oxide film 203B) as a bonding surface, the single crystal silicon substrate 202A is bonded to a supporting substrate 201 made of silicon, quartz, glass, or the like. In the bonding step, for example, a method of directly bonding the two substrates by performing a heat treatment at 300 ° C. for 2 hours can be adopted. Further, in order to further increase the bonding strength, it is necessary to further raise the heat treatment temperature to about 450 ° C., but there is a large difference in the thermal expansion coefficient between the support substrate 201 made of quartz or the like and the single crystal silicon substrate 202A. Therefore, if heating is performed as it is, defects such as cracks may occur in the single crystal silicon layer, and the quality of the manufactured SOI substrate 200 may be deteriorated.

Therefore, in order to suppress the occurrence of defects such as cracks, the single crystal silicon substrate 202A once subjected to a heat treatment for bonding at 300 ° C. is subjected to wet etching or CMP (chemical mechanical polishing). After the thickness is reduced to about 100 to 150 [mu] m by the method, it is preferable to further perform a high-temperature heat treatment. For example, 80 ° C
After performing etching so that the thickness of the single crystal silicon substrate 202A becomes 150 μm using a KOH aqueous solution, bonding to the supporting substrate 201 is performed, and heat treatment is performed again at 450 ° C. to increase the bonding strength. desirable.

Next, as shown in FIG. 3B, the two bonded substrates are subjected to a heat treatment to
Most of the single-crystal silicon substrate 202A is peeled off while leaving the thin-film single-crystal silicon layer 202 on the surface of the substrate 1. This substrate peeling phenomenon occurs because the bonding of silicon is broken by hydrogen ions introduced into the single crystal silicon substrate 202A. That is, in the single crystal silicon substrate 202A, the high concentration layer 206 of hydrogen ions
The single crystal silicon substrate 202A can be divided near the boundary between the single crystal silicon substrate 202A and the portion where hydrogen ions are not implanted.

The heat treatment for peeling the single crystal silicon substrate 202A is performed, for example, by bonding the two bonded substrates at a rate of 2 minutes per minute.
It can be carried out by heating to 600 ° C. at a temperature rising rate of 0 ° C. By this heat treatment, most of the bonded single crystal silicon substrate 202A becomes a supporting substrate 201.
From the surface of the support substrate 201, for example, about 20
Single-crystal silicon layer 2 having a thickness of about 0 nm ± 5 nm
02 is formed. Note that the single crystal silicon layer 202
By changing the acceleration voltage of the hydrogen ion implantation performed for the single crystal silicon substrate 202A described above,
It can be formed in any thickness from nm to 3000 nm.

As described above, the SOI substrate 200 is manufactured as shown in FIG.

After the single-crystal silicon substrate 202A and the support substrate 201 are bonded together, the single-crystal silicon substrate 2
The method for forming the single crystal silicon layer 202 by thinning 02A is not limited to the above-described method using hydrogen ions, and the single crystal silicon layer 202 of the thin film is formed by bonding a single crystal silicon substrate and a supporting substrate. After that, the surface of the single crystal silicon substrate was polished to a thickness of 3 to 5 μm, and then PACE (Plasma Assiste).
d Chemical Etching) to finish the film by etching to a thickness of about 0.05 to 0.8 μm, or to bond the epitaxial silicon layer formed on the porous silicon by selective etching of the porous silicon layer on the supporting substrate. ELTRAN to transfer to
(Epitaxial Layer Transfer
It can also be obtained by the method r).

According to the method for manufacturing an SOI substrate of this embodiment, a single crystal silicon substrate 202A having a silicon nitride film or a silicon nitride oxide film 204 formed on its surface and a support substrate 201 are bonded to each other to form a silicon nitride film or a silicon nitride film. Since the silicon nitride oxide film 204 can be positioned closer to the single crystal silicon layer 202 than the bonding surface of the support substrate 201 and the single crystal silicon substrate 202A, the impurity contained in the support substrate 201 and the It is possible to completely prevent impurities adsorbed on the surface bonded to the single crystal silicon substrate 202A from diffusing to the single crystal silicon layer 202 side.

Further, the second silicon oxide film 203A, the silicon nitride film or the silicon nitride oxide film 204, and the first silicon oxide film 203B are formed by CVD or the like.
The layers may be sequentially formed on the surface of the single crystal silicon substrate 202A. However, in this case, the manufacturing process becomes complicated, and the thickness of the second silicon oxide film 203A, the silicon nitride film or the silicon nitride oxide film 204, and the first silicon oxide film 203B may be non-uniform. is there.

However, in this embodiment, after the first silicon oxide film 203B is formed by thermally oxidizing the surface of the single crystal silicon substrate 202A, the single crystal silicon substrate 202A on which the first silicon oxide film 203B is formed is formed.
By nitriding or oxynitriding the surface, a silicon nitride film or a silicon nitride oxide film 204 is formed on the first silicon oxide film 203B side of the single crystal silicon substrate 202A, and further a silicon nitride film or a silicon nitride oxide film 204 is formed. The method of forming the second silicon oxide film 203A on the single crystal silicon substrate 202A side of the silicon nitride film or the silicon nitride oxide film 204 by thermally oxidizing the surface of the single crystal silicon substrate 202A, A flat first silicon oxide film 203B, a silicon nitride film or a silicon nitride oxide film 204 having a thickness, and a second silicon oxide film 203A can be formed.

By forming these films having a uniform film thickness as described above, it is possible to prevent the occurrence of voids on the bonding surface between the supporting substrate 201 and the single crystal silicon substrate 202A. The strength can be improved, and in the case where a transistor element or the like is formed using the SOI substrate 200, film peeling or the like can be prevented, so that the product yield can be improved.

According to this method, the first silicon oxide film 203B, the silicon nitride film or the silicon nitride oxide film 204, and the second silicon oxide film 203A can be formed integrally with the single crystal silicon substrate 202A. Therefore, the first silicon oxide film 203B, the silicon nitride film or the silicon nitride oxide film 204, the second silicon oxide film 203A, and the single crystal silicon layer 202 have high adhesion.
The OI substrate 200 can be manufactured.

Further, according to the present embodiment, the first silicon oxide film 203B is formed on the surface of the silicon nitride film or the silicon nitride oxide film 204, and the surface of the first silicon oxide film 203B is used as a bonding surface. Therefore, the first silicon oxide film 203B is not formed on the surface of the silicon nitride film or the silicon nitride oxide film 204, and the support substrate 201 is formed more than when the surface of the silicon nitride film or the silicon nitride oxide film 204 is used as a bonding surface. Adhesion with the single crystal silicon substrate 202A can be improved, and bonding strength can be improved.

Note that the first silicon oxide film 203B, the silicon nitride film or the silicon nitride oxide film 204,
The silicon oxide film 203A of the single crystal silicon substrate 202
In the case where a flat film can be formed by using a CVD method or the like without being integrally formed with A, other than the first silicon oxide film 203B, the silicon nitride film, Examples of a method for forming the silicon nitride oxide film 204 and the second silicon oxide film 203A and a pattern of bonding between the single crystal silicon substrate 202A and the supporting substrate 201 can be given.

In the present embodiment, the second silicon oxide film 203A is formed after the silicon nitride film or the silicon nitride oxide film 204. However, the second silicon oxide film 203A is formed on the single crystal silicon substrate 202A. This is only when a lattice defect is formed when the silicon oxide film 204 is directly formed. In particular, when a silicon nitride oxide film is formed, lattice defects are hardly formed.
The second silicon oxide film 203A need not be formed.

Referring to FIGS. 4A to 4D, a method of forming the first silicon oxide film 203B, the silicon nitride film or the silicon nitride oxide film 204, and the second silicon oxide film 203A other than those described above, and bonding. The pattern will be briefly described. FIGS. 4A to 4D show a combination of a support substrate 201 to be bonded and a single-crystal silicon substrate 202A taken out.

As shown in FIG. 4A, a second silicon oxide film 203A, a silicon nitride film or a silicon nitride oxide film 204, and a first silicon oxide film are formed on the surface of a single crystal silicon substrate 202A by a CVD method. After sequentially forming 203B, the single crystal silicon substrate 202A and the supporting substrate 201 may be bonded to each other.

After the second silicon oxide film 203A is formed by thermally oxidizing the surface of the single crystal silicon substrate 202A, the silicon nitride film or the silicon nitride oxide film 204 and the first silicon oxide film 20 are formed by the CVD method.
The method described above, such as sequentially forming 3B, and CVD
It may be formed in combination with the method.

In the case where a silicon oxide film and a silicon nitride film or a silicon nitride oxide film are formed on the surface of the single crystal silicon substrate 202A by using the CVD method, FIG.
As shown in (b), a silicon nitride film or a silicon nitride oxide film 204 may be formed directly on the surface of the single crystal silicon substrate 202A without providing the second silicon oxide film 203A.

Even with such a structure, the silicon nitride film or the silicon nitride oxide film 204 can be positioned closer to the single crystal silicon layer 202 than the bonding surface between the supporting substrate 201 and the single crystal silicon substrate 202A. It is also possible to completely prevent the impurities contained in the support substrate 201 and the impurities adsorbed on the bonding surface of the support substrate 201 and the single crystal silicon substrate 202A from diffusing to the single crystal silicon layer 202 side.

In FIGS. 4A and 4B, the case where a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film is formed on the single crystal silicon substrate 202A side and then bonded is described. The invention is not limited to this. Hereinafter, a case in which a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film is formed on the supporting substrate 201 side and then bonded will be described with reference to FIGS. 4C and 4D.

As shown in FIG. 4C, a first silicon oxide film 203 is formed on the surface of the support substrate 201 by the CVD method.
B, silicon nitride film or silicon nitride oxide film 20
4. After sequentially forming the second silicon oxide film 203A,
The supporting substrate 201 and the single-crystal silicon substrate 202A may be attached to each other.

In this case, it is desirable to previously form a silicon oxide film 203C on the surface of single crystal silicon substrate 202A by thermal oxidation or CVD, and thus support substrate 201, single crystal silicon substrate 202A
By setting the outermost surface on the bonding side of any of the substrates to a silicon oxide film, the adhesion between the two substrates after bonding can be improved.

When the support substrate 201 is made of a quartz substrate or a glass substrate, the main component of the support substrate 201 is silicon oxide, and therefore, as shown in FIG. The first silicon oxide film 203B may not be formed, and the supporting substrate 201 may be formed by using the CVD method.
Silicon nitride film or silicon nitride oxide film 20
4. After sequentially forming the second silicon oxide film 203A,
This support substrate 201 and a single crystal silicon substrate 202A having a silicon oxide film 203C formed on the surface may be attached to each other.

In the bonding patterns shown in FIGS. 4C and 4D, the silicon nitride film or the silicon oxynitride film 204 has a larger thickness than the bonding surface.
Thus, the impurities contained in the supporting substrate 201 can be prevented from diffusing to the single crystal silicon layer 202 side, but the impurities adsorbed on the bonding surface can be diffused to the single crystal silicon layer 202 side. Can not be prevented. That is, the bonding patterns shown in FIGS. 4C and 4D are effective when a substrate containing impurities such as a quartz substrate or a glass substrate is used as the support substrate 201.

[Element Substrate] Next, the structure of the element substrate 210 according to the embodiment of the present invention manufactured using the SOI substrate 200 having the above structure will be described with reference to FIG.
An element substrate 210 shown in FIG. 5 is manufactured by forming a single crystal silicon layer 202 of an SOI substrate 200 in a predetermined pattern, and then forming a TFT (transistor element) using the single crystal silicon layer. is there.

In FIG. 5, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 5, reference numeral 220 indicates a TFT, and reference numeral 208 indicates an SOI substrate 20.
1 shows a semiconductor layer which is formed from a single crystal silicon layer 202 and forms a TFT. In FIG. 5, a supporting substrate 201, an insulating portion 205 including a first silicon oxide film 203B and a silicon nitride film or a silicon nitride oxide film 204 and a second silicon oxide film 203A, and a single crystal silicon layer 202 are formed. The formed semiconductor layer 208 is an SOI substrate.

As shown in FIG. 5, a TFT 220 including a semiconductor layer 208, a gate insulating film 209, a gate electrode 211, a source electrode 215, a drain electrode 216, and an interlayer insulating film 212 is formed on the surface of the insulating portion 205. ing.

More specifically, a gate insulating film 209 is formed on the surface of the support substrate 201 on which the semiconductor layer 208 is formed, and a gate electrode 211 is formed on the surface of the gate insulating film 209. Further, an interlayer insulating film 212 is provided on the surface of the support substrate 201 on which the gate electrode 211 is formed.

The interlayer insulating film 212 and the gate insulating film 209
Are formed with contact holes 217 and 218 communicating with a source region and a drain region (both not shown) formed in the semiconductor layer 208.
5, the drain electrode 216 is in contact hole 21
It is formed so as to be electrically connected to the source region and the drain region of the semiconductor layer 208 via 7, 218.

The element substrate 210 of this embodiment is formed by
Since it is formed using the OI substrate 200, impurities contained in the support substrate 201 and the support substrate 201
And the single crystal silicon substrate 202A can be completely prevented from diffusing impurities adsorbed on the surface to be bonded to the semiconductor layer 208 (TFT 220) side.
20 can be prevented from deteriorating.

[Electro-Optical Device] Next, as an example of the electro-optical device according to the embodiment of the present invention, an active device using a TFT (transistor element) as a switching element, which is preferably used for a projection display device such as a projector. A matrix type liquid crystal device will be described.

The liquid crystal device of the present embodiment has an element substrate manufactured using the SOI substrate of the present invention. That is, as described above, the basic structure of the element substrate constituting the electro-optical device according to the present embodiment includes a first silicon oxide film on a surface of a substrate body corresponding to a support substrate,
An insulating portion made of a silicon nitride film, a silicon nitride oxide film, or a second silicon oxide film is provided, and a semiconductor layer formed of a single crystal silicon layer is provided on the surface thereof.
The FT is formed.

In the projection type display device, light usually enters from the substrate side (the surface of the liquid crystal device) of the two substrates constituting the liquid crystal device which faces the element substrate. In order to prevent light leak current from being incident on the channel region of the TFT formed on the surface of the element substrate, TF
In general, a structure in which a light-shielding layer is provided on the side where T light is incident is adopted.

However, even if a light-shielding layer is provided on the side of the TFT on which light enters, the light incident on the liquid crystal device may be reflected at the interface on the back surface of the element substrate and return to the channel portion of the TFT as light. . This return light is small as a percentage of the amount of light incident from the surface of the liquid crystal device,
In a device using a very strong light source such as a projector, a sufficient light leakage current can be generated. That is, the return light from the back surface of the element substrate affects the switching characteristics of the TFT and degrades the characteristics of the device.

Therefore, in the present embodiment, in order to prevent the TFT characteristics from deteriorating due to such return light,
A light-shielding film is provided directly above a substrate body corresponding to a support substrate, corresponding to each TFT (transistor element), and a first light-shielding film made of metal or the like is electrically insulated from a semiconductor layer constituting the TFT. An interlayer insulating film is provided, and an insulating portion including a first silicon oxide film, a silicon nitride film or a silicon nitride oxide film, and a second silicon oxide film is provided over a surface of the first interlayer insulating film.

(Structure of Electro-Optical Device) First, the structure of the electro-optical device according to the embodiment of the present invention will be described with reference to a liquid crystal device.

FIG. 6 shows an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix forming a pixel portion (display area) of the liquid crystal device. FIG. 7 is an enlarged plan view showing a plurality of adjacent pixel groups on an element substrate on which data lines, scanning lines, pixel electrodes, light-shielding films, and the like are formed. FIG. 8 is a sectional view taken along the line AA ′ of FIG.

6 to 8, reference numeral 30 denotes a TFT.
(Transistor element), reference numeral 1a denotes a semiconductor layer formed of a single crystal silicon layer and constituting a TFT.
6 to 8, the same components as those in FIGS. 1 and 5 are denoted by the same reference numerals, and description thereof will be omitted. still,
6 to 8, the scale of each layer and each member is different for each layer and each member in order to make the size recognizable in the drawings.

In FIG. 6, a plurality of pixels formed in a matrix and constituting a pixel portion of the liquid crystal device are composed of a plurality of pixel electrodes 9a formed in a matrix and a TFT 30 for controlling the pixel electrodes 9a. The data line 6a to which the image signal is supplied is electrically connected to the source of the TFT 30. The image signal S1 written to the data line 6a,
S2,..., Sn may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6a for each group. The scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signal G1 and the scanning signal G1 are pulsed to the scanning line 3a at a predetermined timing.
, Gm are applied line-sequentially in this order.

The pixel electrode 9a is electrically connected to the drain of the TFT 30 and has a switching element TF
By closing the switch for a certain period of time T30, the image signals S1, S2,
..., Sn is written at a predetermined timing. Pixel electrode 9a
Image signal S of a predetermined level written on the liquid crystal through
, Sn are held for a certain period of time between a later-described counter electrode formed on a later-described counter substrate.

The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level.
Enables gradation display. In the normally white mode, the incident light cannot pass through the liquid crystal portion according to the applied voltage. In the normally black mode, the incident light passes through the liquid crystal portion according to the applied voltage. The liquid crystal device emits light having a contrast corresponding to the image signal as a whole.

Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. For example, the voltage of the pixel electrode 9a is set to be equal to the storage capacitance 70 for a time that is three digits longer than the time when the voltage is applied to the data line.
Is held by Thereby, the holding characteristics are further improved, and a liquid crystal device having a high contrast ratio can be realized. In the present embodiment, in particular, in order to form such a storage capacitor 70, a capacitor line 3b having the same resistance as the scanning line or a low resistance using a conductive light-shielding film is provided as described later.

Next, a planar structure in a pixel portion (display area) of the element substrate will be described in detail with reference to FIG. As shown in FIG. 7, a plurality of transparent pixel electrodes 9a (indicated by dotted lines 9a ') are provided in a matrix in a pixel portion on an element substrate of the liquid crystal device.
The data lines 6a,
A scanning line 3a and a capacitance line 3b are provided. The data line 6a is electrically connected to a source region described later in the semiconductor layer 1a of the single crystal silicon layer via the contact hole 5, and the pixel electrode 9a is electrically connected to the source layer in the semiconductor layer 1a through the contact hole 8. It is electrically connected to a drain region described later. Further, the scanning line 3a is arranged so as to face a channel region (a hatched region on the upper right in the figure) of the semiconductor layer 1a, and the scanning line 3a functions as a gate electrode.

The capacitance line 3b has a main line portion extending substantially linearly along the scanning line 3a (that is, the scanning line 3a in a plan view).
(A first region formed along the data line 6a) and a protruding portion (upward in the figure) protruding along the data line 6a from a point intersecting the data line 6a (ie, the data line 6a extending along the second region 6a).

A plurality of first light-shielding films 11a are provided in a region shown by oblique lines rising upward in the drawing. More specifically, the first light-shielding film 11a is provided at a position where the TFT including the channel region of the semiconductor layer 1a in the pixel portion covers the element substrate when viewed from the substrate body side, which will be described later. A main line portion that extends linearly along the scanning line 3a opposite to the main line portion of the data line 6b, and a step side adjacent to the data line 6a from a portion that intersects with the data line 6a (ie,
(A downward direction in the figure). The tip of the downward protruding portion in each stage (pixel row) of the first light-shielding film 11a overlaps the tip of the upward protruding portion of the capacitor line 3b in the next stage below the data line 6a. A contact hole 13 that electrically connects the first light-shielding film 11a and the capacitance line 3b to each other is provided in the overlapping portion. That is, in the present embodiment, the first light-shielding film 11a is formed by the contact hole 13 in the first or second stage capacitance line 3b.
Is electrically connected to

Next, a sectional structure in the pixel portion of the liquid crystal device will be described with reference to FIG. As shown in FIG. 8, in the liquid crystal device, a liquid crystal layer (electro-optical material layer) 50 is provided between the element substrate 10 and the opposing substrate 20 disposed opposite thereto.
Is pinched.

The element substrate 10 is a substrate body (supporting substrate) 10 made of a light-transmitting substrate such as silicon, quartz, glass or the like.
A and the pixel electrode 9 formed on the liquid crystal layer 50 side surface
a, TFT (transistor element) for pixel switching 3
The counter substrate 20 includes a substrate body 20A made of a light-transmitting substrate such as transparent glass or quartz and a counter electrode (common electrode) formed on the surface of the liquid crystal layer 50 side. ) 21 and an alignment film 22.

The liquid crystal layer 5 of the substrate body 10A of the element substrate 10
A pixel electrode 9a is provided on the 0-side surface, and an alignment film 16 on which a predetermined alignment process such as a rubbing process is performed is provided on the liquid crystal layer 50 side, and is adjacent to each pixel electrode 9a. A pixel switching TFT 30 that controls the switching of each pixel electrode 9a is provided at the position. The pixel electrode 9a is made of a transparent conductive thin film such as ITO (indium tin oxide), for example.
For example, it is made of an organic thin film such as polyimide.

Immediately above the substrate body 10A of the element substrate 10 (on the surface on the liquid crystal layer 50 side), each pixel switching TFT
The first light shielding film 11a is provided at a position corresponding to 30. The first light-shielding film 11a is preferably made of a simple metal, an alloy, a metal silicide, or the like containing at least one of Ti, Cr, W, Ta, Mo, and Pd, which are preferably opaque refractory metals.

In the present embodiment, since the first light-shielding film 11a is formed on the element substrate 10 as described above, return light and the like from the element substrate 10 side are used for the pixel switching TFT.
30 can be prevented from being incident on the channel region 1a 'or the LDD regions 1b and 1c, and the characteristics of the pixel switching TFT 30 as a transistor element can be prevented from deteriorating due to generation of a photocurrent.

On the surface of the first light-shielding film 11a, the semiconductor layer 1a constituting the pixel switching TFT 30 is formed over the entire surface of the substrate main body 10A.
In order to electrically insulate from the substrate a and flatten the surface of the substrate body 10A on which the first light shielding film 11a is formed,
First interlayer insulating film made of a silicate glass film such as NSG (non-doped silicate glass), PSG (phosphosilicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), a silicon nitride film, a silicon oxide film, or the like 12 is provided. On the surface of the first interlayer insulating film 12, an insulating portion 205 including a first silicon oxide film 203B, a silicon nitride film or a silicon nitride oxide film 204, and a second silicon oxide film 203A is further provided. The pixel switching TFT 30 is provided on the surface of the insulating unit 205. The TFT 30 is
The semiconductor device includes a semiconductor layer 1a provided on the surface of the insulating portion 205 and formed from a single crystal silicon layer. In this embodiment, the thickness of the silicon nitride film or the silicon nitride oxide film 204 is 100 nm in order to prevent a light transmittance from being reduced due to the presence of the silicon nitride film or the silicon nitride oxide film 204.
It is desirable to set the following. In addition, the insulating part 2
The structure of 05 is the same as the structure of the insulating portion 205 of the SOI substrate 200 and the element substrate 210 except that the contact hole 13 is opened, so that the description is omitted.

On the other hand, an opposing electrode (common electrode) 21 is provided on the entire surface of the opposing substrate 20 on the liquid crystal layer 50 side of the substrate body 20A, and a rubbing treatment is applied to the liquid crystal layer 50 side. There is provided an alignment film 22 that has been subjected to a predetermined alignment process such as. The counter electrode 21 is made of, for example, ITO.
The alignment film 22 is made of, for example, an organic thin film such as polyimide.

As shown in FIG. 8, on the surface of the substrate body 20A on the liquid crystal layer 50 side, a second light-shielding film 23 is provided in a region other than the opening region of each pixel portion. By providing the second light-shielding film 23 on the counter substrate 20 side in this manner, incident light from the counter substrate 20 side can
The channel region 1a 'of the semiconductor layer 1a of the FT 30 or the LDD
(Lightly Doped Drain) It is possible to prevent intrusion into the regions 1b and 1c and improve the contrast.

The sealing material formed between the peripheral portions of the two substrates is provided between the element substrate 10 and the opposing substrate 20 having the above configuration, in which the pixel electrode 9a and the opposing electrode 21 are arranged to face each other. A liquid crystal (electro-optical material) is sealed in a space surrounded by (not shown), and a liquid crystal layer (electro-optical material layer) 50 is formed.
Are formed.

The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several kinds of nematic liquid crystals are mixed, and the alignment film 16 is not applied with an electric field from the pixel electrode 9a.
A predetermined orientation state is taken by (2) and (2).

The sealing material is made of an adhesive such as a photo-curable adhesive or a thermo-curable adhesive for bonding the element substrate 10 and the counter substrate 20 at their peripheral edges. Spacers such as glass fibers and glass beads for adjusting the distance between the two substrates to a predetermined value are mixed.

In the present embodiment, the gate insulating film 2 is extended from a position facing the scanning line 3a and used as a dielectric film, and the semiconductor film 1a is extended and used as a first storage capacitor electrode 1f. A storage capacitor 70 is formed by using a part of the capacitor line 3b facing these as a second storage capacitor electrode.

More specifically, a high-concentration drain region 1e of the semiconductor layer 1a extends below the data line 6a and the scanning line 3a, and also extends along the data line 6a and the scanning line 3a. The first storage capacitor electrode (semiconductor layer) 1f is opposed to the first storage capacitor electrode with the insulating film 2 interposed therebetween.
In particular, since the insulating film 2 as a dielectric of the storage capacitor 70 is nothing but the gate insulating film 2 of the TFT 30 formed on the single-crystal silicon layer by high-temperature oxidation, it can be a thin and high withstand voltage insulating film. The storage capacitor 70 can be configured as a large-capacity storage capacitor with a relatively small area.

Further, in the storage capacitor 70, as can be seen from FIGS. 7 and 8, the first light-shielding film 11a is provided on the first storage capacitor electrode 1f on the opposite side of the capacitor line 3b as the second storage capacitor electrode. By arranging the third storage capacitor electrode facing each other with one interlayer insulating film 12 interposed therebetween (see the storage capacitor 70 on the right side in FIG. 8), the storage capacitor is further provided. That is, in the present embodiment, a double storage capacitor structure in which storage capacitors are provided on both sides of the first storage capacitor electrode 1f is constructed, and the storage capacitance further increases. With such a structure, it is possible to improve the function of the liquid crystal device of the present embodiment for preventing flicker and image sticking in a display image.

As a result, the space outside the opening area, that is, the area under the data line 6a and the area where the liquid crystal disclination occurs along the scanning line 3a (that is, the area where the capacitance line 3b is formed) is effective. To increase the storage capacitance of the pixel electrode 9a.

In this embodiment, the first light shielding film 11a is used.
(And the capacitance line 3b electrically connected thereto) is electrically connected to a constant potential source, and the first light-shielding film 11a and the capacitance line 3b are set to a constant potential. Therefore, the pixel switching TFT 30 that is disposed to face the first light shielding film 11a
On the other hand, the potential fluctuation of the first light shielding film 11a does not adversely affect. Further, the capacitance line 3b can function well as a second storage capacitor electrode of the storage capacitor 70.

As shown in FIGS. 7 and 8, in the present embodiment, in addition to providing the first light-shielding film 11a on the element substrate 10, the first light-shielding film 11a It is configured to be electrically connected to the preceding or subsequent capacitive line 3b. In the case of such a configuration, each first light-shielding film 11a is formed along the edge of the opening area of the pixel portion in comparison with the case where each first light-shielding film 11a is electrically connected to its own capacitance line. In this case, the step in the region where the capacitor line 3b and the first light-shielding film 11a are formed is small relative to other regions. When the steps along the edge of the opening area of the pixel portion are small, disclination (poor alignment) of the liquid crystal caused by the steps can be reduced, so that the opening area of the pixel portion can be expanded. Become.

The first light-shielding film 11a has the contact hole 13 formed in a protruding portion protruding from the main line portion extending linearly as described above. Here, as for the opening of the contact hole 13, cracks are less likely to occur because the stress is more likely to be diffused from the edge as it is closer to the edge. Therefore, the stress applied to the first light-shielding film 11a during the manufacturing process depends on how close the contact hole 13 is opened to the tip of the protruding portion (preferably, depending on how close the tip is to the margin). Is alleviated, cracks can be more effectively prevented, and the yield can be improved.

The capacitance line 3b and the scanning line 3a are made of the same polysilicon film. The dielectric film of the storage capacitor 70 and the gate insulating film 2 of the TFT 30 are made of the same high-temperature oxide film. The storage capacitor electrode 1f, the channel forming region 1a and the source region 1d, and the drain region 1 of the TFT 30.
e and the like consist of the same semiconductor layer 1a. For this reason, the laminated structure formed on the surface of the substrate main body 10A of the element substrate 10 can be simplified. Further, in the method of manufacturing a liquid crystal device described later, the capacitor line 3b and the scanning line 3a are simultaneously formed in the same thin film forming step. The dielectric film of the storage capacitor 70 and the gate insulating film 2 can be formed simultaneously.

The capacitance line 3b and the first light shielding film 11a are
Although both are electrically connected reliably and with high reliability via a contact hole 13 opened in the interlayer insulating film 12, such a contact hole 13
A hole may be formed for each pixel, or a hole may be formed for each pixel group including a plurality of pixels.

The contact hole 13 provided for each pixel or each pixel group is opened below the data line 6a when viewed from the counter substrate 20 side. For this reason,
Since the contact hole 13 is provided outside the opening area of the pixel portion and is provided in the portion of the first interlayer insulating film 12 where the TFT 30 and the first storage capacitor electrode 1f are not formed, effective use of the pixel portion is achieved. At the same time, it is possible to prevent the TFT 30 and other wiring from becoming defective due to the formation of the contact hole 13.

In FIG. 3, the pixel switching TFT 30 has an LDD (Lightly Doped Drain) structure, and includes a scanning line 3a and a channel region of the semiconductor layer 1a where a channel is formed by an electric field from the scanning line 3a. 1
a ', gate insulating film 2 for insulating scanning line 3a from semiconductor layer 1a, data line 6a, low-concentration source region (source-side LDD region) 1b and low-concentration drain region (drain-side LDD region) 1c of semiconductor layer 1a , A high concentration source region 1d and a high concentration drain region 1e of the semiconductor layer 1a.

A corresponding one of the plurality of pixel electrodes 9a is connected to the high-concentration drain region 1e. As will be described later, the source regions 1b and 1d and the drain regions 1c and 1e have a predetermined concentration for N-type or P-type with respect to the semiconductor layer 1a depending on whether an N-type or P-type channel is formed.
It is formed by doping a type dopant. An N-type channel TFT has an advantage of a high operation speed, and is often used as a pixel switching TFT 30 which is a pixel switching element.

The data line 6a is formed of a light-shielding thin film such as a metal film such as Al or an alloy film such as metal silicide. On the scanning line 3a, the gate insulating film 2, and the first interlayer insulating film 12, a contact hole 5 leading to the high-concentration source region 1d and a contact hole 8 leading to the high-concentration drain region 1e are respectively formed. Interlayer insulating film 4
Are formed. Through the contact hole 5 to the source region 1b, the data line 6a is connected to the high concentration source region 1
d.

Further, the data line 6a and the second interlayer insulating film 4
A third interlayer insulating film 7 having a contact hole 8 to the high-concentration drain region 1e formed thereon.
The pixel electrode 9a is electrically connected to the high-concentration drain region 1e via the contact hole 8 to the high-concentration drain region 1e. The above-described pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 configured as described above. Note that the pixel electrode 9a and the high concentration drain region 1e are
The same Al film as the data line 6a or the same polysilicon film as the scanning line 3b may be relayed and electrically connected.

The pixel switching TFT 30 preferably has an LDD structure as described above, but may have an offset structure in which impurity ions are not implanted into the low-concentration source region 1b and the low-concentration drain region 1c. Alternatively, a self-aligned TFT in which impurity ions are implanted at a high concentration using the gate electrode (scanning line 3a) as a mask to form high-concentration source and drain regions in a self-aligned manner may be used.

Further, the single gate structure in which only one gate electrode (scanning line 3a) of the pixel switching TFT 30 is arranged between the source-drain regions 1b and 1e is used, but two or more gate electrodes are provided between them. It may be arranged. At this time, the same signal is applied to each gate electrode. When a TFT is formed with a double gate or a triple gate or more as described above, a leak current at a junction between a channel and a source-drain region can be prevented, and a current in an off state can be reduced. If at least one of these gate electrodes has an LDD structure or an offset structure, the off-state current can be further reduced, and a stable switching element can be obtained.

Here, in general, the single-crystal silicon layer constituting the channel region 1a ', the low-concentration source region 1b, the low-concentration drain region 1c, etc. of the semiconductor layer 1a is formed by the photoelectric conversion effect of silicon when light enters. Although a photocurrent is generated and the transistor characteristics of the pixel switching TFT 30 are deteriorated, in the present embodiment, the data line 6a is formed of a light-shielding metal thin film such as Al so as to cover the scanning line 3a from above. Therefore, at least the semiconductor layer 1
It is possible to prevent the incident light from entering the channel region 1a 'and the LDD regions 1b and 1c.

As described above, since the first light-shielding film 11a is provided below the pixel switching TFT 30 (on the substrate body 10A side), at least the semiconductor layer 1 is provided.
It is possible to prevent return light from entering the channel region 1a 'and the LDD regions 1b and 1c.

In the present embodiment, since the capacitance line 3b provided in the adjacent preceding or succeeding pixel is connected to the first light-shielding film 11a, the uppermost or lowermost pixel is not connected. A capacitance line 3b for supplying a constant potential to the first light shielding film 11a is required. Therefore, it is preferable to provide one extra capacitor line 3b with respect to the number of vertical pixels.

(Method of Manufacturing Electro-Optical Device) Next, a method of manufacturing a liquid crystal device having the above structure will be described. First, a method for manufacturing the element substrate 10 will be described as a method for manufacturing the element substrate according to the embodiment of the present invention with reference to FIGS. 9 to 14 show a part of the element substrate in each step, similarly to FIG.
It is a process drawing shown corresponding to a section. Also, in FIGS. 10 to 14, in order to simplify the drawings, an insulating portion 20 is shown.
5 is omitted.

First, a substrate body (supporting substrate) 10A such as a silicon substrate, a quartz substrate, or a glass substrate is prepared. Here, preferably, under an inert gas atmosphere such as N ₂ (nitrogen), about 850 to 1300 ° C., more preferably 1000 ° C.
Annealing is performed at a high temperature, and pre-processing is performed so that distortion generated in the substrate body 10A in a high-temperature process performed later is reduced. That is, the substrate body 10A is previously heat-treated at the same temperature or higher in accordance with the highest temperature to be processed in the manufacturing process.

As shown in FIG. 9A, Ti, Cr, W, and T are formed on the entire surface of the substrate body 10A thus processed.
a, a metal such as Mo and Pd, or a metal alloy film such as a metal silicide by sputtering or the like, for 100 to 500
The light-shielding layer 11 having a thickness of about nm, preferably about 200 nm is formed.

Next, as shown in FIG. 9B, a photoresist 207 corresponding to the pattern of the first light shielding film 11a (see FIG. 7) is formed by photolithography.

Next, as shown in FIG. 9C, the first light-shielding film 11a having the pattern shown in FIG. 7 is formed by etching the light-shielding layer 11 via the photoresist 207. .

Next, as shown in FIG. 9D, a TEOS (tetra-ethyl-ortho-silicate) gas and a TEB (tetra-・ Ethyl boat rate) gas, T
The first interlayer insulating film 12 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed by using an MOP (tetra methyl oxy phosphate) gas or the like. The thickness of the first interlayer insulating film 12 is, for example, about 400 to 1000 n.
m, more preferably about 800 nm.

Next, as shown in FIG. 9E, the entire surface of the first interlayer insulating film 12 is polished and flattened by a CMP (chemical mechanical polishing) method or the like.

Next, as shown in FIG. 9F, a substrate body 10A shown in FIG. 9E on which a first interlayer insulating film 12 having a flattened surface is formed, and a first silicon oxide Membrane 2
03B, silicon nitride film or silicon nitride oxide film 2
04, insulating portion 2 made of second silicon oxide film 203A
Bonding is performed with the single crystal silicon substrate 202A on which the substrate 05 is formed. Next, as shown in FIG. 9 (g), most of the single crystal silicon substrate 202A is peeled off while leaving the thin single crystal silicon layer 202 on the surface of the substrate body 10A.

The method of forming the insulating portion 205 on the surface of the single crystal silicon substrate 202A, the single crystal silicon substrate 202A having the insulating portion 205 formed on the surface and the substrate body 10A
Bonding method and single crystal silicon substrate 202A
Since the method of peeling the SOI substrate 200 has been described in detail in the above-described method of manufacturing the SOI substrate 200, the description is omitted.

Next, as shown in FIG. 9H, the single-crystal silicon layer 202 is formed into a predetermined pattern through a photolithography step, an etching step, and the like, thereby forming a semiconductor having a predetermined pattern as shown in FIG. The layer 1a is formed. That is, in particular, in the region where the capacitance line 3b is formed below the data line 6a and in the region where the capacitance line 3b is formed along the scanning line 3a, the third region extending from the semiconductor layer 1a constituting the pixel switching TFT 30 is formed. One storage capacitor electrode 1f is formed.

Next, as shown in FIG. 9I, the first storage capacitor electrode 1f together with the semiconductor layer 1a constituting the pixel switching TFT 30 is heated at a temperature of about 850 to 1300 ° C., preferably at a temperature of about 1000 ° C. By thermally oxidizing for about 72 minutes, a relatively thin thermally oxidized silicon film of about 60 nm is formed, and the gate insulating film 2 for capacitance formation is formed together with the gate insulating film 2 of the pixel switching TFT 30. As a result, the semiconductor layer 1a and the first storage capacitor electrode 1f
The thickness of the gate insulating film 2 is about 30 to 170 nm.
Has a thickness of about 60 nm.

Next, as shown in FIG. 10A, a resist film 301 is formed at a position corresponding to the N-channel semiconductor layer 1a.
Is formed, and the P-channel semiconductor layer 1a is doped with a dopant 302 of a group V element such as P at a low concentration (for example, P ions at an acceleration voltage of 70 keV and a dose of 2 × 10 ¹¹ / cm ² ). .

Next, as shown in FIG. 10B, a resist film is formed at a position corresponding to the P-channel semiconductor layer 1a (not shown), and a group III element such as B is formed on the N-channel semiconductor layer 1a. At a low concentration (for example,
B ions are accelerated to an acceleration voltage of 35 keV, 1 × 10 ¹² / cm ²
Doping).

Next, as shown in FIG. 10C, the channel region 1 of each semiconductor layer 1a is provided for each of the P channel and the N channel.
A resist film 305 is formed on the surface of the substrate 10 excluding the end of a ′, and a dopant of a group V element such as P having a dose about 1 to 10 times that of the step shown in FIG. 306, the N channel is doped with a dopant 306 of a group III element such as B at a dose of about 1 to 10 times that of the step shown in FIG.

Next, as shown in FIG. 10D, in order to lower the resistance of the first storage capacitor electrode 1f formed by extending the semiconductor layer 1a, the scanning line 3a (gate electrode) on the surface of the substrate body 10A is formed. The resist film 307 (scanning line 3a)
Is formed, and a dopant 308 of a group V element such as P is formed thereon at a low concentration (for example, P ions are accelerated at an acceleration voltage of 70 keV, 3 × 10 3).
Doping at a dose of ¹⁴ / cm ² ).

Next, as shown in FIG. 11A, the first interlayer insulating film 12 and the insulating portion 205 (not shown) are subjected to reactive etching and contact holes 13 reaching the first light shielding film 11a. It is formed by dry etching such as etching or by wet etching. At this time, there is an advantage that opening the contact hole 13 or the like by anisotropic etching such as reactive etching or reactive ion beam etching can make the opening shape almost the same as the mask shape. However, if the dry etching and the wet etching are performed in combination, the contact holes 13 and the like can be tapered, so that there is an advantage that disconnection during wiring connection can be prevented.

Next, as shown in FIG.
After the polysilicon layer 3 is deposited to a thickness of about 350 nm by the VD method or the like, phosphorus (P) is thermally diffused to make the polysilicon film 3 conductive. Alternatively, P ions are added to the polysilicon film 3.
May be used. Thereby, the conductivity of the polysilicon layer 3 can be increased.

Next, as shown in FIG. 11C, the capacitor lines 3b are formed along with the scanning lines 3a having a predetermined pattern as shown in FIG. 7 by a photolithography process using a resist mask, an etching process and the like. After that, the polysilicon remaining on the back surface of the substrate body 10A is removed from the substrate body 10A.
The surface of A is covered with a resist film and removed by etching.

Next, as shown in FIG. 11D, in order to form a P-channel LDD region in the semiconductor layer 1a, N
The position corresponding to the semiconductor layer 1a of the channel is defined by
09, and using a scanning line 3a (gate electrode) as a diffusion mask, a dopant 310 of a group III element such as B is first added at a low concentration (for example, BF ₂ ions are accelerated at an acceleration voltage of 90 keV, 3 × 10 ¹³ / cm ² ). Dope)
A lightly doped source region 1b and a lightly doped drain region 1c of the channel are formed.

Subsequently, as shown in FIG. 11E, in order to form a P-channel high-concentration source region 1d and a high-concentration drain region 1e in the semiconductor layer 1a, positions corresponding to the N-channel semiconductor layer 1a are formed. Is covered with a resist film 309, and although not shown, a resist layer is formed on the scanning line 3a corresponding to the P channel with a mask wider than the scanning line 3a. Dopant 311 of a group element is doped at a high concentration (for example, BF ₂ ions are doped at an acceleration voltage of 90 keV and a dose of 2 × 10 ¹⁵ / cm ² ).

Next, as shown in FIG. 12A, in order to form an N-channel LDD region in the semiconductor layer 1a, P
A position corresponding to the semiconductor layer 1a of the channel is covered with a resist film (not shown), and using the scanning line 3a (gate electrode) as a diffusion mask, a dopant 60 of a group V element such as P at a low concentration (for example, P ion Is 70 keV acceleration voltage, 6
X10 ¹² / cm ^{2 at} a dose), and the N-channel lightly doped source region 1b and lightly doped drain region 1c.
To form

Subsequently, as shown in FIG. 12B, in order to form an N-channel high-concentration source region 1d and a high-concentration drain region 1e in the semiconductor layer 1a, a mask wider than the scanning line 3a is used. After a resist 62 is formed on the scanning line 3a corresponding to the N channel, a dopant 61 of a group V element such as P is also applied at a high concentration (for example, 70
(doping at an accelerating voltage of keV and a dose of 4 × 10 ¹⁵ / cm ² ).

Next, as shown in FIG. 12C, a normal pressure or reduced pressure CVD method, a TEOS gas, or the like is applied so as to cover the capacitance line 3b and the scanning line 3a together with the scanning line 3a in the pixel switching TFT 30. Using NSG, PS
A second interlayer insulating film 4 made of a silicate glass film such as G, BSG, BPSG, etc., a silicon nitride film, a silicon oxide film or the like is formed. The thickness of the second interlayer insulating film 4 is about 500 to
1500 nm is preferable, and 800 nm is more preferable.

Thereafter, an annealing process at about 850 ° C. is performed for about 20 minutes to activate the high-concentration source region 1d and the high-concentration drain region 1e.

Next, as shown in FIG. 12D, a contact hole 5 for the data line 31 is formed by dry etching such as reactive etching or reactive ion beam etching or by wet etching. Further, a contact hole for connecting the scanning line 3a and the capacitance line 3b to a wiring (not shown) is also formed in the second interlayer insulating film 4 in the same process as the contact hole 5.

Next, as shown in FIG. 13A, a light-shielding layer A is formed on the second interlayer insulating film 4 by a sputtering process or the like.
1 as a metal film 6 having a thickness of about 100 to 700 nm, preferably about 350 nm.
Then, as shown in FIG. 13B, a data line 6a is formed by a photolithography process, an etching process and the like.

Next, as shown in FIG. 13 (c), NSG, PSG, BSG,
Silicate glass film such as BPSG, silicon nitride film,
A third interlayer insulating film 7 made of a silicon oxide film or the like is formed. The thickness of the third interlayer insulating film 7 is about 500 to 1500 n.
m is preferable, and 800 nm is more preferable.

Next, as shown in FIG. 14A, in the pixel switching TFT 30, a contact hole 8 for electrically connecting the pixel electrode 9a to the high concentration drain region 1e is formed by reactive etching and reactive etching. It is formed by dry etching such as reactive ion beam etching.

Next, as shown in FIG. 14B, a transparent conductive thin film 9 of ITO or the like is deposited on the third interlayer insulating film 7 by sputtering or the like to a thickness of about 50 to 200 nm. Then, as shown in FIG. 14C, a pixel electrode 9a is formed by a photolithography process, an etching process, and the like. When the liquid crystal device of the present embodiment is a reflection type liquid crystal device, the pixel electrode 9a may be formed of an opaque material having a high reflectance such as Al.

Subsequently, after applying a coating liquid for a polyimide-based alignment film on the pixel electrode 9a, a rubbing process is performed in a predetermined direction so as to have a predetermined pretilt angle, and the like. FIG. 8) is formed.

The element substrate 10 is manufactured as described above.

According to the method of manufacturing an element substrate of this embodiment, a single crystal silicon substrate 202A having a silicon nitride film or a silicon nitride oxide film 204 formed on its surface and a substrate body 10A are bonded to each other to form a silicon nitride film or a silicon nitride film. Since the silicon nitride oxide film 204 can be located on the semiconductor layer 1a (TFT 30) side of the bonding surface between the substrate main body 10A and the single crystal silicon substrate 202A, the impurities contained in the substrate main body 10A and the substrate main body 10A And the single crystal silicon substrate 202A can completely prevent impurities adsorbed on the bonding surface from diffusing to the semiconductor layer 1a (TFT 30) side.

The element substrate 10 manufactured by the method of manufacturing an element substrate according to the present embodiment is adsorbed on the impurities contained in the substrate body 10A and on the bonding surface between the substrate body 10A and the single-crystal silicon substrate 202A. Since the diffusion of the impurity to the semiconductor layer 1a (TFT 30) side can be completely prevented, deterioration of the characteristics of the TFT 30 can be prevented.

Next, a method of manufacturing the counter substrate 20 and a method of manufacturing a liquid crystal device from the element substrate 10 and the counter substrate 20 will be described.

With respect to the counter substrate 20 shown in FIG. 8, a light-transmitting substrate such as a glass substrate is prepared as the substrate main body 20A, and the second light-shielding film 23 and a peripheral part to be described later are formed on the surface of the substrate main body 20A. A second light shielding film is formed. Second
The light-shielding film 23 and a second light-shielding film serving as a peripheral part to be described later are formed through a photolithography process and an etching process after sputtering a metal material such as Cr, Ni, or Al. These second light-shielding films may be formed of a material such as resin black in which carbon, Ti, or the like is dispersed in a photoresist, in addition to the above-described metal materials.

Thereafter, a transparent conductive thin film of ITO or the like is deposited on the entire surface of the substrate body 20A by sputtering or the like to a thickness of about 50 to 200 nm to form the counter electrode 21. Further, after applying a coating liquid for an alignment film such as polyimide on the entire surface of the counter electrode 21, a rubbing treatment is performed in a predetermined direction so as to have a predetermined pretilt angle, and the like. 3). As described above, the opposing substrate 20
Is manufactured.

Finally, the element substrate 10 and the counter substrate 20 manufactured as described above are bonded together by a sealing material so that the alignment films 16 and 22 are opposed to each other. The liquid crystal device having the above structure is manufactured by sucking, for example, a liquid crystal obtained by mixing a plurality of types of nematic liquid crystals into the space between the substrates to form a liquid crystal layer 50 having a predetermined thickness.

(Overall Configuration of Liquid Crystal Device) The overall configuration of the liquid crystal device of the present embodiment configured as described above will be described with reference to FIGS. FIG. 15 shows the element substrate 10.
16 is a plan view as viewed from the counter substrate 20 side, and FIG. 16 is a cross-sectional view taken along the line HH ′ of FIG.

In FIG. 15, a sealing material 52 is provided on the surface of the element substrate 10 along the edge thereof, and as shown in FIG. 16, substantially the same contour as that of the sealing material 52 shown in FIG. The opposing substrate 20 is fixed to the element substrate 10 by the sealing material 52.

As shown in FIG. 15, on the surface of the counter substrate 20, a second light-shielding film 53, which is made of the same or different material as the second light-shielding film 23, is arranged in parallel with the inside of the sealing material 52, for example. Is provided.

In the element substrate 10, the sealing material 5
2, a data line driving circuit 101 and a mounting terminal 102 are provided along one side of the element substrate 10, and a scanning line driving circuit 104 is provided along two sides adjacent to the one side. ing. If the delay of the scanning signal supplied to the scanning line 3a does not matter, the scanning line driving circuit 1
It goes without saying that 04 may be on one side only.

Further, the data line driving circuits 101 may be arranged on both sides along the sides of the display area (pixel portion). For example, the odd-numbered data lines 6a supply an image signal from a data line driving circuit arranged along one side of the display area, and the even-numbered data lines 6a are arranged along the opposite side of the display area. An image signal may be supplied from the provided data line driving circuit. If the data lines 6a are driven in a comb-tooth shape in this manner, the area occupied by the data line driving circuit can be expanded, so that a complicated circuit can be formed.

Further, a plurality of wirings 105 for connecting between the scanning line driving circuits 104 provided on both sides of the display area are provided on the remaining one side of the element substrate 10, and a second light shielding as a peripheral parting is provided. A precharge circuit may be provided hidden under the film 53. In at least one of the corners between the element substrate 10 and the opposing substrate 20, a conductive material 106 for establishing electric conduction between the element substrate 10 and the opposing substrate 20 is provided.

Further, on the surface of the element substrate 10, an inspection circuit or the like for inspecting the quality, defects, and the like of the liquid crystal device during manufacturing or shipping may be formed. Further, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the surface of the element substrate 10, for example, a driving L mounted on a TAB (tape automated bonding substrate) is used.
The SI may be electrically and mechanically connected via an anisotropic conductive film provided in a peripheral region of the element substrate 10.

Further, TN, for example, is provided on the side of the opposing substrate 20 on which light is incident and on the side of the element substrate 10 on which light is emitted.
(Twisted nematic) mode, STN (super TN) mode, D-STN (dual scan-ST)
N) A polarizing film, a retardation film, a polarizing means, and the like are arranged in a predetermined direction according to an operation mode such as a mode or a normally white mode / normally black mode.

When the liquid crystal device of the present embodiment is applied to a color liquid crystal projector (projection display device), three liquid crystal devices are used as RGB light valves, and each panel has an RGB color valve. The light of each color decomposed via the dichroic mirror for decomposition is respectively incident as projection light. Therefore, in that case, the color filter is not provided on the opposing substrate 20 as described in the above embodiment.

However, the substrate body 2 of the opposite substrate 20
On the surface of the liquid crystal layer 50 on the side of the liquid crystal layer 0A, a predetermined area facing the pixel electrode 9a where the second light shielding film 23 is not formed
A GB color filter may be formed together with the protective film. With such a configuration, the liquid crystal device of the above embodiment can be applied to a color liquid crystal device such as a direct-view or reflection type color liquid crystal television other than the liquid crystal projector.

Further, one pixel per pixel is provided on the surface of the counter substrate 20.
A micro lens may be formed so as to correspond to each of them. By doing so, by improving the light collection efficiency of the incident light,
A bright liquid crystal device can be realized. Furthermore, the opposing substrate 20
A plurality of interference layers having different refractive indices may be deposited on the surface of the device to form a dichroic filter that produces RGB colors by using light interference. According to the counter substrate with the dichroic filter, a brighter color liquid crystal device can be realized.

In the liquid crystal device according to the present embodiment,
Although the incident light is made to enter from the counter substrate 20 side,
Since the first light-shielding film 11a is provided on the element substrate 10, incident light may be incident from the element substrate 10 side and may be emitted from the counter substrate 20 side. That is, even if the liquid crystal device is attached to the liquid crystal projector in this manner, the channel region 1a ′ and the LDD regions 1b, 1b
Light can be prevented from entering c, and a high-quality image can be displayed.

The liquid crystal device according to the present embodiment has the element substrate 10 manufactured by the method for manufacturing an element substrate according to the present embodiment.
, The impurities contained in the substrate body 10A, and the substrate body 10A and the single crystal silicon substrate 20A.
The impurities adsorbed on the surface to be bonded to 2A are the semiconductor layers 1a.
Since the diffusion to the (TFT 30) side can be completely prevented, deterioration of the characteristics of the TFT (transistor element) 30 can be prevented, and the performance is excellent.

(Electronic Apparatus) As an example of an electronic apparatus using the liquid crystal device (electro-optical device) of the above embodiment, a configuration of a projection display device will be described with reference to FIG.

In FIG. 17, a projection type display device 1100
Prepares three liquid crystal devices of the above embodiment, and
FIG. 3 is a schematic configuration diagram of an optical system of a projection type liquid crystal device used as the liquid crystal devices 962R, 962G, and 962B for B.

A light source device 920 and a uniform illumination optical system 923 are employed in the optical system of the projection display device of this embodiment. Then, the projection display apparatus uses the uniform illumination optical system 9.
A color separation optical system 92 as a color separation unit that separates the light flux W emitted from the light into red (R), green (G), and blue (B).
4, three light valves 925R, 925G, and 925B as modulation means for modulating the color light beams R, G, and B;
A color synthesizing prism 910 as a color synthesizing unit for re-synthesizing the modulated color luminous flux, and a projection surface 10
A projection lens unit 906 is provided as a projection unit that performs enlarged projection on the surface of the projection lens 0. Further, a light guide system 927 for guiding the blue light flux B to the corresponding light valve 925B is also provided.

The uniform illumination optical system 923 includes two lens plates 921 and 922 and a reflection mirror 931. The two lens plates 921 and 922 are arranged so as to be orthogonal to each other with the reflection mirror 931 interposed therebetween. Uniform illumination optical system 923
The two lens plates 921 and 922 each include a plurality of rectangular lenses arranged in a matrix. The light beam emitted from the light source device 920 is transmitted to the first lens plate 92.
The light is split into a plurality of partial light beams by one rectangular lens.
Then, these partial light beams are divided into three light valves 925R and 925R by the rectangular lens of the second lens plate 922.
Superimposed around 5G and 925B. Therefore, by using the uniform illumination optical system 923, even when the light source device 920 has an uneven illuminance distribution in the cross section of the emitted light beam, the three light valves 925R, 925G, and 925B are used.
Can be illuminated with uniform illumination light.

Each color separation optical system 924 includes a blue-green reflecting dichroic mirror 941, a green reflecting dichroic mirror 942, and a reflecting mirror 943. First, in the blue-green reflecting dichroic mirror 941, the blue light beam B and the green light beam G included in the light beam W are reflected at right angles, and head toward the green reflecting dichroic mirror 942. The red light beam R passes through the mirror 941, is reflected at a right angle by the rear reflection mirror 943, and is emitted from the emission unit 944 of the red light beam R to the prism unit 910 side.

Next, the green reflecting dichroic mirror 942
Of the blue and green light fluxes B and G reflected by the blue-green reflection dichroic mirror 941,
Only the green light beam G is reflected at a right angle, and is emitted from the emission unit 945 of the green light beam G to the color combining optical system side.

The blue light flux B that has passed through the green reflection dichroic mirror 942 is emitted from the emission section 946 of the blue light flux B to the light guide system 927 side. In this example, the distances from the light emitting portion of the light beam W of the uniform illumination optical element to the light emitting portions 944, 945, and 946 of the color light beams in the color separation optical system 924 are set to be substantially equal.

The red and green luminous fluxes R,
Condensing lenses 951 and 952 are arranged on the emission sides of the G emission sections 944 and 945, respectively. Therefore,
The red and green luminous fluxes R and G emitted from the respective emission sections are incident on these condenser lenses 951 and 952 and are parallelized.

The red and green luminous fluxes R and G thus collimated enter the light valves 925R and 925G and are modulated to add image information corresponding to each color light. That is, the switching of these liquid crystal devices is controlled in accordance with the image information by a driving unit (not shown), whereby the modulation of each color light passing therethrough is performed. On the other hand, the blue light flux B is guided to the corresponding light valve 925B via the light guide system 927, where it is similarly modulated according to image information. Note that the light valves 925R, 925G, and 925B of the present example further include incident-side polarization means 960R, 960G, and 960B, emission-side polarization means 961R, 961G, and 961B, and liquid crystal devices 962R and 962G disposed therebetween. , 962
B and a liquid crystal light valve.

The light guide system 927 includes a light emitting section 94 for the blue light flux B.
6, a condenser lens 954 disposed on the exit side, an incident-side reflection mirror 971, an exit-side reflection mirror 972, an intermediate lens 973 disposed between these reflection mirrors, and disposed on the front side of the light valve 925B. And a condenser lens 953. The blue light flux B emitted from the condenser lens 946 is transmitted through the light guide system 927 to the liquid crystal device 962B.
And modulated. The optical path length of each color beam, that is,
Each liquid crystal device 962R, 962G, 9
The distance to 62B is the longest for the blue luminous flux B, and therefore the loss of light quantity of the blue luminous flux is the largest. However, by interposing the light guide system 927, the loss of light amount can be suppressed.

Each light valve 925R, 925G, 92
The color light fluxes R, G, and B modulated through 5B are incident on a color combining prism 910, where they are combined. The light combined by the color combining prism 910 is enlarged and projected on the surface of the projection surface 100 at a predetermined position via the projection lens unit 906.

The projection display 1100 having the above structure
Is provided with the liquid crystal device of the above embodiment, so that the characteristics of the TFT (transistor element) can be prevented from deteriorating, and the performance is excellent.

[0179]

As described above, according to the present invention,
Since an insulating portion including at least a silicon nitride film or a silicon nitride oxide film is provided between the supporting substrate and the single crystal silicon layer, it is possible to prevent impurities contained in the supporting substrate from diffusing to the single crystal silicon layer side. An SOI substrate that can be completely prevented can be provided.

[0180] Further, by forming a silicon nitride film or a silicon nitride oxide film on the single crystal silicon substrate side and then bonding the single crystal silicon substrate and the support substrate, the impurities contained in the support substrate and the support substrate are removed. And a method for manufacturing an SOI substrate that can completely prevent impurities adsorbed on the surface to be bonded to the single crystal silicon substrate from diffusing to the single crystal silicon layer side.

[0181] An element substrate can be manufactured using the SOI substrate of the present invention. The element substrate of the present invention can be formed using an impurity contained in a supporting substrate or a bonding surface of a supporting substrate and a single crystal silicon substrate. The effect of the impurities adsorbed on the transistor element on the transistor element can be prevented, and the deterioration of the characteristics of the transistor element can be prevented.

Further, by providing the element substrate of the present invention, deterioration of the characteristics of the transistor element can be prevented, and an electro-optical device and an electronic apparatus having excellent performance can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of an SOI substrate according to an embodiment of the present invention.

FIGS. 2A to 2E are process diagrams showing a method for manufacturing an SOI substrate according to an embodiment of the present invention.

FIGS. 3A to 3C are process diagrams showing a method for manufacturing an SOI substrate according to an embodiment of the present invention.

FIGS. 4A to 4D are views showing a bonding pattern of a support substrate and a single crystal silicon substrate in a method for manufacturing an SOI substrate according to an embodiment of the present invention.

FIG. 5 is a sectional view showing a structure of an element substrate according to an embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram of various elements and wiring constituting a pixel portion in the electro-optical device according to the embodiment of the present invention.

FIG. 7 is a plan view of a plurality of pixel groups adjacent to each other on an element substrate in the electro-optical device according to the embodiment of the present invention.

FIG. 8 is a sectional view taken along line A-A 'of FIG.

FIGS. 9A to 9I are process diagrams showing a method for manufacturing an element substrate according to an embodiment of the present invention.

FIGS. 10A to 10D are process diagrams showing a method for manufacturing an element substrate according to an embodiment of the present invention.

FIGS. 11A to 11E are process diagrams showing a method for manufacturing an element substrate according to an embodiment of the present invention.

FIGS. 12A to 12D are process diagrams showing a method for manufacturing an element substrate according to an embodiment of the present invention.

FIGS. 13A to 13C are process diagrams showing a method for manufacturing an element substrate according to an embodiment of the present invention.

FIGS. 14A to 14C are process diagrams illustrating a method for manufacturing an element substrate according to an embodiment of the present invention.

FIG. 15 is a plan view of the element substrate of the electro-optical device according to the embodiment of the present invention, together with the components formed thereon, as viewed from the counter substrate side.

FIG. 16 is a sectional view taken along line HH ′ of FIG.

FIG. 17 is a configuration diagram of a projection display device as an example of an electronic apparatus using the electro-optical device according to the embodiment of the invention.

FIGS. 18A and 18B are process diagrams showing a conventional SOI substrate manufacturing method.

[Explanation of symbols]

 200 SOI substrate 201 support substrate 202 single crystal silicon layer 202A single crystal silicon substrate 203B first silicon oxide film 203A second silicon oxide film 204 silicon nitride film or silicon nitride oxide film 205 insulating part 210 element substrate 220 TFT (transistor element) 208 semiconductor layer 1a semiconductor layer 1a 'channel region 1b low concentration source region (source side LDD region) 1c low concentration drain region (drain side LDD region) 1d High-concentration source region 1e High-concentration drain region 10 Element substrate 10A Substrate body (supporting substrate) 20 Counter substrate 20A Substrate body 11a First light-shielding film 12 First interlayer insulating film 30 Pixel-switching TFT ( Transistor element) 50: liquid crystal layer (electro-optic material layer)

Continued on the front page F-term (reference) 2H092 GA29 JA24 JA37 JA41 JA46 JB51 KA03 KB25 MA13 MA17 NA27 PA01 PA12 QA07 QA10 5F110 AA26 BB01 BB04 CC02 DD02 DD03 DD05 DD13 DD14 DD15 DD17 DD25 EE45 FF02 FF23 GG02 GG12 JG12H HL03 HL05 HL07 HL23 HM15 NN03 NN04 NN22 NN23 NN24 NN25 NN26 NN44 NN45 NN46 NN47 NN54 NN72 NN73 QQ17

Claims (17)

[Claims] 1. An SOI substrate having a single-crystal silicon layer on one surface of a support substrate, wherein the SOI substrate has a single-layer or laminated structure of an insulating film between the support substrate and the single-crystal silicon layer. An SOI substrate, provided with an insulating portion, wherein the insulating portion includes at least a silicon nitride film or a silicon nitride oxide film. 2. The semiconductor device according to claim 1, wherein the insulating portion has a stacked structure of the silicon nitride film or the silicon nitride oxide film and a silicon oxide film formed on an upper surface or a lower surface of the silicon nitride film or the silicon nitride oxide film. The SOI substrate according to claim 1, wherein 3. The S according to claim 1, wherein the supporting substrate has a light transmitting property.
OI substrate. 4. The SOI substrate according to claim 3, wherein the thickness of the silicon nitride film or the silicon nitride oxide film forming the insulating portion is 100 nm or less. 5. The method according to claim 1, wherein:
13. An element substrate, comprising: a transistor element including the semiconductor layer made of the single-crystal silicon layer of the SOI substrate according to item 10. 6. An element substrate according to claim 5, and another substrate disposed so as to face a surface of the element substrate on which the transistor element is formed, and sandwiched between these two substrates. An electro-optical device comprising: an electro-optical material layer. 7. The electro-optical device according to claim 6, wherein a light-shielding film is formed on a lower surface of the silicon nitride film or the silicon nitride oxide film via an insulating film made of a silicon oxide film. 8. An electronic apparatus comprising the electro-optical device according to claim 6. 9. A step of forming a silicon nitride film or a silicon nitride oxide film on one surface of either a single crystal silicon substrate or a support substrate; and forming a silicon oxide film on a surface of the silicon nitride film or the silicon nitride oxide film. Forming, bonding the single crystal silicon substrate and the support substrate using the surface of the silicon oxide film as a bonding surface, and thinning the single crystal silicon substrate bonded to the support substrate And a method for manufacturing an SOI substrate. 10. A step of forming a silicon oxide film on a surface of a single crystal silicon substrate, a step of forming a silicon nitride film or a silicon nitride oxide film on the single crystal silicon substrate side of the silicon oxide film, SOI comprising: a step of bonding the single crystal silicon substrate to a supporting substrate with a surface of the film as a bonding surface; and a step of thinning the single crystal silicon substrate bonded to the supporting substrate. Substrate manufacturing method. 11. A step of forming the silicon oxide film by thermally oxidizing a surface of the single crystal silicon substrate in the step of forming the silicon oxide film, and forming the silicon nitride film or the silicon nitride oxide film Wherein the surface of the single crystal silicon substrate on which the silicon oxide film is formed is nitrided or oxynitrided with dinitrogen monoxide or nitrogen monoxide, so that the silicon nitride film or the silicon nitride oxide film is combined with the silicon oxide film. The method for manufacturing an SOI substrate according to claim 10, wherein the SOI substrate is formed between the single crystal silicon substrates. 12. A step of forming a first silicon oxide film on one surface of either a single crystal silicon substrate or a support substrate; and forming a silicon nitride film or a silicon nitride oxide film on a surface of the first silicon oxide film. Forming a second silicon oxide film on the surface of the silicon nitride film or the silicon nitride oxide film; and forming the single crystal silicon substrate using the surface of the second silicon oxide film as a bonding surface. A method for manufacturing an SOI substrate, comprising: a step of bonding a semiconductor substrate to a support substrate; and a step of thinning the single crystal silicon substrate bonded to the support substrate. 13. A step of forming a first silicon oxide film on a surface of a single crystal silicon substrate, and forming a silicon nitride film or a silicon nitride oxide film on the single crystal silicon substrate side of the first silicon oxide film. Forming a second silicon oxide film on the silicon nitride film or the silicon nitride oxide film on the side of the single crystal silicon substrate; and forming the single crystal using the surface of the first silicon oxide film as a bonding surface. A method for manufacturing an SOI substrate, comprising: a step of bonding a silicon substrate to a support substrate; and a step of thinning the single crystal silicon substrate bonded to the support substrate. 14. In the step of forming the first silicon oxide film, the first silicon oxide film is formed by thermally oxidizing a surface of the single crystal silicon substrate; In the step of forming a silicon film, the surface of the single crystal silicon substrate on which the first silicon oxide film is formed is nitrided or oxynitrided with dinitrogen monoxide or nitrogen monoxide,
Forming the silicon nitride film or the silicon nitride oxide film; and, in the step of forming the second silicon oxide film, thermally oxidizing a surface of the single crystal silicon substrate on which the silicon nitride film or the silicon nitride oxide film is formed. 14. The method for manufacturing an SOI substrate according to claim 13, wherein the second silicon oxide film is formed by the following. 15. A step of forming a light-shielding film on a surface of the support substrate; a step of forming a second silicon oxide film on a surface of the support substrate including the light-shielding film; 12. The method according to claim 10, further comprising: flattening a surface.
3. The method for manufacturing an SOI substrate according to 1. 16. A step of forming a light-shielding film on the surface of the support substrate; a step of forming a third silicon oxide film on the surface of the support substrate including the light-shielding film; 15. The method according to claim 13, further comprising: flattening a surface.
3. The method for manufacturing an SOI substrate according to 1. 17. An SOI substrate manufactured by the method for manufacturing an SOI substrate according to claim 9, wherein a transistor element is formed by the single crystal silicon layer of the SOI substrate. A method for manufacturing an element substrate, comprising a step of forming a semiconductor layer.