JP4548064B2 - Light emitting device array drive device, print head - Google Patents

Description

  The present invention relates to a light emitting element array driving apparatus for driving a plurality of light emitting elements arranged side by side, and more particularly to a light emitting element array driving apparatus for driving a self-scanning light emitting element array.

  In an image forming apparatus employing an electrophotographic system, an electrostatic latent image is obtained by irradiating image information on a uniformly charged photoreceptor by an optical recording means, and then toner is applied to the electrostatic latent image. In addition, the image is formed by visualizing and transferring and fixing on a recording sheet. As such an optical recording means, in addition to an optical scanning method in which a laser is used to scan and expose a laser beam in the main scanning direction, an LED (Light Emitting Diode) has recently been received in response to a request for downsizing of the apparatus. Optical recording means using LED print heads (LPH: LED Print Head) arranged in large numbers in the main scanning direction is employed.

  The LPH generally has an LED array in which a plurality of LED chips in which a large number of LEDs are arranged in a line are arranged, and a large number of rod lenses for imaging the light output from the LEDs on the surface of the photosensitive member (photosensitive drum). And a SELFOC (registered trademark) lens in which are arranged. In the image forming apparatus, each LED of the LPH is driven based on input image data, light is output toward the photosensitive member, and light is imaged on the surface of the photosensitive member by the SELFOC lens. An electrostatic latent image is formed in the sub-scanning direction by relatively moving the photoconductor and LPH.

In particular, recently, as this type of LPH, a self-scanning LED (SLED) is proposed. This SLED employs a thyristor structure as a portion corresponding to a switch for selectively turning on / off a light emitting point.
FIG. 6 shows an example of a circuit configuration of the SLED array 100 using such a thyristor. In this example, the SLED array 100 includes 128 thyristors (S1 to S128), 128 LEDs (LED1 to LED128), 127 diodes (CR1 to CR127), 128 resistors (R1 to R128), and Consists of transfer current limiting resistors (R1A, R2A, R3A) that prevent excessive current from flowing through the signal lines.

  The anode terminals (A1 to A128) that are the input ends of the thyristors (S1 to S128) are connected to the power supply line 102. A power supply voltage VDD (VDD = 5.0 V) is supplied from the power supply 101 to the power supply line 102. Further, the transfer signal CK1 is supplied to the cathode terminals (K1, K3,..., K127) that are the output terminals of the odd-numbered thyristors (S1, S3,..., S127) via the transfer current limiting resistor R1A. Further, the transfer signal CK2 is supplied to the cathode terminals (K2, K4,..., K128) which are the output terminals of the even-numbered thyristors (S2, S4,..., S128) via the transfer current limiting resistor R2A.

  On the other hand, the gate terminals (G1 to G128) which are control terminals of the thyristors (S1 to S128) are connected to the power supply line 103 via resistors (R1 to R128) provided corresponding to the thyristors S1 to S128. The power supply line 103 is grounded (GND). The gate terminals of the LEDs (LED1 to LED128) provided corresponding to the thyristors (S1 to S128) are connected to the gate terminals (G1 to G128) of the thyristors (S1 to S128), respectively. Further, the anode terminals of the diodes (CR1 to CR127) are connected to the gate terminals (G1 to G128) of the thyristors (S1 to S128). Furthermore, the cathode terminals of the diodes (CR1 to CR127) are connected to the gate terminals of the next-stage thyristors, respectively. That is, the diodes (CR1 to CR127) are connected in series. The anode terminal of the diode CR1 receives the transfer signal CKS via the transfer current limiting resistor R3A. Moreover, the cathode terminal of LED (LED1-LED128) has received the lighting signal CKI.

Next, the operation of the SLED array 100 will be described with reference to the timing chart shown in FIG. Here, a case where all the LEDs (L1 to L128) are turned on will be described as an example.
First, when the SLED array 100 is instructed to start operation, a high-level transfer signal CKS as shown in FIG. 7A is supplied. That is, a high-level transfer signal is input to the gate terminal G1 of the thyristor S1 shown in FIG. When the transfer signal CKS is at high level and the transfer signal CK1 is set at low level as shown in FIG. 7B, the thyristor S1 is turned on. Further, after a period Ta has elapsed after the transfer signal CK1 is set to the low level, the transfer signal CK2 is set to the high level.

  As described above, the potential of the gate terminal is the highest among the odd-numbered thyristors (S1, S3,...) To which the low-level transfer signal CK1 is supplied in a state where the transfer signal CKS is set to the high level. That is, the thyristor S1 having a gate voltage equal to or higher than the thyristor threshold is turned on. At this time, since the transfer signal CK2 is set to the high level as shown in FIG. 7C, the potentials of the cathode terminals (K2, K4,...) Of the even-numbered thyristors (S2, S4,...). Remains high and the even-numbered thyristors (S2, S4,...) Remain off. Furthermore, since the lighting signal CKI is set to a high level as shown in FIG. 7D, the voltage of the cathode terminal of the LEDs (LED1 to LED128) is high, and the LEDs (LED1 to LED128) are not lit. Then, when the lighting signal CKI is set from a high level to a low level after a period Tb has elapsed since the transfer signal CK2 has become a high level as shown in FIG. 7D, the potential of the cathode terminal of the LED 1 is changed. It becomes low and LED1 lights up. When the LED 1 is not lit, the lighting signal CKI may be maintained at a high level while the thyristor S1 is on.

Next, when the thyristor S1 is on, the transfer signal CK2 is set to a low level as shown in FIG. 7C, and when the lighting signal CKI is set to a high level, a low-level transfer signal CK2 is supplied. Among the even-numbered thyristors (S2, S4,...), The thyristor S2 having the highest potential at the gate terminal, that is, the gate voltage equal to or higher than the threshold value of the thyristor is turned on, and the LED 1 is turned off (off). When the transfer signal CK1 is set to a high level as shown in FIG. 7B, the thyristor S1 is turned off, the potential of the gate terminal G1 is gradually lowered by the resistor R1, and the potential of the gate terminal G2 is To rise. Along with this, the potentials of the gate terminals G3,.
Thereafter, when the lighting signal CKI is set from the high level to the low level as shown in FIG. 7D, the potential of the cathode terminal of the LED 2 becomes low, and the LED 2 is lit. When the LED 2 is not lit, the lighting signal CKI may be maintained at a high level while the thyristor S2 is on. Similarly, when the thyristor S2 is turned on, the transfer signal CK1 is set to the low level again as shown in FIG. 7B, and when the lighting signal CKI is set to the high level, the thyristor S3 is turned on and the LED2 Turns off (off). Then, as shown in FIG. 7C, when the transfer signal CK2 becomes high level, the thyristor S2 is turned off.

  As described above, in the SLED array 100, the thyristors (S1 to S1) are switched by alternately switching between the high level and the low level while providing the overlapping period (the period of Ta shown in FIG. 7) in which the transfer signals CK1 and CK2 are both at the low level. The LEDs (LED1 to LED128) can be sequentially turned on by sequentially turning on the S128) and setting the lighting signal CKI to the low level after the period Tb shown in FIG. Therefore, the signal lines connected to the SLED array 100 include a total of three transfer signals CKS, CK1, and CK2, one for the lighting signal CKI, and two power lines (one of which is grounded). Only six lines are required, and there is an advantage that the wiring can be simplified.

  In FIG. 7, a period from when the transfer signal CK1 (or CK2) falls to when the other transfer signal CK2 (or CK1) falls is called a thyristor transfer cycle T. A period Ta shown in FIG. 7 is a period from when the transfer signal CK1 (or CK2) falls to when CK2 (or CK1) rises. That is, a period during which both the transfer signals CK1 and CK2 are at a low level, This is a period in which two adjacent thyristors (for example, thyristors S1 and S2) are both turned on. Further, the period Tb shown in FIG. 7 is a period from when the transfer signal CK1 (or CK2) rises to when the lighting signal CKI falls (LED starts to light), and corresponds to the LED to be lit from now on. This is a period necessary for the gate voltage of the thyristor (for example, thyristor S2) to be higher than the gate voltage of the thyristor (for example, thyristor S1) corresponding to the already lit LED.

LPH is also used to correct fluctuations in the sensitivity of the photoconductor due to changes over time such as component variations, photoconductor degradation, and environmental changes such as temperature and humidity, for the purpose of forming high-quality images. Therefore, it is required to uniformly control the exposure amount of all dots. In addition, in order to suppress uneven density due to differences in light spot diameters periodically generated by the SELFOC lens array and unevenness in the amount of light of the LED itself, it is also required to individually control the exposure amount of each dot. Yes.
Therefore, in the SLED, a lighting signal that is output to light each LED is created by a pulse width modulation method, and the number of lighting pulses that are output to each LED, that is, the length of the lighting time is adjusted, thereby exposing all dots. There is a technique for correcting the amount uniformly and correcting the exposure amount of each dot individually (see Patent Document 1).

JP 2002-36628 A (page 7-8, FIG. 12)

  By the way, when the pulse width modulation method as described in Patent Document 1 is adopted, the lighting time of the LED to be lit changes depending on the set correction amount. Here, referring to FIG. 7, the lighting possible time T1 during which the LED can be lit is a time obtained by subtracting the period Ta and the period Tb from the thyristor transfer period T (T1 = T−Ta−Tb). The actual lighting time of the LED is set within the lighting possible time T1. 7 shows an example in which the lighting times of the LEDs 1, 2, 3,... Are set to be the same as the lighting possible time T1.

  However, for example, when a program bug or a setting abnormality occurs, a situation may occur in which the LED lighting time set by pulse width modulation exceeds the lighting possible time T1. In such a case, the lighting time of the LED will cut into the period Ta and the period Tb that are set after the lighting possible time T1.

Here, let us consider a case where the lighting time of the LED 1 shown in FIGS. When the lighting period of LED1 exceeds the lighting-enabled period T1, when the Ta period and the Tb period disappear, the LED1 continues to light even if the thyristor S1 is turned off, so that the potential of the gate G1 of the thyristor S1 is I won't go down. Then, when the LED 2 is next lit, since the thyristor S1 is also kept on in addition to the thyristor S2, a current flows through the LED 1, and both the LED 1 and the LED 2 are lit. End up. Then, when the next LED 3 is to be turned on, the thyristor S1 remains on, and this time, the LED 3 cannot be turned on and the LED 1 is turned on.
When a transfer failure of the thyristor occurs in this way, all the LEDs corresponding to one block of the SLED cause a lighting abnormality, so that a formed image is lost.

  The present invention has been made to solve such a technical problem, and an object of the present invention is to prevent the occurrence of a lighting failure of a light emitting element due to a switching failure of a switch element for lighting the light emitting element. There is to do.

  For this purpose, a light emitting element array driving apparatus to which the present invention is applied is provided corresponding to a plurality of light emitting elements, a power source serving as a power supply source for the plurality of light emitting elements, and the plurality of light emitting elements. By setting the ON state, the power from the power source is supplied to the light emitting element, and a plurality of switch elements each enabling the light emitting element to be turned on, and transfer for sequentially turning on the switch elements for the plurality of switch elements A transfer signal generating means for generating a signal and sequentially turning on the plurality of switch elements, and the transfer signal generating means transfers the ON state from a predetermined switch element to another switch element among the plurality of switch elements. And a lighting prohibiting means for prohibiting the lighting of the light emitting element.

  Here, the plurality of switching elements include a thyristor having an input terminal for inputting power from a power source, an output terminal for outputting input power, and a control terminal for inputting a control signal for outputting the input power from the output terminal. It can be characterized by comprising. In this case, the lighting prohibiting means is a light emitting element until the voltage applied to the control terminal of the thyristor as the predetermined switch element becomes lower than the voltage applied to the control terminal of the thyristor as the other switch element. Can be characterized by prohibiting the lighting of.

  From another viewpoint, the light emitting element array driving apparatus to which the present invention is applied corresponds to a plurality of light emitting elements, a power source serving as a power supply source for the plurality of light emitting elements, and a plurality of light emitting elements. A plurality of switch elements that are provided and set to an on state to supply electric power from the power source to the light emitting elements and each of the light emitting elements can be turned on, and the switch elements are sequentially turned on for the plurality of switch elements. For generating a transfer signal for a plurality of switch elements, and for generating a lighting signal that corrects the amount of light emitted by each light emitting element by adjusting the lighting time for each light emitting element The lighting period of the light emitting element in which the lighting time of the lighting signal created by the signal creating means and the lighting signal creating means is determined based on the generation period of the transfer signal by the transfer signal generating means It does not exceed, and a lighting time adjusting means for adjusting the lighting time of the light emitting element.

  Here, the plurality of switching elements include a thyristor having an input terminal for inputting power from a power source, an output terminal for outputting input power, and a control terminal for inputting a control signal for outputting the input power from the output terminal. It can be characterized by comprising. Further, the lighting signal creation means can create a lighting signal using a pulse width modulation method.

  Furthermore, from another point of view, the print head to which the present invention is applied has an exposure unit that exposes the photoconductor, and an optical unit that forms an image of light exposed from the exposure unit on the photoconductor, The exposure unit is provided corresponding to the plurality of light emitting elements, a power source serving as a power supply source for the plurality of light emitting elements, and the plurality of light emitting elements, and is set to an on state to thereby generate power from the power source. And a plurality of switch elements that respectively turn on the light emitting elements, and a transfer signal for sequentially turning on the switch elements with respect to the plurality of switch elements are generated, so that the plurality of switch elements can be sequentially turned on. A transfer signal generator, a lighting signal generator that creates a lighting signal that corrects the amount of light emitted by each light emitting element by adjusting the lighting time for each light emitting element, and the points of the lighting signal created by the lighting signal generator Time, so as not to exceed the lighting period of the light-emitting element is determined based on the generation period of the transfer signal by the transfer signal generating unit, and a lighting time adjustment unit that adjusts a lighting time of the light emitting element.

  Here, it is detected whether or not the lighting time of the lighting signal created by the lighting signal creation unit exceeds the lighting-enabled period of the light emitting element determined based on the transfer signal generation cycle by the transfer signal generation unit. It may further include a detection unit and a warning output unit that outputs a warning when the detection unit detects that the lighting time exceeds the lighting-enabled period.

  ADVANTAGE OF THE INVENTION According to this invention, generation | occurrence | production of the lighting defect of the light emitting element accompanying the switching defect of the switch element for lighting a light emitting element can be prevented.

The best mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described below in detail with reference to the accompanying drawings.
FIG. 1 is a diagram showing an overall configuration of an image forming apparatus to which the exemplary embodiment is applied, and shows a so-called tandem type image forming apparatus. The image forming apparatus shown in FIG. 1 includes an image process system 10 that forms an image corresponding to gradation data of each color, and a control unit 20 that controls the entire image forming apparatus including the image process system 10. Yes. In the present embodiment, for example, a personal computer (PC) 2, an image reading device (IIT) 3, a FAX modem 4 and the like are connected to the control unit 20, and the control unit 20 receives images received from these. Predetermined image processing is performed on the data.

  The image processing system 10 includes an image forming unit 11 composed of a plurality of engines arranged in parallel at regular intervals in the horizontal direction. The image forming unit 11 is composed of four image forming units 11Y, 11M, 11C, and 11K of yellow (Y), magenta (M), cyan (C), and black (K). A photosensitive drum 12 that is an image carrier (photosensitive member) that forms an image and carries a toner image, a charger 13 that uniformly charges the surface of the photosensitive drum 12, and a photosensitive drum that is charged by the charger 13. 12 includes an LED print head (LPH) 14 that exposes 12 and a developing device 15 that develops a latent image obtained by the LPH 14. Further, the image process system 10 conveys the recording paper in order to multiplex-transfer the toner images of the respective colors formed on the photosensitive drums 12 of the image forming units 11Y, 11M, 11C, and 11K onto the recording paper. A paper transport belt 16, a drive roll 17 that is a roll for driving the paper transport belt 16, and a transfer roll 18 that transfers the toner image on the photosensitive drum 12 to a recording paper are provided.

  The image forming units 11Y, 11M, 11C, and 11K have substantially the same configuration except for the toner stored in the developing device 15. Image signals input from the PC 2, IIT 3, and FAX modem 4 are subjected to image processing by the control unit 20, and are supplied to the image forming units 11Y, 11M, 11C, and 11K through the interface. The image processing system 10 operates based on a control signal such as a synchronization signal supplied from the control unit 20. First, in the yellow image forming unit 11Y, an electrostatic latent image is formed on the surface of the photosensitive drum 12 charged by the charger 13 by the LPH 14 based on the image signal obtained from the control unit 20. The developing unit 15 forms a yellow toner image on the formed electrostatic latent image, and the formed yellow toner image is transferred to a recording sheet on a sheet conveying belt 16 that rotates in the direction of the arrow in the figure. 18 is used for transcription. Similarly, magenta, cyan, and black toner images are formed on the respective photosensitive drums 12 and are multiple-transferred onto a recording sheet on the sheet conveying belt 16 using a transfer roll 18. The multiple transferred toner images on the recording paper are conveyed to a fixing device 19 and fixed on the recording paper by heat and pressure.

  FIG. 2 is a cross-sectional view showing the configuration of the LED print head (LPH) 14. The LPH 14 supports a self-scanning LED array (SLED array) 31 as an exposure means in which a large number of light emitting diodes (LEDs) are arranged as light emitting elements, and a drive for controlling the driving of the SLED array 31. A printed circuit board 32 on which a circuit 40 (see FIG. 3 below) is formed, and a SELFOC (registered trademark) lens array (SLA) as optical means for forming an image of the light beam emitted from each light emitting diode on the photosensitive drum 12. 33, the printed circuit board 32 and the Selfoc lens array 33 are held by a housing 34. Here, the SLED array 31 includes light emitting diodes arranged in the number of pixels in the main scanning direction. In the present embodiment, optical writing (latent image formation) can be performed at a resolution of 1200 dpi corresponding to A3 Nobi, and 15360 LEDs are arranged with high accuracy every about 21.1 μm. .

FIG. 3 is a circuit block diagram showing a circuit configuration of the LPH 14. The LPH 14 includes the SLED array 31 and the drive circuit 40 described above, a level shift circuit 50 provided between the SLED array 31 and the drive circuit 40, and an EEPROM 60.
The SLED array 31 is configured by arranging 120 SLED blocks 35 in series. As will be described later, each of these SLED blocks 35 has 128 light-emitting diodes arranged in a straight line, and is further provided with 128 thyristors that function as switching elements for lighting these light-emitting diodes. ing.

The drive circuit 40 includes a thyristor transfer signal generator 41, a PWM DATA GEN circuit 42, a correction memory 43, a PLL (Phase Locked Loop) circuit 44, a plurality of PWM (Pulse Width Modulation) circuits 45, a plurality of NAND circuits 46, A limit detection circuit 47 is provided.
The thyristor transfer signal generation unit 41 generates a transfer signal for each thyristor of each SLED block 35 constituting the SLED array 31 with reference to the line synchronization signal Lsync input from the control unit 20. The thyristor transfer signal generator 41 also outputs a limit signal to the NAND circuit 46 as will be described later. The PWM DATA GEN circuit 42 serving as a lighting signal generating unit synchronizes with the line synchronization signal Lsync input from the control unit 20, and the image data VDATA input from the control unit 20 to the SLED block 35 configuring the SLED array 31. It converts into lighting data (PWM DATA) corresponding to each light emitting diode, and outputs it. The correction memory 43 stores a light amount correction value for each light emitting diode, and outputs the light amount correction value to the PWM DATA GEN circuit 42. The PWM DATA GEN 42 circuit generates lighting data while correcting the lighting data of each light emitting diode using the light amount correction value read from the correction memory 43. Further, the PLL circuit 44 generates a clock PWM CLK used for pulse width modulation and outputs it to each PWM circuit 45. The number of PWM circuits 45 and NAND circuits 46 corresponding to the number of SLED blocks 35 (120 in this embodiment) is provided. The PWM circuit 45 performs pulse width modulation on the PWM DATA output from the PWM DATA GEN circuit 42 using the clock PWM CLK output from the PLL circuit 44, and outputs a PWM signal. The NAND circuit 46 as the lighting prohibiting means or the lighting time adjusting means calculates a lighting signal using the limit signal output from the thyristor transfer signal generating unit 41 and the PWM signal output from the PWM circuit 45, and copes with it. To the SLED block 35. The Limit detection circuit 47 detects whether the PWM pulse is active during a period Tb described later in the lighting operation of the light emitting diode, and outputs the detection result to the control unit 20.

In addition, the control unit 20 and the thyristor transfer signal generation unit 41, the PWM DATA GEN circuit 42, the correction memory 43, the PLL circuit 44, the PWM circuit 45, the limit detection circuit 47, and the EEPROM 60 perform bidirectional communication using Serial DATA. It is possible.
Here, the light amount correction value stored in the correction memory 43 is originally stored in the EEPROM 60, and is downloaded from the EEPROM 60 to the correction memory 43 when the power is turned on, for example. The frequency of the clock PWM CLK in the PLL circuit 44 can be changed by the control unit 20. This is because the amount of light of all the light-emitting diodes is changed in accordance with a change in sensitivity of the photosensitive drum 12, a change in toner density in the developing device 15, and the like.
Further, between each NAND circuit 46 provided in the drive circuit 40 and each corresponding SLED block 35, a transfer current limiting resistor RID for limiting the amount of current flowing between the two is connected.

  The level shift circuit 50 provided between the thyristor transfer signal generator 41 provided in the drive circuit 40 and each SLED block 35 is connected to the thyristor transfer signal output from the thyristor transfer signal generator 41 of the drive circuit 40. It has a function to shift the level. In this embodiment, the thyristor transfer signal generator 41 and the level shift circuit 50 constitute a transfer signal generator.

FIG. 4 is a circuit diagram showing the configuration of the drive circuit 40, the level shift circuit 50, and the SLED array 31 in the LPH 14. The SLED array 31 is configured by arranging 120 SLED blocks 35 in series as described above. In FIG. 4, one SLED block 35 is representatively shown. .
The SLED block 35 includes 128 thyristors S1 to S128 as switching elements, 128 light emitting diodes (LEDs) L1 to L128 as light emitting elements, 128 diodes D1 to D128, 128 resistors R1 to R128, and Consists of transfer current limiting resistors R1A and R2A that prevent excessive current from flowing through the signal line. The other SLED blocks 35 are similarly configured.
In the following description, a part mainly composed of thyristors S1 to S128 and diodes D1 to D128 for controlling the supply of current to the light emitting diodes L1 to L128 is referred to as a transfer unit.

In the SLED block 35, anode terminals (input terminals) A 1 to A 128 of the thyristors S 1 to S 128 are connected to the power supply line 36. A power supply voltage VDD (VDD = 3.3 V) is supplied to the power supply line 36 from a power supply (not shown).
Further, the transfer signals output from the thyristor transfer signal generator 41 of the drive circuit 40 through the level shift circuit 50 are applied to the cathode terminals (output terminals) K1, K3,... K127 of the odd-numbered thyristors S1, S3,. CK1 is transmitted via the transfer current limiting resistor R1A. On the other hand, transfer signals output from the thyristor transfer signal generator 41 of the drive circuit 40 through the level shift circuit 50 are applied to the cathode terminals (output terminals) K2, K4,..., K128 of the even-numbered thyristors S2, S4,. CK2 is transmitted via the transfer current limiting resistor R2A.

On the other hand, the gate terminals (control terminals) G1 to G128 of the thyristors S1 to S128 are respectively connected to the power supply line 37 via resistors R1 to R128 provided corresponding to the thyristors S1 to S128. The power supply line 37 is grounded (GND).
The gate terminals G1 to G128 of the thyristors S1 to S128 are connected to the gate terminals of the light emitting diodes L1 to L128 provided corresponding to the thyristors S1 to S128, respectively. Furthermore, the cathode terminals of the diodes D1 to D128 are connected to the gate terminals G1 to G128 of the thyristors S1 to S128. The anode terminals of the next-stage diodes D2 to D128 are connected to the gate terminals G1 to G127 of the thyristors S1 to S127, respectively. That is, the diodes D2 to D128 are connected in series with the gate terminals G2 to G127 interposed therebetween.
The anode terminal of the diode D1 is connected to the thyristor transfer signal generator 41 of the drive circuit 40 via the transfer current limiting resistor R2A and the level shift circuit 50, and the transfer signal CK2 is transmitted. The cathode terminals of the light emitting diodes L1 to L128 are connected to the NAND circuit 46 of the drive circuit 40 via a transfer current limiting resistor RID provided outside the SLED block 35, and the lighting signal ΦI is transmitted from the NAND circuit 46. It is supposed to be sent.

  A thyristor transfer signal generator 41 provided in the drive circuit 40 is a tristate buffer B1R that outputs a transfer signal CK1R used to generate the transfer signal CK1, and a transfer that is also used to generate the transfer signal CK1. A tri-state buffer B1C that outputs a signal CK1C is provided. Further, the thyristor transfer signal generator 41 is a tristate buffer B2R that outputs a transfer signal CK2R used to generate the transfer signal CK2, and a tristate that outputs a transfer signal CK2C that is also used to generate the transfer signal CK2. A buffer B2C is provided. These tri-state buffers B1R, B1C, B2R, and B2C can output H (1) and L (0), and can take a state of High-Z (in the following description, expressed as Hiz). It consists of a three-state output circuit. Here, the Hiz state means that the output is substantially in an open state.

  On the other hand, the cathode terminals K1, K3,..., K127 of the odd-numbered thyristors S1, S3,..., S127 are connected to the level shift circuit 50 via the transfer current limiting resistor R1A. In this part of the level shift circuit 50, a circuit is formed in which a signal line connected to the resistor R1B connected to the tristate buffer B1R and a signal line connected to the capacitor C1 connected to the tristate buffer B1C are branched in parallel. Yes. Further, the even-numbered thyristors S2, S4,..., S128 cathode terminals K2, K4,..., K128 and the anode terminal of the diode D1 are connected to the level shift circuit 50 via a transfer current limiting resistor R2A. In this portion of the level shift circuit 50, a circuit is formed in which a signal line connected to the resistor R2B connected to the tristate buffer B2R and a signal line connected to the capacitor C2 connected to the tristate buffer B2C are branched in parallel. Yes.

Next, driving (lighting operation) of the LPH 14 in the image forming operation will be described with reference to a timing chart shown in FIG. Note that the timing chart shown in FIG. 5 shows the case where all the light emitting diodes L1 to L128 perform optical writing (light emission).
(1) First, when a reset signal (RST) (not shown) is input from the control unit 20 to the drive circuit 40, the thyristor transfer signal generation unit 41 of the drive circuit 40 sets the tristate buffer B1C to “H”. As a result, the transfer signal CK1C is output as “H”, and the transfer signal CK1R is output as “H” by setting the tristate buffer B1R to the high level “H” (hereinafter, simply referred to as “H”). In response to this, the level shift circuit 50 sets the transfer signal CK1 to “H”. On the other hand, in the thyristor transfer signal generation unit 41 of the drive circuit 40, the transfer signal CK2R is output as “L” by setting the tristate buffer B2R to a low level (hereinafter simply referred to as “L”). By setting B2C to “L”, the transfer signal CK2C is output as “L”. In response to this, the level shift circuit 50 sets the transfer signal CK2 to “L” and outputs it. As a result, all thyristors S1 to S128 are set to an off state (FIG. 5A).

(2) Subsequent to the reset signal (RST), the line synchronization signal Lsync output from the control unit 20 becomes “H” for a predetermined period (FIG. 5A), so that the SLED array 31 (each SLED block 35 ) Starts. Then, in synchronization with the line synchronization signal Lsync, the thyristor transfer signal generation unit 41 sets the tristate buffer B2C and the tristate buffer B2R to “H” as shown in FIGS. Thus, the transfer signal CK2C and the transfer signal CK2R are set to “H”. In response to this, the level shift circuit 50 sets the transfer signal CK2 to “H” as shown in FIG. 5G (FIG. 5B).
(3) Next, as shown in FIG. 5C, in the thyristor transfer signal generator 41, the transfer signal CK1R is set to L by setting the tristate buffer B1R to “L” (FIG. 5C). In the level shift circuit 50, the charge accumulated in the capacitor C1 flows in the direction toward the resistor R1B, and the potential of the transfer signal CK1 eventually becomes GND. Here, since the potential of the transfer signal CK1C is set to 3.3V, the potential at both ends of the capacitor C1 is 3.3V (= VDD).

(4) Subsequently, as shown in FIG. 5B, the transfer signal CK1C is set to L by setting the tristate buffer B1C of the thyristor transfer signal generator 41 to “L” (FIG. 5D). ), The potential of the transfer signal CK1 is about −3.3 V because charges are accumulated in the capacitor C1. Further, the potential (Vg1) of the gate terminal G1 starts to rise, and Vg1 = CK2 potential−Vf = about 1.9V. Here, the potential of the transfer signal CK2 is about 3.3V, and Vf is the forward voltage of the diode D1 made of AlGaAs, which is about 1.4V. Further, Φ1 potential = G1 potential (Vg1) −Vf = 0.5V. At this time, since the potential of the lighting signal ΦI is 0 V, a potential difference of about 3.8 V is generated between the lighting signal ΦI and the transfer signal CK1.
In this state, the gate current of the thyristor S1 starts to flow along the route of the gate terminal G1, the signal line Φ1, and the transfer signal CK1. At that time, the tri-state buffer B1R of the thyristor transfer signal generation unit 41 is set to high impedance (Hiz) to prevent current backflow.
Thereafter, the thyristor S1 starts to turn on by the gate current flowing through the thyristor S1, and the gate current gradually increases. At the same time, when a current flows into the capacitor C1 of the level shift circuit 50, the potential of the transfer signal CK1 gradually increases.

(5) After elapse of a predetermined time (the time when the potential of the transfer signal CK1 becomes close to GND), the tristate buffer B1R of the drive circuit 40 is set to “L”, and the transfer signal CK1R is set to “L” (FIG. 5 ( e)). As a result, the potential of the gate terminal G1 rises to raise the potential of the signal line Φ1 and the potential of the transfer signal CK1, and accordingly, a current starts to flow to the resistor R1B side of the level shift circuit 50. On the other hand, the current flowing into the capacitor C1 of the level shift circuit 50 gradually decreases as the potential of the transfer signal CK1 increases.
When the thyristor S1 is completely turned on and enters a steady state, a current for maintaining the on state of the thyristor S1 flows to the resistor R1B of the level shift circuit 50, but does not flow to the capacitor. The transfer signal CK1 potential is CK1 potential = (3.3−Vf) × R1B / (R1A + R1B).
When the tristate buffer B1R is set to “L”, the tristate buffer B1C of the drive circuit 40 is set to high impedance (Hiz) as shown in FIG. 5B (FIG. 5E).

(6) When the thyristor S1 is completely turned on, the light emitting diode L1 is ready to be lit (FIG. 5 (H)). Therefore, if the lighting signal ΦI is set to “L” at this time, the light emitting diode L1 can be turned on. This lighting control will be described later.
(7) Next, as shown in FIG. 5F, the transfer signal CK2R is set to “L” by setting the tristate buffer B2R of the thyristor transfer signal generator 41 to “L” (FIG. 5 (g) )), A current flows in the same manner as in FIG. 5C, and a voltage is generated across the capacitor C2 of the level shift circuit 50. In the steady state just before the end of FIG. 5 (g), the potential of the gate terminal G2 is 1.9V. Therefore, the potential at each point is slightly different from that in FIG. This is because the signal line Φ2 potential = gate terminal G2 potential−Vf = 1.9-1.4 = about 0.5 V in the steady state just before the end of FIG. This is because the thyristor S2 does not turn on because this amount is small. In this case, the potential of the transfer signal CK2 is about CK2 potential = 0.5 × R2B / (R2A + R2B) = about 0.15V.

(8) As shown in FIG. 5E, in this state, by setting the tristate buffer B2C of the thyristor transfer signal generator 41 to “L”, the transfer signal CK2C is set to “L” (FIG. 5 (h) )), The potential of the gate terminal G2 starts to rise, and the thyristor S2 is turned on.
(9) Then, as shown in FIGS. 5B and 5C, by setting the tristate buffers B1C and B1R of the thyristor transfer signal generator 41 to “H” at the same time, the transfer signals CK1C and CK1R are simultaneously set to H. Then (FIG. 5 (i)), the transfer signal CK1 becomes “H”. When the transfer signal CK1 becomes “H”, the thyristor S1 is turned off, and by discharging through the resistor R1, the potential of the gate terminal G1 gradually decreases. At that time, the potential of the gate terminal G2 of the thyristor S2 becomes 3.3V and is completely turned on.
(10) When the thyristor S2 is completely turned on, the light emitting diode L2 is ready to emit light. Therefore, if the lighting signal ΦI is set to “L” at this time, the light emitting diode L1 can be turned on. In a normal case, since the potential of the gate terminal G1 is already lower than the potential of the gate terminal G2, the light emitting diode L1 does not turn on.

  Further, as shown in FIG. 5B, since the tristate buffer B1C of the thyristor transfer signal generation unit 41 is set to high impedance (Hiz) (FIGS. 5E to 5H), the CK1 potential = Although (3.3−Vf) × R1B / (R1A + R1B), the capacitor C1 of the level shift circuit 50 is not charged so much, and a large potential difference does not occur in the capacitor C1. For this reason, when the transfer signals CK1C and CK1R are simultaneously set to “H” (FIG. 5 (i)), it is possible to suppress the occurrence of a large spike potential in the transfer signal CK1, and thus the drive circuit passes through the resistor R1B. A large current does not flow instantaneously through 40, and an excessive load can be suppressed from being applied to the drive circuit 40.

That is, if the transfer signal CK1C is set to L before the transfer signals CK1 and CK2 in FIG. 5 (i) are simultaneously set to H, the potential of the transfer signal CK1 is present at both ends of the capacitor C1 of the level shift circuit 50. Specifically, (3.3−Vf) × R1B / (R1A + R1B) is generated. In this state, when the transfer signals CK1C and CK1R are simultaneously set to H (FIG. 5 (i)), a large current that instantaneously flows to the drive circuit 40 through the resistor R1B is generated, and an excessive load is applied to the drive circuit 40. It will take.
On the other hand, in the present embodiment, the tristate buffer B1C of the drive circuit 40 is set to high impedance (Hiz) before the transfer signals CK1C and CK1R in FIG. No current flows into the capacitor C1, and a large potential difference does not occur. For this reason, since generation of a large spike potential in the transfer signal CK1 is suppressed, it is possible to prevent a large current from flowing into the drive circuit 40.

  (11) Thereafter, the other light emitting diodes L3 to L128 can be sequentially turned on by performing the same control. Then, after the last light emitting diode L128 is turned off, the next reset signal (RST) is input, and the light emitting diodes L1 to L128 are turned on in the same process.

  In FIG. 5, a period from when the transfer signal CK1 (or CK2) falls to when the other transfer signal CK2 (or CK1) falls is called a thyristor transfer cycle T. A period Ta shown in FIG. 5 is a period from when the transfer signal CK1 (or CK2) falls to when CK2 (or CK1) rises. That is, a period during which both the transfer signals CK1 and CK2 are at a low level, This is a period in which two adjacent thyristors (for example, thyristors S1 and S2) are both turned on. Further, a period Tb shown in FIG. 5 is a period from when the transfer signal CK1 (or CK2) rises to when the lighting signal CKI falls (LED starts to light), and corresponds to the LED to be lit from now on. This is a period necessary for the gate voltage of the thyristor (for example, thyristor S2) to be higher than the gate voltage of the thyristor (for example, thyristor S1) corresponding to the already lit LED.

Next, the supply of the lighting signal in driving the LPH 14 described above will be described.
When the image data VDATA is input from the control unit 20 to the PWM DATA GEN circuit 42, the PWM DATA GEN circuit 42 creates lighting data (PWM DATA) for the light emitting diode to be turned on. Here, the PWM DATA GEN circuit 42 uses the light amount correction value read from the correction memory 43 and creates lighting data (PWM DATA) in consideration of the entire correction value. Accordingly, lighting data in which the lighting pulse length (lighting time) is set is created for each light emitting diode to be turned on.

  Next, the PWM circuit 45 performs pulse width modulation on the PWM DATA output from the PWM DATA GEN circuit 42 using the clock PWM CLK output from the PLL circuit 44, and the PWM signal shown in FIG. Is output. On the other hand, the thyristor transfer signal generator 41 outputs a limiter signal (Limiter) in which “H” is set only in the period Tb shown in FIG. Then, the NAND circuit 46 generates a lighting signal ΦI shown in FIG. 5K based on the input PWM signal and limiter signal, and outputs it to each SLED block 35.

  Consider a case where a PWM signal as shown in FIG. 5I is output from the PWM DATA GEN circuit 42 to the light emitting diodes L1 to L128, for example. The pulse width (length of time) of the PWM signal is set for each of the light emitting diodes L1, L2,..., L127, L128 by taking the light quantity correction value and the like into consideration. Here, for example, it is assumed that the PWM signal for L1 becomes large due to some cause, for example, exceeds the lighting possible period T1 and bites into the period Ta and the period Tb. If the light emitting diode L1 is turned on using the PWM signal as it is, the thyristor S1 remains turned on even after the period Tb has elapsed, and the potential of the gate G1 of the thyristor S1 cannot be lowered. On the other hand, since the potential of the gate G2 of the thyristor S2 is increased, the light emitting diode L1 is also turned on together with the light emitting diode L2 at the next lighting timing.

Here, in the present embodiment, the PWM signal and the limiter signal are input to the NAND circuit 46 to generate the final lighting signal ΦI. That is, by using the limiter signal, the light emitting diode L1 is not forcibly turned on at least during the period Tb in which the thyristor transfer is performed from the thyristor S1 to the next thyristor S2 (from the previous thyristor Sn to the next thyristor Sn + 1). A simple lighting signal ΦI is created. Therefore, in the period Tb, the lighting signal ΦI can be always set to “H”, and the lighting of the light emitting diode can be prohibited (turned off). As a result, the potential of the gate G1 of the thyristor S1 can be made lower than the potential of the gate G2 of the thyristor S2 during the period Tb, and the light emitting diode L2 next to the light emitting diode L1 (the light emitting diode Ln + 1 next to the light emitting diode Ln). Can be lit.
On the other hand, from another point of view, the present embodiment can be said to adjust the lighting pulse width (corresponding to the lighting time) using the limit signal so as not to exceed the lighting-enabled period of the light emitting diode L1. .

  In the present embodiment, the limit detection circuit 47 monitors whether the pulse width of each PWM signal exceeds the lighting-enabled period T1 permitted for the light emitting diode. If it is detected that the lighting possible time T1 has been exceeded, the detection result is output to the control unit 20. In this way, for example, the control unit 20 can notify the user that an abnormality has occurred in the LPH 14 via, for example, a display device or the like. For this reason, it is also possible to prevent the occurrence of image defects due to poor lighting.

It is a figure which shows the image forming apparatus with which the LED print head (LPH) with which this Embodiment is applied was mounted | worn. It is sectional drawing explaining the structure of LPH. It is a figure which shows the circuit structure of LPH. It is a figure which shows the circuit structure of a drive circuit, a level shift circuit, and a self-scanning type LED array (SLED array). 6 is a timing chart illustrating LPH driving in an image forming operation. It is a figure which shows the circuit structure of a self-scanning type LED array (SLED array). It is a timing chart explaining the drive of an SLED array.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Main body, 2 ... Personal computer (PC), 3 ... Image reader (IIT), 4 ... FAX modem, 10 ... Image process system, 11 (11Y, 11M, 11C, 11K) ... Image forming unit, 12 ... Photosensitive Body drum, 13 ... charger, 14 ... LED print head (LPH), 15 ... developer, 20 ... control unit, 31 ... self-scanning LED array (SLED array), 32 ... printed substrate, 33 ... selfoc lens array 34 ... Housing, 35 ... SLED block, 40 ... Drive circuit, 41 ... Thyristor transfer signal generator, 42 ... PWM DATA GEN circuit, 43 ... Correction memory, 44 ... PLL circuit, 45 ... PWM circuit, 46 ... NAND circuit, 47 ... Limit detection circuit, 50 ... Level shift circuit, 60 ... EEPROM

Claims (8)

A plurality of light emitting elements;
A power source serving as a power supply source for the plurality of light emitting elements;
A plurality of switch elements that are provided corresponding to the plurality of light emitting elements and that are set to an on state to supply power from the power source to the light emitting elements, and each of the light emitting elements is in a lighting enabled state;
A transfer signal generating means for generating a transfer signal for sequentially turning on the switch elements with respect to the plurality of switch elements, and enabling the plurality of switch elements to be turned on sequentially;
A lighting signal creating means for creating a lighting signal by correcting the light emission quantity for each light emitting element by adjusting the lighting time for each light emitting element;
The lighting time of the lighting signal created by the lighting signal creating means is for transferring the ON state from a predetermined switch element to another switch element among the plurality of switch elements in the transfer signal generating means. A light emitting element array driving device including lighting prohibiting means for permitting lighting of the light emitting element before the transfer period and prohibiting lighting of the light emitting element during the transfer period when overlapping with the transfer period .   The plurality of switch elements include a thyristor having an input terminal for inputting power from the power source, an output terminal for outputting input power, and a control terminal for inputting a control signal for outputting the input power from the output terminal. The light-emitting element array driving apparatus according to claim 1, comprising:   The lighting prohibiting means, until the voltage applied to the control terminal of the thyristor as the predetermined switch element is lower than the voltage applied to the control terminal of the thyristor as the other switch element. 3. The light emitting element array driving apparatus according to claim 2, wherein lighting of the light emitting elements is prohibited. A plurality of light emitting elements;
A power source serving as a power supply source for the plurality of light emitting elements;
A plurality of switch elements that are provided corresponding to the plurality of light emitting elements and that are set to an on state to supply power from the power source to the light emitting elements, and each of the light emitting elements is in a lighting enabled state;
A transfer signal generating means for generating a transfer signal for sequentially turning on the switch elements with respect to the plurality of switch elements, and enabling the plurality of switch elements to be turned on sequentially;
A lighting signal creating means for creating a lighting signal by correcting the light emission quantity for each light emitting element by adjusting the lighting time for each light emitting element;
When the lighting time of the lighting signal created by the lighting signal producing means has exceeded a lighting period of said light emitting element is determined based on the generation period of the transfer signal by the transfer signal generating means, said lighting A light emitting element array driving device including lighting time adjusting means for adjusting a lighting time of the light emitting element so that the light emitting element emits light during the possible period and does not emit light after the lighting possible period .   The plurality of switch elements include a thyristor having an input terminal for inputting power from the power source, an output terminal for outputting input power, and a control terminal for inputting a control signal for outputting the input power from the output terminal. The light-emitting element array driving device according to claim 4, comprising:   6. The light emitting element array driving device according to claim 5, wherein the lighting signal generating means generates the lighting signal using a pulse width modulation method. Exposure means for exposing the photoreceptor;
Optical means for imaging light exposed from the exposure means on the photoreceptor,
The exposure means includes
A plurality of light emitting elements;
A power source serving as a power supply source for the plurality of light emitting elements;
A plurality of switch elements that are provided corresponding to the plurality of light emitting elements and that are set to an on state to supply power from the power source to the light emitting elements, and each of the light emitting elements is in a lighting enabled state;
A transfer signal generator for generating a transfer signal for sequentially turning on the switch elements for the plurality of switch elements, and enabling the plurality of switch elements to be turned on sequentially;
A lighting signal creating unit that creates a lighting signal by correcting the amount of light emitted by each light emitting element by adjusting the lighting time for each light emitting element;
When the lighting time of the lighting signal created by the lighting signal generator has exceeded the lighting period of the light emitting element is determined based on the occurrence period of the transfer signal by the transfer signal generating unit, the lighting A lighting time adjusting unit that adjusts a lighting time of the light emitting element so that the light emitting element emits light during the possible period and does not emit light after the lighting possible period. Print head. Detects whether the lighting time of the lighting signal created by the lighting signal creating unit exceeds the lighting-enabled period of the light emitting element determined based on the generation period of the transfer signal by the transfer signal generating unit A detector to perform,
The print head according to claim 7, further comprising a warning output unit that outputs a warning when the detection unit detects that the lighting time exceeds the lighting-enabled period.

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