JP2002036628A - Imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an imaging apparatus employing an SLED as the light source of an exposing means in which uneven density is corrected accurately and the SLED is controlled inexpensively trough a simple arrangement. SOLUTION: At an LPH drive section 26, a control section 126 controls the quantity of exposure uniformly for all LEDs (all dots) of an SLED when lighting time reference data is set at a total quantity of light designating section 112. On the other hand, lighting time of each LED 60 in a possible lighting time is corrected such that uneven density is eliminated by correcting the lighting time reference data based on uneven density correction data at an operating section 142. Since both the quantity of light control and the correction of uneven density are effected by lighting time control, uneven density can be corrected stably even if the quantity of exposure of all dots is varied by the quantity of light control.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus, and more particularly, to an image forming apparatus to which a self-scanning LED is applied as a light source of an exposing means for forming an image by exposing a photosensitive member.

[0002]

2. Description of the Related Art Conventionally, as a print head of an image forming apparatus such as a printer, a copying machine, a facsimile, etc., an LED print head (LPH: LED Print) using an LED as a light source.
Head) is used.

In recent years, a self-scanning LED (SLE) has been
D: Self-scanning LED) has been proposed. The SLED employs a thyristor structure as a portion corresponding to a switch for selectively turning on / off a light emitting point, and by applying this thyristor structure, the switch section can be arranged on the same chip as the light emitting point. It is a light emitting light source array.

In this SLED, the on / off timing of the switch can be selectively emitted by two signal lines, so that the data line can be shared.
Wiring can be simplified.

Here, as shown in FIG. 17, an explanation will be given using an equivalent circuit of the thyristor 90.
When the trigger is set to a high level when is off, the current It
r flows to the point P, and at the same time, the current Ib2 flows from the point P to the base of the transistor Q2 (Itr ≒ Ib2). As a result, the transistor Q2 turns on, and this transistor Q2
Collector current flows. That is, the transistor Q1
, The base current Ib1 flows, and the transistor Q1 is also turned on.

When the transistor Q1 is turned on, the collector current IC1 of the transistor Q1 flows, the voltage at the point P rises, and the current Itr stops flowing. However, since the collector current Ic1 of the transistor Q1 flows to the base of the transistor Q2 (current Ib2), the ON state of the transistor Q2 is maintained.

As a result, even if the trigger goes low, the transistors Q1 and Q2 remain on. In this state, the voltage VEE is held and the LED
Can be turned on, and a predetermined light amount can be obtained by performing pulse width modulation.

In order to turn off the thyristor 90, no base current flows through the transistor Q2 even when the transistor Q1 is on. That is, the thyristor 90
In the self-holding state, when the voltage VEE is set to 0 V, the voltage at the point P becomes high impedance, the electric charge stored in the parasitic capacitance is discharged through the high resistance R, and as a result, the transistor Q1 and the transistor Q2 are turned off.

Here, the actual operation speed is determined by the Turn On Time (rise time) and the Turn Off Time of each thyristor.
(Fall time). That is, in response to changes in the transfer control clocks (the two control signals) V1 and V2, the time (Turn O) until the thyristor is actually turned on.
n Time) cannot send a data signal (image signal). Further, since the thyristor uses the saturated state of the PNP connection, the Turn Off Time is much longer than the Turn On Time. Therefore, for example, from the Turn Off of the Nth (P is a positive integer) point P to the N + 2nd Turn O
Until n, the N-th LED is turned on until N
The third point P needs to go down.

In the case of the array-like light source as described above, the variation in the light amount at the light emitting points causes streaks in the image, so it is necessary to correct the variation in the light amount. In particular, when a SELFOC lens array is applied as the optical system, even if the light amount of the light emitting point itself does not vary,
Since the SELFOC lens array itself has an uneven transmittance, structurally, a variation in light amount occurs.

For this reason, Japanese Patent Laid-Open Publication No. Hei 4-23367 proposes an SLED in which a drive circuit can be simplified and a substrate can be downsized. In this SLED, by controlling the drive current, in particular, independent control of dots can be performed by a simple control circuit.

Japanese Patent Application Laid-Open No. 10-297017 discloses an SLED in which each LED is turned on by intensity modulation in accordance with an image signal, and a driving current at this time is corrected based on correction data for unevenness in light amount in the SLED. Has been proposed. In this SLED, in particular, the light amount unevenness due to the internal wiring resistance in the SLED chip is used as a correction target.

By the way, generally, the following control is required for LPH to form a high quality image. In order to compensate for fluctuations in the sensitivity of the photoconductor due to changes over time such as component variations, film thinning of the photoconductor, and environmental changes such as temperature and humidity, the exposure amount by the LPH is uniformly controlled for all dots ( Hereinafter, “light amount control”). In order to correct the unevenness of the light spot diameter and light amount that periodically occurs in the rod lens array, the position error of the dots, and the density unevenness caused by the LPH caused by the wiring resistance, the exposure amount is independently controlled for each dot. (Hereinafter referred to as “density unevenness correction”).

In general, it is necessary to secure a control range of about ± 50% for light quantity control. However, it is known that driving an LED at high speed causes overshoot. The power varies with the intensity of the light beam.

[0015]

However, in the case of controlling the exposure amount by driving current control, that is, intensity modulation, as in the prior art, the light intensity control and the density unevenness correction are performed, so that the correction ratio of the density unevenness correction is reduced. Will change. That is, even if the density unevenness is corrected to eliminate the density unevenness, there is a problem that the density unevenness occurs when the light beam intensity of all the dots is changed by the light amount control.

Further, in the case of an LPH using an SLED as a light source, the lighting duty must be reduced as compared with a normal LPH, and a high-speed D / A converter, an operational amplifier, and the like are required, resulting in an increase in cost. There was also the problem of getting lost. Furthermore, even if the SLED is formed into an IC because a high-precision resistor or the like is required, the number of external parts is large, the number of pins of the IC, the board area, and the like are large, and the size cannot be reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide an image forming apparatus using an SLED as a light source of an exposure means, which can perform density unevenness correction with high accuracy. . In addition to the above objects, it is another object of the present invention to provide an image forming apparatus capable of controlling an SLED with an inexpensive and simple configuration.

[0018]

In order to achieve the above object, the present invention is directed to a self-scanning LED as a light source of an exposure means for forming an image by exposing a photoreceptor.
And a setting unit for setting a lighting time reference value for controlling the entire light amount, and the lighting based on a correction amount of each pixel for correcting density unevenness of the image. Comprising a time reference value, calculating means for calculating the lighting time of each pixel, and lighting control means for controlling lighting of the LED of each pixel based on the lighting time obtained by the calculating unit. Features.

According to the first aspect of the present invention, the setting means sets the lighting time reference value for controlling the overall light quantity of the self-scanning LED. In the calculating means, based on the correction amount of each pixel for correcting the density unevenness of the image,
The lighting time of each pixel is obtained by correcting the set lighting time reference value. Based on the lighting time, lighting of the LED of each pixel is controlled by the lighting control means. That is, since both the light amount control and the density unevenness correction are performed by the LED lighting time control, even if the exposure amount of all dots is changed by the light amount control by changing the setting value of the lighting time reference value, the density is stably maintained. Unevenness correction can be performed.

As described in claim 2,
The image processing apparatus may further include a correction amount storage unit that stores a correction amount of each of the pixels. In this case, the calculation unit includes:
The lighting time is obtained each time the LED of each pixel is lit. Alternatively, as described in claim 3, a lighting time storage means for storing a lighting time of each pixel obtained by the arithmetic means may be further provided. In this case, an LED of each pixel is provided. The lighting time of each pixel previously stored in the lighting time storage means is used for lighting.

Further, as described in claim 4,
A reference clock generating means for generating a reference clock for dividing the lightable period of the LED into a predetermined number, a counting means for counting the number of reference clocks in the lightable period, a counting result by the counting means, and Comparing means for comparing the calculated lighting time with the calculated lighting time, wherein the setting means sets the lighting time reference value using the reference clock as a basic unit, and the lighting control means controls the lighting means by the comparing means. The lighting of the LED of each pixel may be controlled based on the comparison result. In this case, as described in claim 5, the reference clock generating means is a PLL.
It may be a circuit.

Also, as described in claim 6,
It is preferable that the image processing apparatus further includes a quantization error correction unit that corrects a quantization error caused by the arithmetic unit.

Further, as described in claim 7,
The lighting period of the LED may be from the timing when the period up to the end timing of the lighting enabled period coincides with the lighting time to the end timing.

[0024]

Next, an example of an embodiment according to the present invention will be described in detail with reference to the drawings.

(Overall Configuration) FIG. 1 is a schematic diagram of the overall configuration of an image forming apparatus to which the present invention is applied. As shown in FIG. 1, the image forming apparatus 10 includes a photosensitive drum 12 that rotates at a constant speed in the direction of arrow A.

Around the photosensitive drum 12, a charger 14, an LED printer head (LPH) 16, a developing device 18, a transfer roller 20, a cleaner 22, an erase lamp 24 are arranged along the rotating direction of the photosensitive drum 12. Are arranged in order.

That is, the photosensitive drum 12 is connected to the charger 1
After the surface is uniformly charged by 4, the LPH 16 irradiates a light beam to form a latent image on the photosensitive drum 12. The LPH 16 is connected to the LPH drive unit 26, is controlled to be turned on by the LPH drive unit 26, and emits a light beam based on image data.

A toner is supplied to the formed latent image by a developing device 18 to form a toner image on the photosensitive drum 12. The toner image on the photosensitive drum 12 is transferred by the transfer roller 20 onto a sheet 28 conveyed from a sheet tray (not shown). Photoreceptor drum 1 after transfer
The toner remaining in 2 is removed by the cleaner 22, the charge is removed by the erase lamp 24, then charged again by the charger 14, and the same processing is repeated.

On the other hand, the sheet 28 onto which the toner image has been transferred is
Fixing device 3 including pressure roller 30A and heating roller 30B
And is subjected to a fixing process. Thus, the toner image is fixed, and a desired image is formed on the paper 28. The sheet 28 on which the image is formed is discharged out of the apparatus.

Around the photosensitive drum 12 and between the developing device 18 and the transfer roller 20, the photosensitive drum 12
, A density sensor 32 is provided. The density sensor 32 detects the density of the toner image on the photosensitive drum 12 when, for example, a test patch (density sample) is formed. The output of the density sensor 32 is L
The LPH driving unit 26 is connected to the PH driving unit 26 and outputs the LPH based on the density reading result of the density sensor 32.
16 is controlled.

(Detailed Configuration of LPH) Next, the configuration of the LPH 16 will be described in detail. As shown in FIG. 2, the LPH 16 is a print in which the LED array 50 and a circuit 70 (detailed later) for supporting the LED array 50 and supplying various signals for controlling the driving of the LED array 50 are formed. The substrate 52 and the self-fox lens array (S
LA) 54.

The printed circuit board 52 is disposed in the housing 56 with the mounting surface of the LED array 50 facing the photosensitive drum 12, and is supported by a leaf spring 58.

The LED array 50 is, as shown in FIG.
A plurality of LEDs 60 are arranged along the axial direction of the photosensitive drum 12.
Are arranged in series and a plurality of SLED chips 62 are arranged in series.
A light beam can be irradiated at a predetermined resolution in the direction of the second axis. In the present embodiment, 58 SLED chips 62 are aligned in series and LE
A D array 50 is configured, and each SLED chip 62
Has 128 LEDs 60 at 600 SPI (spots pe
r inch).

The SLA 54 is, as shown in FIG.
The light beam emitted from each LED 60, supported by the holder 64, forms an image on the photosensitive drum 12.

Next, the circuit configuration on the printed board 52 will be described. FIG. 4 shows a circuit 70 formed on the printed circuit board 52.

As shown in FIG. 4, the circuit 70 includes E
An EPROM 72 and 58 SLED chips 62 are provided. In the following, when distinguishing each SLED chip 62, a description will be given by giving chip numbers 1 to 58 to each SLED chip 62.

The circuit 70 includes a power supply line 74 and GND.
A (ground) line 76 is provided, and a predetermined voltage (5 V) is supplied from a power supply device (not shown). Further, the circuit 70 is connected to the LPH driving unit 26,
The SCL signal and the SDA signal are input and output to and from the LPH drive unit 26. Further, the circuit 70 includes
A lighting control signal ΦI (1 to 58: chip number) for each SLED chip 62, transfer signals CK1 and CK2, and a start signal ΦS are input from the LPH drive unit 26.

The EEPROM 72 stores density unevenness correction data for each pixel. The writing and reading of the density unevenness correction data to and from the EEPROM 72 are performed by a signal transmitted / received to / from the control unit 126 (see FIG. 6) via the LPH driving unit 26 (a write signal from the control unit 126: SC
L signal, read signal: SDA signal). Also, E
The EPROM 72 includes a power supply line 74 and a GND line 7
6 and a predetermined voltage (5 V) as a drive voltage.
Is supplied.

Each SLED chip 62 has a VGA terminal 7
8, a SUB terminal 80, a ΦI input terminal 82, a CK1 input terminal 84, a CK2 input terminal 86, and a ΦS input terminal 88.

The VGA terminal 78 is connected to the GND line 76, SU
The B terminal 80 is connected to the power supply line 74 and each SL
A predetermined voltage (5V) is supplied to the ED chip 62.

Each SLED chip 62 receives a lighting control signal φI for the SLED chip 62 via a φI input terminal 82. Also, the CK1 input terminal 84,
Transfer signals CK1 and CK2 and a start signal ΦS are input via a CK2 input terminal 86 and a ΦS input terminal 88, respectively.

Next, referring to FIG.
SLED provided to drive each LED 60
The circuit configuration inside the chip 62 will be described. Note that the circuit configuration for driving each LED 60 is basically a combination of a single drive circuit shown in FIG.
A detailed description of the thyristor 90 and the like is omitted here.

In the SLED chip 62, the SLED 6
A thyristor 90 is provided for each of the plurality (128) of LEDs 60 arranged in the LED array 2, and the anode side of each thyristor 90 is connected to the SUB terminal 80.

The point P1 connected to the gate side of the first-stage thyristor 90 (the number following the point P is a plurality of LEDs 6
0 is connected to the ΦS input terminal 88, and a start signal ΦS (voltage) is applied to the point P1 as a trigger for lighting the LED 60 of the SLED chip 62.

The points P (1 to 128) connected to the gate of the thyristor 90 in each stage are connected in series via a diode 92. The points P (1 to 12)
8) are connected to the base line 96 connected to the VBA terminal 78 via the resistor 94, respectively. Base line 96
Is designed to maintain a predetermined voltage at the first stage, and decrease by a predetermined potential (Vf) as going to each stage.

The point P (1 to 128) is
The cathode side of the LED 60 is connected to the ΦI input terminal 82 and to a lighting control signal line 98 that outputs a pulse wave serving as a lighting control signal for each stage. When the lighting control signal is at a low level (L), the thyristor 9 having the point P (1-128) as a gate
If 0 is ON, the LED 60 is turned on.

The cathode side of the odd-numbered thyristor 90 is connected to the first transfer line 100, and the cathode side of the even-numbered thyristor 90 is connected to the second transfer line 102. CK2 is supplied. According to the transfer signals CK1 and CK, the point P (1 to 12)
The potential of 8) is increased by a predetermined potential (Vf). That is, the potential of the point P sequentially reaches the predetermined potential at which the LED 60 can be turned on from the initial point P1 to the subsequent stage, and the SLED chip 62 can perform self-scanning.

(Detailed Configuration of LPH Driving Unit) Next, the configuration of the LPH driving unit 26 will be described in detail with reference to FIG.

The LPH driving section 26 includes the image data dividing section 1
10, overall light quantity instructing unit 112, density unevenness correction memory 1
14, oscillator 116, timing generator 118, PLL
The circuit 120 is provided. The LPH drive unit 26 includes a lighting control signal generation unit 12 for each SLED chip 62.
4 are provided.

Image data is serially transmitted to the image data dividing section 110 from an image memory (not shown). The image data dividing unit 110 divides the transmitted image data into the 1st to 128th dots, the 129th to 256th dots,... The image data is output to the corresponding lighting control signal generator 124. In the following, the image data will be described as 1-bit data for simplicity of description.

The total light amount instructing unit 112 is controlled by the control unit 126, which controls the operation of the image forming apparatus 10, to control the exposure amount of the LPH 16 uniformly for all dots based on the detection result of the density sensor 32. Lighting time reference data of 0 to 255) is input. That is, the control unit 1
26 corresponds to the setting means of the present invention.

The total light quantity instructing section 112 holds the lighting time reference data and outputs the lighting time reference data to all the lighting control signal generating sections 124 at a predetermined timing.

The density unevenness correction memory 114 is a line memory, and stores 4-bit (0 to 15) density unevenness correction data read from the EEPROM 72 by the control unit 126. The density unevenness correction memory 114 stores the density unevenness correction data in the first to 128th dots, 129 to 2
56th dot, ..., 7297-7424 dots and each S
The data is divided into density unevenness correction data for each LED chip 62, and the divided density unevenness correction data is divided into the corresponding lighting control signal generators 1 in synchronization with the LED lighting timing.
24. The density unevenness correction memory 11
Reference numeral 4 corresponds to the correction amount storage means of the present invention.

The oscillator 116 oscillates at a predetermined frequency,
An oscillation signal (clock signal) is output to the timing generator 118. The timing generator 118 generates transfer signals CK1 and CK2 and a start signal voltage Vs based on the oscillation signal. The start signal voltage Vs is supplied to the circuit 70 as a start signal ΦS via the resistor 128.

Further, the timing generation section 118 includes an LED
A BCLK signal having one cycle of the lighting enabled period (T1) of 60 is generated (see FIG. 7) and supplied to the PLL circuit 120. The PLL circuit 120 generates a clock signal for dividing the lighting enabled period (T1) into 256 based on the BCLK signal. That is, this PLL circuit 12
0 corresponds to the reference clock generation means of the present invention.

More specifically, the PLL circuit 120 is configured as shown in FIG.
As shown in the figure, a voltage controlled oscillator 130 and a frequency divider 132
And a phase comparator 134. Voltage controlled oscillator 130 outputs a clock signal at a frequency based on the control voltage. In the present embodiment, a control voltage corresponding to a frequency that divides the lighting possible period (T1) into 256 is supplied, a clock signal of the frequency is generated, and the clock signal is output to all the lighting control signal generators 124.
Further, the clock signal output from the voltage controlled oscillator 130 is also branched to the frequency divider 132 and input to the frequency divider 1.
32 divides the frequency of the clock signal output from the voltage controlled oscillator 130 based on the frequency division ratio set by the control unit 126. In this embodiment, the division ratio is 256
Is set.

The phase comparator 134 receives BC as a reference signal.
The LK signal is input, and the frequency is compared with the frequency division result of the clock signal by the frequency divider 132. According to the comparison result (phase difference) by the phase comparator 134, the voltage-controlled oscillator 13
The control voltage supplied to 0 is controlled, and the frequency of the clock signal is controlled with high accuracy.

The lighting control signal generating section 124 corrects the lighting time reference data based on the density unevenness correction data, obtains the lighting time of each pixel, and turns on the LED 60 of each pixel based on the obtained lighting time. To generate a control signal. That is, the lighting control signal generation unit 124
Has the functions of the calculating means and the lighting control means of the present invention.

More specifically, the lighting control signal generating section 124
Quantization error correction unit 140, calculation unit 142, counter 14
4, a comparator 146, and a NAND circuit 148.

The operation unit 142 includes a quantization error correction unit 14
In addition to the image data input through the line 0, the lighting time reference data and the density unevenness correction data are also input. The calculation unit 142 calculates the lighting time of each pixel based on the image data, the lighting time reference data, and the density unevenness correction data, and inputs the result to the comparator 146.

The quantization error correction unit 140 stores the quantization error generated by the arithmetic unit 142 when the image data is ON (1 or H level), and stores the quantization error when the same dot is turned ON next time. Are sequentially added to the conversion error. When a carry occurs, the carry is added to the calculation unit 142 and output. The quantization error correction section 140 corresponds to a quantization error correction unit of the present invention.

The counter 144 includes a timing generator 1
The enable signal indicating the lighting enabled period (T1) from 18 and the output clock signal of the PLL circuit 120 are input. The counter 144 is enabled when the lighting enabled period (T1) is reached, counts up the clock signal, and the count result is input to the comparator 146. Note that the counter 144 corresponds to the counting means of the present invention.

Comparator 146 compares the operation result of operation unit 142 with the count result of counter 144. If the operation result> count result, the output of comparator 146 becomes active, and the output signal of H level is sent to NAND circuit 148. Is entered.

Image data is also input to the NAND circuit 148, and a NAND operation is performed on the output signal of the comparator 146. The output signal I from the NAND circuit 148 is supplied to the circuit 70 via the resistor 150 as the lighting control signal ΦI. That is, the lighting control signal ΦI is at the L level only when the image data is ON and the output signal of the comparator 146 is at the H level.

(Operation) Next, the operation of the present embodiment will be described. First, the operation of the SLED chip 62 will be described with reference to the timing charts of FIGS.

As shown in FIGS. 9 and 10, when the start signal ΦS (Vs) is set to the high level (H), the potential of the point P1 becomes H, and the potential of the point P2 connected from the point P1 through the diode 92 is reduced. The potential is P2 = Φs−Vf
(Due to the LED voltage drop). Similarly, the potential at point P3 is P3 = P2-Vf, and the potential at point P4 is P4 = P
3-Vf,..., The potential at the point PN is PN = P (N−1) −
Vf. However, since saturation occurs at the Φga potential, Φga
It does not fall below.

Here, when CK1 becomes L, the thyristor 90 of P1 turns on, and at this time, the potential of the point P1 becomes ΦS →
The potential of 0 V and CK1 becomes Φ1 → −Vf. Here, the point P, which is equivalent to the point P1, that is, the odd-numbered stage point P is not turned on because the potential is lowered in units of 2Vf.

By changing ΦI from H to L in this state, 1
The LED 60 of the stage can be turned on. Also, ΦI
From L to H, the first-stage LED 60 is turned off,
At this time, the potential of ΦI becomes -Vf.

Next, by setting CK2 to L, the thyristor 90 of P2 is turned on, and P2 = 0V, P3 = -Vf, P3
4 = −2Vf. At this time, the potential Φ2 of CK2 becomes-
Vf, the thyristor 90 of the even-numbered stage after P4
Does not turn on.

When the thyristor 90 of P2 is turned on, CK1 → H is set so that the thyristor 9 of P1 does not turn on by the next data signal.
Turn off 0.

In this state, by changing ΦI from H to L,
The second-stage LED 60 is turned on. At this time, the potential of ΦI becomes -Vf. Then, by changing ΦI from L to H,
The second-stage LED 60 is turned off (the potential of ΦI is 0 V).

Hereinafter, CK1 is an odd-numbered thyristor 90
(LED 60) is turned on (lit), and CK2 controls the even-numbered thyristor 90 (LED 60) on (lit), and also controls the amount of exposure by each LED 60 by the lighting control signal φI. .

In the LPH 16, the above control is simultaneously performed on each of the 58 SLED chips 62 by the LPH driving section 26, and the LED 60 is turned on. As a result, as shown in FIG.
2, self-scanning is performed, and an image is written on the photosensitive drum 12.

At this time, the lighting enabled period of each LED 60 is defined as T1, and from the falling timing of CK1 or CK2,
If one cycle period is T until the falling timing of CK2 or CK1, T is the time for turning on the thyristor 90 of the current stage, and Tb is the time for turning off the thyristor 90 of the preceding stage, T1 = T−Ta− Tb. By controlling the time during which the lighting control signals ΦI (1 to 58) for each SLED chip 62 are set to L level within the lighting enabled period (T1), the lighting time, that is, each LED 60
Can be controlled.

Next, the operation of the LPH drive section 26 will be described with reference to the timing chart of FIG.

In the LPH driving section 26, the PLL circuit 120
As a result, a clock signal that divides the lighting enabled period (T1) by 256 is generated and supplied to each lighting control signal generation unit 124.

The control unit 126 calculates lighting time reference data for uniformly controlling the exposure amount of the LPH 16 for all dots based on the density detection result of the density sensor 32, and stores the data in the total light amount instruction unit 112. . In the total light quantity instructing unit 112, the lighting time reference data is input to each lighting control signal generating unit 124.

The lighting time reference data is, as shown in FIG. 13, a cycle T of the output clock signal of the PLL circuit 120.
It is 8-bit integer value (0 to 255) data with p (= T1 / 256) as one unit. In the present embodiment, 0 to 64 are set prohibited areas. If the lighting time reference data falls within the set prohibited area, it is set to the lowest value (64) in the set area.

Then, each lighting control signal generating section 124
For each corresponding SLED chip 62, the image data divided by the image data dividing unit 110 and the density unevenness correction data split by the density unevenness correction memory 114 are sequentially input for each pixel. In FIG. 12, 1
Only signals input to the two lighting control signal generators 124 are shown.

In the lighting control signal generating section 124, the arithmetic section 1
According to 42, when the input image data is ON, the lighting time reference data set uniformly for all the dots is corrected by multiplying the density unevenness correction data to obtain the lighting time of each pixel. The value of the density unevenness correction data is processed as a coefficient as shown in Table 1.

[0081]

[Table 1]

The lighting time corrected by the density unevenness correction data (coefficient) as described above is an 8-bit integer value (0 to 2).
55) is input to the comparator 146 as lighting time data.

Then, the period during which the LED 60 can be turned on (T
In the case of 1), the timing generation section 118 sends the counter 1
The enable signal to 44 becomes L. When the enable signal becomes L, the counter 144 resets the count value to the initial value (0), enters an enabled state, and starts counting the output clock signal of the PLL circuit 120.

The comparator 146 calculates the value of P by the counter 144.
From the start of counting the output clock signal of the LL circuit 120, the active state is maintained until the count value reaches the value of the lighting time data, and an H level output signal is output. That is, the timing of returning the output signal of the comparator 146 to L is controlled based on the calculation result of the calculation unit 142 (see arrow B).

The output signal of the comparator 146 is the NAND signal
The circuit 148 performs a NAND operation on the image data, and when the image data is ON and the output signal of the comparator 146 is at the H level, the lighting control signal φI which is at the L level is SLE.
It is supplied to the D chip 62. As a result, the LED 60 is turned on with the lighting period (T2) being the time from the start timing of the lighting enabled period (T1) to the elapse of the lighting time.

That is, based on the calculation result of the calculation unit 142, the lighting control signal Φ at the start of the lighting enabled period (T1).
The lighting period (T2) is changed by changing and controlling the timing of returning to the H level (the rising timing of the lighting control signal ΦI) after the I becomes the L level (see arrow C). .

The quantization error (fraction below the decimal point) when the corrected lighting time is converted into 8-bit integer data by the arithmetic unit 142 is stored in the quantization error correction unit 140. Then, when the same dot is turned on next, the stored previous quantization error and the current quantization error are added. Similarly, when carry is generated by sequentially adding, the calculation unit 142 outputs The carry is added and output. By correcting the quantization error in this manner, highly accurate density unevenness correction can be performed.

As described above, in the present embodiment, by setting the lighting time reference data, the exposure amount of all the LEDs 60 (all dots) is uniformly controlled, and the lighting time reference data is determined based on the density unevenness correction data. By performing the correction, the lighting enabled period (T
The lighting time (T2) within 1) is corrected. That is, since both the light quantity control and the density unevenness correction are performed by the lighting time control, even after the density unevenness correction (after obtaining the density unevenness correction data), even if the exposure amount of all the dots is changed by the light quantity control, it is stable. Density unevenness correction can be performed.

Also, by using a clock signal that divides the lightable period (T1) into a predetermined number (256 in the above example) and setting the lighting time reference data to a value in which this clock signal is one unit, the clock signal A signal indicating the lighting period (T2) can be generated by simply comparing the counting result with the corrected lighting time. In other words, the LED lighting duty with respect to the lightable period can be controlled.
Thus, the LPH driving unit 2 can be used without requiring any special members.
6 can be realized, and cost reduction can be achieved.

Further, a clock signal for dividing the lightable period (T1) into a predetermined number is generated by the PLL circuit 120. In general, the PLL circuit 120 can be built in a CMOS circuit. Most of the current ASICs are CMO
By using the PLL circuit 120 which is manufactured by the S process and can be built in the CMOS circuit,
Since the LPH driving unit 26 can be realized by the MOS ASIC, the size can be reduced, and the LPH driving unit 26 can be easily manufactured at low cost. Also,
Since the PLL circuit 120 can easily generate a high-frequency clock, it is possible to perform highly accurate density unevenness correction.

In the first embodiment, the correction amount of each pixel is stored in the density unevenness correction memory 114, and each time the LED 60 is turned on, the lighting time is calculated by the calculation unit 142 ( Correction) has been described as an example, but the present invention is not limited to this. If the lighting time of each pixel is determined and stored in advance, each LED 60
In the case of lighting, the calculation can be omitted.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
As an embodiment of the present invention, an example in which a lighting time of each pixel is obtained and stored in advance will be described.

FIG. 14 shows L according to the second embodiment.
The detailed configuration of the PH drive unit 26 is shown. Note that LP
Except for the H drive unit 26, the configuration is the same as that of the first embodiment, and the description is omitted. In FIG. 14, the first
The same reference numerals as in the first embodiment (see FIG. 6) denote the same members as in the first embodiment, and a detailed description thereof will be omitted here.

As shown in FIG. 14, in the second embodiment, the LPH total light quantity instructing unit 112 and the density unevenness correction memory 114 of the first embodiment are omitted, and instead, the lighting time storage means is used. A lighting time setting memory 180 that stores the lighting time of each pixel is provided. Further, an adder 182 is provided instead of the arithmetic unit 142.

Next, the operation of the second embodiment will be described.

In the LPH drive section 26, similarly to the first embodiment, the PLL circuit 120 generates a clock signal that divides the lightable period (T1) by 256, and supplies the clock signal to each light control signal generating section 124. ing.

The control unit 126 calculates lighting time reference data for uniformly controlling the exposure amount of the LPH 16 for all dots based on the detection result of the density sensor 32, and calculates the density non-uniformity read from the EEPROM in the LPH 16 based on the calculated lighting time reference data. The correction data is multiplied, and the result is stored in the lighting time setting memory 180 as the lighting time for each pixel. That is, in the second embodiment, the control unit 126 has the function of the calculation unit of the present invention.

The value of the density unevenness correction data is processed as a coefficient in the same manner as in the first embodiment, and the value of the lighting time stored in the lighting time setting memory 180 is a value including a decimal part.

The integer part of the lighting time is input to the adder 182, and the decimal part (quantization error) is input to and stored in the quantization error correction unit 140 when the image data is ON.
The next time the image data of the same dot is turned on, the quantization error correction unit 140 adds the stored previous quantization error and the input current quantization error,
When a carry occurs, the carry is added to the adder 182.
Is added to the integer part of the lighting time.

The subsequent processing is the same as in the first embodiment, except that the result of addition by the adder 182 and the counter 144
The comparator 146 compares the count result with
ND circuit 148 performs NAND operation on the image data and
By generating the lighting control data ΦI, the same effect as in the first embodiment can be obtained.

In the first and second embodiments, the case where the quantization error is corrected by the quantization error correction unit 140 has been described as an example. However, the correction of the quantization error is not always necessary. Absent. That is, FIGS.
As shown in (1), the quantization error correction unit 140 may be omitted from the first and second embodiments.

For example, when the printing speed of the image forming apparatus 10 is low, the multiplication rate of the PLL circuit 120 can be increased. That is, the frequency of the clock signal output from the PLL circuit 120 with respect to the BCLK signal can be increased. As a result, the lighting period can be divided more finely than 256, and the lighting time and the lighting period can be changed in finer steps (high-precision lighting time control is possible). The correction of the quantization error due to is unnecessary.

In the first and second embodiments, the period from the start of the lighting period to the elapse of the lighting period is defined as the lighting period (that is, the lighting period is from the front edge to the rear edge of the lighting period). ), But the present invention is not limited to this.

For example, the initial value of the counter 144 is 255
When the counter 144 is enabled in the lighting enabled period, the output clock signal of the PLL circuit 120 is down-counted.
In the comparator 146 which compares the operation result of 2 with the count result of the counter 144, the output becomes active if the operation result> the count result. In this case, the lighting period extends from the timing when the period up to the end timing of the lightable period coincides with the lighting time to the end timing (that is, the lighting time grows from the rear edge of the lightable period toward the front), and the thyristor LED when 90 is stable
Since 60 is turned on, a more stable exposure can be obtained.

Although the above description has been made on the assumption that the image data is 1-bit image data, image data including gradations, such as 8-bit image data, may of course be used. In this case, the lighting time may be determined in consideration of the gradation (light quantity control, density unevenness correction, and gradation expression are all controlled by the lighting time). Alternatively, the voltage value of ΦI, that is, L
The drive current of the ED 60 may be controlled (light amount control, lighting time control for uneven density correction, and intensity modulation for gradation expression). However, when SLED is used as the light source of LPH,
Considering that the lighting time of one LED is short, the latter is more preferable.

[0106]

As described above, the present invention provides the SLE
In an image forming apparatus using D as a light source of an exposure unit, there is an excellent effect that density unevenness correction can be performed with high accuracy. Further, in addition to the above effects, there is an effect that the SLED can be controlled with an inexpensive and simple configuration.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an image forming apparatus according to an embodiment.

FIG. 2 is a sectional view showing an internal configuration of an LED print head (LPH).

FIG. 3 is a perspective view showing an appearance of the LED array.

FIG. 4 is a circuit configuration diagram on a printed circuit board.

FIG. 5 is an internal circuit diagram of the SLED.

FIG. 6 is a block diagram illustrating a detailed configuration of an LPH driving unit according to the first embodiment.

FIG. 7 is a diagram showing a BCLK signal.

FIG. 8 is a block diagram illustrating a detailed configuration of a PLL circuit.

9 is an operation timing chart of an internal circuit of the SLED shown in FIG.

FIG. 10 shows an LED of an internal circuit of the SLED shown in FIG.
FIG. 4 is a characteristic diagram showing a light emitting state.

FIG. 11 is a timing chart showing the operation of the entire LED array.

12 is an operation timing chart of the LPH driving section shown in FIG.

FIG. 13 is a graph showing a setting prohibition / possible area of lighting time reference value data.

FIG. 14 is a block diagram illustrating a detailed configuration of an LPH driving unit according to a second embodiment.

FIG. 15 is a modification example of FIG. 6;

FIG. 16 is a modification of FIG.

FIG. 17 is a drive circuit diagram of a single LED in the SLED.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Image forming apparatus 12 Photoreceptor drum 16 LPH 26 LPH drive part 32 Density sensor 50 LED array 60 LED 62 SLED chip 72 EEPROM 90 Thyristor 110 Image data division part 112 Total light quantity indication part 114 Memory for density unevenness correction 116 Oscillator 118 Timing generation Unit 120 PLL circuit 124 Lighting control signal generation unit 126 Control unit 140 Quantization error correction unit 142 Operation unit 144 Counter 146 Comparator 180 Lighting time setting memory 182 Adder

Claims (7)

[Claims] 1. An image forming apparatus to which a self-scanning LED is applied as a light source of an exposure means for forming an image by exposing a photoreceptor, wherein a lighting time reference value for controlling the total light amount is set. Setting means, based on a correction amount of each pixel for correcting the density unevenness of the image, calculating means for correcting the lighting time reference value to obtain a lighting time of each pixel; A lighting control unit that controls lighting of the LED of each pixel based on the lighting time. 2. The image forming apparatus according to claim 1, further comprising a correction amount storage unit configured to store a correction amount of each of the pixels. 3. The image forming apparatus according to claim 1, further comprising a lighting time storage unit that stores a lighting time of each pixel obtained by the calculation unit. 4. A reference clock generating means for generating a reference clock for dividing a lighting enabled period of the LED into a predetermined number, a counting means for counting the number of reference clocks in the lighting enabled period, and a counting result by the counting means. And a comparing unit that compares the lighting time obtained by the arithmetic unit with the setting unit, wherein the setting unit uses the reference clock as a basic unit,
4. The lighting time reference value is set, and the lighting control means controls lighting of the LED of each pixel based on a comparison result by the comparing means. 2. The image forming apparatus according to claim 1. 5. The image forming apparatus according to claim 4, wherein said reference clock generation means is a PLL circuit. 6. The image forming apparatus according to claim 4, further comprising a quantization error correction unit configured to correct a quantization error by the calculation unit. 7. The LED lighting period from a timing when a period until the end timing of the lightable period coincides with the lighting time to a period until the end timing is defined as an LED lighting period. The image forming apparatus according to claim 1.