JP4424230B2 - Image forming apparatus - Google Patents

Description

  The present invention relates to an image forming apparatus.

  2. Description of the Related Art Conventionally, an image forming apparatus that includes a plurality of light beam scanning devices that scan with a light beam such as a laser beam and forms a color image is known. In such an image forming apparatus, each color (for example, black: K, cyan: C, magenta: M, yellow: Y) is provided with an image forming unit, and the toner of each color is superimposed on the sheet and transferred. , Perform multi-color printing.

  However, the writing start position of each color is shifted and may appear as a color shift when transferred by being superimposed on the paper, thereby deteriorating the print quality.

  In addition, digital copying machines, laser printers, and the like as such image forming apparatuses have recently been required to increase the speed, and during continuous printing in order to perform high-speed printing while maintaining high-quality images. A technique for correcting color misregistration without interrupting a print job is required.

  As a technique for correcting registration deviation, a toner image of a specific pattern of each color is formed on the intermediate transfer member, the specific pattern is detected by a sensor including a light source and a photodetector, and the registration deviation amount is calculated and corrected. A specific pattern is created in advance outside the image forming area of the intermediate transfer member, and the pattern is detected by a sensor during image formation of each color, and the detection timing of the pattern and the writing start signal in the main scanning direction are detected. There is a method of performing correction by calculating a registration deviation amount based on detection timing.

  Among the techniques for correcting the registration deviation as described above, in particular, for a registration deviation of one line or less in the sub-scanning direction, rotation of a rotating polygon mirror (hereinafter also referred to as a polygon mirror) arranged in the image forming unit is performed. Conventionally, a technique for correcting a registration shift by controlling the writing position by controlling the phase has been proposed.

  For example, the misregistration amount detection means detects the misregistration amounts of images of different colors, divides the misregistration amount by the scanning pitch, and separates it into a quotient N and a remainder R. Based on the quotient N, the corresponding exposure means It has been proposed to adjust the recording position of an image of a different color to a positional deviation less than the scanning pitch by changing the exposure timing and changing the scanning phase of the corresponding exposure means based on the remainder R (for example, Patent Document 1).

  On the other hand, the polygon mirror is attached to the drive motor, and a PLL is generated by a synchronous clock supplied to the motor and a comparison clock generated in synchronization with the rotation of the polygon mirror so that the polygon mirror rotates accurately at a constant rotational speed. In general, (Phase Lock Loop) control is performed. The comparison clock is, for example, a sensor arranged outside the scanning surface in the scanning exposure apparatus that serves as an output from a frequency generator provided in the drive motor, a Hall element output, or a writing timing signal in the main scanning direction. Is a scanning light position detector output.

  The rotation phase of the polygon mirror can be controlled by controlling the phase of the synchronous clock supplied to the drive motor that rotates the polygon mirror. In other words, when the phase of the synchronous clock changes, a phase difference occurs between the synchronous clock and the comparison clock, and the rotational speed of the drive motor changes and the rotational phase also changes to eliminate this phase difference. Along with this, the output timing of the write timing signal in the main scanning direction also changes, so the start of writing in the sub scanning direction changes.

  As a technique for controlling the writing start position in the sub-scanning direction by controlling the synchronous clock supplied to such a drive motor, in an image forming apparatus, a toner image pattern is used as an intermediate transfer body for detecting the misregistration of each color. Based on the formed toner image pattern, the positional deviation amount of the writing position of each color component in the sub-scanning direction is detected, and only the phase of the drive motor is controlled based on the positional deviation amount, and the position in the sub-scanning direction A technique for preventing the shift has been proposed (see, for example, Patent Document 2).

  In Patent Document 2, the phase control of the drive motor uses the PLL control means for controlling the phase based on the comparison result between the synchronous clock supplied to the drive motor and the comparison clock according to the rotation speed of the polygon mirror. By changing the duty of the synchronous clock based on the amount of positional deviation, the positional deviation of less than one line in the sub-scanning direction is corrected.

  In order to facilitate the rotation phase control, the number of polygon mirror surfaces and the number of magnetic poles of the drive motor correspond to each other, and the surface phase of the polygon mirror is uniquely determined by the phase of the pulses generated by the magnetic poles of the drive motor. A technique for preventing the positional deviation in the sub-scanning direction has been proposed (see, for example, Patent Document 3).

Further, the control angle obtained by dividing the number of pulses generated by the drive motor per rotation by one rotation angle of the polygon mirror is an integral multiple of the division angle obtained by dividing the polygon mirror number by the one rotation angle of the polygon mirror. By performing equal phase control, the degree of freedom in selecting a drive motor is increased, and a technique for preventing positional deviation in the sub-scanning direction using a drive motor having a number of magnetic poles with good torque generation efficiency has been proposed (for example, (See Patent Document 4).
Japanese Patent No. 3282353 JP 11-218696 A JP 2000-94747 A JP 2003-312056 A

  The phase shift can be both delayed and advanced with respect to the target phase, but when controlling the phase shift of the polygon mirror, if the phase is controlled in the forward direction, the polygon drive There is a problem that the rotation of the motor is accelerated, stress is generated in the bearing portion, and a failure is caused.

  In Patent Document 1, the amount of misalignment is divided by the scanning pitch and separated into a quotient N and a remainder R, the exposure timing of the corresponding exposure means is changed based on the quotient N, and the polygon mirror corresponding to the remainder R is changed. Since the scanning phase is changed, there is a problem that the phase may be controlled in the advance direction depending on the direction of positional deviation.

  Similarly, Patent Documents 2, 3, and 4 also have a problem that control may be performed in the advance direction depending on the direction of positional deviation.

  Furthermore, in Patent Document 2, there is a problem in that correction of one line or more cannot be performed because the positional deviation is corrected only by scanning phase control of the polygon mirror.

  In Patent Document 3, since the number of magnetic poles of the drive motor is uniquely determined by the number of polygon mirror surfaces, the number of magnetic poles with high torque generation efficiency of the drive motor cannot be selected, and phase adjustment can be performed only in stages. was there.

  In Patent Document 4, the degree of freedom in selecting the drive motor has increased, but the number of mirror surfaces of the polygon mirror and the number of pulse signals generated per rotation by the drive motor are still limited, and the most efficient polygon mirror and drive are available. There is a problem in selecting a combination with a motor.

  Therefore, the present invention reduces the color misregistration in the sub-scanning direction by reliably controlling the phase of the polygon mirror without imposing a burden on the motor that drives the polygon mirror when correcting the color misregistration generated in the image forming apparatus. An object of the present invention is to provide an image forming apparatus capable of reducing the failure and having a long product life.

  The object of the present invention can be achieved by the following constitution.

(Claim 1)
An image carrier that is driven to rotate, a laser element that is output-controlled in accordance with image data, and a polygon mirror that reflects laser light emitted from the laser element and scans and exposes the image carrier in the main scanning direction. A transfer belt that is provided with at least two image forming units and that is rotated by a sub-scanning direction orthogonal to the main-scanning direction, or a transfer material that is conveyed by the transfer belt, in which different color images created by the respective image-forming units are rotated. Each of the image forming means generates a mirror driving means for rotationally driving the polygon mirror and a comparison clock signal synchronized with the rotation of the polygon mirror. and a comparison clock signal generating means for said image forming apparatus is configured to control the respective image forming means, each said image forming means And control means for forming a resist pattern of colors respond on a transfer belt, the resist pattern is detected and the the reference image forming means one of the at least two image forming means, the reference image forming means Color misregistration information acquisition means for acquiring a color misregistration amount for the other image forming means based on a distance between the resist pattern by the image forming apparatus and the resist pattern by other image forming means other than the reference image forming means ; A reference clock signal generating means for generating a reference clock signal; a writing position correcting means for correcting a writing position in the sub-scanning direction of the other image forming means in units of a scanning pitch of the other image forming means; and the reference by correcting the phase of the reference clock signal generated by the clock signal generating means, and a clock correcting unit that the synchronous clock signal relative to the other image forming means, before Based on the comparison clock signal generated by the corrected synchronizing clock signal and the comparison clock signal generating means by the clock correction means, have a drive control means for controlling the mirror drive means of the other image forming means, wherein When the amount of color misregistration of the other image forming means is an amount indicating that it is delayed from the writing position of the reference image forming means, and is advanced from the writing position of the reference image forming means. In any case, the writing position correction means corrects the writing position of the other imaging means so that it is in a state advanced from the writing position of the reference imaging means. In addition, the clock correction unit corrects the phase of the reference clock signal to be delayed.

(Claim 2)
When the color misregistration amount of the other image forming unit is an amount indicating that it is delayed from the write position of the reference image forming unit, the write position correcting unit is configured to display the color of the other image forming unit. After the correction is made so that the writing position of the other image forming means advances by the number of scan pitch widths obtained by adding 1 to the quotient obtained by dividing the deviation amount by the scan pitch, the clock correction means performs the phase of the reference clock signal. Is corrected to delay, and the amount of color misregistration of the other image forming means is an amount indicating that it is advanced from the start position of the reference image forming means. After correcting the writing position of the other image forming means to be delayed by the scan pitch width of the quotient obtained by dividing the color misregistration amount of the other image forming means by the scan pitch, the clock correcting means Delay the phase of the reference clock signal The image forming apparatus according to claim 1 for correcting so as to.

(Claim 3)
The clock correction unit corrects the phase of the reference clock signal generated by the reference clock signal generation unit by a plurality of times by an amount smaller than a half cycle of the reference clock signal to obtain a synchronous clock signal. The image forming apparatus according to claim 1, wherein:

According to the first or second aspect of the invention, the writing position in the sub-scanning direction of the image forming unit is corrected, and the amount of color misregistration is changed so that the writing position in the sub-scanning direction of the reference image forming unit is different from that of the other image forming unit. By replacing with the color shift amount delayed from the writing position of the image means in the sub-scanning direction, the phase can be controlled by always decelerating the rotation of the polygon mirror. It is possible to provide an image forming apparatus having a long sub-scanning color misregistration.

  According to the invention described in claim 3, regardless of the relationship between the number of mirror surfaces and the number of pulses generated per rotation of the polygon mirror and the number of motor poles, the phase of the polygon mirror is reliably controlled, and the color in the sub-scanning direction is determined. An image forming apparatus with reduced shift can be provided.

  Hereinafter, an embodiment of an image forming apparatus according to the present invention will be described as a tandem color printer (hereinafter simply referred to as “printer”) having a four-color configuration of cyan (C), magenta (M), yellow (Y), and black (K). ")") As an example.

  FIG. 1 is a conceptual diagram showing a schematic configuration of a printer 1 which is an embodiment of an image forming apparatus according to the present invention.

  The printer 1 includes image forming units 101C, 101M, 101Y, and 101K for each color arranged along the transfer belt 23. The image forming units 101C, 101M, 101Y, and 101K for each color have the same configuration. For example, in the cyan (C) image forming unit 101C, around the image carrier 17C that is rotationally driven in the direction of arrow A, A scanning exposure apparatus 10C, a developing device 104C, a charging charger 102C, and a cleaner 103C are arranged. Further, the image forming units 101C, 101M, 101Y, and 101K for the respective colors are provided with transfer chargers 105C, 105M, 105Y, and 105K facing each other with the transfer belt 23 interposed therebetween.

  The transfer belt 23 is stretched by two transport rollers 231 and 232 and is driven to rotate in the direction indicated by the arrow B. In the present embodiment, the arrow B direction in which the transfer belt 23 is rotationally driven is defined as the sub-scanning direction.

  In addition, the printer 1 includes paper feed rollers 22a and 22b that convey the transfer material S in the direction indicated by arrow F, a TOD sensor 24 that detects the passage of the transfer material S conveyed by the paper feed roller 22a, and a transfer belt 23. A registration sensor 25 that detects a resist pattern to be formed, and a secondary transfer roller 26 that transfers an image on the transfer belt 23 to a transfer material S are provided.

  The image forming process of the image forming units 101C, 101M, 101Y, and 101K for each color will be described using the cyan image forming unit 101C as an example. The image carrier 17C is first charged by the charging charger 102C and then exposed to the laser light emitted by the scanning exposure device 10C, whereby an electrostatic latent image is formed on the surface thereof. This electrostatic latent image is developed by the developing device 104C, and a toner image is formed on the image carrier 17C. This toner image is transferred to the transfer belt 23 by the transfer charger 105C at a position where the image carrier 17C and the transfer belt 23 are in contact with each other. Thereafter, the toner remaining on the image carrier 17C is cleaned by the cleaner 103C. By this process, a cyan image is formed on the surface of the transfer belt 23.

  Following the formation of the cyan image by the cyan image forming unit 101C, magenta, yellow, and black images are sequentially formed by the other three color image forming units 101M, 101Y, and 101K, and the cyan image on the transfer belt 23 is sequentially formed. Overlaid on top. The four color images superimposed on the transfer belt 23 are transferred to the transfer material S by the transport roller 232 and the secondary transfer roller 26. Thereafter, the transfer material S carrying the toner image is fixed and discharged by a fixing device (not shown).

  Note that the image forming units 101C, 101M, 101Y, and 101K for each color and the rotational driving of the transfer belt 23 are synchronized with reference to the passing detection timing of the transfer material S by the TOD sensor 24.

  The scanning exposure apparatuses 10Y, 10M, 10C, and 10K shown in FIG. 1 will be described using the scanning exposure apparatus 10C of the cyan image forming means 101C as an example with reference to FIG. FIG. 2 is a perspective view showing a schematic configuration of the scanning exposure apparatus 10C and the image carrier 17C shown in FIG. The scanning exposure apparatuses 10C, 10M, 10Y, and 10K all have the same configuration and operation.

  The scanning exposure apparatus 10C includes a light source unit 11C, a collimator lens 12C, a polygon mirror 13C, an fθ lens 14C, a reflecting mirror 15C, an SOS (Start On Scan) sensor 16C serving as position detection means, a polygon drive motor 18C, and the like.

  The light source unit 11C irradiates a laser beam L by oscillating a semiconductor laser (not shown) by an image signal modulated according to image data.

  The collimator lens 12C collects the laser beam L emitted from the light source unit 11C and emits it to the polygon mirror 13.

  The polygon mirror 13C that is rotationally driven by the polygon drive motor 18C deflects the laser beam L incident from the collimator lens 12C and emits it to the fθ lens 14C.

  The fθ lens 14C removes the curvature of field of the laser beam L incident from the polygon mirror 13C and realizes constant speed scanning with the laser beam L on the image carrier 17C.

  The reflecting mirror 15C guides the laser beam L to the SOS sensor 16C, and the SOS sensor 16C detects the laser beam L deflected by the polygon mirror 13C and scans the image carrier 17C, and uses a start timing signal of one scanning line. A certain HSYNC signal is output.

  In the present embodiment, the scanning direction (arrow H direction) of the laser beam L is the main scanning direction orthogonal to the sub-scanning direction.

  A functional configuration relating to registration deviation correction in the image forming apparatus according to the present invention will be described with reference to FIG. FIG. 3 is a block diagram illustrating a functional configuration of the printer 1 illustrated in FIGS. 1 and 2.

  The printer 1 includes a microcomputer 43, an image memory 41, a reference clock generation circuit 44, a TOD sensor 24, a registration sensor 25, and scanning exposure apparatuses 10Y, 10M, and 10C corresponding to the respective image forming units 101C, 101M, 101Y, and 101K. 10K, and dot clock circuits 45C, 45M, 45Y, 45K and the like. The same components as those shown in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof is omitted.

  Scanning exposure apparatuses 10Y, 10M, 10C, and 10K are respectively motor control circuits 54C, 54M, 54Y, and 54K, polygon drive motors 18C, 18M, 18Y, and 18K, and rotational speed detection signal generators (hereinafter referred to as FG) 52C and 52M. , 52Y, 52K, LD drivers 55C, 55M, 55Y, 55K and SOS sensors 16C, 16M, 16Y, 16K.

  The microcomputer 43 includes a CPU (Central Processing Unit) (not shown), a work memory, a nonvolatile memory, and the like, and controls various components of the printer 1 based on a program stored in the nonvolatile memory.

  The microcomputer 43 has functions as a control unit 431, a clock correction unit 432, and a write position correction unit 433.

The control unit 431 controls the image forming units 101 </ b> C, 101 </ b> M, 101 </ b> Y, and 101 </ b> K for each color to form a resist pattern group composed of each color on the transfer belt 23.
The clock correction unit 432 corrects the phase of the reference clock signal CLK generated by the reference clock generation circuit 44 that is the reference clock signal generation unit, based on the color shift information acquired by the registration sensor 25 that is the color shift information acquisition unit. The synchronous clock signals SCLK_C, SCLK_M, SCLK_Y, and SCLK_K are input to the scanning exposure apparatuses 10Y, 10M, 10C, and 10K for the respective colors.

  The writing position correction unit 433 corrects the writing position in the sub-scanning direction of the image forming unit for each color in units of one scanning line in the main scanning direction.

  The image memory 41 stores image data input from a communication unit (not shown).

  The reference clock generation circuit 44 is composed of a known oscillator or the like, and generates a reference clock signal CLK for driving the microcomputer 43 or the like.

  Since each component of the scanning exposure devices 10Y, 10M, 10C, and 10K and the dot clock circuits 45C, 45M, 45Y, and 45K have the same configuration and operation for each color, the cyan scanning exposure device 10C and the dot clock circuit 45C. Will be described as an example.

  The FG 52C functioning as a comparison clock signal generating means is composed of a hall element (not shown) and the like, and detects a magnetic field formed by magnetic poles provided on a rotor (not shown) that rotates with the polygon mirror 13C. That is, when the polygon mirror 13C and the rotor rotate, the magnetic field intensity detected by the Hall element changes, and the comparison clock signal RCLK_C corresponding to the change in the magnetic field intensity is output. That is, the FG 52C generates the comparison clock signal RCLK_C that is synchronized with the rotation of the polygon mirror 13C. The comparison clock signal RCLK_C is a pulse signal that repeats the levels of “H” and “L” at a frequency corresponding to the rotational speed of the polygon mirror 13C.

  When a rotation signal is output from the microcomputer 43 according to the operation of the printer 1, the motor control circuit 54C functioning as a drive control means rotates the polygon drive motor 18C. The motor control circuit 54C performs PLL (Phase Locked Loop) control based on the synchronous clock signal SCLK_C input from the microcomputer 43 and the comparison clock signal RCLK_C input from the FG 52C, and the polygon mirror 13C rotates at a constant speed. In this way, the polygon drive motor 18C is driven. Further, when a stop signal is output from the microcomputer 43, the motor control circuit 54C stops the driving of the polygon drive motor 18C.

  The dot clock circuit 45C outputs the reference clock CLK to the image memory 41 as a dot clock signal DCLK_C delayed by a predetermined time in accordance with the timing at which the image forming unit 101C forms an image on the transfer belt 23. The image data stored in the image memory 41 is read in synchronization with the dot clock signal DCLK_C and output to the LD driver 55C.

  The LD driver 55C causes the light source unit 11C to emit a laser beam L in accordance with image data output from the image memory 41 and a command from the microcomputer 43 in synchronization with the dot clock signal DCLK_C.

  The PLL control performed by the motor control circuits 54C, 54M, 54Y and 54K shown in FIG. 3 will be described using the motor control circuit 54C as an example with reference to FIG. FIG. 4A is a block diagram showing an internal configuration of the motor control circuit 54C, and FIG. 4B is a timing chart showing states of various signals related to PLL control performed by the motor control circuit 54C. The motor control circuits 54M, 54Y and 54K have the same configuration as the motor control circuit 54C.

  In FIG. 4A, the motor control circuit 54C includes a motor drive unit 541C and a PLL control unit 89C.

  The motor drive unit 541C controls the start and stop of the polygon drive motor 18C in accordance with instructions from the microcomputer 43 shown in FIG.

  The PLL control unit 89C includes a phase comparator 80C, a low-pass filter 83C, an amplifier 84C, and a PLL lock detection circuit 85C. The PLL control unit 89C outputs a motor control voltage to the polygon drive motor 18C based on the synchronous clock signal SCLK_C input from the microcomputer 43 and the comparison clock signal RCLK_C input from the FG 52C. The PLL lock signal PLL_C is output.

  Table 1 below is a logic table of the phase comparator 80C.

  The phase comparator 80C determines whether the input level is “H” or “L” with a predetermined voltage as a threshold value. When both the synchronous clock signal SCLK_C and the comparison clock signal RCLK_C are “H”, the phase comparison output Q is set to “L”. 'And. In other cases, the phase comparison output Q is 'H'.

  For example, in FIG. 4B, at time t1, it is determined that the synchronous clock signal SCLK_C becomes 'H', and the comparison clock signal RCLK_C is also 'H', so the Q output becomes 'L'. At time t2, it is determined that the comparison clock signal RCLK_C has become “L”, and since the synchronous clock signal SCLK_C is “H”, the Q output becomes “H”. The period between time t1 and time t2, that is, the duty DT corresponds to the phase difference between the synchronous clock signal SCLK_C and the comparison clock signal RCLK_C.

  The phase comparison output Q of the phase comparator 80C is rectified by the low-pass filter 83C, further amplified to a voltage proportional to the duty DT of the phase comparison output Q by the amplifier 84C, and supplied to the drive motor 18C as a motor control voltage. The drive motor 18C generates a driving force corresponding to the motor control voltage supplied from the PLL control unit 89C. As described above, the drive motor 18C rotates at a phase corresponding to the synchronous clock signal SCLK_C.

  The PLL lock detection circuit 85C determines whether or not the motor control voltage amplified by the amplifier 84C is within a predetermined voltage range. If the motor control voltage is within the predetermined voltage range, the PLL lock signal PLL_C becomes “H”. . That is, the PLL lock signal PLL_C becomes active when the drive motor 18C is rotating in phase synchronization.

  The operation of the image forming apparatus according to the present invention will be described.

  First, the operation timing of each unit when image formation is performed in the printer 1 will be described. FIG. 5 is a timing chart showing the operating state of each part of the printer 1 when the printer 1 forms an image.

  When the microcomputer 43 receives a print instruction (not shown), the rotation / stop signal output is set to 'L' (t11), and the polygon control motors 18C, 18M, 18Y are supplied to the motor control circuits 54C, 54M, 54Y, 54K for the respective colors. , 18K rotation is commanded. In the rotation / stop signal, 'L' indicates motor rotation and 'H' indicates motor stop.

  When the polygon drive motors 18C, 18M, 18Y, and 18K rotate at a constant speed, the motor control circuits 54C, 54M, 54Y, and 54K for the respective colors have the PLL lock signals PLL_C, PLL_M, PLL_Y, and PLL_K that are not illustrated in FIG. Becomes H ′ and notifies the microcomputer 43 of the state. When the microcomputer 43 detects that the PLL lock signals PLL_C, PLL_M, PLL_Y, and PLL_K of each color are all “H”, the microcomputer 43 sets the light emission instruction signal to “L” (t12), and the LD drivers 55C, 55M, and Commands 55Y and 55K to emit laser light. When the laser light is emitted, the HSYNC signal HSYNC_C, HSYNC_M, HSYNC_Y and HSYNC_K become 'L' (for example, t13C, t13M, t13Y, t13K).

  The TOD signal is a signal that becomes 'L' when the passage of the transfer material S is detected. In FIG. 5, the period TC from the time when the print instruction is issued until the time t14 when the TOD signal becomes “L” is called a phase control period, and the phase at the time of laser recording of each color of C, M, Y, and K within this period. To match. The control performed in the phase control period TC is shown in FIG. 8, and details thereof will be described later.

  The microcomputer 43 includes internal counters 4 to 7 (not shown) that count the number of HSYNC_K pulses triggered by a falling edge at which the TOD signal becomes 'L'. Counters 4 to 7 are provided for the purpose of counting the start and end timings of C, M, Y, and K image output, respectively.

  Each of the counters 4 to 7 is reset at the falling edge when the TOD signal becomes “L”, starts counting the number of pulses of HSYNC_K (t15), and has a predetermined count number set for each color The status of the counters 4 to 7 becomes “H” (t16C, t16Y, t16M, t16K).

  In the present embodiment, the predetermined count numbers CNT_C, CNT_M, CNT_Y, and CNT_K are predetermined, and are set to large values in the order of CNT_C, CNT_M, CNT_Y, and CNT_K. CNT_C, CNT_M, CNT_Y, and CNT_K are, for example, positions where the image carrier is scanned by the laser beam L with reference to a certain position on the transfer belt 23 in each color image forming means (106C, 106M, 106Y, 106K) according to the total length of the transfer belt 23 and the image carrier surface.

  Next, the drawing timing will be described.

  The counters 1 to 3 are provided in the microcomputer 43 for the purpose of measuring the C, M, and Y drawing periods, respectively. The counter 8 is provided for the purpose of measuring the K drawing period.

  Since the counters 4 to 7 are counting HSYNC_K pulses, they are not necessarily synchronized with the corresponding HSYNC_C, HSYNC_M, and HSYNC_Y of each color. Therefore, after the counters 4 to 6 corresponding to the C, M, and Y colors become “H” (t16C, t16Y, and t16M), the HSYNC_C by the counters 1 to 3 at the timing when the HSYNC_C, HSYNC_M, and HSYNC_Y become “H”. , HSYNC_M and HSYNC_Y are counted (t17C, t17M, t17Y).

  Since the counter 8 is a K counter, the synchronized HSYNC_K pulses are counted as they are.

  The statuses of the counters 1 to 3 are “H” from the time when the counters 1 to 3 start counting the number of pulses of the corresponding HSYNC_C, HSYNC_M, and HSYNC_Y, respectively, until the predetermined counts CNTA_C, CNTA_M, and CNTA_Y are counted. 'become. During the status 'H', the microcomputer 43 activates an image request signal and instructs the image memory 41 to read an image. The image data of each color read from the image memory 41 in synchronization with the dot clock signals DCLK_C, DCLK_M, DCLK_Y, DCLK_K output from the dot clock circuit 45 of each color is output to the color LD driver 55, respectively, and the image of each color Are drawn on the image carrier 17 of each color image forming means 101 by each color scanning exposure apparatus 10.

  As described above, in the printer 1, a color image is formed by synchronizing the image forming timings of the image forming units 101C, 101M, 101Y, and 101K for the respective colors. Registration shift occurs due to deformation of each part constituting the printer 1 and wear of driving parts. Therefore, in order to form an image without registration deviation, it is necessary to periodically perform registration deviation correction.

  The operation of correcting registration deviation in the image forming apparatus according to the present invention will be described with reference to FIG. FIG. 6 is a flowchart showing the flow of registration deviation correction processing executed by the printer 1. In the present embodiment, the registration deviation correction is executed as a correction mode when the printer 1 is turned on or every fixed operation time. In the flowchart of FIG. Is from.

  In step S <b> 1, the control unit 431 controls the image forming unit 101 for each color to form a set of resist patterns on the transfer belt 23. For example, as shown in FIG. 7, a predetermined pattern of each color is formed on the transfer belt 23 as a set of resist patterns.

  In step S2, the specific pattern formed in step S1 is detected by the registration sensor 25. The detected specific pattern of each color is output to the microcomputer 43 as color misregistration information.

  Here, in FIG. 7A, the distance a between MY and the distance b between CM are the same, but the distance c between K and C is larger than a and b. That is, the writing position in the sub-scanning direction of the Y, M, and C color image forming means is slightly earlier than the writing position of the K image forming means. When there is no registration deviation, the specific patterns of the respective colors are equally spaced a ′ = b ′ = c ′ as shown in FIG. 7B. In FIG. 7C, the distance a ″ between Y and M is the same as the distance b ″ between M and C, but the distance c ″ between C and K is smaller than a ″ and b ″. The writing position of Y, M, and C in the sub-scanning direction is slightly delayed from the writing position of the K image forming means.

  In step S3, based on the detection timing signal of the specific pattern of each color output in step S2, the shift amount of the writing position of each color in the sub-scanning direction is calculated based on the writing position of the K image forming means. In other words, in the present embodiment, the K image forming means is the first image forming means, and the Y, M, and C color image forming means are the second image forming means.

  In a state where there is no color shift, the relationship between the distance a between MY and the distance b between CM and the distance c between CK and the design value X is X = a = b = c. X is a predetermined value obtained from the design values of the position of the image carrier 17 of each color and the conveyance speed of the transfer belt 23.

  The design distance between K and C is X, and the color shift amount ΔC = c−X. The distance between KM is 2X by design, and the color misregistration amount ΔM = (b + c) −2X. Similarly, the distance between KY is 3X by design, and the color misregistration amount ΔY = (a + b + c) −3X.

  For example, in the case of FIG. 7A, if Δx = c−X and a = b = X, then ΔC = Δx, ΔM = Δx, and ΔY = Δx.

Returning to FIG. 6, when the color shift amount Δx calculated in step S3 is positive, that is, the writing position in the sub-scanning direction of the second image forming means is the writing position in the sub-scanning direction of the first image forming means. If the amount is an amount indicating a more advanced range (step S4; Yes), the writing position correcting unit 433 uses the color shift amounts ΔY, ΔM, and ΔC calculated in step S3 at the scanning pitch of the image forming unit for each color. Divide and divide the quotient N into the remainder R. In this case, since the writing position of the C, M, and Y color image forming means is ahead of the K writing position, the number of scans SC_Y, SC_M, and SC_C to be delayed based on the writing position correction means 433 and the quotient N Scanning phases φY, φM, and φC that are delayed based on R_Y, R_M, and R_C are calculated for each color (step S5).

When the shift amount is negative, that is, the color shift amount Δx is an amount indicating a range in which the writing position in the sub-scanning direction of the first image forming means is ahead of the writing position in the sub-scanning direction of the second image forming means. If there is (step S4; No), the writing position correcting means 433 divides the color misregistration amounts ΔY, ΔM, and ΔC calculated in step S3 by the scanning pitch of the image forming means for each color to obtain the quotient N as in step S5. And remainder R. However, in this case, since the writing position of the C, M, and Y color image forming means is delayed from the K writing position, when the scanning phase is calculated in the same way as when the shift amount is positive, the scanning phase is Compared to the original phase, correction is made in the advance direction, and the rotation of the polygon drive motor 18 for each color of C, M, and Y is accelerated. Therefore, the writing position correction means 433 adds the writing position by one line (one scanning) and advances it, thereby correcting the scanning phase in a direction delayed from the original phase. That is, the writing position correcting unit 433 calculates the scanning line numbers SC_Y, SC_M, and SC_C that advance the writing position based on the quotient N, adds 1 to each, and based on the remainders R_Y, R_M, and R_C, the phases pY, pM, Find pC. Since one line corresponds to the phase difference 2π, the writing position correcting unit 433 calculates the scanning phases φY, φM, and φC that are actually delayed by the following equation (step S6).

φY = 2π-pY
φM = 2π-pM
φC = 2π-pC
That is, in step S6, the writing position in the sub-scanning direction of the image forming unit is corrected in units of one line in the main scanning direction, and the color misregistration amount is determined as the writing position in the sub-scanning direction of the K image forming unit 101K. Is corrected to a range that is delayed from the writing position in the sub-scanning direction of each of the multi-color image forming means 101C, 101M, and 101Y.

  The number of scan lines SC_Y, SC_M, SC_C, which is calculated in step S6, and 1 is added to the scan line number is output to the dot clock circuit 45 for each color, and the dot clock signals DCLK_C, DCLK_M for each color with respect to the reference clock CLK. , And is reflected in the delay time of DCLK_Y.

  In step S7, the microcomputer 43 calculates correction amounts Da_Y, Da_M, Da_C of the synchronous clocks SCLK_C, SCLK_M, SCLK_Y corresponding to the scanning phases φY, φM, φC determined in step S5 or step S6.

  In step S8, the clock correction unit 432 corrects the phases of the synchronous clocks SCLK_C, SCLK_M, and SCLK_Y based on the correction amounts Da_Y, Da_M, and Da_C calculated in step S7, and corrects them to the motor control circuit 54 for each color. Output synchronous clock. The phase correction control in step S8 will be described in detail later with reference to FIG.

  In step S9, the microcomputer 43 stores the correction amounts Da_Y, Da_M, Da_C of the synchronous clocks SCLK_C, SCLK_M, SCLK_Y in the correction amount storage means 434 built in the microcomputer 43, and ends the process.

  The correction amounts Da_Y, Da_M, and Da_C of the synchronous clocks SCLK_C, SCLK_M, and SCLK_Y stored in the correction amount storage unit 434 are each time an image is formed (for example, FIG. 5) except when the resist pattern is formed in step S1. In the phase control period TC shown in FIG. 5), the clock correction unit 432 reads out the data and corrects the synchronous clock.

  The registration shift correction process described above defines a first image forming unit serving as a reference out of two or more image forming units, and is different from the first image forming unit serving as a reference. In this embodiment, the writing positions of the C, M, and Y image forming means 101C, 101M, and 101Y are corrected based on the K image forming means 101K. For example, after correcting the writing position of the C image forming means 101C with reference to the K image forming means 101K, the writing position of the M image forming means 101M is set with reference to the corrected writing position of the C image forming means 101C. It can also be corrected.

  The phase control period TC shown in FIG. 5 and the synchronous clock phase correction processing executed in step S8 of FIG. 6 will be described with reference to FIG. The same processing is performed for each of the colors Y and M.

  FIG. 8 is a flowchart for explaining the first embodiment of the synchronous clock phase correction processing executed by the clock correction means 432 in the phase control period TC shown in FIG. 5 and step S8 in FIG. This flowchart describes that the phase correction amount Da_C of the polygon mirror 13C calculated in advance is divided into phase correction amounts that can be phase controlled by the PLL control circuit unit 89C, which is a PLL control unit, and is controlled stepwise.

  In step S301, it is determined whether or not registration deviation correction processing is performed at the start of this processing. When registration deviation correction processing is performed, that is, when a resist pattern is formed (step S301; YES), the correction amount Da_C calculated in step S7 of FIG. 6 is input from the writing position correction unit 433 ( Step S302). When the resist pattern is not formed (step S301; NO), Da_C generated in the registration deviation correction process performed in the past and stored in the correction amount storage unit 434 is read (step S303).

  In step S304, it is determined whether or not the phase correction amount Da_C is within a predetermined range.

  If the phase correction amount Da_C is within a predetermined range (step S304; Yes), the phase control is terminated.

  When the phase correction amount Da_C exceeds the predetermined range (step S304; No), it is determined whether Da_C <maximum correction amount Dmax_C per operation (step S305). The maximum correction amount Dmax_C per operation will be described in detail later.

  If Da_C ≧ Dmax_C (step S305; No), the microcomputer 43 sets the correction amount to Dmax_C per time (step S306), and delays the synchronization clock SCLK_C by Dmax_C (step S307).

  If Da_C <Dmax_C (step S305; Yes), the microcomputer 43 keeps the correction amount Da_C per time (step S308), and delays the synchronization clock by Da_C (step S309).

  Next, a timing unit (not shown) waits for a predetermined time sufficient for the PLL control circuit unit 89C to output the PLL lock signal PLL_C, that is, for the polygon drive motor 18C to rotate at a constant speed (step S310). After the amount Da_C is replaced with a value obtained by subtracting the correction amount per time from Da_C, the processing returns to step S304.

  Thus, since the correction amount per time is smaller than the controllable maximum correction amount Dmax per time, when Da_C <Dmax_C, the correction amount Da_C in step S301 is within a predetermined range in one correction. Must not. Therefore, the process shown in FIG. 8 is repeated until the correction amount Da_C falls within a predetermined range.

  That is, in this embodiment, the correction amount per one time of the synchronous clock SCLK_C is set to an amount that can be followed by the motor control circuit 54C of the polygon mirror 13C without releasing the PLL lock by the PLL control means, and the rotation of the polygon drive motor 18C is A step control method is performed in which phase correction is performed again after stabilization. Note that the correction amount per time of SCLK_C is preferably smaller than a half period of the reference clock signal CLK.

  Further, when phase correction is performed by accelerating the polygon drive motor 18C, the stress of the bearing portion of the motor increases, and the life of the polygon drive motor 18C is shortened. For this reason, the phase correction is performed only in the direction of decelerating the polygon drive motor 18C.

  FIG. 9 is a flowchart for explaining a second embodiment of the synchronous clock phase correction processing executed in the phase control period TC shown in FIG. 5 and step S8 in FIG.

  The processing from step S301 to step S309 is the same as that in the flowchart shown in FIG.

  In the present embodiment, instead of waiting for a predetermined time until the PLL is locked as in Step S311 of the first embodiment, it waits until the PLL lock signal PLL_C becomes active (Step S311; Yes). The point is that the process returns to step S304. That is, in the second embodiment, the PLL lock detection circuit 85C functions as synchronization detection means.

  The state of the clock signal in the image forming apparatus according to the present invention will be described. FIGS. 10 and 11 are timing charts showing states of various clock signals in the synchronous clock phase correction processing shown in FIGS.

  10 and 11, the start timing signal HSYNC_M for one scanning line in the M scanning exposure apparatus 10M, which is executed in the phase control period TC shown in FIG. 5, is started in the K scanning exposure apparatus 10K as the drawing reference timing. A case will be described in which the timing signal HSYNC_K is synchronized at a timing delayed by a predetermined correction amount Da. The same control is performed when synchronizing HSYNC_C and HSYNC_Y of the C and Y colors.

  FIG. 10A shows a state before timing t20 is delayed by a predetermined correction amount Da, and HSYNC_M is synchronized at the same timings t20 and t21 as HSYNC_K.

  Since the waveform of the synchronous clock SCLK_M is distorted due to the stray capacitance of the circuit, a delay occurs from the rising edge of the waveform until the phase level reaches the threshold level at which the phase comparator 80 determines “H”. The phase comparator 80 also has a delay time of the internal circuit. Therefore, in FIG. 10A, even if the synchronous clock SCLK_M rises at the timing t20, the delay time until the phase comparison output Q of the phase comparator 80 becomes the “L” level corresponding to the synchronous clock SCLK_M′H ”. There is a delay in DL. For this reason, the phase comparison output Q becomes 'L' at timing t25 delayed by DL from t20. Therefore, it is preferable to determine the correction amount Da per time in consideration of the delay time generated at the rising edge of the reference clock signal and the delay time generated by the drive control means.

  In step S309 in FIG. 8, when the rising edge of the synchronous clock SCLK_M is delayed by Da (t23), the falling edge of the phase comparison output Q is delayed (t24), and the interval 'L' is shortened (Tp2). For this reason, the output voltage of the low-pass filter 83 is lowered and the polygon drive motor 18M is controlled to decelerate. In this state, since the PLL is not locked, the PLL lock signal is inactive.

  When a predetermined time elapses in step S311 of FIG. 8, finally, as shown in FIG. 10B, HSYNC_M is synchronized with the timing of t22, which is delayed by a predetermined correction amount Da with respect to HSYNC_K. In this state, the output voltage of the low-pass filter 83 is a constant voltage, and the PLL is locked, so the PLL lock signal is active.

  As described above, when the polygon drive motor 18M is started up, it is started up with a synchronous clock having a predetermined phase difference. Therefore, the phase relationship between the HSYNC of each polygon drive motor 18 after the PLL lock and the synchronous clock SCLK is, for example, When the number of surfaces of the polygon mirror 13 is 4 and the number of poles of the FG 52 is 12, the phase difference can be 2/3 of the maximum HSYNC period. When the polygon drive motor 18 is simply started, sub-scanning direction color misregistration correction of one dot or less can be performed in a short time compared to a phase difference of one cycle at the maximum.

  In step S307 in FIG. 8, the microcomputer 43 sets the synchronization clock SCLK_M to the timing t34 obtained by delaying the maximum correction amount Dmax from the original timing t33 as shown by the dotted line in FIG.

  At this time, the phase comparison output Q which is the output of the phase comparator 80 becomes “L” for a moment when the synchronous clock SCLK_M and the comparison clock RCLK_M become “H” at the same time (t33). H '. For this reason, the output voltage of the low-pass filter 83 is lowered, and the polygon drive motor 18 is controlled to be decelerated to the maximum. In this state, as in FIG. 10A, since the PLL is not locked, the PLL lock signal is inactive.

  When a predetermined time elapses in step S314 in FIG. 8, finally, as shown in FIG. 11B, HSYNC_M is synchronized at timing t34 where HSYNC_K is delayed by a predetermined maximum correction amount Dmax with respect to HSYNC_K. In this state, as in FIG. 10B, since the PLL is locked, the PLL lock signal is active.

  When the synchronization clock is delayed by Dmax or more, the phase comparison output Q remains 'H' and exceeds the range of phase control, so that the polygon drive motor 18 may run away. Therefore, it is necessary to control the phase within the range of the maximum correction amount Dmax per time.

  Therefore, the maximum correction amount Dmax set by the microcomputer 43 is a time obtained by subtracting the delay time DL due to waveform distortion or circuit delay from the half period of the period T of the synchronous clock, that is, Dmax = T / 2−. DL.

  As described above, according to the present embodiment, the writing position in the sub-scanning direction of the image forming unit is corrected, and the amount of color misregistration and the writing position in the sub-scanning direction of the first image forming unit are the second image forming positions. By making the range delayed from the writing position in the sub-scanning direction of the means, the phase can be controlled by always decelerating the rotation of the polygon mirror, so there is no stress on the bearing part, there is little failure and the product life is long, An image forming apparatus with reduced color misregistration in the sub-scanning direction can be provided.

  Further, according to the present embodiment, regardless of the relationship between the number of mirror surfaces and the number of pulses generated per rotation of the polygon mirror and the number of motor poles, the phase of the polygon mirror is reliably controlled and color shift in the sub-scanning direction is achieved. Can be provided.

  Further, according to the present embodiment, even if the reference clock for rotation of the polygon mirror is delayed due to distortion or there is a delay during the control of the PLL control means, the phase control is reliably performed in the sub-scanning direction. An image forming apparatus with reduced color misregistration can be provided.

  Further, according to the present embodiment, the phase of each polygon mirror can be synchronized in a short time when the driving of the polygon mirror of the image forming apparatus is started, so that it is possible to provide an image forming apparatus that can start up quickly and have high image quality.

  Further, according to the present embodiment, the rotational phase control of the polygon mirror can be stably performed, so that it is possible to provide a high-quality image forming apparatus that reliably reduces color misregistration in the sub-scanning direction.

  Further, according to the present embodiment, there is no stress in the bearing portion that occurs when the rotation of the polygon mirror is accelerated, so that it is possible to provide an image forming apparatus that has few failures and a long product life.

  Note that the description in the present embodiment described above is an example of a suitable image processing apparatus 1 according to the present invention, and the present invention is not limited to this. For example, although the case where the number of surfaces of the polygon mirror is four has been described as an example, the number of surfaces and the number of magnetic poles are not limited to this.

1 is a schematic view showing an image forming apparatus according to the present invention. 1 is a perspective view showing a schematic configuration of a scanning exposure apparatus provided in an image forming apparatus according to the present invention. 1 is a block diagram illustrating a functional configuration of an image forming apparatus according to the present invention. FIG. 4A is a block diagram showing an internal configuration of the motor control circuit, and FIG. 4B is a timing chart showing states of various signals related to control performed by the motor control circuit. 3 is a timing chart showing the operating state of each part when the image forming apparatus according to the present invention forms an image. 6 is a flowchart showing a flow of registration deviation correction processing executed by the image forming apparatus according to the present invention. It is a figure which shows an example of the resist pattern which concerns on this invention. It is a flowchart which shows the flow of the process which concerns on 1st Embodiment of synchronous clock phase correction. It is a flowchart which shows the flow of the process which concerns on 2nd Embodiment of synchronous clock phase correction. 6 is a timing chart (1/2) showing a state of a clock signal in a synchronous clock phase correction process executed by the image forming apparatus according to the present invention. 6 is a timing chart (2/2) showing a state of a clock signal in a synchronous clock phase correction process executed by the image forming apparatus according to the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Printer 101C, 101M, 101Y, 101K Image forming means 10C, 10M, 10Y, 10K Scanning exposure apparatus 11C Light source unit 12C Collimator lens 13C Polygon mirror 14C fθ lens 15C Reflector 16C SOS sensor 17C, 17M, 17Y, 17K Body 18C, 18M, 18Y, 18K Polygon drive motor 23 Transfer belt 24 TOD sensor 25 Registration sensor 43 Microcomputer 52C, 52M, 52Y, 52K Rotational speed detection signal generator (FG)
54C, 54M, 54Y, 54K Motor control circuit 89C PLL control circuit unit 100 Drive control unit

Claims (3)

An image carrier that is driven to rotate, a laser element that is output-controlled in accordance with image data, and a polygon mirror that reflects laser light emitted from the laser element and scans and exposes the image carrier in the main scanning direction. A transfer belt that is provided with at least two image forming units and that is rotated by a sub-scanning direction orthogonal to the main-scanning direction, or a transfer material that is conveyed by the transfer belt, in which different color images created by the respective image-forming units are rotated. An image forming apparatus that forms an image by multiple transfer to
Each of the image forming means includes
Mirror driving means for rotationally driving the polygon mirror;
Comparison clock signal generation means for generating a comparison clock signal synchronized with the rotation of the polygon mirror,
The image forming apparatus includes:
Control means for controlling the respective image forming means to form a resist pattern of a color corresponding to each of the image forming means on the transfer belt;
The resist pattern is detected, and one of the at least two image forming means is used as a reference image forming means, and the resist pattern by the reference image forming means and other image forming means other than the reference image forming means are used. Color misregistration information acquisition means for acquiring a color misregistration amount for the other image forming means based on the distance from the resist pattern by the image means ;
A reference clock signal generating means for generating a reference clock signal;
Write position correction means for correcting the write position in the sub-scanning direction of the other image forming means in units of the scanning pitch of the other image forming means;
A clock correction unit that corrects the phase of the reference clock signal generated by the reference clock signal generation unit and sets it as a synchronous clock signal for the other imaging unit;
Based on the comparison clock signal generated by the corrected synchronizing clock signal and the comparison clock signal generating means by said clock correction means, have a drive control means for controlling the mirror drive means of the other image forming means,
The color misregistration amount of the other image forming means is an amount indicating that it is delayed from the writing position of the reference image forming means, and is advanced from the writing position of the reference image forming means. In any case, the writing position correction means corrects the writing position of the other imaging means so as to be advanced from the writing position of the reference imaging means. Then, the clock correction unit corrects the phase of the reference clock signal to be delayed.   When the color misregistration amount of the other image forming unit is an amount indicating that it is delayed from the write position of the reference image forming unit, the write position correcting unit is configured to display the color of the other image forming unit. After the correction is made so that the writing position of the other image forming means advances by the number of scan pitch widths obtained by adding 1 to the quotient obtained by dividing the deviation amount by the scan pitch, the clock correction means performs the phase of the reference clock signal. To compensate for the delay,
  When the color misregistration amount of the other image forming unit is an amount indicating that the color misregistration amount of the other image forming unit is advanced from the writing position of the reference image forming unit, the write position correcting unit performs color misregistration of the other image forming unit. The clock correction means delays the phase of the reference clock signal after correcting the writing position of the other imaging means to be delayed by the scanning pitch width of the quotient obtained by dividing the quantity by the scanning pitch. The image forming apparatus according to claim 1, wherein the correction is performed as follows. The clock correction unit corrects the phase of the reference clock signal generated by the reference clock signal generation unit by a plurality of times by an amount smaller than a half cycle of the reference clock signal to obtain a synchronous clock signal. The image forming apparatus according to claim 1, wherein:

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