JP4421814B2 - Capacitor element manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a capacitive element, and more particularly to a method for manufacturing a capacitive element having a ferroelectric film or a high dielectric film.
[0002]
[Prior art]
FeRAM stores information using the hysteresis characteristics of ferroelectrics. A ferroelectric capacitor having a ferroelectric film as a capacitor dielectric between a pair of electrodes generates polarization according to the voltage applied to the pair of electrodes, and has spontaneous polarization even when the applied voltage is removed. If the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. Therefore, information can be read by detecting this spontaneous polarization.
[0003]
FeRAM, like other semiconductor devices, will require a reduction in cell area in the future. In order to reduce the cell area, a stacked capacitor is useful. The stack structure refers to a structure in which a capacitor is formed immediately above a plug formed on the drain of a MOS transistor. Here, the capacitor is formed by laminating various materials such as a barrier metal (oxygen diffusion barrier layer), a lower electrode, a ferroelectric film, and an upper electrode immediately above a tungsten (W) plug. The barrier metal plays a role in suppressing oxygen diffusion into the W plug. Since a material that also functions as the lower electrode is often selected as the barrier metal, the barrier metal and the lower electrode cannot be clearly distinguished. These materials include titanium nitride (TiN), iridium (Ir), iridium oxide (IrO₂), Platinum (Pt), SRO (SrRuO_Three) Is selected.
[0004]
In the ferroelectric capacitor, in order to improve the (111) orientation strength of the ferroelectric layer, generally, Pt is used for the lower electrode sandwiching the ferroelectric layer. However, since Pt has high oxygen permeability, there is a problem that when it is used immediately above the plug in a capacitor having a stack structure, oxygen easily permeates and the plug is oxidized by heat treatment. Therefore, in a ferroelectric capacitor with a stack structure, Pt / IrO is used as the lower electrode from the capacitor dielectric film side.₂A structure laminated with / Ir is often used (see, for example, Patent Document 1). Ir and IrO₂Use Ir or IrO₂This is because the oxygen permeability is very small and functions as an oxygen diffusion barrier layer in heat treatment.
[0005]
[Patent Document 1]
JP-A-9-22829
[0006]
[Problems to be solved by the invention]
However, when using a PZT film deposited by sputtering as the capacitor dielectric film, an iridium-based oxygen diffusion barrier layer (Ir film, IrO₂It has been found that the use of a lower electrode having a structure including a film increases the leakage current of the capacitor. The reason is considered as follows.
[0007]
When a PZT film is deposited on the lower electrode by sputtering, the PZT film immediately after deposition is in an amorphous state. In order to make full use of the ferroelectric properties, it is necessary to crystallize the PZT film, which requires high-temperature heat treatment. However, when a lower electrode with a Pt film formed on an iridium-based oxygen diffusion barrier layer is used, high-temperature heat treatment is performed for crystallization of the PZT film on the lower electrode. The Ir element in the barrier layer permeates the Pt film, diffuses into the PZT film, and is taken into the PZT crystal. For this reason, the insulating property of the PZT crystal is lowered.
[0008]
Such a phenomenon can be avoided by growing a PZT film in a crystalline state directly on the lower electrode or crystallizing the PZT film at a low temperature, but the dielectric constant of the formed PZT film is small. turn into.
[0009]
It is an object of the present invention to prevent oxidation of a conductive plug immediately below a lower electrode during deposition of a capacitor dielectric film and during crystallization of the deposited film, and also prevent metal diffusion from the lower electrode to the capacitor dielectric film. Another object of the present invention is to provide a method for manufacturing a capacitive element having excellent ferroelectric characteristics.
[0010]
[Means for Solving the Problems]
  The above issues areIr single layer structure or Ir and IrO _x It consists of either of the two-layer structureA first conductive film containing a first metal;By sputteringDifferent from the first metal on the dummy substrate in the forming step and in the chamberPtA step of forming a film made of the second metal and removing residual oxygen from the chamber, and after removing the residual oxygen, increasing the orientation strength of the third conductive film formed later in the chamberHaving (111) orientationAn interface conductive film made of the second metal is formed on the first conductive film.By sputteringForming a second conductive film made of a metal oxide of the second metal which is a diffusion barrier layer of the first metal on the interface conductive film in an atmosphere containing oxygen in the chamber.By sputteringThe step of forming is different from the first metal, which is an orientation control layerPtThe third conductive film made of a third metal is disposed on the second conductive film.By sputteringForming, heat-treating, crystallizing the third conductive film, and on the third conductive filmMade of ferroelectric materialForming a dielectric film;Performing a heat treatment to crystallize the dielectric film;Forming a fourth conductive film on the dielectric film; and patterning the first conductive film, the interface conductive film, the second conductive film, and the third conductive film to form a capacitive element lower electrode. And a step of patterning the dielectric film to form a capacitor element dielectric film, and a step of patterning the fourth conductive film to form a capacitor element upper electrode. Solved.
[0011]
In order to remove residual oxygen in the chamber by the above-described method for manufacturing a capacitive element, an interface conductive film is formed on a dummy substrate.
[0013]
Furthermore, the capacitor element includes a semiconductor substrate under the insulating film, an opening penetrating the insulating film, and a buried conductive film embedded in the opening, and the first conductive film of the capacitor element. Is connected to the semiconductor substrate through a buried conductive film. Therefore, it is possible to apply the above-described method for manufacturing a capacitive element to a method for manufacturing an FeRAM or other semiconductor device.
[0014]
Incidentally, in Japanese Patent Application No. 2001-213547 filed by the same applicant, platinum / platinum oxide / iridium oxide / iridium (Pt / PtO) is used as a lower electrode of a ferroelectric capacitor having a stacked structure._x/ IrO_x/ Ir) structure or platinum / platinum oxide / iridium (Pt / PtO)_x/ Ir) structure has been proposed, and a PtO film is formed between a conductive film containing no Ir and a conductive film containing Ir._xA conductive oxide layer containing no Ir is interposed. Ir, IrO_xSuppresses oxygen diffusion, PtO_xSuppresses diffusion of Ir into the PZT film, and IrO_xIncreases the orientation of Pt.
[0015]
With such a lower electrode structure, during the deposition of the capacitor dielectric film and in the crystallization process of the deposited film, for example, PtO_xIt is possible to prevent the metal diffusion from the lower electrode to the capacitor dielectric film by the metal diffusion barrier layer made of the film, and to secure the characteristics of the ferroelectric film. Further, when applied to a manufacturing method of a semiconductor device such as FeRAM, for example, Ir, IrO_xOxidation of the conductive plug directly under the lower electrode can be prevented by the oxygen diffusion barrier layer made of
[0016]
However, higher performance is required, and Pt / PtO_xIn the / Ir structure, further stability of the electrical characteristics of the capacitor is required. Pt / PtO_x / IrO_xIn the / Ir structure, it is required to increase the ferroelectricity of the PZT film after crystallization. In order to meet this requirement, Japanese Patent Application No. 2002-16083 of the same applicant states that PtO_xMembrane and IrO_xBetween membranes or PtO_xBy sandwiching the Pt-interface layer between the film and the Ir film, the (111) orientation strength of the lower electrode was increased, and a ferroelectric film having high ferroelectricity could be obtained. And IrO_xIt was possible to increase the ferroelectricity by reducing the degree of oxidation (referred to as metallic).
[0017]
However, the stack structure created by the method of Japanese Patent Application No. 2002-16083 is still insufficient for the demand for higher performance. First, metallic IrO_xIs unstable, so when crystallizing a ferroelectric film, IrO_xIs easily reoxidized and the film is easily peeled off. Second, PtO_x/ Pt is a continuous film, so Pt film and PtO on one substrate_xThere is a possibility that a complete metal platinum film cannot be formed due to the influence of oxygen remaining in the chamber when the Pt film is formed on the next substrate after the film is continuously formed. In this case, there is a possibility that the function of the Pt-interface layer for enhancing the (111) orientation strength cannot be exhibited. That is, when the function of the Pt-interface layer is not sufficiently exhibited, the (111) orientation strength of the orientation control layer (Pt film) underlying the capacitor dielectric film in the lower electrode of the stack structure is weakened. The ferroelectricity does not increase as expected.
[0018]
In the present invention, a second conductive film made of a metal oxide of a second metal (for example, PtO_xFilm) and the first metal oxide film (for example, IrO)_xA second conductive film made of a metal oxide of a second metal (for example, PtO)_xIn forming a lower electrode structure in which a second metal interface conductive film (for example, Pt-interface layer) is interposed between a first metal film (for example, an Ir film), a second metal interface conductive film is formed. (Eg, Pt-interface layer) and a second conductive film (eg, PtO_xFilm) in the same chamber, residual oxygen in the chamber is removed before the second metal interface conductive film is formed.
[0019]
For example, the lot organization includes one or more dummy substrates in addition to the formal substrate for forming the capacitive element, and the same film is formed on the dummy substrate before the film formation on the formal substrate. In this case, a method of continuously forming the second conductive film made of the second metal interface and the second conductive film made of the metal oxide of the second metal one by one may be used. It is more efficient to form the metal interface conductive film and the second conductive film made of the metal oxide of the second metal in lot units.
[0020]
In the chamber, a second conductive film (eg, PtO) made of a metal oxide of a second metal with respect to the previous substrate or the previous lot._xEven if oxygen remains when the film is formed, the same film is formed on the dummy substrate before the second metal interface conductive film (eg, Pt-interface layer) is formed on the substrate. By filming, residual oxygen in the chamber is consumed and removed from the chamber. Therefore, when forming the interface conductive film of the second metal on the substrate, it is possible to form the interface conductive film made of the complete second metal free from oxygen contamination.
[0022]
As described above, the interface strengthening function is exhibited by the interface conductive film that does not contain oxygen, for example, the Pt-interface layer, so that the (111) orientation strength of the third conductive film underlying the capacitor ferroelectric film can be increased. Thereby, the (111) orientation strength of the capacitor ferroelectric film on the lower electrode can be increased and the ferroelectricity thereof can be increased.
[0023]
Such a method is applied to a second conductive film made of a metal oxide of a second metal (for example, PtO_xAfter the film is formed, it is preferably applied when a third conductive film (for example, a Pt film) made of the third metal under the capacitor ferroelectric film is formed. As a result, when the third conductive film is formed on the substrate, there is a possibility that oxygen may be mixed in the first several lots in the conventional method. Then, a third conductive film made of a complete third metal free from oxygen can be formed.
[0024]
In addition, this allows iridium oxide (IrO_xWhen the lower electrode having an oxygen diffusion barrier layer including a film is used, the ferroelectricity of the capacitor ferroelectric film can be sufficiently enhanced without reducing the oxidation degree of iridium oxide, that is, without making it metallic. For this reason, film peeling of the laminated structure of the lower electrode can be prevented.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0026]
(First embodiment)
(Capacitor structure)
Next, the structure of the capacitive element produced by the manufacturing method according to the first embodiment of the present invention will be described with reference to FIG. FIG. 5 is a cross-sectional view showing the structure of the capacitive element.
[0027]
In the capacitive element, an interlayer insulating film 12 composed of a silicon oxide film, a silicon nitride film, or the like is formed on a silicon substrate 10. A contact hole 14 reaching the silicon substrate 10 is formed in the interlayer insulating film 12. A conductive plug 16 that is electrically connected to the silicon substrate 10 is formed in the contact hole 14. On the interlayer insulating film 12 in which the plug 16 is embedded, a lower electrode 30a composed of a multilayer conductive film, a capacitor dielectric film 32a made of a PZT film formed on the lower electrode 30a, and a capacitor dielectric film A capacitor element having an upper electrode 34a made of a platinum (Pt) film formed on 32a is formed. The lower electrode 30a includes an iridium (Ir) film (first conductive film, oxygen diffusion barrier layer) 18, iridium oxide (IrO_x) Film (first conductive film, oxygen diffusion barrier layer) 20, first platinum (Pt) film (interface conductive film, Pt-interface layer) 21, platinum oxide (PtO)_x) Film (second conductive film, Ir diffusion barrier layer) 22 and second platinum (Pt) film (third conductive film, orientation control layer) 24 are sequentially laminated.
[0028]
(Capacitance element structure according to modification)
In the above, the oxygen diffusion barrier layer is IrO_xAlthough a two-layer structure of / Ir is used, an Ir single-layer structure may be used. FIG. 6 is a cross-sectional view showing the structure of a capacitive element using an Ir single layer structure as the oxygen diffusion barrier layer constituting the lower electrode 30b.
[0029]
In the structure of the capacitive element, a capacitor comprising an interlayer insulating film 12 having the same structure as that shown in FIG. 5, a lower electrode 30b including an Ir single layer structure as an oxygen diffusion barrier layer, and a PZT film formed on the lower electrode 30b. A capacitive element having a dielectric film 32a and an upper electrode 34a made of a Pt film formed on the capacitor dielectric film 32a is formed. The lower electrode 30b includes an Ir film (first conductive film, oxygen diffusion barrier layer) 18, a first Pt film (interface conductive film, Pt-interface layer) 21, and PtO._xA film (second conductive film, Ir diffusion barrier layer) 22 and a second Pt film (third conductive film, orientation control layer) 24 are sequentially stacked.
[0030]
As described above, the capacitive element according to the present embodiment shown in FIGS. 5 and 6 includes the lower electrodes 30a and 30b, the oxygen diffusion barrier layer, the first Pt film 21, and the PtO._xThe main feature is that it is formed of a laminated film of the film 22 and the second Pt film 24. In FIG. 5, the oxygen diffusion barrier layer is formed of Ir film 18 and IrO._xIt consists of two layers of film 20, and in FIG.
[0031]
Hereinafter, the reason why the lower electrodes 30a and 30b are configured in such a stacked structure in the capacitor according to the present embodiment will be described.
[0032]
In Japanese Patent Application No. 2001-213547 filed by the same applicant, Pt / PtO is used as a lower electrode of a ferroelectric capacitor having a stacked structure._x/ IrO_x/ Ir structure or Pt / PtO_x/ Ir structure has been proposed, PtO between the conductive film not containing Ir and the conductive film containing Ir_xA conductive oxide layer containing no Ir is interposed. Ir, IrO_xSuppresses oxygen diffusion, PtO_xSuppresses diffusion of Ir into the PZT film, and IrO_xIncreases the orientation of Pt.
[0033]
With such a lower electrode structure, during the deposition of the capacitor dielectric film and in the crystallization process of the deposited film, for example, PtO_xIt is possible to prevent the metal diffusion from the lower electrode to the capacitor dielectric film by the metal diffusion barrier layer made of the film, and to secure the characteristics of the ferroelectric film. Further, when applied to a manufacturing method of a semiconductor device such as FeRAM, for example, Ir, IrO_xOxidation of the conductive plug directly under the lower electrode can be prevented by the oxygen diffusion barrier layer made of
[0034]
For the above ferroelectric capacitors, higher performance is required, and Pt / PtO_xIn the / Ir structure, further stability of the electrical characteristics of the capacitor is required. Pt / PtO_x / IrO_xIn the / Ir structure, it is required to increase the ferroelectricity of the PZT film after crystallization.
[0035]
In order to meet this requirement, Japanese Patent Application No. 2002-16083 of the same applicant states that PtO_xMembrane and IrO_xBetween membranes or PtO_xBy sandwiching the Pt-interface layer between the film and the Ir film, the (111) orientation strength of the lower electrode was increased, and a ferroelectric film having high ferroelectricity could be obtained. And IrO_xIt was possible to increase the ferroelectricity by reducing the degree of oxidation (referred to as metallic).
[0036]
Such a structure is applied to the capacitive element of FIGS. 5 and 6 of the present invention. Therefore, the Ir film 18 and the IrO are formed according to the configuration of the capacitive element shown in FIGS._xThe film 20 or the Ir film 18 functions as an oxygen diffusion barrier, and PtO_xSince the film 22 functions as an Ir diffusion barrier, it is possible to prevent oxygen from entering the capacitor dielectric film 32 and diffusing Ir into the capacitor dielectric film 32. Therefore, it is possible to form the capacitor dielectric film 32a having a desired dielectric constant while maintaining the contact characteristics between the plug 16 and the lower electrodes 30a and 30b. In addition, PtO_xFilm 22 and IrO_xBetween membranes 20 or PtO_xBy sandwiching the Pt-interface layer 21 between the film 22 and the Ir film 18, the (111) orientation strength of the lower electrodes 30a and 30b can be increased, and a ferroelectric film having high ferroelectricity can be obtained.
[0037]
As described above, a ferroelectric capacitor capable of exhibiting excellent performance in terms of the element structure was obtained. However, the stack structure created by the method shown in Japanese Patent Application No. 2002-16083 is in response to the demand for further higher performance. There are still some inadequacies: First, metallic IrO_xIs unstable, so when crystallizing a ferroelectric film, IrO_xMay be easily reoxidized and the film may be easily peeled off. Second, PtO_x/ Pt is a continuous film, so Pt film and PtO on one substrate_xThere is a possibility that a complete metal platinum film cannot be formed due to the influence of oxygen remaining in the chamber when the Pt film is formed on the next substrate after the film is continuously formed. When oxygen is mixed into the Pt-interface layer (first Pt film), the function of the Pt-interface layer to increase the (111) orientation cannot be exhibited. For this reason, the orientation control layer (second Pt film) (111) orientation strength underlying the capacitor dielectric film becomes weak, and the ferroelectricity of the capacitor dielectric film cannot be sufficiently increased.
[0038]
Therefore, in the present invention, when the stack structure is created, a film is formed using a manufacturing apparatus described below and by a manufacturing method described subsequently.
[0039]
(Capacitance element manufacturing equipment)
FIG. 2 is a side view showing a manufacturing apparatus used in the method for manufacturing a capacitive element according to the first embodiment of the present invention. The manufacturing apparatus is an apparatus for forming a multi-layered conductive film that is configured by one multi-chamber system and forms a lower electrode of a capacitive element.
[0040]
As shown in FIG. 2, the apparatus configuration includes first and second load lock chambers 102a and 102b, and an iridium (Ir) -containing conductive film deposition chamber (hereinafter referred to as an Ir chamber) 103. , A platinum (Pt) -containing conductive film deposition chamber (hereinafter referred to as a Pt chamber) 104 is connected to the transfer chamber 101 via an open / close valve. Each chamber 101, 102a, 102b, 103, 104 can be decompressed independently of each other.
[0041]
The first and second load lock chambers 102a and 102b serve as loading / unloading ports for loading / unloading substrates into / from the film forming chambers 103 and 104. Although the first and second load lock chambers 102a and 102b are normally depressurized, the first and second load lock chambers 102a and 102b are made large in order to match the atmospheric pressure when the substrate is loaded / unloaded. Set to atmospheric pressure. The first load lock chamber 102a is used when the Ir-containing conductive film is formed, and the second load lock chamber 102b is used when the Pt-containing conductive film is formed. The first and second load lock chambers 102a and 102b do not have to be divided for each type of film to be formed. However, in the process of forming a multilayer in mass production, the film formation time is long or short depending on the type of film to be formed. Therefore, separating the chambers 102a and 102b depending on the type of film to be formed is beneficial for efficient film formation.
[0042]
In the Ir chamber 103, an Ir film or IrO serving as an oxygen diffusion barrier layer._xIn the Pt chamber 104, a first Pt film serving as a Pt-interface layer, a second Pt film serving as an orientation control layer, and PtO serving as an Ir diffusion barrier layer are formed._xA film is formed. The transfer chamber 101 serves as a relay place when the substrate is moved from one chamber to another among the chambers 102a, 102b, 103, and 104.
[0043]
FIG. 3 is a diagram showing the configuration of another manufacturing apparatus used in the method for manufacturing a capacitive element according to the first embodiment of the present invention. This manufacturing apparatus is composed of two multi-chamber systems (apparatus 1 and apparatus 2), and is an apparatus for forming a multi-layer lower electrode conductive layer in a different chamber for each layer.
[0044]
As shown in FIG. 3, the first multi-chamber system (apparatus 1) 202 includes first and second load lock chambers 112a and 112b, first and second Ir chambers 113 and 114, and a first A Pt chamber 115 is connected to the transfer chamber 111 via an open / close valve. Each chamber 111, 112a, 112b, 113, 114, 115 can be decompressed independently of each other.
[0045]
The first and second load lock chambers 112a and 112b serve as loading / unloading ports for loading / unloading substrates into / from the film forming chambers 113, 114, and 115. Although the first and second load lock chambers 112a and 112b are normally depressurized, the first and second load lock chambers 112a and 112b are loaded into and unloaded from the first and second load lock chambers 112a and 112b. The inside of the lock chambers 112a and 112b is set to atmospheric pressure. The first load lock chamber 112a is used when the Ir-containing conductive film is formed, and the second load lock chamber 112b is used when the Pt-containing conductive film is formed.
[0046]
In the Ir chambers 113 and 114, an Ir film and an IrO film serving as an oxygen diffusion barrier layer, respectively._xA film is formed, and in the first Pt chamber 115, a first Pt film serving as a Pt-interface layer is formed. The transfer chamber 111 serves as a relay place when the substrate is moved from one chamber to another chamber among the chambers 112a, 112b, 113, 114, and 115.
[0047]
Further, as shown in FIG. 3, the second multi-chamber system (device 2) 203 includes third and fourth load lock chambers 122a and 122b, and second and third Pt chambers 123 and 124, respectively. It is connected to the transfer chamber 121 via an open / close valve. Each chamber 121, 122a, 122b, 123, 124 can be decompressed independently of each other.
[0048]
In the second Pt chamber 123, platinum oxide (PtO) serving as an Ir diffusion barrier layer._x) A film is formed, and in the third Pt chamber 124, a second Pt film to be an orientation control layer is formed.
[0049]
The third and fourth load lock chambers 122a and 122b serve as loading / unloading ports for loading / unloading the substrate into / from the film forming chambers 123 and 124, respectively. Although the pressure in the third and fourth load lock chambers 122a and 122b is normally reduced, the third and fourth loads are loaded when the substrates are loaded into and unloaded from the first and second load lock chambers 122a and 122b. The inside of the lock chambers 122a and 122b is set to atmospheric pressure. PtO_xThe third load lock chamber 122a is used for film formation, and the fourth load lock chamber 122b is used for film formation of the second Pt film.
[0050]
The transfer chamber 121 serves as a relay place when the substrate is moved from one chamber to another between the chambers 122a, 122b, 123, and 124.
[0051]
(Description of manufacturing method of capacitive element using manufacturing apparatus of FIG. 2)
Next, a method for manufacturing a capacitive element using the manufacturing apparatus shown in FIG. 2 according to the first embodiment of the present invention will be described with reference to FIGS. 1, 4A to 4C, and FIG. FIG. 1 is a flowchart showing a method for manufacturing a capacitive element, and FIGS. 4A to 4C and FIG. 5 are process cross-sectional views showing the method for manufacturing the capacitive element. Using the manufacturing apparatus of FIG. 2, a multilayer lower electrode conductive layer among the elements constituting the capacitor element is formed.
[0052]
In the manufacturing method using the manufacturing apparatus of FIG. 2, the first Pt film (Pt-interface layer, interface conductive film made of the second metal) in the lower electrode conductive layer, and PtO_xFilm (Ir diffusion barrier layer, second conductive film made of metal oxide of second metal) and second Pt film (orientation control layer, third conductive film made of second metal) underlying capacitor dielectric film ) In the same Pt chamber, and at least before the first Pt film is formed and before the second Pt film is formed, residual oxygen in the chamber is removed. Then, one lot is formed by 20 formal substrates and 5 dummy substrates, and a plurality of lots are processed. Each lot is characterized in that a film is formed on five dummy substrates prior to the formal film formation on the substrate in order to remove residual oxygen in the chamber.
[0053]
First, a process until a substrate (CMOS substrate) shown in FIG. 4A is formed (process P1 shown in FIG. 1) will be described. In the process of P1, the following processes are sequentially performed on the silicon substrates constituting at least two lots.
[0054]
A silicon oxide film having a film thickness of, for example, 700 nm is deposited on the silicon substrate 10 by, eg, CVD, and an interlayer insulating film 12 made of the silicon oxide film is formed.
[0055]
Next, a contact hole reaching the silicon substrate 10 is formed in the interlayer insulating film 12 by photolithography and dry etching.
[0056]
Next, a titanium (Ti) film with a thickness of 20 nm, a titanium nitride (TiN) film with a thickness of 10 nm, and a tungsten (W) film with a thickness of 300 nm are deposited on the entire surface by, eg, CVD.
[0057]
Next, the W film, the TiN film, and the Ti film are polished flatly by, for example, CMP (Chemical Mechanical Polishing) method until the surface of the interlayer insulating film 12 is exposed, and the W / TiN / Ti structure is laminated. A plug 16 having a structure and embedded in the contact hole 14 is formed (FIG. 4A).
[0058]
Next, steps required until the structure shown in FIG. 4B is formed (steps P2 to P6 shown in FIG. 1) will be described. In the step of forming a multilayer lower electrode conductive layer, the manufacturing apparatus shown in FIG. 2 is used.
[0059]
First, 25 substrates are extracted from the plurality of substrates having the structure 4 (a), 5 dummy substrates and 20 formal substrates are set, and one lot is organized. In this way, at least two lots are organized.
[0060]
First, in step P2, the first load lock chamber 102a is set to atmospheric pressure, and a dummy substrate having a structure shown in FIG. 4A is carried into the first load lock chamber 102a. Next, the first load lock chamber 102a is depressurized, and when a predetermined pressure is reached, the opening / closing valve is opened, the dummy substrate is unloaded from the first load lock chamber 102a, and loaded into the transfer chamber 101. Next, the open / close valve is opened, and the dummy substrate is unloaded from the transfer chamber 101 and loaded into the Ir chamber 103. In the Ir chamber 103, an Ir film 18 having a thickness of, for example, about 200 nm is formed on the entire surface of the interlayer insulating film 12 and the plug 16 of the dummy substrate by, eg, sputtering. For example, the film is formed for 140 seconds at a substrate temperature of 500 ° C., a power of 1 kW, and an argon (Ar) gas flow rate of 100 sccm. After the film formation is completed, the dummy substrate is put on standby in the first load lock chamber 102a or in the substrate storage cassette outside the apparatus by the reverse route. After sequentially forming the films on the five dummy substrates as described above, the films are sequentially formed on the 20 official substrates in the same manner. In the case of the structure shown in FIG. 6, the process proceeds to step P3 after the film formation is completed.
[0061]
Next, the dummy substrate is loaded again into the Ir chamber 103, and the IrO film having a film thickness of, for example, about 28 nm is formed on the Ir film 18 by, for example, sputtering in the Ir chamber 103._xA film 20 is formed. For example, the film is formed for 10 seconds at a substrate temperature of 50 ° C., a power of 1 kW, an Ar gas flow rate of 60 sccm, and an oxygen gas flow rate of 60 sccm. After sequentially forming the films on the five dummy substrates as described above, the films are sequentially formed on the 20 official substrates in the same manner. Each time the film formation is completed, the substrate is unloaded from the Ir chamber 103 and placed in a standby state in the second load lock chamber 102b or in a substrate storage cassette outside the apparatus.
[0062]
Next, in step P3, the dummy substrate is unloaded from the second load lock chamber 102b and loaded into the Pt chamber 104 via the transfer chamber 101. In the Pt chamber 104, IrO_xA first Pt film 21 having a film thickness of, for example, about 15 nm is formed on the film 20 by, eg, sputtering. 6 is formed, the first Pt film 21 is formed on the Ir film 18.
[0063]
For example, the substrate temperature is set to 350 ° C., the power is set to 1 kW, Ar gas is introduced into the growth atmosphere at a flow rate of 100 sccm, the pressure is adjusted to 0.38 Pa, and the growth time is set to 8 seconds. The first Pt film 21 is an interface conductive film for enhancing the (111) orientation of the second Pt film 24. After sequentially forming the films on the five dummy substrates as described above, the films are sequentially formed on the 20 official substrates in the same manner. Each time the film formation is completed, the substrate is unloaded from the Pt chamber 104 and kept in the second load lock chamber 102b or in a substrate storage cassette outside the apparatus.
[0064]
Next, in the process of P4, the dummy substrate is unloaded from the second load lock chamber 102b and loaded into the Pt chamber 104 via the transfer chamber 101. In the Pt chamber 104, a PtO film having a thickness of, for example, about 25 nm is formed on the first Pt film 21 of the dummy substrate by, eg, sputtering._xA film 22 is formed. For example, the film is formed for 22 seconds at a substrate temperature of 350 ° C., a power of 1 kW, an Ar gas flow rate of 36 sccm, an oxygen gas flow rate of 144 sccm, and a pressure of 6.2 Pa. At this time, PtO_xThe composition ratio x of the film 22 is, for example, in the range of greater than 0 and 2 or less. After sequentially forming the films on the five dummy substrates as described above, the films are sequentially formed on the 20 official substrates in the same manner. Each time film formation is completed, the substrate is unloaded from the Pt chamber 104 and kept in the load lock chamber 102b or a substrate storage cassette outside the apparatus.
[0065]
PtO_xWhen the substrate temperature at the time of forming the film 22 is lower than 200 ° C. or 400 ° C. or higher, a decrease in the residual charge amount is observed. PtO_xWhen the substrate temperature when forming the film 22 is lower than 200 ° C. or 400 ° C. or higher, the leakage current increases. Also, at substrate temperatures above 400 ° C, PtO_xDuring the formation of the film 22, oxygen is dissociated and a Pt film is formed. Therefore, PtO_xThe substrate temperature when forming the film 22 is desirably set to 200 ° C. or higher and lower than 400 ° C. Further, the residual charge amount becomes larger as the film forming temperature is higher within the temperature range. Therefore, PtO_xThe substrate temperature when forming the film 22 is desirably set to a higher temperature in the above temperature range, for example, a temperature of about 350 ° C.
[0066]
Also, under the above film formation conditions, PtO_xAlthough the film thickness of the film 22 is about 25 nm, a film thickness of 15 nm or more can be appropriately selected. If the film thickness is less than 15 nm, PtO_xThe adhesion of the film 22 is not sufficient, and if it is too thick, the subsequent workability deteriorates. Therefore, PtO_xThe thickness of the film 22 is preferably 15 nm or more and is appropriately selected according to the device structure and process to be applied.
[0067]
Also, under the above film formation conditions, PtO_xThe gas flow ratio in forming the film 22 is Ar: O.₂= 1: 4, but the gas flow ratio is Ar: O₂= 7: 2 to 1: 9 (oxygen concentration 40 to 90%) Even if it changes, the residual charge amount of the capacitor element to be formed hardly changes. That is, PtO_xIt is considered that the gas flow rate ratio when forming the film 22 does not affect the residual charge amount. From this, PtO_xAny number of gas flow ratios may be used for forming the film 22, and the oxygen concentration is preferably 40 to 80%.
[0068]
Next, in step P5, the dummy substrate is unloaded from the second load lock chamber 102b and loaded into the Pt chamber 104 via the transfer chamber 101. In the Pt chamber 104, PtO_xA second Pt film 24 having a thickness of, for example, about 50 nm is formed on the film 22 by, eg, sputtering. For example, the substrate temperature is 100 ° C., the power is 1 kW, the Ar gas flow rate is 100 sccm, the pressure is adjusted to 0.4 Pa, and the film is formed for 32 seconds. After sequentially forming the films on the five dummy substrates as described above, the films are successively formed on the 20 official substrates in the same manner. At this time, the Pt chamber 104 has a PtO of the previous process._xOxygen used during film formation may remain, so oxygen may be mixed into the formed Pt film. However, since the film is first formed on the dummy substrate, it remains due to film formation on the dummy substrate. Oxygen is consumed and diluted so that there is no risk of contamination. Therefore, it is possible to form a Pt film free from oxygen contamination on a formal substrate.
[0069]
The substrate on which film formation has been completed is unloaded from the Pt chamber 104 every time film formation is completed, and is kept waiting in the load lock chamber 102b or a substrate storage cassette outside the apparatus.
[0070]
The substrate temperature when forming the second Pt film 24 is set to less than 400 ° C. When forming a film at a temperature of 400 ° C or higher, the underlying PtO_xThis is because oxygen is dissociated from the film 22 and the Ir diffusion preventing action is deteriorated.
[0071]
Next, in the process of P6, a rapid heat treatment is performed in an Ar gas atmosphere at 600 to 750 ° C. for 60 seconds to crystallize the second Pt film 24. By this heat treatment, since the second Pt film 24 has a predetermined orientation direction, the orientation direction of the PZT film to be formed later can be controlled.
[0072]
Next, steps required until the structure shown in FIG. 4C is formed (steps P7 to P9 shown in FIG. 1) will be described.
[0073]
In the process of P7, on the second Pt film 24, for example, PZT (Pb (Zr_x, Ti_1-x) O_ThreeA dielectric film 32 made of a film is formed. Other methods for forming the dielectric film 32 include a MOD (Metal Organic Deposition) method, a MOCVD (Organic Metal CVD) method, and a sol-gel method. In addition to PZT, the dielectric film 32 is made of other PZT materials such as PLZT and PLCCSZT, and SBT (SrBi₂Ta₂O₉), SrBi₂(Ta, Nb)₂O₉Bi layered structure compound materials such as, and other metal oxide ferroelectrics may also be used. In addition, when a high-dielectric capacitor is to be formed, a Ba film is used instead of a ferroelectric film._zSr_1-xTiO_Three, SrTiO_ThreeA high dielectric film such as PLZT is formed.
[0074]
Next, in step P8, a rapid heat treatment at 750 ° C. is performed in an oxygen atmosphere to crystallize the PZT film 32. At this time, the PZT film 32 is (111) oriented to reflect the orientation direction of the underlying second Pt film 24. Also, the PZT film 32 and IrO_xPtO functioning as an Ir diffusion barrier layer between the film 20_xSince the film 22 is formed, Ir does not diffuse into the PZT film 32 even if such high-temperature heat treatment is performed.
[0075]
Next, in the process of P9, IrO with a film thickness of, for example, 100 nm is formed on the PZT film 32 by, for example, sputtering._xA film (upper electrode conductive layer) 34 is formed. For example, the film is formed for 54 seconds at a substrate temperature of 13 ° C., a power of 1 kW, and an Ar gas flow rate of 100 sccm.
[0076]
Next, steps required until the structure shown in FIG. 5 is formed (steps P10 and P11 shown in FIG. 1) will be described.
[0077]
In the process of P10, IrO is performed by photolithography and dry etching._xFilm 34, PZT film 32, second Pt film 24, PtO_xFilm 22, first Pt film 21, IrO_xThe film 20 and the Ir film 18 are patterned into the same shape, and the second Pt film 24 / PtO_xFilm 22 / First Pt film 21 / IrO_xA lower electrode 30a made of the film 20 / Ir film 18, a capacitor dielectric film 32a made of a PZT film formed on the lower electrode 30a, and an IrO film formed on the capacitor dielectric film 32a._xAn upper electrode 34a made of a film is formed.
[0078]
Thus, the second Pt film 24 / PtO_xFilm 22 / First Pt film 21 / IrO_xThe capacitive element of FIG. 5 having the lower electrode 30a made of the film 20 / Ir film 18 can be formed. IrO_xWhen the film 20 is omitted, the second Pt film 24 / PtO_xThe capacitive element of FIG. 6 having the lower electrode 30b made of the film 22 / first Pt film 21 / Ir film 18 can be formed.
[0079]
Next, in the process of P11, annealing after patterning is performed in order to recover the crystallinity of the dielectric film, if necessary.
[0080]
Next, regarding the second lot, a capacitive element is created in the same manner as in the first lot. In the second lot, the first lot of IrO_xAfter the film 20 is formed, the first lot may be loaded into the first load lock chamber 102a while the first lot is waiting in the second load lock chamber 102b, and the film formation may be started. In this case, the first lot of IrO_xAfter the film 20 is formed, the Ir film 18 of the second lot is formed while the first lot is waiting in the second load lock chamber 102b or the like. Alternatively, after all the film formation of the first lot is completed, the film may be loaded into the first load lock chamber 102a and the film formation may be started.
[0081]
In the above description, when the Pt-interface layer 21 of the second lot is formed in the Pt chamber 104, the second Pt film 24 underlying the capacitor dielectric film with respect to the first lot is immediately before the same Pt chamber 104. However, for example, PtO with respect to the first lot immediately before in the Pt chamber 104 is not a problem._xWhen the film 22 is formed, residual oxygen is removed by a dummy substrate, thereby forming a Pt-interface layer made of a complete metal platinum film free from oxygen contamination.
[0082]
Thus, according to the present embodiment, even if oxygen remains when the platinum oxide film of the previous lot is formed in the Pt chamber 104, the Pt-interface layer is formed on the substrate of the lot. By depositing the same film on the dummy substrate before deposition, residual oxygen in the Pt chamber 104 is consumed and removed from the Pt chamber 104. Therefore, when forming the Pt-interface layer on the substrate of the lot, it is possible to form the Pt-interface layer made of a complete metal platinum film free from oxygen contamination.
[0083]
As described above, the function of enhancing the alignment is exhibited by the Pt-interface layer not containing oxygen, so that the (111) orientation strength of the second Pt film underlying the capacitor ferroelectric film can be increased. Thereby, the (111) orientation strength of the capacitor dielectric film 32 on the lower electrode 30a can be increased and the ferroelectricity thereof can be increased.
[0084]
PtO_xThe method of removing residual oxygen using a dummy substrate is also applied when the second Pt film 24 underlying the capacitor dielectric film 32 is formed after the film 22 is formed. As a result, when the second Pt film 24 is formed on the official substrate, the complete metal platinum film 24 free from oxygen contamination can be formed. As a result, the (111) orientation strength of the second Pt film 24 underlying the capacitor dielectric film 32a can be further increased, so that the ferroelectricity of the capacitor dielectric film 32a can be further increased.
[0085]
This makes IrO_xWhen the lower electrode 32a having the oxygen diffusion barrier layer including the film 20 is used, IrO_xEven if the degree of oxidation of the lower electrode 30a is not reduced, that is, it is not made metallic, the ferroelectricity of the capacitor dielectric film 32a can be sufficiently increased, so that the layered structure of the lower electrode 30a can be prevented from peeling off.
[0086]
(Description of manufacturing method of capacitive element using manufacturing apparatus of FIG. 3)
Next, a method for manufacturing a capacitive element using the manufacturing apparatus of FIG. 3 according to the embodiment of the present invention will be described. Among the elements constituting the capacitive element, the layer structure of the lower electrode and the film formation conditions of the layer structure are the same as described above, and the manufacturing method of the components other than the lower electrode is the same as the above manufacturing method.
[0087]
In the manufacturing method using the manufacturing apparatus of FIG. 3, the first Pt film (Pt-interface layer) 21 and the PtO_xA film (Ir diffusion barrier layer) 22 and a second Pt film (orientation control layer) 24 under the capacitor dielectric film are formed in different chambers. In this case, since there is no possibility of oxygen mixing into the Pt-interface layer and the orientation control layer under the capacitor ferroelectric film, it is possible to form one lot with only a formal substrate. However, if it is desired to remove oxygen remaining in the chamber more completely, a lot may be formed using a dummy substrate in addition to the official substrate. Below, the case where one lot is comprised only with the formal board | substrate is demonstrated.
[0088]
First, in the step P1, a substrate having the structure shown in FIG. 4A is formed in the same manner as described above.
[0089]
Next, in step P2, the inside of the first load lock chamber 112a is set to atmospheric pressure, and the substrate having the structure shown in FIG. 4A is carried into the first load lock chamber 112a. Next, the inside of the first load lock chamber 112a is depressurized, and when a predetermined pressure is reached, the opening / closing valve is opened, the substrate is unloaded from the first load lock chamber 112a, and loaded into the transfer chamber 111. Next, the opening / closing valve is opened, and the substrate is unloaded from the transfer chamber 111 and loaded into the first Ir chamber 113. In the first Ir chamber 113, an Ir film (oxygen diffusion barrier layer) 18 is formed on the entire surface of the interlayer insulating film 12 and the plug 16. In the case of the structure shown in FIG. 6, after the Ir film 18 is formed, the process proceeds to P3.
[0090]
Next, the substrate is moved from the first Ir chamber 113 to the second Ir chamber 114 through the transfer chamber 111. At this time, a new substrate having the structure shown in FIG. 4A is carried into the first Ir chamber 113 of the apparatus 1 and a film forming process is performed in the same manner as described above. The substrate carried into the second Ir chamber 114 is formed on the Ir film 18 by IrO, for example, by sputtering._xA film (oxygen diffusion barrier layer) 20 is formed. However, if there is a previous lot that has already been completed until the Ir film is formed, it takes a considerable amount of time to form the Ir film. The substrate of the lot which has been completed until the film formation is carried in from the second load lock chamber 112b and IrO_xIt is preferable to perform film formation after the film. In this case, the substrate of a new lot after the Ir film is formed is carried out from the first load lock chamber 112a. By doing in this way, processing efficiency can be improved.
[0091]
Next, in the step P3, the substrate is unloaded from the second Ir chamber 114, and loaded into the first Pt chamber 115 via the transfer chamber 111. In the first Pt chamber 115, IrO_xA first Pt film (Pt-interface layer, interface conductive film) 21 is formed on the film 20 by sputtering, for example. In the case of producing the capacitive element shown in FIG. 6, the first Pt film 21 is formed on the Ir film 18.
[0092]
Next, the substrate is unloaded from the first Pt chamber 115 and loaded into the second load lock chamber 112b through the transfer chamber 111. Subsequently, the second load lock chamber 112b is returned to atmospheric pressure, and the substrate is carried out of the apparatus from the second load lock chamber 112b.
[0093]
Next, in the step P4, the substrate formed up to the first Pt film 21 is carried into the third load lock chamber 122a of the apparatus 2. Further, the substrate is unloaded from the third load lock chamber 122 a and loaded into the second Pt chamber 123 through the transfer chamber 121. In the second Pt chamber 123, a PtO film is formed on the first Pt film 21 by sputtering, for example._xA film (Ir diffusion barrier layer) 22 is formed.
[0094]
Next, in the process of P5, the substrate is unloaded from the second Pt chamber 123, and loaded into the third Pt chamber 124 through the transfer chamber 121. Next, in the third Pt chamber 124, a second Pt film (orientation control layer) 24 is formed on the platinum oxide film 22 by, eg, sputtering.
[0095]
Thereafter, in the processes of P6 to P11, the dielectric film 32 and the upper electrode conductive layer 34 are stacked in the same manner as described above, and then patterned to form a capacitive element having the structure shown in FIG. IrO_xWhen the film 20 is omitted, the capacitive element shown in FIG. 6 is created.
[0096]
As described above, the first Pt film 21 and PtO_xWhen the film 22 is formed in a different chamber, since only the same type of film is formed in the same chamber, there is no possibility that oxygen is mixed into the first Pt film 21. Therefore, a complete Pt-interface layer free from oxygen contamination can be formed on a formal substrate.
[0097]
Therefore, since the orientation enhancement function is exhibited by the Pt-interface layer 21 not containing oxygen, the (111) orientation strength of the orientation control layer 24 underlying the capacitor ferroelectric film can be increased. Thereby, the (111) orientation strength of the capacitor dielectric film 32a on the lower electrode 30a can be increased and the ferroelectricity thereof can be increased.
[0098]
PtO_xSince the film 22 and the second Pt film 24 underlying the capacitor dielectric film 32a are also formed in different chambers, when the second Pt film 24 is formed on a formal substrate, there is no oxygen contamination. A metal platinum film can be formed. As a result, the (111) orientation strength of the orientation control layer 24 underlying the capacitor dielectric film 32a can be further increased, so that the ferroelectricity of the capacitor ferroelectric film can be further enhanced.
[0099]
This makes IrO_xWhen the lower electrode 30a having an oxygen diffusion barrier layer including a film is used, IrO_xEven if the degree of oxidation of the lower electrode 30a is not reduced, that is, it is not made metallic, the ferroelectricity of the capacitor dielectric film 32a can be sufficiently increased, so that the layered structure of the lower electrode 30a can be prevented from peeling off.
[0100]
(Characteristic characteristics investigation)
Next, the characteristics of the capacitive element produced by the manufacturing method of the capacitive element using the manufacturing apparatus of FIG. 2 or the manufacturing apparatus of FIG. 3 will be described with reference to FIGS. While explaining. The investigating capacitive element of this embodiment has the structure shown in FIG.
[0101]
The capacitive element according to the present invention was produced by the manufacturing method described above. That is, the formation of the first Pt film (Pt-interface layer) 21 and the PtO_xThe formation of the platinum oxide film (Ir diffusion barrier layer) 22 and the formation of the second Pt film (orientation control layer) 24 under the dielectric film 32 are performed in the same chamber. For the investigation, in particular, before the first Pt film 21 was formed, PtO_xA film 22 was formed. And PtO_xAfter the film 22 is formed and before the first Pt film 21 is formed, and before the second Pt film 24 underlying the dielectric film 32 is formed, residual oxygen in the chamber is formed by film formation on the dummy substrate. Removed. Alternatively, each film formation was performed in different chambers. Both are common in that the residual oxygen gas is formed so as not to affect the formation of the first Pt film 21 and the formation of the second Pt film 24 under the dielectric film 32. ing.
[0102]
7 to 10, a capacitor element (indicated as “discontinuous”) using a PZT film having a thickness of 200 nm is used as the capacitor dielectric film 32a, and as the capacitor dielectric film 32a in FIGS. Capacitance elements using PZT films with thicknesses of 200 nm and 140 nm (represented as “discontinuous” and “discontinuous PZT 140 nm”, respectively) were used.
[0103]
Note that, through FIGS. 7 to 17, a capacitor element (indicated as “continuous”) in which a lower electrode was formed by the following method was used as a comparative sample. That is, of the lower electrode, the first Pt film (Pt-interface layer) 21 is formed and PtO._xThe film (Ir diffusion barrier layer) 22 was formed on each substrate continuously in the same chamber and without removing oxygen before the first Pt film 21 was formed. In addition, the first Pt film 21 and PtO_xThe films 22 were alternately formed through one lot. Thereafter, the second Pt film 24 under the dielectric film 32 was formed through one lot. In this case, the first Pt film 21 of the second and subsequent substrates is made of PtO._xThe film 22 is directly affected by the film formation. As a sample for investigation, a film formed on the second and subsequent substrates was used.
[0104]
Furthermore, as a standard sample, a capacitor element (indicated as “Ver2” in FIGS. 7 to 10) having a Pt film / Ti film two-layer lower electrode, and a Pt film / TiO film._xA capacitive element having a lower electrode having a two-layer structure of a film (in FIGS. 11 to 17, “Pt / TiO_x")" Was used.
[0105]
Through FIG. 7 to FIG. 17, the planar shapes of the capacitor elements of all the samples were 50 μm × 50 μm.
[0106]
(I) (111) orientation integral strength of the orientation control layer 24 and the capacitor dielectric film (PZT film) 32a under the capacitor dielectric film
Both (111) orientation integral intensities were measured by the X-ray diffraction method. FIG. 7 is a graph showing the (111) integrated integral intensity of the orientation control layer (second Pt film of the lower electrode) 24 under the capacitor dielectric film, and FIG. 111) This is a graph showing the integrated integral intensity. In each figure, the vertical axis represents (111) orientation integrated intensity (CPS) expressed in a linear scale, and the horizontal axis represents the measurement position of a sample (a circular substrate such as a wafer). Regarding the measurement position, “CENTER” indicates the center of the sample, “TOP” similarly indicates the peripheral portion, and “TC” indicates the intermediate position between “CENTER” and “TOP”.
[0107]
Regarding the orientation control layer (second Pt film of the lower electrode) 24 under the capacitor dielectric film, as shown in FIG. 7, the “discontinuous” of the present invention is compared with the “continuous” of the comparative example ( 111) The orientation strength is about 2.4 times higher.
[0108]
As for the capacitor dielectric film (PZT film) 32a, as shown in FIG. 8, the “discontinuous” of the present invention has a (111) orientation strength of about 1.5 compared to the “continuous” of the comparative example. It is about twice as high.
[0109]
The reason for this is that the first Pt film 21 and the second Pt film 24 are formed by the manufacturing method of the present invention, and in particular, the influence of the residual oxygen gas in the formation of the first Pt film 21. It is presumed that this was because they did not receive it. As a result, the (111) orientation strength of the Pt-interface layer (first Pt film) 21 is increased, and as a result, the (111) of the orientation control layer (second Pt film) 24 underlying the capacitor dielectric film 32a. It is presumed that the orientation strength, and hence the (111) orientation strength of the capacitor dielectric film (PZT film) 32a is increased.
[0110]
(Ii) Polarization inversion charge amount (switching charge amount) (Qsw)
Regarding the investigation on the polarization inversion charge amount (Qsw), the polarization change of the ferroelectric capacitor with respect to the change of the applied voltage was measured as the voltage change of the load capacitor using a Soya tower circuit. A triangular wave or a square wave was used as the applied voltage.
[0111]
(A) FIG. 9 is a graph showing the investigation results of the polarization inversion charge amount (Qsw). The vertical axis represents the linear scale, and Qsw at 3 V (square wave) (μC / cm²) And the horizontal axis indicates the type of sample.
[0112]
According to FIG. 9, the “discontinuous” of the present invention has a Qsw of 2 to 3 μC / cm compared with the “continuous” of the comparative example.²About high. Moreover, it was about the same or higher than the standard sample “Ver 2”.
[0113]
(B) FIG. 11 is a graph showing the results of investigating the dependence relationship between the polarization inversion charge amount (Qsw) of the capacitor and the voltage. The vertical axis of FIG. 11 is Qsw (μC / cm expressed in a linear scale.²The horizontal axis indicates the applied voltage (V) expressed in a linear scale. A square wave was used as the applied voltage, and the voltage was varied in the range of 1.2V to 3V.
[0114]
According to FIG. 11, “discontinuous”, “discontinuous PZT140 nm” of the present invention, “Pt / TiO” of the standard sample,_x”And“ continuous ”in the comparative example, the polarization inversion charge amount (Qsw) increases as the applied voltage increases. Among these, “continuous” of the comparative example is “discontinuous” of the present invention, “discontinuous PZT140 nm”, “Pt / TiO of the standard sample”_x”And lower at lower voltage. In addition, the “Pt / TiO” of the standard sample with respect to the change of the “discontinuous” polarization inversion charge amount (Qsw) and applied voltage of the present invention._xIt changes with almost the same size. Further, as can be seen from the result of “discontinuous PZT140nm” of the present invention, when the ferroelectric film is thinned, the polarization inversion charge amount (Qsw) is saturated from a low voltage (at about 2 V or more) with respect to the change of the applied voltage. There is a tendency.
[0115]
(C) FIGS. 12 and 13 are graphs showing the results of investigation of the polarization inversion charge amount (Qsw). The vertical axis of FIG. 12 is represented by a linear scale, and Qsw at 1.8 V (μC / cm²) And the horizontal axis indicates the type of sample. The vertical axis of FIG. 13 is represented by a linear scale, and Qsw at 3 V (μC / cm²) And the horizontal axis indicates the type of sample.
[0116]
According to FIG. 12, regarding the Qsw characteristic at a voltage of 1.8 V, the “discontinuity” of the present invention is approximately 7 (μC / cm) as compared with the comparative example (“continuous”).²) So high. As can be seen from the result of “discontinuous PZT140 nm” of the present invention, the Qsw becomes higher when the thickness of the ferroelectric film is reduced, which is about 4 (μC / cm) compared with the “discontinuous” of the present invention.²) So high. The “discontinuity” of the present invention is the “Pt / TiO” of the standard sample._xIt was also high compared to On the other hand, according to FIG. 13, regarding the Qsw characteristic at a voltage of 3 V, only “discontinuous” of the present invention is 2 to 3 (μC / cm) compared to the comparative example (“continuous”).²) It is so high that the standard sample “Pt / TiO_xIt was also high compared to However, as can be seen from the result of “discontinuous PZT 140 nm”, when the thickness of the ferroelectric film is reduced, Qsw tends to decrease._xIt was low compared with the comparative example ("continuous").
[0117]
(Iii) Polarization saturation voltage (V90)
The polarization saturation voltage (V90) is defined as the voltage at which the polarization inversion charge amount (switching charge amount) reaches 90% of the saturation value. In order to examine the polarization saturation voltage (V90), the hysteresis characteristic of the capacitive element was measured using a Soya tower circuit.
[0118]
FIG. 14 is a graph showing the investigation result of the polarization saturation voltage (V90). The vertical axis represents V90 (V) expressed in a linear scale, and the horizontal axis represents the type of sample.
[0119]
According to FIG. 14, the “discontinuity” of the present invention was distributed in the range of 2.25 V to 2.5 V, but the center of the distribution is about 2.3 V, which is about 2.4 V of “Ver2” of the standard sample. Was also low. In the comparative example (“continuous”), the center of the distribution is 2.5 V or more, which is higher by about 0.2 V or more than the case of the present invention. Further, as can be seen from the result of “discontinuous PZT140nm”, V90 tends to be lower when the film thickness of the ferroelectric film is reduced, the center of the distribution is about 2V, and 1.9V to 2.1V. Distributed in the range.
[0120]
According to the above-described investigation result of the polarization saturation voltage (V90), low voltage operation is possible in the present invention.
[0121]
(Iv) Fatigue loss (fatigue) characteristics
Fatigue loss characteristics were investigated by voltage acceleration. Polarization inversion is performed by applying a voltage of ± 7 V to the capacitive element to be investigated, and the operation cycle of polarization inversion is 250 ns.⁷This is the rate of polarization charge loss measured after the cycle. The measurement voltage was 3V.
[0122]
(A) FIG. 10 is a graph showing the investigation results of fatigue loss characteristics. The vertical axis represents fatigue loss (%) expressed in a linear scale, and the horizontal axis represents the type of sample.
[0123]
According to FIG. 10, the “discontinuity” of the present invention suppresses the fatigue loss (has an improvement effect of about 4%) as compared to the “continuous” of the comparative example (fatigue loss of about 8%). Even when compared with “Ver2”, it can be seen that the fatigue loss is suppressed to the same extent as “continuous” in the comparative example.
[0124]
(B) FIG. 15 is a graph showing the investigation results of the fatigue loss characteristics. The vertical axis represents fatigue loss (%) expressed in a linear scale, and the horizontal axis represents the type of sample.
[0125]
According to FIG. 15, the “discontinuity” of the present invention is the “Pt / TiO” of the standard sample._xThe fatigue loss can be suppressed as compared with “continuous” in the comparative example (having an improvement effect of about 8%). However, as can be seen from the result of “discontinuous PZT140 nm”, the fatigue loss tends to increase when the thickness of the ferroelectric film is reduced, and the fatigue loss is larger than that of the comparative example (“continuous”).
[0126]
(V) Imprint characteristics
The imprint characteristic is a polarization maintaining characteristic in which the amount of polarization charge decreases with time after the capacitive element is polarized in one direction by voltage application. For example, 3V is applied to the upper electrode of the capacitive element to be polarized in the positive direction and left at a temperature of 150 ° C. for a certain period of time. For example, −3V is applied to the upper electrode to be polarized in the negative direction to 150 ° C. The amount of polarization value retained (decreased amount) is measured for each of the cases where the sample is left for a certain period of time at a temperature of.
[0127]
FIG. 16 is a graph showing the examination result of imprint characteristics. The vertical axis represents the charge reduction rate (Q3Rate) (%), and the horizontal axis represents the sample type.
[0128]
According to FIG. 16, the “discontinuity” of the present invention can improve the imprint characteristics by about 0.5% compared to the “continuous” of the comparative example. As can be seen from the result of “discontinuous PZT140 nm” of the present invention, when the thickness of the ferroelectric film is reduced, the imprint characteristics tend to deteriorate.
[0129]
(Vi) Leakage current
The leakage current was measured by applying a DC voltage between the lower electrode and the upper electrode, and at that time, the polarity of the applied DC voltage was changed and measured in two directions (positive direction and negative direction).
[0130]
FIGS. 17A and 17B are graphs showing the investigation results of the leakage current density distribution, respectively. In both FIGS. 17A and 17B, the vertical axis represents the percentage of the cumulative number of occurrences with respect to the total number of measurements expressed on a logarithmic scale, and the horizontal axis represents the leakage current at +3 V (positive direction) in FIG. Density (A / cm²FIG. 17B shows the leakage current density (A / cm at −3 V (negative direction).²).
[0131]
As shown in FIGS. 17A and 17B, the “discontinuity” of the present invention is the “Pt / TiO” of the standard sample in both the positive and negative directions._xThe leakage current density distribution was almost the same as "." On the other hand, as can be seen from the result of “discontinuous PZT140nm”, when the thickness of the ferroelectric film is reduced, the leakage current density is about an order of magnitude or less than the “discontinuous” of the present invention. However, the distribution was about an order of magnitude lower than that of the comparative example (“continuous”).
[0132]
As described above, regarding the leakage current, it can be said that the effect of removing the residual oxygen in the chamber before the formation of the first Pt film 21 or the second Pt film 24 is very large.
[0133]
From the above investigation results of various characteristics, the capacitive element created by the manufacturing method of the present invention is Pt / Ti, or Pt / TiO._xCompared with a general planar capacitor having a lower electrode of the two-layer structure, it can be said that it has excellent characteristics. In particular, as shown in FIGS. 11 and 12, since the polarization inversion charge amount (switching charge amount) Qsw at a low voltage can be increased, the possibility of application to the next generation FeRAM is also high.
[0134]
(Second Embodiment)
An example in which the above-described capacitive element manufacturing method according to the second embodiment of the present invention is applied to an FeRAM manufacturing method will be described with reference to FIGS.
[0135]
FIG. 18 is a schematic cross-sectional view showing the structure of the FeRAM according to the present embodiment, and FIGS. 19 to 21 are process cross-sectional views showing the manufacturing method of the FeRAM according to the present embodiment.
[0136]
First, the structure of the FeRAM according to the present embodiment will be described with reference to FIG.
[0137]
In the FeRAM, an element isolation film 42 is formed on a silicon substrate 40. A memory cell transistor having a gate electrode 48 and a source / drain diffusion layer 56 is formed in the element region defined by the element isolation film 42. An interlayer insulating film 62 is formed on the silicon substrate 40 on which the memory cell transistors are formed. Plugs 66 electrically connected to the source / drain diffusion layers 56 are embedded in the interlayer insulating film 62.
[0138]
On the interlayer insulating film 62 in which the plug 66 is embedded, the second Pt film / PtO_xFilm / First Pt film / IrO_xFilm / Ir film structure (Pt / PtO)_x/ Pt / IrO_x/ Ir structure. ) Lower electrode 30a. A capacitor dielectric film 32a made of PZT is formed on the lower electrode 30a. On the capacitor dielectric film 32a, an upper electrode 34a made of Pt is formed. Thus, the ferroelectric capacitor is constituted by the lower electrode 30a, the capacitor dielectric film 32a, and the upper electrode 34a. As the material of the upper electrode 34a, IrO_xMay be used.
[0139]
On the interlayer insulating film 62 on which the ferroelectric capacitor is formed, a ferroelectric capacitor protective film 86 and an interlayer insulating film 88 are formed. A plug 92 electrically connected to the plug 66 is embedded in the interlayer insulating film 88 and the ferroelectric capacitor protective film 86. On the interlayer insulating film 88 in which the plug 92 is embedded, a wiring layer 96 electrically connected to the source / drain diffusion layer 56 via the plugs 92 and 66 and a wiring connected to the upper electrode 34a of the capacitor element. Layer 98 is formed.
[0140]
Thus, in the FeRAM according to the present embodiment, the capacitor lower electrode 30a of the ferroelectric memory has the same Pt / PtO as the lower electrode structure of the capacitive element shown in FIG. 5 according to the first embodiment._x/ Pt / IrO_x/ Ir structure is characteristic. By constructing a ferroelectric memory in this way, IrO_xThe film and the Ir film prevent oxygen diffusion during the capacitor dielectric film formation process, and PtO_xThe film can prevent the diffusion of Ir from the oxygen barrier layer to the capacitor dielectric film. Therefore, even when the capacitor dielectric film is formed by sputtering, the capacitor dielectric film can be sufficiently crystallized while preventing Ir diffusion. As a result, a high-performance ferroelectric memory having desired electrical characteristics can be manufactured.
[0141]
Next, the manufacturing method of the FeRAM according to the present embodiment will be explained with reference to FIGS.
[0142]
First, an element isolation film 42 embedded in the silicon substrate 40 is formed on the silicon substrate 40 by, for example, a shallow trench method.
[0143]
Next, for example, boron ions are ion-implanted into a region where a memory cell is to be formed, thereby forming a P well 44 (FIG. 19A).
[0144]
Next, the surface of the silicon substrate 40 is oxidized by, for example, a thermal oxidation method, and a gate insulating film 46 made of a silicon oxide film is formed on the element region defined by the element isolation film 42.
[0145]
Next, a polycrystalline silicon film and a silicon nitride film are deposited on the gate insulating film 46 by, eg, CVD.
[0146]
Next, the silicon nitride film and the polycrystalline silicon film are patterned in the same shape, and a gate electrode 48 made of a polycrystalline silicon film having an upper surface covered with the silicon nitride film 50 is formed.
[0147]
Next, ions are implanted into the silicon substrate 40 using the gate electrode 48 as a mask, and impurity diffusion regions 52a are formed in the silicon substrate 40 on both sides of the gate electrode 48 (FIG. 19B).
[0148]
Next, after a silicon nitride film is deposited on the entire surface by, eg, CVD, the silicon nitride film is etched back to form a sidewall insulating film 54 made of a silicon nitride film on the side walls of the gate electrode 48 and the silicon nitride film 50. .
[0149]
Next, ions are implanted into the silicon substrate 40 using the gate electrode 48 and the sidewall insulating film 54 as a mask, and impurity diffusion regions 52 b are formed in the silicon substrate 40 on both sides of the gate electrode 48. Thereby, a source / drain diffusion layer 56 composed of the impurity diffusion regions 52a and 52b is formed (FIG. 19C).
[0150]
Thus, a memory cell transistor having the gate electrode 48 and the source / drain diffusion layer 56 is formed.
[0151]
Next, a 20 nm-thickness silicon nitride film 58 and a 700 nm-thickness silicon oxide film 60 are deposited on the silicon substrate 40 on which the memory cell transistors are formed by, for example, CVD.
[0152]
Next, the surface of the silicon oxide film 60 is planarized by, eg, CMP, and an interlayer insulating film 62 made of the silicon nitride film 58 and the silicon oxide film 60 and planarized is formed.
[0153]
Next, a contact hole 64 reaching the silicon substrate 40 is formed in the interlayer insulating film 62 by photolithography and dry etching.
[0154]
Next, a 20 nm thick Ti film, a 10 nm thick TiN film, and a 300 nm thick W film are deposited on the entire surface by, eg, CVD.
[0155]
Next, the W film, the TiN film, and the Ti film are polished flatly by CMP, for example, until the surface of the interlayer insulating film 62 is exposed, and a plug 66 having a W / TiN / Ti structure and embedded in the contact hole 64 is formed. (FIG. 19D).
[0156]
Next, in the same manner as the method for forming the lower electrode 30a in the method for manufacturing the capacitive element according to the first embodiment, for example, by sputtering, for example, the Ir film 18 having a thickness of 200 nm and the IrO film having a thickness of 28 nm are formed._xA film 20; a first Pt film 21 having a thickness of 15 nm; and a PtO film having a thickness of 25 nm._xA film 22 and a second Pt film 24 having a thickness of 50 nm are formed.
[0157]
Next, a rapid heat treatment at 750 ° C. is performed in an argon atmosphere to crystallize the second Pt film 24.
[0158]
Next, a PZT film 32 of, eg, a 200 nm-thickness is formed on the second Pt film 24 by sputtering. For example, the film is formed for 360 seconds at a substrate temperature of 13 ° C., a power of 1 kW, and an Ar gas flow rate of 24 sccm.
[0159]
Next, a rapid heat treatment at 750 ° C. is performed in an oxygen atmosphere to crystallize the PZT film 32.
[0160]
Next, a Pt film 34 of, eg, a 200 nm-thickness is formed on the PZT film 32 by, eg, sputtering (FIG. 20A). For example, the film is formed for 81 seconds at a substrate temperature of 13 ° C., a power of 1 kW, an Ar gas flow rate of 100 sccm, and an oxygen gas flow rate of 100 sccm.
[0161]
Next, by photolithography and dry etching, the Pt film 34, the PZT film 32, the second Pt film 24, the PtO_xFilm 22, first Pt film 21, IrO_xThe film 20 and the Ir film 18 are patterned in the same shape, and the second Pt film 24 / PtO_xFilm 22 / First Pt film 21 / IrO_xA lower electrode 30a made of the film 20 / Ir film 18, a capacitor dielectric film 32a made of a PZT film formed on the lower electrode 30a, and an IrO film formed on the capacitor dielectric film 32a._xAn upper electrode 34a made of a film or a Pt film is formed (FIG. 20B).
[0162]
Thus, a ferroelectric capacitor including the lower electrode 30a, the capacitor dielectric film 32a, and the upper electrode 34a, in which the lower electrode 30a is electrically connected to the source / drain diffusion layer 56 through the plug 66, is formed.
[0163]
Next, a 40 nm-thickness PZT film is formed on the entire surface by, eg, sputtering. This PZT film functions as a ferroelectric capacitor protective film 86 (FIG. 20C).
[0164]
Next, a silicon oxide film having a thickness of 1100 nm is formed on the ferroelectric capacitor protective film 86 by, eg, CVD.
[0165]
Next, the surface of the silicon oxide film is polished by, eg, CMP, and an interlayer insulating film 88 made of a silicon oxide film and having a flattened surface is formed (FIG. 21A).
[0166]
Next, a contact hole 90 reaching the plug 66 is formed in the interlayer insulating film 88 by photolithography and dry etching.
[0167]
Next, a 20 nm thick Ti film, a 10 nm thick TiN film, and a 300 nm thick W film are deposited on the entire surface by, eg, CVD.
[0168]
Next, the W film, the TiN film, and the Ti film are polished flatly by, for example, a CMP method until the surface of the interlayer insulating film 88 is exposed, and a plug 92 having a W / TiN / Ti structure embedded in the contact hole 90 is formed. (FIG. 21B).
[0169]
Next, a contact hole 94 reaching the upper electrode 34a of the capacitor element is formed in the interlayer insulating film 88 by photolithography and dry etching.
[0170]
Next, on the entire surface, for example, by sputtering, for example, a Ti film with a thickness of 60 nm, a TiN film with a thickness of 30 nm, an Au—Cu film with a thickness of 400 nm, a Ti film with a thickness of 5 nm, and a TiN film with a thickness of 70 nm. A film is sequentially deposited.
[0171]
Next, a conductor having a TiN / Ti / Au-Cu / Ti / TiN structure is patterned, and a wiring layer 96 electrically connected to the source / drain diffusion layer 56 through plugs 66 and 92, and an upper portion of the capacitive element A wiring layer 98 electrically connected to the electrode 34a is formed (FIG. 21C).
[0172]
Thus, a ferroelectric memory having two transistors and two capacitors can be manufactured.
[0173]
As described above, according to the present embodiment, when the Pt-based conductive film is formed in the same chamber in the FeRAM capacitor lower electrode 30a, before the Pt-interface layer 21 is formed on the substrate. By depositing the same film on the dummy substrate, residual oxygen in the chamber is consumed and removed from the chamber. Alternatively, when each film formation is performed in different chambers, there is no risk of oxygen contamination. Therefore, when forming the Pt-interface layer 21 on the substrate, it is possible to form the Pt-interface layer 21 made of complete metal platinum without oxygen contamination.
[0174]
As described above, the function of enhancing the alignment is exhibited by the Pt-interface layer 21 not containing oxygen, so that the (111) orientation strength of the orientation control layer 24 underlying the capacitor dielectric film 32a can be increased. Thereby, the (111) orientation strength of the capacitor dielectric film 32a on the lower electrode 30a can be increased and the ferroelectricity thereof can be increased.
[0175]
In addition, this allows IrO_xWhen the lower electrode 30a having the oxygen diffusion barrier layer including the film 20 is used, IrO_xEven if the degree of oxidation of the lower electrode 30a is not reduced, that is, it is not made metallic, the ferroelectricity of the capacitor dielectric film 32a can be sufficiently increased, so that the layered structure of the lower electrode 30a can be prevented from peeling off.
[0176]
PtO_xEven when the second Pt film 24 underlying the capacitor dielectric film 32 is formed after the film 22 is formed, residual oxygen is removed by film formation on the dummy substrate. As a result, when the second Pt film 24 is formed on the formal substrate, a complete metal platinum film free from oxygen contamination can be deposited on the first formal substrate in the lot.
[0177]
In the above embodiment, the capacitor of the first embodiment shown in FIG. 5 is applied as the capacitor of the ferroelectric memory. However, the ferroelectric element using the capacitor according to the modification of the first embodiment shown in FIG. A memory may be configured. FIG. 22 is a cross-sectional view showing the structure of an FeRAM according to a modification of the second embodiment, including the capacitive element according to the modification of the first embodiment shown in FIG. The lower electrode 30b of the capacitive element Q is Pt / PtO_xIt has a / Pt / Ir structure. 22, the same reference numerals as those in FIGS. 6 and 18 denote the same elements as those in FIGS. Regarding the manufacturing method, the capacitive element Q is the same as the manufacturing method described with reference to FIG. 6, and the other portions are the same as the manufacturing method described with reference to FIGS.
[0178]
(Third embodiment)
The present invention is not limited to the above embodiment, and various modifications can be made.
[0179]
For example, in the above embodiment, the oxygen diffusion barrier layer is IrO._x/ Ir structure and Ir single-layer structure were shown, but IrO_xA single layer of film may be used. In addition, Ir / IrO_xStructure and IrO_xA conductive film having an oxygen barrier function other than a film or an Ir film may be used. The conductive film having an oxygen barrier function only needs to be interposed between the plug and the capacitor dielectric film, and is not limited to the lowermost layer of the lower electrode. However, when the orientation control of the capacitor dielectric film is taken into consideration, as described above, the uppermost layer of the lower electrode is a platinum film. It is desirable to comprise.
[0180]
In the above embodiment, the PtO layer is used as the Ir diffusion barrier layer 22._xAlthough a film is used, it may be formed of another conductive film. Platinum group elements are elements having properties similar to Pt, and include ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), and iridium (Ir). Of these, elements other than Ir are considered to be applicable as an Ir diffusion barrier layer. Therefore, conductive oxides of these metal elements, that is, RuO_x, RhO_x, PdO_x, OsO_xOne of the PtO_xIt is thought that it can be used instead of a membrane. In this case, Ru, Rh, Pd, and Os may be used as the material of the interface conductive film in correspondence with the metal material of the Ir diffusion barrier layer.
[0181]
Similarly, a Ru film, Rh film, Pd film, or Os film may be used in place of the second Pt film 24 formed on the upper layer of the Ir diffusion barrier layer 22.
[0182]
In the above embodiment, the PZT film is used as the capacitor dielectric film 32a. However, the present invention can be similarly applied to the case where another capacitor dielectric film is used. For example, as the capacitor dielectric film 32a, BST ((Ba, Sr) TiO_Three) Film, ST (SrTiO_x) Film, Ta₂O_FiveA high dielectric constant film such as a film or a ferroelectric film such as Y1 can be applied.
[0183]
In the second embodiment, the case where the capacitive element according to the present invention is applied to FeRAM (ferroelectric memory) has been described. However, it can also be applied to other semiconductor devices. For example, a DRAM may be configured using the capacitive element according to the present invention, or the capacitive element according to the present invention may be used alone.
[0184]
In the above embodiment, the platinum oxide film is made of PtO._xAnd iridium oxide film with IrO_xThe oxygen composition ratio x of these metal oxides can be selected as appropriate. In a typical film, the composition ratio x can be in the range of 0 <x ≦ 2.
[0185]
As the upper electrode of the capacitive element, IrO instead of Pt_xMay be formed.
[0186]
As described above in detail, the characteristics of the method for manufacturing a capacitive element according to the present invention are summarized as follows.
(Appendix 1) A step of forming a first conductive film containing a first metal on an insulating film, and an interface conductive film made of a second metal different from the first metal after removing residual oxygen in the chamber Forming on the first conductive film; forming a second conductive film made of a metal oxide of the second metal on the interface conductive film in an atmosphere containing oxygen in the chamber; Forming a third conductive film made of a third metal different from the first metal on the second conductive film, forming a dielectric film on the third conductive film, and over the dielectric film Forming a fourth conductive film on the substrate, patterning the first conductive film, the interface conductive film, the second conductive film, and the third conductive film to form a capacitive element lower electrode, and the dielectric film Patterning the capacitive element Process and method for producing a capacitor characterized by having the step of said fourth conductive layer is patterned capacitor element upper electrode and collector layer.
(Supplementary note 2) The method for producing a capacitive element according to supplementary note 1, wherein the interface conductive film is formed on a dummy substrate in order to remove residual oxygen in the chamber.
(Additional remark 3) The said 2nd metal is the same element as the said 3rd metal, The manufacturing method of the capacitive element of Additional remark 1 or 2 characterized by the above-mentioned.
(Supplementary Note 4) The step of forming the third conductive film on the second conductive film is performed in the chamber and removing residual oxygen in the chamber before forming the third conductive film. The manufacturing method of the capacitive element according to supplementary note 3, characterized in that it includes:
(Supplementary note 5) The method for manufacturing a capacitive element according to supplementary note 4, wherein the step of removing residual oxygen in the chamber includes a step of forming the third conductive film on a dummy substrate.
(Appendix 6) Forming a first conductive film containing a first metal on an insulating film, and an interface conductive film made of a second metal different from the first metal in the first chamber, the first conductive film And forming a second conductive film made of a metal oxide of the second metal on the interface conductive film in an oxygen-containing atmosphere in a second chamber different from the first chamber. A step of forming a third conductive film made of a third metal different from the first metal on the second conductive film, a step of forming a dielectric film on the third conductive film, and the dielectric Forming a fourth conductive film on the body film; patterning the first conductive film, the interface conductive film, the second conductive film, and the third conductive film to form a capacitor element lower electrode; Patterning the dielectric film The method of manufacturing the capacitor element, characterized in that it comprises the steps of: a quantity element dielectric film, and a step of a capacitor upper electrode by patterning the fourth conductive layer.
(Supplementary note 7) The method of manufacturing a capacitive element according to supplementary note 6, wherein the step of forming the third conductive film on the second conductive film is performed in a third chamber different from the second chamber.
(Additional remark 8) The said 2nd metal is the same element as the said 3rd metal, The manufacturing method of the capacitive element of Additional remark 6 or 7 characterized by the above-mentioned.
(Supplementary note 9) The first metal is iridium, the metal oxide of the second metal is a platinum group metal oxide different from iridium, and the third metal is a platinum group metal different from iridium. 9. A method for manufacturing a capacitive element according to any one of appendices 1 to 8, which is characterized by the following.
(Additional remark 10) The process of forming the said 1st electrically conductive film includes the process of forming the said 1st metal film and the oxide film of the said 1st metal in order, The any one of Additional remark 1 thru | or 9 characterized by the above-mentioned. The manufacturing method of the capacitive element as described in 2.
(Additional remark 11) It has the semiconductor substrate under the said insulating film, the opening part which penetrates the said insulating film, and the embedded electrically conductive film embedded in this opening part, The said 1st electrically conductive film is the said embedded electrically conductive film 11. The method for manufacturing a capacitive element according to any one of appendices 1 to 10, wherein the capacitive element is connected to the semiconductor substrate via a substrate.
(Additional remark 12) The material of the said embedded conductive film is tungsten, The manufacturing method of the capacitive element of Additional remark 11 characterized by the above-mentioned.
(Supplementary note 13) The method for manufacturing a capacitive element according to supplementary note 11 or 12, wherein an impurity diffusion region is formed in a surface layer of the semiconductor substrate, and the buried conductive film is in contact with the impurity diffusion region.
(Supplementary note 14) The method for manufacturing a capacitive element according to supplementary note 13, wherein the impurity diffusion region is a source / drain region of an insulated gate field effect transistor.
[0187]
【The invention's effect】
As described above, according to the present invention, the first conductive film containing iridium, the interface conductive film made of platinum group metal other than iridium, for example, platinum, formed on the first conductive film, and the interface A second conductive film made of a platinum group metal oxide excluding iridium formed on the conductive film, and a third conductive film made of a platinum group metal excluding iridium formed on the second conductive film. Since the capacitor element is constituted by the lower electrode having the capacitor dielectric film formed on the lower electrode and the upper electrode formed on the capacitor dielectric film, the capacitor dielectric film is formed by the first conductive film. The diffusion of oxygen to the lower plug in the process can be prevented, and the diffusion of iridium from the first conductive film to the capacitor dielectric film can be prevented by the second conductive film. .
[0188]
Therefore, even when the capacitor dielectric film is formed by sputtering, sufficient crystallization of the capacitor dielectric film can be achieved while preventing the diffusion of iridium. As a result, a high-performance capacitive element having desired electrical characteristics can be manufactured.
[0189]
Furthermore, since the interface conductive film made of a platinum group metal other than iridium, for example, platinum, is formed between the first conductive film and the second conductive film, the third conductive film and the ferroelectric film thereon are formed in view of the structure. The (111) orientation strength of the body film can be increased.
[0190]
When the interface conductive film made of a platinum group metal other than iridium and the second conductive film made of a metal oxide of a platinum group metal other than iridium are formed in the same chamber, the interface conductive film is formed. Oxygen is removed from the chamber before starting. Alternatively, these films are formed in different chambers. Thereby, since the interface conductive film without oxygen mixing can be formed from the viewpoint of manufacturing, the (111) orientation strength of the lower electrode and the capacitor ferroelectric film thereon can be increased.
[0191]
As described above, according to the present invention, the (111) orientation strength of the lower electrode and the capacitor ferroelectric film thereon can be increased in terms of the structure and manufacturing of the capacitive element. A ferroelectric capacitor having the same can be obtained.
[Brief description of the drawings]
FIG. 1 is a flowchart showing a method for manufacturing a capacitive element according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a manufacturing apparatus used in the method for manufacturing a capacitive element according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a manufacturing apparatus used in a method for manufacturing a capacitive element according to a modification of the first embodiment of the present invention.
FIG. 4 is a process cross-sectional view (No. 1) illustrating the method for manufacturing the capacitive element according to the first embodiment of the invention.
FIG. 5 is a process cross-sectional view (part 2) illustrating the method for manufacturing the capacitive element according to the first embodiment of the invention;
FIG. 6 is a cross-sectional view showing the structure of a capacitive element according to a modification of the first embodiment of the present invention.
FIG. 7 is a graph showing the (111) orientation integrated intensity of the second platinum film of the lower electrode in the capacitive element according to the first embodiment of the present invention.
FIG. 8 is a graph showing (111) orientation integrated intensity of a capacitor dielectric film in the capacitive element according to the first embodiment of the present invention;
FIG. 9 is a graph showing the polarization inversion charge amount (Qsw) in the capacitive element according to the first embodiment of the present invention.
FIG. 10 is a graph showing fatigue loss in the capacitive element according to the first embodiment of the present invention.
FIG. 11 is a graph showing the applied voltage dependence of the polarization inversion charge amount (Qsw) in the capacitive element according to the first embodiment of the present invention.
FIG. 12 is a graph showing the polarization inversion charge amount (Qsw) in the capacitive element according to the first embodiment of the present invention.
FIG. 13 is a graph showing the polarization inversion charge amount (Qsw) in the capacitive element according to the first embodiment of the present invention.
FIG. 14 is a graph showing the polarization saturation pressure reduction (V90) in the capacitive element according to the first embodiment of the present invention.
FIG. 15 is a graph showing fatigue loss in the capacitive element according to the first embodiment of the present invention.
FIG. 16 is a graph showing imprint characteristics of the capacitive element according to the first embodiment of the present invention.
17A and 17B are graphs showing a leakage current density distribution in the capacitive element according to the first embodiment of the present invention.
FIG. 18 is a schematic cross-sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention.
FIG. 19 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment of the invention;
FIG. 20 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention;
FIG. 21 is a process cross-sectional view (No. 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment of the invention;
FIG. 22 is a schematic cross-sectional view showing the structure of a semiconductor device according to a modification of the second embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10,40 ... Silicon substrate (semiconductor substrate) 12, 62, 88 ... Interlayer insulation film 14, 64, 90, 94 ... Contact hole (opening), 16, 66, 92 ... Plug (buried conductive film), 18 ... Iridium film (first conductive film, oxygen diffusion barrier layer), 20 ... Iridium oxide film (first conductive film, oxygen diffusion barrier layer), 21 ... First platinum film (interface conductive film, Pt-interface layer), 22 ... Platinum oxide film (second conductive film, Ir diffusion barrier layer) 24 ... Second platinum film (third conductive film, orientation control layer), 30a, 30b ... Lower electrode, 32 ... PZT film (dielectric film) ), 32a ... capacitor dielectric film, 34 ... upper electrode conductive layer (fourth conductive film), 34a ... upper electrode, 42 ... element isolation film, 44 ... P well, 46 ... gate insulating film, 48, 48a, 48b ... gate power , 50, 58 ... silicon nitride film, 52a, 52b ... impurity diffusion region, 54 ... sidewall insulating film, 56 ... source / drain diffusion layer, 60 ... silicon oxide film, 86 ... ferroelectric capacitor protective film, 96, 98 ... wiring layer, 101, 111, 121 ... transfer chamber, 102a, 112a ... first load lock chamber, 102b, 112b ... second load lock chamber, 122a ... third load lock chamber, 122b ... fourth load Lock chamber, 103 ... Ir chamber, 113 ... First Ir chamber, 114 ... Second Ir chamber, 104 ... Pt chamber, 115 ... First Pt chamber, 123 ... Second Pt chamber 124 ... Third Pt chamber.

Claims (4)

Forming a first conductive film containing a first metal having either an Ir single-layer structure or a two-layer structure of Ir and IrO _x on an insulating film by sputtering ;
Forming a film made of a second metal that is Pt different from the first metal in a chamber, and removing residual oxygen from the chamber;
After removing the residual oxygen, an interface conductive film made of the second metal having a (111) orientation that increases the orientation strength of a third conductive film to be formed later is sputtered on the first conductive film in the chamber. Forming, and
Forming a second conductive film made of a metal oxide of the second metal, which is a diffusion barrier layer of the first metal, on the interface conductive film by sputtering in an atmosphere containing oxygen in the chamber; ,
Forming the third conductive film, which is an orientation control layer, made of a third metal having a Pt different from the first metal by sputtering on the second conductive film;
Performing a heat treatment to crystallize the third conductive film;
Forming a dielectric film made of a ferroelectric material on the third conductive film;
Performing a heat treatment to crystallize the dielectric film;
Forming a fourth conductive film on the dielectric film;
Patterning the first conductive film, the interface conductive film, the second conductive film, and the third conductive film to form a capacitive element lower electrode;
Patterning the dielectric film to form a capacitive element dielectric film;
And a step of patterning the fourth conductive film to form a capacitive element upper electrode. Wherein the step of the third conductive film is formed on the second conductive layer is carried out in the chamber, and wherein prior to forming the third conductive film, forming a third conductive film on the dummy substrate, the 2. The method of manufacturing a capacitive element according to claim 1, further comprising a step of removing residual oxygen from the chamber.   The step of forming the first conductive film includes a step of forming either a film made of the first metal or an oxide film of the first metal, a film made of the first metal, and the first metal. The method for manufacturing a capacitive element according to claim 1, further comprising a step of sequentially forming oxide films. A semiconductor substrate under the insulating film, an opening penetrating the insulating film, and a buried conductive film embedded in the opening;
The first conductive film is a diffusion barrier layer that suppresses diffusion of oxygen into the embedded conductive film, and is connected to the semiconductor substrate through the embedded conductive film. 2. A method for producing a capacitive element according to claim 1.

Images