JP2003197772A - Capacitor, semiconductor storage device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitor of an electrode structure wherein reaction between a conductive plug and a lower electrode of the capacitor and diffusion can be prevented and a superior contact characteristic is obtained, and to provide a semiconductor storage device and its manufacturing method. <P>SOLUTION: A first electrode film, a second electrode film and a dielectric thin film sandwiched by the first and second electrode films are installed. The first electrode film includes a diffusion preventing layer and a boride layer of high melting point metal. The first electrode film is formed by laminating the diffusion preventing layer and the boride layer of high melting point metal in order from the dielectrics thin film side. The boride layer of high melting point metal has conductivity and barrier property to silicon. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a capacitor including a dielectric film made of a high dielectric film material or a ferroelectric film material, a semiconductor memory device having the same, and a method of manufacturing the same. Regarding

[0002]

2. Description of the Related Art In recent years, with the increase in storage capacity due to higher density and higher integration of semiconductor memory devices, a high dielectric thin film material having a higher dielectric constant than a silicon oxide film which has been conventionally used is used. Semiconductor memories such as DRAM (dynamic random access memory) have been studied. On the other hand, a non-volatile semiconductor memory device (ferroelectric semiconductor memory device) (FeRAM) using a ferroelectric substance having a unique electrical property called spontaneous polarization (USP487366)
4) is not only conventional non-volatile memory but also SRAM because of its features such as high speed writing / reading and low voltage operation.
It has the potential to replace most memories such as (static RAM) and DRAM, and many studies are currently underway.

A DRAM memory cell using a high dielectric thin film is composed of one transistor and one storage capacitor (1T / 1C), and the amount of charge stored in the storage capacitor serves as stored information. By using an insulating film having a high dielectric constant, even if the cell area and the area of the storage capacitor are small, this capacitor has a sufficiently large capacitance value and the electric charge amount as the information amount does not become small. As a result, the information storage capacity of the DRAM can be further increased.

There are roughly two types of memories that utilize the spontaneous polarization characteristics of ferroelectric substances. The first type is one in which the paraelectric material is replaced with a ferroelectric material for the memory capacitor material of a normal DRAM type memory cell. This is the difference in the current that flows through the ferroelectric capacitor when a voltage for writing and reading is applied by applying a voltage to the ferroelectric capacitor to set the polarization state, that is, the amount of charge stored in the ferroelectric capacitor. Is to detect the polarization state. The second type has a structure in which the gate insulating film of the MOS-FET is replaced with a ferroelectric substance. this is,
The polarization state is detected by the difference in the current flowing through the channel portion between the source and drain corresponding to the polarization direction of the ferroelectric gate. As the first type ferroelectric memory cell, for example, 1 transistor + 1 capacitor (1T / 1 in which a selection transistor is added to a ferroelectric capacitor) is used.
A non-volatile memory cell having a C) structure can be mentioned. A capacitor using such a ferroelectric or high-dielectric thin film is composed of, for example, a lower electrode and an upper electrode, and a ferroelectric or high-dielectric thin film sandwiched between them.

As a high dielectric material, STO (SrTi
O ₃ : Strontium titanate) and BST ((Ba, S
r) TiO _3: barium titanate, there are strontium titanate), tantalum oxide film _(Ta 2 _{O 5)} or the like, application to highly integrated DRAM or the like have been studied. Further, as a ferroelectric material, PZT (P
b (Zr, Ti) O ₃ , lead zirconate titanate), PL
Lead-based oxide materials with ABO ₃ type perovskite crystal structure such as ZT ((Pb, La) (Zr, Ti) O ₃ and lead lanthanum zirconate titanate) have been mainly developed, and some of them are already in practical use. Has been converted. As a method for forming these thin films, a sol-gel method or MOD (Metal Organic Deposition) is used.
spin coating method such as composition method, sputtering method, MO
CVD (Metal Organic Chemical Vapor Deposition)
The law is used.

High dielectric materials such as STO and BSTO have 30
It can be formed at a relatively low temperature of about 0 ° C to 600 ° C. Further, PZT, which is an oxide material having a perovskite structure as a ferroelectric material, can also be formed at a relatively low temperature of about 600 ° C. However, a material containing lead as its constituent element, such as PZT, has a high vapor pressure of lead and its oxide, so that lead evaporates during film formation and causes defects in the film, and in severe cases, pinholes. Generate. As a result, there is a drawback that the leak current increases and a fatigue phenomenon occurs in which the magnitude of spontaneous polarization decreases when the polarization inversion is repeated about 10 ⁶ to 10 ⁸ times. In particular, when used in the field of FeRAM using a ferroelectric non-volatile memory, it is necessary to ensure that the characteristics do not change even after 10 ¹⁵ times of polarization reversal, so a ferroelectric film with less fatigue phenomenon is required. Has been.

On the other hand, development of bismuth layer structure compound material
Is being promoted. Bismuth layer structure compound material is 1
Discovered by Smolenskii et al. In 959, Soviet Phy
s. Solid State (USSR), p1 (1959) G. A. Smolenskii,
 Disclosed in V.A.Isupov and A.I.Agranovskaya, p149
Has been done. After that, Subbarao didn't discuss it in detail.
That is J. Phys. Chem. Solids (USA), p23 (1962),
 E. C. Subbarao, p665. Again Carlos
 A. Paz de Araujo et al.
The material SBT film is suitable for FeRAM.
Look, especially 10 ¹²Characteristics change after polarization inversion more than once
It reports excellent fatigue properties that it cannot be seen. Furthermore
In addition, the electric field required for polarization reversal in the SBT film is higher than that in the PZT film.
Highly integrated FeRA whose driving voltage is particularly small due to its small size
Suitable for M. However, the formation of SBT requires 7
It is said that a high temperature process of around 00 ℃ to 800 ℃ is required.
There was a problem.

Next, an example of a conventional semiconductor memory device will be described with reference to the schematic sectional view of FIG. As shown in FIG.
An inter-element isolation oxide film 112 is formed on a semiconductor substrate (for example, a first conductivity type silicon substrate) 111 to isolate an element formation region. A transistor 121 is formed in the formation region of this element (reference numeral 121 is not shown). The transistor 121 is formed on the semiconductor substrate 111.
A gate oxide film 122 formed above and a polysilicon word line (including a gate electrode) 123 formed above the gate oxide film 122.
And the impurity diffusion regions 124 and 125 of the second conductivity type which are formed on the semiconductor substrate 111 on both sides of the gate electrode portion and have the opposite polarity to the first conductivity type. A sidewall insulating film 126 is formed on the sidewall of the polysilicon word line 123.

An interlayer insulating film 113 is formed on the semiconductor substrate 111 to cover the transistor 121. Impurity diffusion regions 124 are formed in the interlayer insulating film 113.
To the impurity diffusion region 124, a conductive plug 115 of the memory portion is formed inside the connection hole 114.

A lower electrode layer 132 of a dielectric capacitor 131 connected to the conductive plug 115, a dielectric film 133, and an upper electrode 134 are laminated on the interlayer insulating film 113 (reference numeral 131 is shown). It has not been). The dielectric capacitor 131 is covered with an interlayer insulating film 116, and an opening is formed on the upper electrode 134 of the dielectric capacitor 131. A plate line 141 connecting to the upper electrode 134 is formed through this opening.

Further, an interlayer insulating film 118 for covering the plate line 141 is formed. This interlayer insulating film 11
On the other hand, the other impurity diffusion regions 12
5, a bit contact hole 119 reaching 5 is formed,
A bit line 142 connected to the impurity diffusion region 125 of the second conductivity type is formed through the bit contact hole 119.

In the conventional semiconductor memory device 110 having the dielectric capacitor 131 using the high dielectric material or the ferroelectric material for the dielectric film 133, as described above,
Lower electrode 132, dielectric film 133 and upper electrode 134
The dielectric capacitor 131 consisting of
The stack type structure formed on 21 is adopted. As a result, the memory cell area is reduced and high integration is possible. In order to enable such a stack-type structure, it is necessary to use a conductive plug 115 for connecting the transistor (selection transistor) 121 and the dielectric capacitor 131.

As the lower electrode material of the dielectric capacitor, a noble metal such as platinum, iridium, ruthenium or the like is generally used from the viewpoint of heat resistance, oxidation resistance, or reaction resistance.

[0014]

In the process of forming a high dielectric film or a ferroelectric film used for a dielectric capacitor, it is necessary to crystallize them to obtain a high dielectric constant or ferroelectricity at 500.degree. Treatment in a high temperature oxidizing atmosphere at 800 ° C. is essential. When these highly integrated semiconductor memory devices are put to practical use, the noble metal lower electrode of the dielectric capacitor and the polysilicon plug or the tungsten plug react at a high temperature during the process of forming the dielectric film, or the plug oxidizes to cause the lower electrode. Contact failure between the plug and the plug, or in the case of a polysilicon plug, the noble metal lower electrode is silicidized and the crystallinity of the dielectric is destroyed, and the noble metal and the constituent elements of the dielectric film diffuse into the substrate. Then, there is a problem that the transistor characteristics are deteriorated. Therefore, it is necessary to devise the design of the lower electrode. For example, it is thermally stable between the plug and the lower electrode of the noble metal and has a strong barrier property against constituent elements (eg, oxygen and silicon) such as the plug, the lower electrode, and the dielectric film. A conductive diffusion barrier layer is provided to prevent reaction of the noble metal lower electrode and the plug at high temperature, and diffusion of constituent elements of the noble metal electrode and the dielectric film into the substrate. The inventor of the present application has continued to make proposals for this problem and has obtained good results. For example, Japanese Patent No. 2118
No. 09 publication discloses the details of one proposal. Further, Japanese Patent Laid-Open No. 2000-138182 discloses a capacitor having a multilayer lower electrode including an oxide film and a silicide film. In addition, JP-A-2000-12442
The semiconductor device disclosed in Japanese Patent No. 8 has a conductive reaction preventing layer made of TiN, TiON, TiW, or MoSi between the lower electrode and the source region. Oxygen diffusion is blocked, and a silicon oxide film that is an insulator is not formed. Further, according to the wiring manufacturing method disclosed in Japanese Unexamined Patent Publication No. 5-347274, by interposing a tungsten nitride (WN _x ) layer between the W plug and the Al wiring, the reaction between Al and W is prevented, and the heat A wiring having a mechanical stability can be obtained. In addition, the publication describes that the tungsten boride (WB _x ) layer has an action of preventing a reaction between W and Al like a barrier metal such as TiN.

In general, the diffusion barrier layer has been generally well adhered to the interlayer insulating film made of silicon oxide.
Titanium nitride, which has high silicidation resistance and oxidation resistance, has been used. However, since the thermal expansion coefficient is greatly different from that of other films, film peeling was caused by heat treatment in a high temperature oxidizing atmosphere. Further, since oxygen, silicon, noble metal, lead, bismuth, etc. diffuse along the columnar crystal grain boundaries, a film thickness of 200 nm or more is required in order to obtain sufficient barrier properties. There is a problem that the step difference becomes large, which hinders high integration, and the film peeling becomes more severe. If the heat treatment temperature of the dielectric film is lowered so as not to cause this problem, problems such as insufficient dielectric constant, insufficient ferroelectricity, and increased leak current may occur. There was a problem that reliability was not obtained.

In order to solve the above problems, tantalum nitride silicide (TaSiN) is used as an amorphous diffusion barrier layer having no crystal grain boundary, instead of titanium nitride,
Attempts have also been made to improve heat resistance by using iridium as a noble metal, which is described in J. Kud.
o et al., IEEE IEDM Technical Digest, p609 (1997)
Is disclosed in. However, in this case as well, the film thickness of the entire lower electrode is as thick as 200 nm to 300 nm and the heat resistance is about 700 ° C., so it was not sufficient as a highly integrated FeRAM using an SBT film.

The present invention has been made in view of the above problems, and an object thereof is to prevent a reaction and diffusion between a conductive plug and a lower electrode of a capacitor even when formed in a high temperature oxidizing atmosphere, and to obtain a good contact. An object is to provide a capacitor having a characteristic electrode structure, a semiconductor memory device, and a manufacturing method thereof.

[0018]

[Means for Solving the Problems] To achieve the above object
The capacitor according to the present invention comprises a first electrode film, a
Sandwiched between the second electrode film and the first and second electrode films
And a dielectric thin film, wherein the first electrode film is a diffusion prevention layer.
And a boride layer of a refractory metal, the first electrode
The film consists of a diffusion prevention layer and a refractory metal from the side of the dielectric film.
It is formed by sequentially stacking a boride layer. Of the refractory metal
The boride layer is electrically conductive and has a barrier to silicon.
Has realism. Preferably, boration of the refractory metal
The material layers are Cr, Hf, La, Mo, Nb, Ta, Ti,
At least one boride selected from V, W, Y, and Zr
Contains. The diffusion barrier layer is made of Ir, Ru, Rh, R.
at least one of e and Os, or I
at least one of r, Ru, Rh, Re, Os
Contains oxides. Also, preferably, the dielectric film is A
BO_ThreeTa-type with a perovskite structure_TwoO₅, Sr
TiO_Three, (Ba, Sr) TiO_Three, Pb (Zr, T
i) O_Three, (Pb, La) (Zr, Ti) O_Three, PbT
iO_Three, BaTiO_Three, LiNbO_Three, LiTaO_Three,
And YMnO_ThreeContains at least one of
It Alternatively, the dielectric film is a bismuth-based layered perovsk force.
Containing a ito structure compound, SrBi_TwoTa_TwoO₉, SrB
i_TwoNb_TwoO₉, SrBi_Two(Ta, Nb)_TwoO₉, B
i_FourTi_ThreeO₁₂, SrBi_FourTi_FourO₁₅, SrBi
_Four(Ti, Zr)_FourO ₁₅, Bi_ThreeTiNbO₉, Bi
_ThreeTiTaO₉, BaBi_TwoTa_TwoO₉, BaBi_TwoN
b_TwoO₉Of these, at least one is included.

In order to achieve the above object, a semiconductor memory device according to the present invention is a semiconductor memory device including a selection transistor and a capacitor electrically connected to one impurity diffusion region of the selection transistor, The capacitor includes a lower electrode film electrically connected to one impurity diffusion region of the select transistor, an upper electrode film above the lower electrode, and a dielectric film sandwiched between the lower electrode film and the upper electrode film. The lower electrode film includes a diffusion prevention layer and a high-melting-point metal boride layer, and the lower electrode film includes a diffusion prevention layer and a high-melting-point metal boride layer from the dielectric film side. It is stacked in order. The material forming the capacitor and its characteristics are the same as described above.

The semiconductor memory device according to the present invention is
It further comprises a conductive contact plug, one reaching the impurity diffusion region of one of the select transistors and the other connecting to the lower electrode of the capacitor. For example, the conductive contact plug comprises doped polysilicon. In this case, a silicide film is formed on the end surface of the conductive contact plug that contacts the lower electrode of the capacitor.

In order to achieve the above object, a method of manufacturing a capacitor according to the present invention comprises a step of forming a first electrode film, a step of forming a second electrode film, and the first electrode film. Forming a dielectric thin film sandwiched between second electrode films, and the first electrode film includes a diffusion prevention layer and a boride layer of a refractory metal. In the step of forming the first electrode film, the diffusion preventing layer and the boride layer of the refractory metal are laminated in this order from the side of the dielectric film, the diffusion preventing layer and the boride layer of the refractory metal. . The material forming the capacitor and its characteristics are the same as described above.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor memory device including a selection transistor and a capacitor connected to one impurity diffusion region of the selection transistor. hand,
Forming the select transistor in a predetermined region of the semiconductor substrate, forming an insulating film on the semiconductor substrate including the select transistor, and providing the insulating film with conductivity reaching one impurity diffusion region of the select transistor. The method includes the step of forming a contact plug and the step of forming the capacitor connected to the conductive contact plug, and the step of forming the capacitor includes forming a lower electrode film on the conductive contact plug. And a step of forming a dielectric thin film on the lower electrode film, and a step of forming an upper electrode film on the dielectric thin film, wherein the lower electrode film is a diffusion prevention layer and a high melting point. A metal boride layer. In the step of forming the lower electrode film,
The diffusion prevention layer and the high-melting-point metal boride layer are laminated in this order from the dielectric film side, including the diffusion-preventing layer and the high-melting-point metal boride layer. The material forming the capacitor and its characteristics are the same as described above.

When the conductive contact plug includes polysilicon in which impurities are implanted, the method of manufacturing a semiconductor memory device according to the present invention is directed to an end face of the conductive contact plug that contacts the lower electrode of the capacitor. The method further includes the step of forming a silicide film.

According to the above-described capacitor, semiconductor memory device, and manufacturing method thereof, the lower electrode of the capacitor is a boride layer of a refractory metal having conductivity and a barrier property against silicon, and prevents diffusion of oxygen from the dielectric. The diffusion barrier layer prevents diffusion of oxygen from the dielectric to the boride layer even if the dielectric film is formed in a high temperature oxidizing atmosphere. Particularly, even when the conductive plug is formed of a silicon-based material such as polysilicon, silicidation of the diffusion layer is prevented. Therefore, since the contact plug and the boride layer are not oxidized, sufficient conductivity can be maintained even after the dielectric film is formed. Even in the case of a silicon-based conductive plug, since no silicon oxide film is formed, conduction failure does not occur.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a capacitor, a semiconductor memory device, and a method of manufacturing the same according to the present invention will be described below with reference to the accompanying drawings.

First Embodiment This embodiment relates to a dielectric capacitor having a lower electrode composed of a boride layer of a refractory metal and a diffusion barrier layer, and a semiconductor memory device having the same. In the present embodiment, the present invention will be described by taking a semiconductor memory device having a 1-transistor + 1-capacitor (1T / 1C) structure as an example.

FIG. 1 is a schematic partial sectional view of the semiconductor memory device of this embodiment, and FIG. 2 shows an equivalent circuit of the semiconductor memory device. The semiconductor memory device 10 shown in FIG.
A gate oxide film 22 formed on the semiconductor substrate 11, a gate electrode 23 formed on the gate oxide film 22, and a second conductive film having a polarity opposite to the first conductive type formed on the semiconductor substrate 11 on both sides of the gate electrode portion. An impurity diffusion region 24 having a mold,
A selection capacitor 21 (reference numeral 21 is not shown) composed of 25, a lower electrode layer 32, a dielectric thin film 33, and an upper electrode layer 34 are laminated to form a dielectric capacitor 31 ( 31 is not shown), that is, it has a 1T / 1C configuration.

More specifically, an element isolation oxide film 12 is formed on the semiconductor substrate 11 to isolate the element formation region. In the formation region of this element, the selection transistor 21
Are formed. A sidewall insulating film 26 is formed on the sidewall of the gate electrode 23. Further, an interlayer insulating film 13 covering the selection transistor 21 is formed on the semiconductor substrate 11. A connection hole 14 reaching the impurity diffusion region 24 is formed in the interlayer insulating film 13, and a conductive plug 15 connected to the impurity diffusion region 24 is formed inside the connection hole 14. This conductive plug 15
Is made of polysilicon doped with impurities, for example.
A lower electrode 32 of a capacitor 31 connected to the conductive plug 15 and a dielectric film 33 are formed on the interlayer insulating film 13.
And the upper electrode 34 are stacked. The lower electrode 3
On the side of the second conductive plug 15, a high-melting-point metal boride layer 51 and a diffusion barrier layer 52 for preventing oxygen diffusion are sequentially formed.

The gate electrode 23 also serves as the word line shown in FIG. 2, and is made of, for example, polysilicon doped with impurities. Interlayer insulating layers 13, 1
6, 18 and the side wall insulating film 26 are made of, for example, silicon oxide.

The lower electrode 32 is formed by laminating the boride layer 51 of the refractory metal and the diffusion barrier layer 52. The refractory metal boride layer 51 is formed of, for example, chromium (Cr), hafnium (Hf), lanthanum (La),
Molybdenum (MO), Niobium (Nb), Tantalum (T
a), titanium (Ti), vanadium (V), tungsten (W), yttrium (Y), zirconium (Zr)
Of these, at least one metal boride having a barrier property against silicon and having conductivity is formed. The diffusion barrier layer 52 is made of, for example, at least one metal selected from the group consisting of iridium (Ir), ruthenium (Ru), rhodium (Rh), rhenium (Re), and osmium (Os), or an oxide of the metal. Or consists of a mixture containing said metal and an oxide of said metal. Here, as an example,
The lower electrode 32 is composed of a boride of tantalum (Ta) (tantalum boride: TaB ₂ ) and a diffusion barrier layer made of iridium (Ir) having an excellent diffusion barrier property with respect to the constituent elements of the dielectric. And The thickness is, for example, T
The aB ₂ is 100 nm and the Ir is 150 nm.

The dielectric film 33 is made of, for example, Ta._TwoO₅,
Or ABO_Three-Type perovskite structure SrTiO 3
_Three, (Ba, Sr) TiO_Three, Pb (Zr, Ti) O_Three
(Lead zirconate titanate), (Pb, La) (Zr, T
i) O_Three(Lead lanthanum zirconate titanate), PbTi
O_Three, BaTiO_Three, LiNbO_Three, LiTaO_Three,
And YMnO_ThreeContains at least one of the
Alternatively, the bismuth-based layered perovskite structure compound S
rBi_TwoTa_TwoO₉(SBT), SrBi_TwoNb_TwoO₉
(SBN), SrBi_Two(Ta, Nb)_TwoO₉, Bi_Four
Ti_ThreeO₁₂, SrBi_FourTi_FourO₁₅, SrBi
_Four(Ti, Zr)_FourO₁₅, Bi_ThreeTiNbO₉, Bi
_ThreeTiTaO₉, BaBi_TwoTa_TwoO₉, BaBi_TwoN
b_TwoO₉Of these, at least one is included. here
Then, as an example, the ferroelectric film 33 is made of S having a thickness of 100 nm.
BT film (SrBi _TwoTa_TwoO₉).

The upper electrode layer 34 preferably contains at least one of the noble metals Pt, Ir, Ru, Rh, Re, Os and Pd, or an oxide thereof. Here, for example, a 100 nm-thickness Ir film is used as the upper electrode layer 3
Used as 4.

The dielectric capacitor 31 is covered with the interlayer insulating film 16, and the plate line 4 connected to the upper electrode 34 through the connection hole on the upper electrode 34 of the dielectric capacitor 31.
1 is formed. The plate line 41 is, for example, A
It is formed from an l-Si alloy. Furthermore, the plate line 4 above
An inter-layer insulating film 18 covering 1 is formed. The other impurity diffusion region 2 is formed in the interlayer insulating films 18, 16 and 13.
5 is formed, and a bit line 42 connected to the impurity diffusion region 25 is formed through the bit contact hole 19. The bit line 42 is formed of, for example, an Al wiring.

The bit line 42 is electrically connected to the impurity diffusion region 25 of the selection transistor 21, while
The plate line 41 is electrically connected to the upper electrode 34 of the capacitor 31. Lower electrode layer 3 of capacitor 31
2 is electrically connected to the other impurity diffusion region 24 of the selection transistor 21 via the contact plug 15. Next is ferroelectric non-volatile memory (FeRAM)
The operation of the semiconductor memory device 10 having the above configuration will be described by taking the above case as an example (see FIG. 2). When writing to the semiconductor memory device 10, a voltage is applied to the gate electrode (word line) 23 of the selection transistor 21 to turn on the selection transistor 21, and a channel region between the source / drain regions 24 and 25 of the selection transistor 21. Conducts. As a result, the bit line 42 connected to the source / drain region 25 via the contact plug 15 is connected to the lower electrode layer 32 of the capacitor 31. Then, a write voltage is applied to the dielectric capacitor 31 from the bit line 42 and the plate line 41 to set the polarization state of the dielectric film 33. As a result, the semiconductor memory device 10 is written.

When reading from the semiconductor memory device 10, the gate electrode (word line) of the selection transistor 21 is selected.
A voltage is applied to 23 to turn on the selection transistor 21, the bit line 41 and the lower electrode 32 are connected, and a read voltage is applied to the dielectric capacitor 31 from the bit line 42 and the plate line 41 to change the voltage. When the voltage is applied, the polarization state is detected by the current flowing through the dielectric capacitor 31, that is, the difference in the amount of charge stored in the dielectric capacitor 31, thereby reading from the semiconductor memory device 10.

The electrical characteristics of such a ferroelectric semiconductor memory device were measured using a known Sawyer tower circuit. The shape of the hysteresis loop is good, the remanent polarization 2Pr is 15 μC / cm ² , the coercive electric field Ec is 30 kV / at an applied voltage of 3V.
The value of cm was obtained, and it was confirmed that the ferroelectric capacitor was sufficiently operated. Moreover, the value of the leak current at an applied voltage of 3 V was 5 × 10 ⁻⁸ A / cm ² , and it was confirmed that the characteristics were sufficient as a ferroelectric capacitor. Next, known fatigue characteristics were measured. That is, it is a measurement of the change in the residual polarization value 2Pr with respect to the number of repeated polarization inversions when a rectangular pulse having a voltage of 3V and a frequency of 1 MHz is applied to the above ferroelectric capacitor to repeatedly perform polarization inversion. As a result, no change was observed in the residual polarization value 2Pr even after 10 ¹² cycles of polarization reversal, indicating good characteristics as a nonvolatile memory.

In the above embodiment, tantalum boride (TaB ₃ ) was used as the material for the lower layer of the lower electrode 32, but the above-mentioned chromium (Cr), hafnium (Hf), lanthanum (La), molybdenum (MO) were used. , Niobium (N
b), tantalum (Ta), titanium (Ti), vanadium (V), tungsten (W), yttrium (Y), zirconium (Zr), a barrier against silicon even when a boride of another metal is used. With the
Since it has conductivity, it exhibited the same effect as tantalum boride (TaB ₃ ).

As materials for the dielectric film of the capacitor 31, Ta ₂ O ₅ (tantalum oxide), STO (SrTi) are used.
O ₃ : Strontium titanate), BST ((Ba, S
r) TiO _3: barium titanate and strontium titanate), in the case of using a high dielectric material such as BaTiO _3, the semiconductor memory device of this embodiment is a DRAM applied to highly integrated. In this case, the capacitor 31 is charged to carry out writing, and the stored data is read from the amount of stored charge.

In the semiconductor memory device 10 having the dielectric capacitor 31, the lower electrode 32 connected to the conductive plug 15 has a boride layer 51 of a refractory metal and a diffusion barrier layer for preventing diffusion of oxygen. 52, and since the boride layer 51 and the diffusion barrier layer 52 are laminated in this order from the conductive plug 15 side, even if the dielectric film 33 is formed in a high temperature oxidizing atmosphere, for example. The diffusion barrier layer 52 prevents diffusion of oxygen into the boride layer 51. Therefore, since the boride layer 51 is not oxidized, the boride layer 51 can maintain sufficient conductivity even after the dielectric film 33 is formed. In particular, even if the conductive plug 15 is formed of a silicon-based material such as polysilicon, since the silicon oxide film is not formed, the conduction failure does not occur.

Further, in the semiconductor memory device 10, since the conductive plug 15 is used for connecting the selection transistor 21 and the dielectric capacitor 31, the ferroelectric capacitor 31 is formed on the transistor 21 in a stacked structure. Can be adopted. As a result, the memory cell area is reduced and high integration is possible. When this structure is used, as described above, a tantalum boride (TaB ₂ ) film having a film thickness of 100 nm is formed as the boride layer 51 on the conductive plug 15, and the film thickness as the oxygen diffusion barrier layer 52 is formed. If a 150 nm iridium (Ir) film is used, even if the dielectric film 33 is formed on the Ir film 52 and exposed to a high temperature of about 750 ° C. to 800 ° C. in oxygen for 1 hour or more, the film is made of polysilicon. No oxidation of the conductive plug 15 or reaction with the electrode occurs. Further, when the iridium film is used as the base of the dielectric film 33, very good dielectric characteristics can be obtained, and thus it is very useful. Therefore,
STO film, BSTO film, and PZT that have a relatively low formation temperature
It can be applied to a film or the like to an SBT film having a high formation temperature, and since the step difference in the capacitor region can be suppressed to a low level, it is extremely advantageous for high integration of the device.

Next, the function of the metal in the oxygen diffusion barrier layer 52 will be described below. As the oxygen diffusion barrier layer 52, titanium nitride (Ti
N), titanium nitride oxide (TiON), tantalum nitride (T
Conductive nitrides such as iN), tantalum nitride silicide (TaSiN), and tungsten nitride (WN) are also conceivable, but these are sufficient in terms of heat resistance when a ferroelectric material is used for the dielectric film 33. is not. However, Ta ₂ O ₅ and STO
In some cases, it can be used in the case of high dielectric materials such as. At present, noble metals or their oxides are the only known diffusion barrier materials that can be used in the case of ferroelectrics.

As the oxygen diffusion barrier layer 52, a noble metal such as iridium (Ir), ruthenium (Ru), rhodium (Rh), rhenium (Re), osmium (Os), iridium oxide (IrO), Conductive oxides such as ruthenium oxide (RuO ₂ ), rhodium oxide (RhO ₃ ), rhenium oxide (ReO ₃ ), and osmium oxide (OsO ₃ ) can be given. Such a diffusion barrier layer 52
In the case of using, the lower electrode structure is such that the conductive plug 15 made of polysilicon (silicide film 53),
A boride layer 51, a buffer layer (not shown), an oxygen diffusion barrier layer 52, a base layer (not shown), and a dielectric film 33 are formed. First, when a conductive oxide such as iridium oxide (IrO ₂ ) is used for the oxygen diffusion barrier layer 52, the metal in the boride layer 51 takes in oxygen in the conductive oxide and oxidizes it. Probability is high. Therefore, iridium (Ir) is formed between the diffusion barrier layer 52 and the boride layer 51.
It is preferable to form a buffer layer (not shown) such as. Further, it is known that when the dielectric film 33 is directly formed on the conductive oxide, the leak current becomes large. Therefore, it is preferable to form a base layer (not shown) made of platinum (Pt) or the like under the dielectric film 33. On the other hand, iridium (Ir) is formed on the diffusion barrier layer 52.
In the case of using, the diffusion barrier layer 52 can have an effect as a base layer of the dielectric film 33 and an effect as a buffer layer, so that the base layer and the buffer layer can be omitted. Similar effects can be obtained in the case of other noble metals (eg ruthenium, rhodium, rhenium, osmium). Therefore, in the example described with reference to FIG. 1, the buffer layer and the base layer are omitted.

When considering the characteristics of the dielectric,
Platinum (Pt) is the best as a stratum, but platinum (Pt)
Since t) does not become a diffusion barrier of oxygen, platinum (P
It is necessary to have a laminated structure of t) and the diffusion barrier layer. Shi
However, in addition to this, platinum (P
t) is added to, for example, iridium platinum (IrPt)
Like gold, the effect of both underlayer and diffusion barrier layer
You may also use it. Regarding lead and bismuth
Either of these is currently a promising ferroelectric material.
Must contain the metal oxides of
Pt_TwoPb_TwoO ₇Forming an oxide layer such as
It may be a diffusion barrier layer, but it is extremely
Considered to be rare.

Second Embodiment This embodiment, like the first embodiment, includes a dielectric capacitor whose lower electrode is composed of a boride layer of a refractory metal and a diffusion barrier layer, and the same. The present invention relates to a semiconductor memory device having a 1-transistor + 1-capacitor (1T / 1C) structure. The difference between this embodiment and the first embodiment is that
A silicide film 53 is formed at the interface between the conductive plug 15 of the semiconductor memory device 10 of FIG. 1 and the boride layer 51 of refractory metal.

FIG. 3 is a schematic partial cross-sectional view of the semiconductor memory device of this embodiment, and the equivalent circuit of the semiconductor memory device is the same as that of FIG. In FIG. 3, the same components as those described with reference to FIG. 1 are designated by the same reference numerals.
Similar to the first embodiment, the semiconductor memory device 60 shown in FIG. 3 has a gate oxide film 22 formed on the semiconductor substrate 11, a gate electrode 23 formed on the gate oxide film 22, and both sides of the gate electrode portion. , A lower electrode layer 32, a lower electrode layer 32, and a dielectric thin film, which are formed on the semiconductor substrate 11 and are composed of impurity diffusion regions 24 and 25 having a second conductivity type having a polarity opposite to the first conductivity type. 33 and a dielectric capacitor 31 (reference numerals 21 and 31 are not shown in FIG. 3) formed by laminating the upper electrode layer 34, that is, a 1T / 1C configuration.

The selection transistor 2 is formed on the semiconductor substrate 11.
An interlayer insulating film 13 is formed so as to cover 1. The interlayer insulating film 13 has a contact hole 14 reaching the impurity diffusion region 24.
Is formed, and a conductive plug 15 connected to the impurity diffusion region 24 is formed therein. The conductive plug 15 is made of, for example, polysilicon doped with impurities. A silicide film 53 is formed only on the surface of the polysilicon conductive plug 15. Here, as an example, the silicide film 53 is cobalt silicide (CoSi ₂ ) having a film thickness of 20 nm. When the conductive plug 15 is polysilicon, the silicide film 5 is formed on the plug surface.
3 is formed, during the high temperature treatment, the lower electrode 32 is silicidized and its characteristics are deteriorated due to the diffusion of silicon from the polysilicon plug 15, and the formation of an insulating film such as silicon oxide is further promoted by the oxidation reaction. It can be suppressed to improve reproducibility and uniformity.

The interlayer insulating film 13 is covered with the silicide film 53, and the lower electrode 32 of the capacitor 31 and the dielectric film 3 are formed.
3 and the upper electrode 34 are laminated. Lower electrode 32
Of the refractory metal on the silicide film 53 side of
1 and a diffusion barrier layer 52 that blocks the diffusion of oxygen are sequentially formed.

As in the first embodiment, the lower electrode 3
2 is formed by laminating a boride layer 51 of a refractory metal and the diffusion barrier layer 52. The refractory metal boride layer 51 is formed of, for example, chromium (Cr) or hafnium (H).
f), lanthanum (La), molybdenum (MO), niobium (Nb), tantalum (Ta), titanium (Ti), vanadium (V), tungsten (W), yttrium (Y), zirconium (Zr) It is made of a material which is made of at least one metal boride and which has a barrier property against silicon and a conductivity. The diffusion barrier layer 52 is formed of, for example, iridium (I
r), ruthenium (Ru), rhodium (Rh), rhenium (Re), osmium (Os), or at least one metal, or an oxide of the above metal,
Alternatively, it is composed of a mixture containing the metal and an oxide of the metal. Here, as an example, the lower electrode 32 is a boride of tantalum (Ta) (tantalum boride: Ta).
B ₂ ) and a diffusion barrier layer made of iridium (Ir) having an excellent diffusion barrier property with respect to the constituent elements of the dielectric. The thickness is, for example, 100 for TaB _2.
nm and Ir are 150 nm.

The material of the dielectric film 33 is the same as that of the first embodiment.
Similar ABO_ThreeHaving a type-Perovs force structure
Or bismuth-based layered perovskite structure compound
Select from the things. Here, as an example, the ferroelectric film 33
Is a 100 nm thick SBT film (SrBi _TwoTa_TwoO₉)
To

The upper electrode layer 34 preferably contains at least one of the noble metals Pt, Ir, Ru, Rh, Re, Os and Pd, or an oxide thereof. Here, for example, a 100 nm-thickness Ir film is used as the upper electrode layer 3
Used as 4.

The subsequent structure is the same as that of the semiconductor memory device 10 in FIG. The operation of the semiconductor memory device 60 having the above configuration is also the same as that of the semiconductor memory device 10 in FIG.

According to the same measurement as in the first embodiment, the above-mentioned capacitor and semiconductor memory device were confirmed to have sufficient operation and characteristics as a ferroelectric capacitor, and showed good characteristics as a non-volatile memory.

The DR of this embodiment is also suitable for high integration.
It is applied to AM.

According to the above semiconductor memory device 60, even if the dielectric film 33 is formed in a high temperature oxidizing atmosphere, the diffusion barrier layer 52 prevents the diffusion of oxygen into the boride layer 51. It Therefore, since the boride layer 51 is not oxidized, the boride layer 51 can maintain sufficient conductivity even after the dielectric film 33 is formed. In particular, even if the conductive plug 15 is formed of a silicon-based material such as polysilicon, since the silicon oxide film is not formed, the conduction failure does not occur. Further, when the conductive plug 15 is polysilicon, a silicide film 53 is formed on the plug surface, so that the lower electrode is silicidized by diffusion of silicon from the polysilicon plug 15 and silicon oxide is formed by an oxidation reaction. It is possible to further suppress the formation of an insulating film such as, and to perform mass production with excellent reproducibility and uniformity.
Other effects are the same as those of the first embodiment.

In the silicide film formed at the interface between the conductive plug 15 and the lower electrode 32, titanium silicide, vanadium silicide, chromium silicide, manganese silicide, iron silicide, nickel silicide, zirconium silicide, niobium, in addition to cobalt silicide. It is also possible to use silicide, molybdenum silicide, ruthenium silicide, rhodium silicide, palladium silicide, hafnium silicide, tantalum silicide, tungsten silicide, rhenium silicide, osmium silicide, iridium silicide, platinum silicide.

The action of the metal in the oxygen diffusion barrier layer 52 is the same as in the first embodiment.

Third Embodiment In this embodiment, the ferroelectric capacitor 31, shown in FIG.
Also, an example of a method for manufacturing the semiconductor memory device 10 will be described.
The semiconductor memory device 10 shown in FIG. 1 is formed on the semiconductor substrate 11 on both sides of the gate oxide film 22 formed on the semiconductor substrate 11, the gate electrode 23 formed on the gate oxide film 22, and the gate electrode portion. 2nd of opposite polarity to 1 conductivity type
A select transistor 21 formed of impurity diffusion regions 24 and 25 having a conductivity type; a lower electrode layer 32;
It has a dielectric thin film 33 and a dielectric capacitor 31 (reference numerals 21 and 31 are not shown) formed by laminating an upper electrode layer 34, that is, has a 1T / 1C configuration.

4 to 5 are partial cross sectional views showing a manufacturing process of the semiconductor memory device 10 shown in FIG. 4 to 5, the same components as those described with reference to FIG. 1 are designated by the same reference numerals. First, as shown in FIG. 4A, an element isolation region 12 having a LOCOS structure is formed on a first conductive semiconductor substrate 11 based on a known method.
To form. Next, the surface of the semiconductor substrate 11 is oxidized to form the gate oxide film 22. Then, after depositing a polysilicon layer on the entire surface by, for example, a CVD method, the polysilicon layer is patterned by a photolithography technique and an etching technique to form a gate electrode 2 made of polysilicon.
3 is formed. Next, the second conductive impurity ions are implanted, and the implanted impurities are activated to form the impurity regions 24 and 25. After that, the side wall 26 is formed by a known method, and the selection transistor 21 is formed.
To form. The gate electrode 23 also serves as a word line.

Next, the interlayer insulating film 13 made of, for example, silicon oxide is covered with CV so as to cover the selection transistor 21.
It is formed by the D method. The film forming temperature of the interlayer insulating film 13 is, for example, about 400 ° C. Then, in the portion of the interlayer insulating film 14 above the impurity region 24 of the selection transistor 21, a contact hole 14 is formed by using a known photolithography method and dry etching method, and polysilicon into which impurities are diffused is buried, Known CMP (Ch
mechanical Mechanical Polish
ng) method, the excess polysilicon on the interlayer insulating film 13 is polished and removed, and the conductive plug 15 is formed by the polysilicon left inside the contact hole 14, and at the same time, the conductive plug is electrically connected to the interlayer insulating film 13. The surface with the sex plug 15 is flattened. The diameter of the conductive plug 15 is
For example, it is 0.4 μm.

Next, as shown in FIGS. 4 (B) and 4 (C),
The capacitor 31 is formed on the plug 15. First, the lower electrode layer 32 is formed on the interlayer insulating film 13 by laminating the refractory metal boride layer 51 and the diffusion barrier layer 52. The refractory metal boride layer 51 is formed of, for example, chromium (Cr), hafnium (Hf), lanthanum (La), molybdenum (MO), niobium (Nb), tantalum (T).
a), titanium (Ti), vanadium (V), tungsten (W), yttrium (Y), zirconium (Zr)
Of these, at least one metal boride having a barrier property against silicon and having conductivity is formed. The diffusion barrier layer 52 is made of, for example, at least one metal selected from the group consisting of iridium (Ir), ruthenium (Ru), rhodium (Rh), rhenium (Re), and osmium (Os), or an oxide of the metal. Or consists of a mixture containing said metal and an oxide of said metal. Here, as an example,
The lower electrode 32 is composed of a boride of tantalum (Ta) (tantalum boride: TaB ₂ ) and a diffusion barrier layer made of iridium (Ir) having an excellent diffusion barrier property with respect to the constituent elements of the dielectric. And The thickness is, for example, T
The aB ₂ is 100 nm and the Ir is 150 nm.

As shown in FIG. 4B, first, a metal boride layer made of tantalum boride (TaB ₂ ) is formed to a thickness of 100 nm by the DC sputtering method. The film forming conditions are tantalum boride (TaB ₂ ) as a target.
A target was used, input power was 2 kW, argon (Ar) was used as a process gas, and an argon supply flow rate was 30.
0 sccm, the pressure of the film forming atmosphere is set to 0.2 Pa, and the substrate temperature is set to 200 ° C. Further, an oxygen diffusion barrier layer made of iridium (Ir) is continuously formed to a thickness of, for example, 150 nm by a DC sputtering method without being exposed to the air. As the film formation conditions, an iridium (Ir) target was used as a target, an input power was 2 kW, argon (Ar) was used as a process gas, an argon supply flow rate was 30.0 sccm, and a film formation atmosphere pressure was 0.2 Pa.
Set the substrate temperature to 200 ° C.

Next, the dielectric film 33 is formed on the lower electrode layer 32.
Are formed (FIG. 4 (B)). Even if the dielectric film 33 is
If Ta_TwoO₅, Or ABO_ThreeType perovskite structure
SrTiO having_Three, (Ba, Sr) TiO_Three, Pb
(Zr, Ti) O_Three(Lead zirconate titanate), (P
b, La) (Zr, Ti) O_Three(Zirconate titanate LA
Lead), PbTiO_Three, BaTiO_Three, LiNbO
_Three, LiTaO_Three, And YMnO_ThreeAt least
Also contains one, or a bismuth-based layered perov
Suite structure compound SrBi_TwoTa_TwoO₉(SBT),
SrBi_TwoNb_TwoO₉(SBN), SrBi_Two(Ta,
Nb)_TwoO₉, Bi_FourTi_ThreeO₁₂, SrBi_FourTi_Four
O₁₅, SrBi_Four(Ti, Zr)_FourO₁₅, Bi_ThreeT
iNbO₉, Bi_ThreeTiTaO₉, BaBi_TwoTa_TwoO
₉, BaBi_TwoNb_TwoO₉At least one of
I'm out. Here, as an example, the film thickness of the ferroelectric film 33 is
100 nm SBT film (SrBi _TwoTa_TwoO₉: Stro
Tin bismuth tantalate).

Known chemical solution coating method (CSD: Che
medical Solution Deposition
n), an SBT thin film is formed as the ferroelectric film 33 on the lower electrode layer 32. First, a commercially available SBT precursor solution is used to form an SBT thin film. The metal composition ratio in the solution is Sr / Bi / Ta = 0.8 / 2.2 / 2.0. After coating by a known spin coating method, heating is performed on a hot plate at 250 ° C. for 5 minutes to volatilize the solvent, and subsequently, heating is performed at 700 ° C. for 30 minutes in an oxygen atmosphere using a diffusion furnace. I went. This film formation process is 3
The ferroelectric SBT film having a film thickness of 100 nm is formed by repeating the process.

Next, the upper electrode 34 is formed on the ferroelectric film 33 (FIG. 4B). The upper electrode layer 34 is preferably noble metals Pt, Ir, Ru, Rh, Re, Os, P.
At least one of d or at least one conductive oxide of noble metals is included. Here, for example, the film thickness is 100 nm
Is used as the upper electrode layer. Similar to the lower electrode 32, an Ir film having a film thickness of 100 nm is formed on the SBT film by a known sputtering method at a substrate temperature of 400 ° C. to form an upper electrode. Next, as shown in FIG.
r Upper electrode layer 34, SBT dielectric film 33, and lower electrode layer 3
2 is processed into a size of, for example, 1.0 μm square by using a known photolithography method and dry etching method.
As a result, on the inter-layer insulating film 13, a lower electrode 32 connected to the conductive plug 15, a dielectric film 33, and an upper electrode 34 are laminated, and a dielectric capacitor having a shape as shown in FIG. A ferroelectric capacitor) 31 is formed.

In the above dry etching, a reactive ion etching apparatus RIE etcher is used and the upper electrode 3
The mixed gas of Ar and Cl ₂ is used as the etching gas for etching 4, the mixed gas of Ar and BCl ₃ is used as the etching gas for etching the SBT dielectric film 33, and the mixed gas of Ar and BCl ₃ is used as the etching gas for etching the lower electrode layer 32. Ar
And a mixed gas of Cl ₂ are used. The profile angle α of the side wall of the formed ferroelectric capacitor 31 is about 60 °, and the CD gain is about 0.1 μm on one side.

Thereafter, in order to recover etching damage when processing the dielectric capacitor 31, annealing is performed at 650 ° C. for 30 minutes in a nitrogen atmosphere using a diffusion furnace.

Next, as shown in FIG. 5A, a known C
By the VD method, an interlayer insulating film 16 covering the dielectric capacitor 31 is formed on the interlayer insulating film 13 by depositing, for example, silicon oxide to a thickness of 150 nm. After that, a connection hole 17 is formed in the interlayer insulating film 16 on the upper electrode 34 so as to have a diameter of 0.4 μm, for example, by using a known lithography technique and etching technique.

Next, the upper electrode 34 is formed on the interlayer insulating film 16.
A plate wire 41 is formed to connect with the plate wire 41. As shown in FIG. 5B, a titanium (Ti) film having a thickness of, for example, 20 nm is formed on the interlayer insulating film 16 by a known sputtering method.
Then, a titanium oxynitride (TiON) film is applied to, for example, 20 nm.
Of aluminum-silicon (Al
-Si) alloy film is formed to a thickness of, for example, 500 nm.
Next, the Ti film, the TiON film, and the Al—Si alloy film were processed by known photolithography technology and dry etching technology to form the plate line 41 connected to the upper electrode 34 through the connection hole 17.

After that, as shown in FIG. 1, after the interlayer insulating film 18 is formed by the CVD method and flattened, the well-known lithographic technique and the etching technique are used, and the other impurity diffusion region 25 is formed. Of the above-mentioned interlayer insulating films 18, 16,
A bit contact hole 19 is formed at 13. Further, the bit line 42 is formed by using the well-known aluminum wiring technique to complete the ferroelectric memory cell (semiconductor memory device).

After that, in order to restore the characteristics of the transistor 21, FGA processing is performed at 450 ° C. for 30 minutes in a forming gas which is a mixed gas of hydrogen and nitrogen.

The electrical characteristics of the ferroelectric memory cell thus manufactured were measured using a known Sawyer tower circuit.
The shape of the hysteresis loop is good, the remanent polarization 2Pr is 15 μC / cm ² and the coercive electric field Ec is 30 k at an applied voltage of 3V.
The value of V / cm was obtained, and it was confirmed that the ferroelectric capacitor operates sufficiently. Moreover, the value of the leak current at an applied voltage of 3 V was 5 × 10 ⁻⁸ A / cm ² , and it was confirmed that the characteristics were sufficient as a ferroelectric capacitor. next,
A known fatigue characteristic was measured. That is, voltage 3V,
This is a measurement of the change in the residual polarization value 2Pr with respect to the number of repeated polarization inversions when a rectangular pulse having a frequency of 1 MHz is applied to the ferroelectric capacitor to repeatedly perform polarization inversion. As a result, no change was observed in the residual polarization value 2Pr even after 10 ¹² cycles of polarization reversal, indicating good characteristics as a nonvolatile memory.

Further, using the process described above, D.
K. Schroder, Semiconductor Material and Device Cha
racterization, Wiley-Interscience, New York, (199
Known four-terminal Kelvin (Kelvin
vin) pattern was prepared, and the contact resistance between the polysilicon conductive plug 15 and the lower electrode 32 was measured. As a result, the conductive plug 15 of polysilicon having a diameter of 0.4 μm is formed.
In the case of, the value is about 200Ω, which is a sufficiently small value in manufacturing the semiconductor memory device having the above configuration.

The semiconductor memory device 10 manufactured as described above
Is a 100 nm tantalum boride (TaB ₂ ) film and a 150 nm iridium (Ir) film on the conductive plug 15.
Even after the film is formed and the dielectric film 33 is formed on the Ir film 52, the conductive plug 15 made of polysilicon is exposed even if exposed to a high temperature of about 750 ° C. to 800 ° C. for one hour or more in oxygen.
Does not oxidize or react with the electrodes. Further, when the iridium film is used as the base of the dielectric film 33, very good dielectric characteristics can be obtained, and thus it is very useful. Therefore, the STO film, BSTO film, P
The present invention can be applied to ZT films and the like as well as SBT films having a high formation temperature.

The above characteristics are the same as those of the capacitor 31 in the manufacturing process of the above-mentioned capacitor and semiconductor memory device.
After the lower electrode 32 is formed, even when the conductive plug is made of a silicon-based material such as polysilicon, even in a high temperature oxidizing atmosphere necessary for forming a dielectric film. In addition, the diffusion barrier layer prevents the diffusion of oxygen into the boride layer and the silicidation action from the polysilicon plug to the lower electrode, so that the boride layer may be oxidized or form a silicon oxide film. In other words, it shows that sufficient electrical conductivity is maintained between the plug and the lower electrode, and no conduction failure occurs.

In the above embodiment, tantalum boride (TaB ₃ ) was used as the material of the lower layer of the lower electrode 32, but the above-mentioned chromium (Cr), hafnium (Hf), lanthanum (La), molybdenum (MO) were used. , Niobium (N
b), tantalum (Ta), titanium (Ti), vanadium (V), tungsten (W), yttrium (Y), zirconium (Zr), a barrier against silicon even when a boride of another metal is used. With the
Since it has conductivity, it exhibited the same effect as tantalum boride (TaB ₃ ).

Further, as the material of the dielectric film 33 of the capacitor 31, Ta ₂ O ₅ (tantalum oxide), STO (Sr
TiO ₃ : Strontium titanate), BST ((B
a, Sr) TiO _3: barium titanate and strontium titanate), when using a high dielectric material such as BaTiO _3, the semiconductor memory device of this embodiment is a DRAM applied to highly integrated.

Fourth Embodiment The present embodiment shows an example of a method of manufacturing the semiconductor memory device 60 shown in FIG. As described in the second embodiment, the semiconductor memory device 60 in FIG. 3 has a 1-transistor + 1-capacitor (1T / 1C) structure, and the lower electrode 32 of the capacitor has the boride layer 5 of refractory metal.
1 and the diffusion barrier layer 52 are laminated. However,
Unlike the first and third embodiments, in the semiconductor memory device 60, the conductive plug 15 and the boride layer 5 of refractory metal 5 are used.
A silicide film 53 is formed at the interface with 1.

6 and 7 are partial sectional views showing a manufacturing process of the semiconductor memory device 60 shown in FIG. In FIGS. 6 and 7, the same components as those described with reference to FIG. 3 are designated by the same reference numerals. First, in FIG. 6A, similarly to the third embodiment, after the select transistor 21 is formed on the first conductive semiconductor substrate 11, the interlayer insulating film 13 made of, for example, silicon oxide is subjected to CV.
For example, the polysilicon conductive plug 1 is formed by the D method and reaches the impurity region 24 of the selection transistor 21.
5 is formed. The diameter of the conductive plug 15 is, for example,
It is 0.4 μm.

Then, after performing a known SC2 cleaning for 10 minutes, a cobalt silicide (CoSi ₂ ) film is formed to a thickness of, for example, 20 nm only on the surface of the conductive plug of polysilicon by a known cobalt silicide technique. .
This CoSi ₂ film corresponds to the silicide film 53. An example of the manufacturing method will be described below. For example, the known D
A cobalt (Co) film is formed, for example, by the C sputtering method to a thickness of 10
After being formed to a thickness of nm, a titanium (Ti) film is subsequently formed to a thickness of 20 nm. Next, RTA (Rapid Ther
mal Annealer) 3 in a nitrogen atmosphere at 550 ° C
A heat treatment was performed for 0 seconds to react polysilicon with cobalt to form cobalt silicide. After that, a known ammonia hydrogen peroxide solution cleaning is performed for 10 minutes, and then a sulfuric acid hydrogen peroxide solution cleaning is performed for 3 minutes to remove only the Ti layer and the unreacted cobalt layer. Then, heat treatment is again performed for 30 seconds in a nitrogen atmosphere at 700 ° C. by RTA. As a result, a cobalt silicide (CoSi ₂ ) film is formed only on the surface of the polysilicon conductive plug.

Subsequently, as shown in FIGS. 6B and 6C, a plug in which a cobalt silicide (CoSi ₂ ) film 53 is formed on the interlayer insulating film 13 by the same method as in the third embodiment. Lower electrode 32 and dielectric film 33 covering 15
Then, the capacitor 31 is formed by stacking the upper electrode 34. The lower electrode layer 32 is formed by stacking a refractory metal boride layer 51 and a diffusion barrier layer 52.

The high-melting-point metal boride layer 51 is, for example,
Chromium (Cr), Hafnium (Hf), Lanthanum (L
a), molybdenum (MO), niobium (Nb), tantalum (Ta), titanium (Ti), vanadium (V), tungsten (W), yttrium (Y), zirconium (Z)
It is formed of a material having a barrier property against silicon and having conductivity, which is made of at least one metal boride of r). The diffusion barrier layer 52 is
For example, iridium (Ir), ruthenium (Ru), rhodium (Rh), rhenium (Re), osmium (O
In s), it consists of at least one metal, or an oxide of the above metal, or a mixture containing the above metal and an oxide of the above metal. The dielectric film 33 is
For example, Ta ₂ O ₅ or SrTiO ₃ having a ABO ₃ type perovskite structure, (Ba, Sr) Ti
O ₃ , Pb (Zr, Ti) O ₃ (lead zirconate titanate), (Pb, La) (Zr, Ti) O ₃ (lead lanthanum zirconate titanate), PbTiO ₃ , BaTiO ₃ ,
At least one of LiNbO ₃ , LiTaO ₃ , and YMnO ₃ is contained, or a bismuth-based layered perovskite structure compound SrBi ₂ Ta ₂ O _{9 is included.}
(SBT), SrBi ₂ Nb ₂ O ₉ (SBN), SrB
i ₂ (Ta, Nb) ₂ O ₉ , Bi ₄ Ti ₃ O ₁₂ , Sr
_{Bi 4 Ti 4 O 15, SrBi} 4 (Ti, Zr) 4 O
₁₅ , Bi ₃ TiNbO ₉ , Bi ₃ TiTaO ₉ , Ba
At least one of Bi ₂ Ta ₂ O ₉ and BaBi ₂ Nb ₂ O ₉ is included. As an example, the lower electrode 32
Is 100 nm of tantalum (Ta) boride (tantalum boride: TaB ₂ ) and 100 nm of iridium (I).
r) A diffusion barrier layer is formed, and a 100 nm ferroelectric SBT film 33 is formed thereon. Further, the dielectric film 33
A 100 nm-thickness Ir film is formed thereon as the upper electrode layer.

Subsequently, as shown in FIGS. 7A and 7B, after the interlayer insulating film 16 is deposited, an Al--Si alloy plate line connected to the upper electrode 34 is formed on the interlayer insulating film 16. 41 is formed. Then, using a known aluminum wiring technique, the bit line 42 connected to the other impurity diffusion region 25 of the selection transistor 21 is formed, and the semiconductor memory device 60 is completed.

By the same measurement as in the third embodiment,
The contact resistance between the polysilicon conductive plug 15 and the lower electrode 32 is about 200Ω in the case of the polysilicon conductive plug 15 having a diameter of 0.4 μm, which is a sufficiently small value in manufacturing the semiconductor memory device. is there. Further, the capacitor 31 and the semiconductor device 60 manufactured as described above.
, Was confirmed to have sufficient operation and characteristics as a ferroelectric capacitor, and showed good characteristics as a non-volatile memory.

According to the capacitor and the semiconductor memory device manufactured by the manufacturing process described above, even if the diffusion barrier layer diffuses oxygen into the boride layer even in a high temperature oxidizing atmosphere necessary for forming a dielectric film, In addition, the silicidation action from the polysilicon plug to the lower electrode is prevented, the boride layer is not oxidized, and sufficient conductivity is maintained between the plug and the lower electrode to prevent conduction failure. It never happens. Particularly, when the conductive plug is formed of a silicon-based material such as polysilicon, the silicide film 53 is formed on the surface of the plug 15 so that the lower portion due to the diffusion of silicon from the polysilicon plug 15 during the high temperature treatment. Silicidation of the electrode 32,
By the oxidation reaction, formation of an insulating film of, for example, silicon oxide can be further suppressed, and reproducibility and uniformity are improved.

In the above-described embodiment, other than tantalum boride (TaB ₃ ) as the material for the lower layer of the lower electrode 32,
The above-mentioned chromium (Cr), hafnium (Hf), lanthanum (La), molybdenum (MO), niobium (Nb), tantalum (Ta), titanium (Ti), vanadium (V),
A boride of any one of tungsten (W), yttrium (Y), and zirconium (Zr) may be used. Further, as a material of the dielectric film of the capacitor 31, Ta ₂ O ₅ (tantalum oxide), STO (SrTiO 3) is used.
₃ : Strontium titanate), BST ((Ba, S
r) TiO ₃ : barium titanate and strontium titanate), BaTiO ₃ or other high dielectric material may be used.

In addition to cobalt silicide, titanium silicide, vanadium silicide, chromium silicide, manganese silicide, iron silicide, nickel silicide, zirconium silicide, and niobium are included in the silicide film formed at the interface between the conductive plug 15 and the lower electrode 32. It is also possible to use silicide, molybdenum silicide, ruthenium silicide, rhodium silicide, palladium silicide, hafnium silicide, tantalum silicide, tungsten silicide, rhenium silicide, osmium silicide, iridium silicide, platinum silicide.

The present invention has been described above based on the preferred embodiments, but the present invention is not limited to the embodiments described above, and various modifications can be made without departing from the gist of the present invention. Is. The structure of the semiconductor memory device described in the capacitor, the semiconductor memory device, and the method for manufacturing the same of the present invention is an example, and the design can be appropriately changed. Although SBT was used as the material of the ferroelectric thin film, the present invention is not limited to this, other ferroelectric materials may be used, and the method of forming the ferroelectric thin film may be other than the above CSD method. The present invention can also be applied to methods such as MOCVD, sputtering and vapor deposition.

[0088]

According to the present invention, the first electrode connected to the conductive plug has a boride layer of a refractory metal and a diffusion barrier layer for preventing diffusion of oxygen, Since the boride layer and the diffusion barrier layer are laminated in this order from the plug side, even if the dielectric film is formed in a high-temperature oxidizing atmosphere, the diffusion barrier layer prevents oxygen from being introduced into the boride layer. The spread has been stopped. Therefore, since the boride layer is not oxidized, it has sufficient conductivity even after the dielectric film is formed. In particular, even when the conductive plug is formed of a silicon-based material such as polysilicon, since the silicon oxide film is not formed, the conduction failure does not occur. Therefore, according to the semiconductor memory device of the present invention, it is possible to provide a highly reliable electrode structure having a remarkable barrier property against a conductive plug and the like, which is extremely useful in practice.

Further, in the semiconductor memory device of the present invention, since the conductive plug is used for connecting the selection transistor and the dielectric capacitor, it is possible to adopt the stack type structure in which the ferroelectric capacitor is formed on the selection transistor. Has become. As a result, the memory cell area is reduced and high integration is possible. According to the method of manufacturing the dielectric capacitor and the semiconductor memory device of the present invention, S having a relatively low formation temperature is used.
It can be applied to a TO film, a BSTO film, a PZT film, and the like, as well as an SBT film having a high formation temperature, and since the step in the capacitor region can be suppressed to a low level, it is extremely advantageous for high integration of elements.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view of a capacitor and a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 shows an equivalent circuit of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a partial cross-sectional view of a capacitor and a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a partial cross sectional view for illustrating the method for manufacturing the capacitor and the semiconductor memory device according to the third embodiment of the present invention.

FIG. 5 is a partial cross-sectional view for explaining the method for manufacturing the capacitor and the semiconductor memory device according to the third embodiment of the present invention, following FIG.

FIG. 6 is a partial cross sectional view for illustrating the method for manufacturing the capacitor and the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 7 is a partial cross-sectional view for explaining the method for manufacturing the capacitor and the semiconductor memory device according to the fourth embodiment of the present invention, following FIG. 6;

FIG. 8 is a schematic sectional view showing a configuration of a conventional semiconductor memory device.

[Explanation of symbols]

10 ... Semiconductor memory device, 11 ... Semiconductor substrate, 12 ... Element isolation region, 13 ... Interlayer insulating layer, 14 ... Contact hole, 15 ... Contact plug, 16 ... Interlayer insulating layer, 1
Reference numeral 7 ... Opening, 18 ... Interlayer insulating layer, 19 ... Bit contact hole, 21 ... Select transistor, 22 ... Gate oxide film, 23 ... Gate electrode, 24, 25 ... Source / drain region, 26 ... Side wall insulating layer, 31 ... Capacitor, 32 ... Lower electrode, 33 ... Dielectric layer, 34 ... Upper electrode layer, 41 ... Plate line, 41 ... Bit line, 51 ... Refractory metal boride layer, 52 ... Diffusion barrier layer, 53 ... Silicide Film, 110 ... Semiconductor memory device, 111 ... Semiconductor substrate, 112 ... Element isolation region, 113 ... Interlayer insulating layer, 11
4 ... Contact hole, 115 ... Contact plug, 116 ... Interlayer insulating layer, 118 ... Interlayer insulating layer, 119
... bit contact hole, 121 ... selection transistor, 122 ... gate oxide film, 123 ... gate electrode, 12
4, 125 ... Source / drain regions, 126 ... Sides
Wall insulating layer, 131 ... Capacitor, 132 ... Lower electrode, 133 ... Dielectric layer, 134 ... Upper electrode layer, 141 ...
Plate line, 141 ... Bit line, α ... Profile angle.

Claims (45)

[Claims] 1. A first electrode film, a second electrode film, and a dielectric thin film sandwiched between the first and second electrode films, wherein the first electrode film is diffusion barrier. A capacitor comprising a layer and a boride layer of a refractory metal. 2. The capacitor according to claim 1, wherein the first electrode film is formed by sequentially stacking a diffusion prevention layer and a boride layer of a refractory metal from the side of the dielectric film. 3. The capacitor according to claim 1, wherein the refractory metal boride layer has conductivity. 4. The capacitor according to claim 1, wherein the refractory metal boride layer has a barrier property against silicon. 5. The boride layer of the refractory metal is formed of Cr, H
f, La, Mo, Nb, Ta, Ti, V, W, Y, Zr
The capacitor of claim 1 including at least one boride of 6. The diffusion barrier layer is made of Ir, Ru, Rh, R.
at least one of e and Os, or I
The capacitor according to claim 1, comprising at least one oxide of r, Ru, Rh, Re, and Os. 7. The capacitor according to claim 1, wherein the dielectric film has an ABO ₃ type perovskite structure. 8. The dielectric film is made of Ta ₂ O ₅ , SrTiO 3.
₃ , (Ba, Sr) TiO ₃ , Pb (Zr, Ti)
O ₃ , (Pb, La) (Zr, Ti) O ₃ , PbTiO
The capacitor according to claim 7, comprising at least one of ₃ , ₃ , BaTiO ₃ , LiNbO ₃ , LiTaO ₃ , and YMnO ₃ . 9. The capacitor according to claim 1, wherein the dielectric film contains a bismuth-based layered perovskite structure compound. 10. The dielectric thin film is SrBi._TwoTa_TwoO
₉, SrBi_TwoNb_TwoO₉, SrBi _Two(Ta, Nb)
_TwoO₉, Bi_FourTi_ThreeO₁₂, SrBi_FourTi
_FourO₁₅, SrBi_Four(Ti, Zr)_FourO₁₅, Bi_Three
TiNbO₉, Bi_ThreeTiTaO₉, BaBi_TwoTa_Two
O₉, BaBi_TwoNb_TwoO₉At least one of
The capacitor of claim 9 including. 11. A semiconductor memory device including a selection transistor and a capacitor electrically connected to one impurity diffusion region of the selection transistor, wherein the capacitor is electrically connected to one impurity diffusion region of the selection transistor. A lower electrode film connected to the upper electrode film, an upper electrode film above the lower electrode, and a dielectric film sandwiched between the lower electrode film and the upper electrode film. A semiconductor memory device including a melting point metal boride layer. 12. The semiconductor memory device according to claim 11, wherein the lower electrode film is formed by sequentially stacking a diffusion prevention layer and a boride layer of a refractory metal from the dielectric film side. 13. The semiconductor memory device according to claim 11, wherein the refractory metal boride layer has conductivity. 14. The semiconductor memory device according to claim 11, wherein the refractory metal boride layer has a barrier property against silicon. 15. The refractory metal boride layer comprises Cr,
Hf, La, Mo, Nb, Ta, Ti, V, W, Y, Z
The semiconductor memory device according to claim 11, which contains at least one boride of r. 16. The diffusion preventing layer comprises Ir, Ru, Rh,
At least one of Re and Os is included, or
The semiconductor memory device according to claim 11, comprising at least one oxide selected from Ir, Ru, Rh, Re, and Os. 17. The semiconductor memory device according to claim 11, wherein the dielectric film has an ABO ₃ type perovskite structure. 18. The dielectric film is made of Ta ₂ O ₅ or SrTi.
O ₃ , (Ba, Sr) TiO ₃ , Pb (Zr, Ti) O
₃ , (Pb, La) (Zr, Ti) O ₃ , PbTi
18. The semiconductor memory device according to claim 17, comprising at least one of O ₃ , BaTiO ₃ , LiNbO ₃ , LiTaO ₃ , and YMnO ₃ . 19. The semiconductor memory device according to claim 11, wherein said dielectric film contains a bismuth-based layered perovskite structure compound. 20. The dielectric thin film is SrBi._TwoTa_TwoO
₉, SrBi_TwoNb_TwoO₉, SrBi _Two(Ta, Nb)
_TwoO₉, Bi_FourTi_ThreeO₁₂, SrBi_FourTi
_FourO₁₅, SrBi_Four(Ti, Zr)_FourO₁₅, Bi_Three
TiNbO₉, Bi_ThreeTiTaO₉, BaBi_TwoTa_Two
O₉, BaBi_TwoNb_TwoO₉At least one of
20. The semiconductor memory device according to claim 19, which includes. 21. The semiconductor memory device according to claim 11, further comprising a conductive contact plug, one of which reaches an impurity diffusion region of one of said selection transistors and the other of which is connected to a lower electrode of said capacitor. . 22. The semiconductor memory device according to claim 21, wherein the conductive contact plug includes impurity-implanted polysilicon. 23. The semiconductor memory device according to claim 22, wherein a silicide film is formed on an end surface of the conductive contact plug which is in contact with the lower electrode of the capacitor. 24. A step of forming a first electrode film, a step of forming a second electrode film, and a step of forming a dielectric thin film sandwiched between the first electrode film and the second electrode film. And a method for manufacturing a capacitor, wherein the first electrode film includes a diffusion barrier layer and a boride layer of a refractory metal. 25. In the step of forming the first electrode film, the diffusion preventing layer and the boride layer of the refractory metal are provided from the side of the dielectric film, the diffusion preventing layer and the boride of the refractory metal. The method of manufacturing a capacitor according to claim 24, wherein the capacitors are laminated in order of layers. 26. The method of manufacturing a capacitor according to claim 24, wherein the refractory metal boride layer has conductivity. 27. The method of manufacturing a capacitor according to claim 24, wherein the refractory metal boride layer has a barrier property against silicon. 28. The refractory metal boride layer is Cr,
Hf, La, Mo, Nb, Ta, Ti, V, W, Y, Z
25. The method of manufacturing a capacitor according to claim 24, wherein at least one boride of r is included. 29. The diffusion preventing layer comprises Ir, Ru, Rh,
At least one of Re and Os is included, or
The method of manufacturing a capacitor according to claim 24, further comprising at least one oxide selected from Ir, Ru, Rh, Re, and Os. 30. The method of manufacturing a capacitor according to claim 25, wherein the dielectric film has an ABO ₃ type perovskite structure. 31. The dielectric film is made of Ta ₂ O ₅ or SrTi.
O ₃ , (Ba, Sr) TiO ₃ , Pb (Zr, Ti) O
₃ , (Pb, La) (Zr, Ti) O ₃ , PbTi
The method of manufacturing a capacitor according to claim 30, comprising at least one of O ₃ , BaTiO ₃ , LiNbO ₃ , LiTaO ₃ , and YMnO ₃ . 32. The method of manufacturing a capacitor according to claim 24, wherein the dielectric film contains a bismuth-based layered perovskite structure compound. 33. The dielectric thin film is SrBi._TwoTa_TwoO
₉, SrBi_TwoNb_TwoO₉, SrBi _Two(Ta, Nb)
_TwoO₉, Bi_FourTi_ThreeO₁₂, SrBi_FourTi
_FourO₁₅, SrBi_Four(Ti, Zr)_FourO₁₅, Bi_Three
TiNbO₉, Bi_ThreeTiTaO₉, BaBi_TwoTa_Two
O₉, BaBi_TwoNb_TwoO₉At least one of
33. A method of making a capacitor according to claim 32 including. 34. A method of manufacturing a semiconductor memory device, comprising: a select transistor; and a capacitor connected to one impurity diffusion region of the select transistor, the process comprising forming the select transistor in a predetermined region of a semiconductor substrate. Forming an insulating film on a semiconductor substrate including the selection transistor; forming a conductive contact plug reaching the one impurity diffusion region of the selection transistor in the insulating film; A step of forming a lower electrode film on the conductive contact plug, and a step of forming a dielectric thin film on the lower electrode film. And a step of forming an upper electrode film on the dielectric thin film, wherein the lower electrode film is a diffusion barrier. The method of manufacturing a semiconductor memory device comprising a layer, a boride layer of a refractory metal. 35. In the step of forming the lower electrode film, the diffusion barrier layer and the refractory metal boride layer are formed.
The method of manufacturing a semiconductor memory device according to claim 34, wherein a diffusion prevention layer and a boride layer of a refractory metal are stacked in this order from the side of the dielectric film. 36. The method of manufacturing a semiconductor memory device according to claim 34, wherein the refractory metal boride layer has conductivity. 37. The method of manufacturing a semiconductor memory device according to claim 34, wherein the refractory metal boride layer has a barrier property against silicon. 38. The boride layer of the refractory metal is Cr,
Hf, La, Mo, Nb, Ta, Ti, V, W, Y, Z
The method of manufacturing a semiconductor memory device according to claim 34, wherein at least one boride of r is included. 39. The diffusion preventing layer comprises Ir, Ru, Rh,
At least one of Re and Os is included, or
The method of manufacturing a semiconductor memory device according to claim 34, comprising at least one oxide of Ir, Ru, Rh, Re, and Os. 40. The method of manufacturing a semiconductor memory device according to claim 34, wherein the dielectric film has an ABO ₃ type perovskite structure. 41. The dielectric film is made of Ta ₂ O ₅ or SrTi.
O ₃ , (Ba, Sr) TiO ₃ , Pb (Zr, Ti) O
₃ , (Pb, La) (Zr, Ti) O ₃ , PbTi
The method of manufacturing a semiconductor memory device according to claim 40, comprising at least one of O ₃ , BaTiO ₃ , LiNbO ₃ , LiTaO ₃ , and YMnO ₃ . 42. The method of manufacturing a semiconductor memory device according to claim 34, wherein the dielectric film contains a bismuth-based layered perovskite structure compound. 43. The dielectric thin film is SrBi._TwoTa_TwoO
₉, SrBi_TwoNb_TwoO₉, SrBi _Two(Ta, Nb)
_TwoO₉, Bi_FourTi_ThreeO₁₂, SrBi_FourTi
_FourO₁₅, SrBi_Four(Ti, Zr)_FourO₁₅, Bi_Three
TiNbO₉, Bi_ThreeTiTaO₉, BaBi_TwoTa_Two
O₉, BaBi_TwoNb_TwoO₉At least one of
43. A method of manufacturing a semiconductor memory device according to claim 42, including:
Law. 44. The method of manufacturing a semiconductor memory device according to claim 34, wherein the conductive contact plug includes impurity-implanted polysilicon. 45. The method of manufacturing a semiconductor memory device according to claim 44, further comprising the step of forming a silicide film on an end face of said conductive contact plug which is in contact with a lower electrode of said capacitor.