JP4498198B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device used for a flash memory using an SOI (Silicon On Insulator) substrate.

  As a nonvolatile semiconductor memory device, a NAND flash memory capable of batch erasing is often used. The NAND flash memory has problems such as a parasitic capacitance in an element isolation region between memory cell transistors and a variation in gate threshold voltage due to an influence of a parasitic capacitance between a wiring and a substrate.

  In order to reduce variations in gate threshold voltage due to the parasitic capacitance in the element isolation region and the parasitic capacitance between the wiring and the substrate, the semiconductor layer (SOI layer) disposed on the buried insulating layer (BOX layer) is an active layer. A NAND flash memory using the SOI technology is being studied (for example, see Patent Document 1). According to the NAND flash memory using the SOI technology, the memory cell transistors adjacent in the row direction are separated from each other by the element isolation insulating film embedded up to the embedded insulating layer, so that the parasitic capacitance in the element isolation region can be reduced. In addition, since the SOI layer is formed on the buried insulating layer, the parasitic capacitance between the wiring and the substrate can be reduced, and variations in the gate threshold voltage can be reduced. However, with the miniaturization of memory cell transistors, even in a NAND flash memory using SOI technology, the distance between the source and drain regions of the memory cell transistors is narrowed, and the influence of the short channel effect is increasing.

  Therefore, it has been studied to use a depletion type (D type) MIS transistor as a memory cell transistor in a NAND flash memory using SOI technology. If a depletion type MIS transistor is used, the channel is depleted in a state where electrons are accumulated in the floating gate electrode, so that the influence of the short channel effect can be reduced.

  By the way, in the NAND flash memory, the batch erase operation is a very important function. In a NAND flash memory using a bulk substrate, when a positive voltage (for example, 18 V) is applied to a p-type well, a bit line, and a source line, the potential of the channel region portion of the memory cell becomes the same potential. At this time, a strong electric field is generated between the floating gate electrode and the channel region, and electrons stored in the floating gate electrode escape to the channel region side due to a tunneling phenomenon, whereby the memory signal is collectively erased.

On the other hand, in the NAND flash memory with the SOI structure, since there is no electrode corresponding to the p-type well in the case of the bulk substrate, the same batch erasure as in the case of the bulk substrate cannot be performed. Even in the case of the SOI structure, even if a positive voltage (for example, 18V) is applied to the bit line and the source line, the n ⁺ type semiconductor region connected to the bit line or the source line and the p-type of the selection gate transistor are used. Between the channel regions is a reverse bias of the pn junction. For this reason, the positive voltage applied to the bit line or the source line may not reach the channel region of the memory cell. That is, in the NAND flash memory having the SOI structure, it is difficult to perform a batch erase because a strong electric field cannot be generated between the channel region of the memory cell and the floating gate electrode.
JP 2000-174241 A

  An object of the present invention is to provide a nonvolatile semiconductor memory device capable of realizing batch erase of memory signals at high speed in a NAND flash memory having an SOI structure.

According to one aspect of the present invention, (b) a plurality of memory cell transistors having a first conductivity type channel region in contact with a buried insulating layer and arranged in a column direction; A first select gate transistor having a second conductivity type channel region adjacent to one end and in contact with the buried insulating layer; and (c) electrically connected to the second conductivity type channel region and higher than the channel region. A source line contact region of a second conductivity type having an impurity density and (d) a source electrically connected to the first conductivity type source region of the first select gate transistor and electrically connected to the source line contact region and a line contact plug, when collective erasure of a plurality of memory cell transistors, each of the channel regions of the plurality of memory cell transistors, a source region and a drain territory NAND type in which a hole inversion layer or an electron inversion layer is formed at the buried insulating layer side interface, and a hole accumulation layer or an electron accumulation layer is formed at the buried insulating layer side interface of the channel region of the first select gate transistor nonvolatile semiconductor memory device is provided for.

  According to the present invention, it is possible to provide a nonvolatile semiconductor memory device capable of realizing batch erase of memory signals at high speed in a NAND flash memory having an SOI structure.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings. Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention includes the material, shape, structure, The layout is not specified as follows. The technical idea of the present invention can be variously modified within the scope of the claims. In the embodiment described below, the “first conductivity type” and the “second conductivity type” are opposite conductivity types. That is, if the first conductivity type is n-type, the second conductivity type is p-type. If the first conductivity type is p-type, the second conductivity type is n-type. In the following description, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type.

As shown in FIG. 1, the nonvolatile semiconductor memory device according to the embodiment of the present invention includes first conductivity type (n ⁻ type) channel regions 411 to 41 n in contact with a buried insulating layer (BOX layer) 2. a plurality of memory cell transistors MT ₁₁ to MT _1n arranged in the row direction, adjacent one end of the array of memory cell transistors MT ₁₁ to MT _1n, second conductivity type in contact with the buried insulating layer 2 (p ^-) The first select gate transistor STS1 including the second channel region 42 and the second conductivity type (p ⁻ ) channel region 42 are electrically connected to each other, and the second conductivity type (p ^{+ having a} higher impurity density than the channel region 42). and source line contact regions 46 of the mold), first a first conductivity type of the selection gate transistor STS1 (n ⁺ -type) source region 43 and electrically connected to the, and source line contact regions 46 and electrically contacts A source line contact plug 18 that is adjacent to the other end of the array of memory cell transistors MT ₁₁ to MT _1n, a second conductivity type (p ^-) and a second select gate transistor STD1 with a channel region 44 of the second The second conductivity type (p ⁺ -type) bit line contact region 47 having a higher impurity density than the channel region 44 and electrically connected to the channel region 44 of the select gate transistor STD1 and the second select gate transistor STD1 The NAND flash memory includes a bit line contact plug 17 electrically connected to the drain region 45 of the first conductivity type (n ⁺ type) and electrically connected to the bit line contact region 47.

FIG. 1 shows a cross-sectional view when viewed along the AA section along the column direction shown in FIG. In FIG. 1, for example, n (n is an integer) memory cell transistors MT _{11 to} MT _1n are arranged adjacent to each other in the column direction. The memory cell transistors MT _{11 to} MT _1n have a stack gate structure in which the floating gate electrode 13 and the control gate electrode 15 are stacked, and are, for example, depletion type MIS transistors. Each of the memory cell transistors MT ₁₁ to MT _1n, and the source and drain regions to share with each other and the memory cell transistors MT ₁₁ to MT _1n adjacent in the column direction 421~42 (n + 1), the source and drain regions 421-42 (n + 1 The floating gate electrode 13 is disposed on the channel regions 411 to 41n sandwiched between them via the gate insulating film (tunnel oxide film) 12, and the inter-electrode insulating film 14 is disposed on the floating gate electrode 13. Each control gate electrode 15 is provided. “Shared with each other” means that between adjacent memory cell transistors MT _{11 to} MT _1n , one drain region is a common region functioning as the other source region.

In the plurality of memory cell transistors MT _{11 to} MT _1n arranged in one column direction in the matrix, for example, the drain region 422 of one memory cell transistor MT ₁₁ is the source region of another adjacent memory cell transistor MT ₁₂ . 422, source regions 421 to 42n, channel regions 411 to 41n and drain regions 422 to 42 (n + 1) are successively extended in one column direction, and corresponding source regions of memory cell transistors in other column directions, A plurality of channel regions and drain regions are arranged in parallel so as to be separated from each other.

As the gate insulating film 12, besides silicon oxide film (SiO ₂ film), silicon nitride (Si ₃ N ₄ ), tantalum oxide (Ta ₂ O ₅ ), titanium oxide (TiO ₂ ), alumina (Al ₂ O) ₃ ) and materials such as zirconium oxide (ZrO ₂ ) can be used.

Examples of the material for the interelectrode insulating film 14 include Si ₃ N ₄ , Ta ₂ O ₅ , TiO ₂ , Al ₂ O ₃ , ZrO ₂ , oxide / nitride / oxide (ONO), phosphorous glass (PSG), and boron phosphorous glass. Organic resins such as (BPSG), silicon nitride oxide (SiON), barium titanate (BaTiO ₃ ), silicon oxyfluoride (SiO _x F _y ), and polyimide can be used.

As a material for the buried insulating layer 2 that realizes the SOI structure, SiO ₂ , sapphire (Al ₂ O ₃ ), or the like can be used. Further, by applying SON (Silicon On Nothing) technology, the embedded insulating layer 2 may be hollow (air), and the hollow functions as an insulating layer. As a material of the semiconductor layer (SOI layer) 3, single crystal silicon, silicon germanium (SiGe), or the like can be used. As a material of the semiconductor layer (SOI layer) 3 that is an active layer, single crystal silicon, silicon germanium (SiGe), or the like can be used. The thickness of the buried insulating layer 2 is about 40 nm, for example, and the thickness of the SOI layer 3 is about 30 nm, for example. A support substrate 1 made of silicon (Si) or the like is disposed under the buried insulating layer 2.

The first selection gate transistor STS1 and the second selection gate transistor STD1 are, for example, enhancement type MIS transistors. First select gate transistor STS1 is an n ⁺ -type drain region 421 to be the source region 421 of the memory cell transistors MT ₁₁ and the common region located at one end in the column direction of the array, is arranged adjacent to the drain region 421 and the second conductivity type ^- a channel region 42 of the (p-type), an n ⁺ -type source region 43 located adjacent to the channel region 42, which is disposed through a gate insulating film 12 on the channel region 42 Select gate electrodes 13a and 15a are provided. The drain region 421, the channel region 42 and the source region 43 are disposed in the SOI layer 3. A source line contact plug 18 is disposed on the source region 43 adjacent to the first select gate transistor STS1.

  Here, a source line contact region 46 is disposed between the source region 43 of the first select gate transistor STS1 and the buried insulating layer 2. The source line contact region 46 is electrically connected to the channel region 42, and the source line contact plug 18 is electrically connected to the source line contact region 46 through the source region 43.

On the other hand, the second select gate transistor STD1 includes an n ⁺ -type source region 42 (n + 1) which is a common region with the drain region 42 (n + 1) of the memory cell transistor MT _1n located at the other end of the column-direction array, A p ⁻ type channel region 44 disposed adjacent to the source region 42 (n + 1), an n ⁺ type drain region 45 disposed adjacent to the channel region 44, and the gate insulating film 12 on the channel region 44. And select gate electrodes 13b and 15b arranged via the electrode. The source region 42 (n + 1), the channel region 44 and the drain region 45 are arranged in the SOI layer 3. A bit line contact plug 17 is disposed on the drain region 45 adjacent to the second select gate transistor STD1.

  Here, a bit line contact region 47 is disposed between the drain region 45 of the second select gate transistor STD 1 and the buried insulating layer 2. The bit line contact region 47 is electrically connected to the channel region 44, and the bit line contact plug 17 is electrically connected to the bit line contact region 47 through the drain region 45.

The p-type impurity density of the source line contact region 46 and the bit line contact region 47 is, for example, about 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ . The p-type impurity density of the channel regions 42 and 44 of the first and second select gate transistors STS1 and STD1 is, for example, about 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ . The n-type impurity density of the source region 43 of the first select gate transistor STS1 and the drain region 45 of the second select gate transistor STD1 is about 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ .

As shown in FIG. 2, in the column direction of the cell array of the nonvolatile semiconductor memory device, the common source line SL connected to the source line contact plug 18 and the selection gate electrode of the first selection gate transistor STS1 shown in FIG. 13a, 15a are connected to selection gate lines SGS, the memory cell transistors MT ₁₁ respectively of the control gate electrode 15 is connected to the word line WL1~WLn of to MT _1n, the second selection gate electrodes 13b of the select gate transistor STD1, Selection gate lines SGD connected to 15b are arranged. In the row direction, bit lines BL1 and BL2 connected to the bit line contact plug 17 are arranged.

FIG. 3 shows a cross-sectional view when viewed along the BB cut surface along the row direction shown in FIG. As shown in FIG. 3, an element isolation insulating film 6 is buried between the floating gate electrode 13 and the channel region 411 of the memory cell transistors MT ₁₁ and MT ₂₁ adjacent in the row direction. That is, the memory cell transistors MT ₁₁ and MT ₂₁ adjacent in the row direction are completely isolated from each other. In addition, a peripheral circuit of the cell array disposed on the semiconductor substrate is further provided outside the cell array composed of a plurality of memory cell transistors.

FIG. 4 shows an equivalent circuit of the nonvolatile semiconductor memory device shown in FIGS. As shown in FIG. 4, for example, m × n (m is an integer) memory cell transistors MT _{11 to} MT _1n , MT _{21 to} MT _2n ,..., MT _{m1 to} MT _mn are included in the cell array 100. . In the cell array 100, a plurality of memory cell transistors MT ₁₁ to MT _1n as a group in a column _{direction, MT 21 ~MT 2n, ·····,} MT m1 ~MT mn are arranged, and in the group memory cell transistors MT _{11 ~MT 1n, MT 21 ~MT 2n,} ·····, by MT _m1 to MT _mn are arranged in a row direction, a plurality of memory cell transistors _{MT 11 ~MT 1n, MT 21 ~MT} 2n, ·· ..., MT _{m1 to} MT _mn are arranged in a matrix.

The memory cell transistors MT _{11 to} MT _1n and the first and second select gate transistors STS 1 and STD ₁ are connected in series to constitute a cell unit 111. A first selection gate transistor for selecting the memory cell transistors MT _{11 to} MT _1n is provided in the source region of the memory cell transistor MT ₁₁ located at the end of the array of the group of memory cell transistors MT _{11 to} MT _1n connected in series. The drain region of STS1 is connected. The drain region of the memory cell transistor MT _1n located at the end of the series-connected group of memory cell transistors MT ₁₁ to MT _1n sequence, the second select gate transistor for selecting a memory cell transistor MT ₁₁ to MT _1n The source region of STD1 is connected. First select gate transistor STS2～STSm, the memory cell transistors _{MT 21 ~MT 2n, ·····, MT} m1 ~MT mn, and the second select gate transistor STD2~STDm also respectively connected in series cell unit 112 , ..., 11m.

A common source line SL is connected to the sources of the first select gate transistors STS1 to STSm. A source line driver 103 that supplies a voltage to the common source line SL is connected to the common source line SL. A common selection gate line SGS for the first selection gate transistors STS1 to STSm, a common selection gate line SGD for the second selection gate transistors STD1 to STDm, and memory cell transistors MT ₁₁ , MT ₂₁ ,. , MT _m1, the memory cell transistors _{MT 12, MT 22, ·····,} MT m2, ····· memory cell transistor MT _1n, MT _2n, ·····, respective word lines of the MT _mn WL1 ˜WLn are connected to the row decoder 101. The row decoder 101 obtains a row address decode signal by decoding the row address signal and selectively supplies an operating voltage to the word lines WL1 to WLn and the select gate lines SGS and SGD. Bit lines BL1 to BLm are connected to the drains of the second select gate transistors STD1 to STDm, respectively. A sense amplifier 102 and a column decoder 104 are connected to the bit lines BL1 to BLm. The column decoder 104 obtains a column address decode signal by decoding the column address signal, and selects one of the bit lines BL1 to BLm based on the column address decode signal. The sense amplifier 102 amplifies the memory signal read from the memory cell transistor selected by the row decoder 101 and the column decoder 104.

Next, each control method of the erase operation, the write operation, and the read operation in the nonvolatile semiconductor memory device according to the embodiment of the present invention will be described. First, an example in which the memory cell transistors MT _{11 to} MT _1n shown in FIG. 1 are collectively erased will be described as a method for controlling the erase operation.

During the batch erase operation, a voltage V _Suberase (for example, −5 V) of 0 V or less is applied to the support substrate 1 as shown at times T _{11 to} T ₁₂ in FIG. A voltage V _sgerase (for example, 18V) is applied to the selection gate lines SGS and SGD, and a voltage V _erase (for example, 18V) is applied to all the bit lines BL1 to BLm and the common source line SL. A voltage V _WLerase (for example, 2 V) is applied to all the word lines WL1 to _WLn .

As shown in FIG. 6, the voltage V _erase (for example, 18 V) transferred from the common source line SL passes through the source line contact region 46 through the source line contact plug 18 and the p of the first selection gate transistor STS1. ^- flow type to the channel region 42. On the other hand, the voltage V _erase (for example, 18V) transferred from the bit line BL1 passes through the bit line contact region 47 via the bit line contact plug 17 and passes through each p ⁻ type channel of the second select gate transistor STD1. Flow to region 44. As a result, the first and second select each of the gate transistor STS1, STD1 p ^- -type hole accumulating layer 48a to the buried insulating layer 2 side interface of the channel region 42, 44, 48b are formed, the memory cell transistors A hole inversion layer 49 is formed at the buried insulating layer 2 side interface between the source and drain regions 421 to 42 (n + 1) of the MT _{11 to} MT _1n and the channel regions 411 to 41n. By this hole inversion layer 49, the voltage V _erase (for example, 18V) from the bit line BL1 and the common source line SL passes through the buried insulating layer 2 side interface of the SOI layer 3 to the central part of the memory cell transistors MT _{11 to} MT _1n. Reportedly. For this reason, an electric field is generated between the floating gate electrode 13 and the SOI layer 3, and electrons in the floating gate electrode 13 are extracted to the SOI layer 3 side. As a result, the memory cell transistors MT ₁₁ to MT _1n are collectively erased.

FIG. 43 shows a comparative example of an SOI structure nonvolatile semiconductor memory device. As shown in FIG. 43, when the source line contact region 46 and the bit line contact region 47 shown in FIG. 6 are not provided, the n ⁺ type source region 43 and the first selection gate connected to the common source line SL. Between the channel region 42 of the transistor STS1 and between the n ⁺ type drain region 45 connected to the bit line BL1 and the p ⁻ type channel region 44 of the second select gate transistor STD1, a pn junction reverse bias is applied. It becomes. For this reason, the voltage V _erase (for example, 18 V) applied to the bit line BL1 or the common source line SL may not reach the channel regions 411 to 41n of the memory cell transistors MT _{11 to} MT _1n . Therefore, holes need to be supplied by generation of electron-hole pairs or leakage current.

  On the other hand, according to the embodiment of the present invention, the source line contact region 46 and the bit line contact region 47 shown in FIG. 6 function as a hole supply source. The hole accumulation layers 48a and 48b and the hole inversion layer 49 can be formed at high speed without depending on the leakage current. Note that the applied voltage described here is an example, and the bias condition at the time of batch erase can be arbitrarily set as long as the hole inversion layer 49 is formed at the buried insulating layer 2 side interface of the SOI layer 3. .

  7 and 8 show the results of verifying the operation of the NAND flash memory using a simulator (device simulator). FIG. 7 shows that in the batch erase operation, 18V is applied to each of the bit line, the source line, and the select gate transistor, 10V is applied to the word line and fixed, and 0V is applied to the support substrate. It is the result which showed the hole concentration distribution after 1 ms. The hole concentration is high at the buried insulating layer side interface of the SOI layer in the select gate transistor region and the buried insulating layer side interface of the SOI layer in the memory cell transistor region, and the buried insulating layer side of the SOI layer in the select gate transistor region It can be seen that a hole accumulation layer is formed at the interface, and a hole inversion layer is formed at the buried insulating layer side interface of the SOI layer in the memory cell transistor region.

  FIG. 8 shows the potential (pseudo Fermi level) distribution in the memory cell transistor region in the same state as FIG. Since the voltage (for example, 18V) applied to the bit line and the source line reaches the center of the NAND string, it can be understood that the batch erase operation can be realized.

When the verify operation is executed after the erase operation, the voltage V _WLverify (for example, 2 V) is applied to all the word lines WL1 to _WLn and 0 or less to the support substrate 1 as shown at times T _{12 to} T ₁₃ in FIG. Voltage V _Subverify (for example, −5 V) is applied to read the potential of the bit line BL1.

Next, an example of a method for controlling the write operation of the nonvolatile semiconductor memory device according to the embodiment of the present invention will be described. As shown at times T _{21 to} T ₂₂ in FIG. 9, the selection gate lines SGS and SGD have a voltage V _BLinhibit (for example, 3V), the selection bit line BL1 has a voltage V _BLpgm (for example, 0V), and the unselected word lines WL2 to A voltage V _pass (for example, 10 V) is applied to WLn, and a voltage V _pgm (for example, 18 V) is applied to the selected word line WL1. 0 V is applied to the support substrate 1. In the memory cell transistor MT ₁₁ , since the voltage V _pgm (for example, 18 V) is applied to the control gate electrode 15 shown in FIG. 1, a high electric field is generated between the floating gate electrode 13 and the channel region 411 immediately below the floating gate electrode 13. As a result, electrons are injected into the floating gate electrode 13 through the gate insulating film 12. When electrons accumulate in the floating gate electrode 13, the threshold voltage of the selected memory cell transistor MT ₁₁ is increased by ΔV from a negative threshold voltage, the memory signal is written.

Incidentally, when performing a verify operation after the write operation, as shown in time T ₂₂ through T ₂₃ in FIG. 9, the voltage _V sgread (e.g. 3V) select gate line SGS, the SGD, unselected word lines WL2~WLn Is applied with a voltage V _read (for example, 4.5 V), a voltage V _sence (for example, 0 V) is applied to the selected word line WL1, and a voltage V _Subverify (for example, −5 V) of less than 0 V is applied to the support substrate 1, respectively. Read the potential of BL1.

  Next, an example of a control method of the write operation and the verify operation in the nonvolatile semiconductor memory device according to the embodiment of the present invention will be described with reference to the flowchart of FIG.

In step S1, the write operation by using the operation voltages shown in time T ₂₁ through T ₂₂ in Figure 10. In step S2, a verify operation is performed. In the verify operation, reads out the potential of the selected bit line BL1 with the operating voltage shown in time T ₂₂ through T ₂₃ in FIG. 10, it is determined whether the write successfully. If it is determined that the writing is not normal, the process proceeds to step S3. On the other hand, if it is determined that the writing is normal, the process proceeds to step S4. In step S3, the memory cell transistors MT ₁₁ not performed normally written, writing operation again. In the write operation again, as shown at times T _{23 to} T ₂₄ in FIG. 10, a voltage (V _pgm + ΔV _pgm ) obtained by boosting the applied voltage V _pgm by ΔV _pgm is applied to the selected word line WL1. Thereafter, the procedure returns to step S2. In step S4, by applying a voltage V _BLinhibit (e.g. 3V) to the bit line BL1 as shown in time T ₂₃ through T ₂₄ in Figure 10 is write-protected, and terminates the write.

Next, an example of a method for controlling the read operation of the nonvolatile semiconductor memory device according to the embodiment of the present invention will be described. For example, when reading the memory signal of the memory cell transistor MT ₁₁ , a substrate voltage V _Subverify (eg, −5 V) of less than 0 V is applied to the support substrate 1 as shown at times T _{22 to} T ₂₃ in FIG. and the selected bit line BL1 and applied after floating the precharge voltage V _BLread (e.g. 0.5~1.1V). At this time, in order to prevent the interference between the adjacent bit lines (between BL and BL), the odd bit lines BL1 and the even bit lines BL2 are alternately read, so that the non-selected BL2 adjacent to the selected bit line BL1 In some cases, the precharge voltage V _BLread is not applied. Next, the voltage V _sgread (for example, 2.5 V) is applied to the selection gate lines SGS and SGD, the voltage V _read (for example, 4.5 V) is applied to the unselected word lines WL2 to WLn, and the determination voltage V _sense (for the selected word line WL1). For example, 0 V) is applied. The application time (TR) of the read potential is desirably set to an appropriate value in consideration of noise such as a BL-BL parasitic capacitance and a rise in the reference potential due to the cell current.

In the memory cell transistor MT ₁₁ , when no electrons are accumulated in the floating gate electrode 13, the selected memory cell transistor MT ₁₁ is turned on, a cell current flows, and the potential of the selected bit line BL 1 drops. Meanwhile, when the electrons in the floating gate electrode 13 are accumulated, the memory cell transistor MT ₁₁ is therefore turned off, the potential of the selected bit line BL1 does not flow cell current holds the precharge voltage V _BLread. After the read potential is applied, the potential of the selected bit line BL1 is compared with the determination reference potential. If the potential of the selected bit line BL1 is higher than the determination reference potential, the write state is determined. On the other hand, if the potential of the selected bit line BL1 is lower than the determination reference potential, the erase state is determined.

According to the nonvolatile semiconductor memory device of the embodiment of the present invention, it is possible to perform the same batch erase operation as when a bulk substrate is used, regardless of the SOI structure. That is, by p ⁺ -type source line contact regions 46 and the bit line contact region 47 as shown in FIG. 6 is a hole supply source, a hole inversion layer 49 to the buried insulating layer 2 side interface of the SOI layer 3 Is formed at a high speed, and the memory can be erased at a high speed.

  Next, an example of a method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention will be described. Here, FIG. 11 (a), FIG. 12 (a),..., FIG. 28 (a) show process cross-sectional views in the column direction as viewed along the AA direction cut surface of the cell array shown in FIG. FIG. 11 (b), FIG. 12 (b),..., FIG. 28 (b) show process sectional views in the row direction as viewed along the cut surface in the BB direction. It should be noted that the method for manufacturing the nonvolatile semiconductor memory device shown in FIGS. 11A to 28B is merely an example, and can be realized by various other manufacturing methods including this modification. is there.

  (A) First, a support substrate 1 made of Si or the like is prepared, and oxygen is ion-implanted into the support substrate 1 by, for example, a SIMOX method to perform heat treatment, as shown in FIGS. 11A and 11B. A buried insulating layer 2 is formed inside the support substrate 1, and a semiconductor layer (SOI layer) 3 is formed on the buried insulating layer 2. Alternatively, the SOI layer 3 may be formed by forming the buried insulating layer 2 on one of the two wafers by bonding and performing heat treatment by bonding them together, and flatly grinding one of the wafers to form a thin film. good.

(B) Next, a resist film 20 is applied on the SOI layer 3, and the resist film 20 is patterned using a lithography technique as shown in FIGS. Subsequently, a p-type impurity such as boron ( ¹¹ B ⁺ ) is ion-implanted using the patterned resist film 20 as a mask. The remaining resist film 20 is removed using a registry mover or the like. Thereafter, heat treatment is performed to activate the impurity ions implanted into the SOI layer 3, and p ⁻ type impurity diffusion layers 40a and 40b are formed in the select gate transistor formation region. Subsequently, a resist film 21 is applied on the SOI layer 3, and the resist film 21 is patterned as shown in FIGS. 13A and 13B by using a lithography technique. Thereafter, n-type impurities such as phosphorus ( ³¹ P ⁺ ) or arsenic ( ⁷⁵ As ⁺ ) are ion-implanted using the patterned resist film 21 as a mask.

(C) Next, as shown in FIGS. 14A and 14B, a gate insulating film (tunnel oxide film) 12 such as a SiO ₂ film is formed to a thickness of about 1 nm to 15 nm by a thermal oxidation method. At this time, the impurity ions implanted into the SOI layer 3 are activated, and an n ⁻ -type impurity diffusion layer 41 is formed in the memory cell transistor formation region. Next, a phosphorus-doped first polysilicon layer (floating gate electrode) 13 to be a floating gate electrode is deposited on the gate insulating film 12 by a low pressure CVD (RPCVD) method to about 10 nm to 200 nm. Next, as shown in FIGS. 15A and 15B, a mask film 5 such as a Si ₃ N ₄ film is deposited by a CVD method to a thickness of about 50 nm to 200 nm.

  (D) Next, a resist film is spin-coated on the mask film 5, and an etching mask for the resist film is formed using a photolithography technique. A part of the mask film 5 is selectively removed by reactive ion etching (RIE) using this etching mask. The resist film is removed after the etching. Using the mask film 5 as a mask, the first polysilicon layer 13, the gate insulating film 12, and a part of the SOI layer 3 are selectively removed in the column direction until reaching the buried insulating layer 2. As a result, as shown in FIGS. 16A and 16B, a trench 7 penetrating the first polysilicon layer 13, the gate insulating film 12, and the SOI layer 3 is formed. In FIG. 16B, a part of the buried insulating layer 2 is removed, but the buried insulating layer 2 may remain flat.

(E) Next, as shown in FIGS. 17A and 17B, the element isolation insulating film 6 is buried in the trench 7 by about 200 nm to 1500 nm by the CVD method or the like. Then, as shown in FIGS. 18A and 18B, the element isolation insulating film 6 is planarized by a chemical mechanical polishing (CMP) method. At this time, the upper surface of the element isolation insulating film 6 is located higher than the gate insulating film 12. As a result, the memory cell transistors MT ₁₁ and MT ₂₁ in the row direction are completely isolated from each other.

  (F) Next, as shown in FIGS. 19A and 19B, the interelectrode insulating film 14 is formed on the upper surface of the first polysilicon layer 13 and the upper surface of the element isolation insulating film 6 by CVD or the like. accumulate. Subsequently, a resist film 23 is applied on the interelectrode insulating film 14, and the resist film 23 is patterned using a lithography technique. Subsequently, as shown in FIGS. 20A and 20B, openings 8a and 8b are formed in part of the interelectrode insulating film 14 by RIE or the like using the patterned resist film 23 as a mask. Thereafter, as shown in FIGS. 21A and 21B, a second polysilicon layer (control gate electrode) 15 serving as a phosphorus-doped control gate electrode is formed on the interelectrode insulating film 14 by a CVD method to a thickness of 10 nm to 10 nm. Deposit about 200 nm.

  (G) A resist film 24 is applied on the second polysilicon layer 15, and the resist film 24 is patterned using a lithography technique. Subsequently, as shown in FIGS. 22A and 22B, using the patterned resist film 24 as a mask, the second polysilicon layer 15, the interelectrode insulating film 14, and the first poly film are formed in the row direction by RIE. Part of the silicon layer 13 is selectively removed in the row direction until reaching the gate insulating film 12. As a result, a trench penetrating the second polysilicon layer 15, the interelectrode insulating film 14, and the first polysilicon layer 13 is formed, and the control gate electrode 15, the interelectrode insulating film 14, the floating gate electrode 13, and the gate insulating film are formed. Twelve stacked structure patterns are formed. Select gate electrodes 13b and 15b are formed in the select gate transistor formation region. Thereafter, the resist film 24 is removed using a registry mover or the like.

(H) Next, the resist film 25 is applied on the control gate electrode 15, p as the resist film 25 shown in FIG. 23 (a) and FIG. 23 (b) by lithography ^- -type impurity diffusion layer Patterning is performed so as to cover 40a and 40b. Using the patterned resist film 25 and the pattern of the laminated structure of the control gate electrode 15, the interelectrode insulating film 14, the floating gate electrode 13, and the gate insulating film 12 as a mask, the n ⁻ -type impurity diffusion is performed through the gate insulating film 12. An n-type impurity such as ³¹ P ⁺ or ⁷⁵ As ⁺ is ion-implanted into the layer 41 in a self-aligning manner. The remaining resist film 25 is removed using a registry mover or the like. If heat treatment is performed thereafter, n-type impurity ions in the SOI layer 3 are activated, and an n ⁺ -type source and an n ⁺ -type source are formed in the SOI layer 3 located below the trench as shown in FIGS. N ⁻ type channel regions 411 to 41n are formed in the drain regions 421 to 42 (n + 1) and the SOI layer 3 immediately below the floating gate electrode 13, and depletion type memory cell transistors MT _{11 to} MT _1n are formed. At this time, a plurality of memory cell transistors (not shown) are formed in a matrix so as to intersect in the column direction and the row direction.

(I) Next, the resist film 26 is applied, n as shown in FIG. 25 (a) and FIG. 25 (b) using the resist film 26 by lithography ^- patterned so as to cover the impurity diffusion layer 41 of the To do. Using the patterned resist film 26 as a mask, p-type impurity ions such as ¹¹ B ⁺ are selectively implanted into the p ⁻ -type impurity diffusion layers 40a and 40b at about 10 keV and 1 × 10 ¹⁵ cm ⁻² , for example. Further, an n-type impurity ion such as ⁷⁵ As ⁺ is shallower than the depth at which the p-type impurity ions are implanted, and is selectively applied to the p ⁻ -type impurity diffusion layers 40a and 40b at about 5 keV and 1 × 10 ¹⁵ cm ⁻² , for example. inject. The resist film 26 is removed using a registry mover or the like. If heat treatment is performed thereafter, the n-type and p-type impurity ions in the SOI layer 3 are activated, and the p ⁻ -type channel region 42, n in the SOI layer 3 as shown in FIGS. 26 (a) and 26 (b). ^{A +} type source region 43 is formed, and an enhancement type first select gate transistor STS1 is formed. Further, a p ⁺ -type source line contact region 46 connected to the channel region 42 of the first selection gate transistor STS1 is formed below the source region 43 of the first selection gate transistor STS1. On the other hand, a p-type channel region 44 and an n ⁺ -type drain region 45 are formed in the SOI layer 3, and an enhancement type second selection gate transistor STD1 is also formed. Further, a p ⁺ -type bit line contact region 47 connected to the channel region 44 of the second selection gate transistor STD1 is formed below the drain region 45 of the second selection gate transistor STD1.

  (N) Next, as shown in FIGS. 27A and 27B, an interlayer insulating film 27 is deposited by a CVD method or the like, and a resist film 28 is applied on the interlayer insulating film 27. The resist film 28 is patterned using a lithography technique. As shown in FIGS. 28A and 28B, the patterned resist film 28 is used as a mask to penetrate through the interlayer insulating film 27, the source region 43, and the drain region 45 by the RIE method or the like, respectively. Openings (contact holes) 29a and 29b reaching the region 46 and the bit line contact region 47 are formed. Thereafter, a metal film is buried in the openings 29a and 29b by CVD or the like, and the source line contact plug 18 and the bit line contact plug 17 shown in FIG. 1 are connected to the source line contact region 46 and the bit line contact region 47, respectively. Each is formed as follows. Finally, predetermined wirings and insulating films are formed and deposited, and the nonvolatile semiconductor memory device shown in FIG. 1 is completed.

  According to the method of manufacturing a semiconductor memory device according to the embodiment of the present invention, the nonvolatile semiconductor memory device shown in FIG. 1 can be realized.

(First modification)
In the nonvolatile semiconductor memory device according to the first modification of the embodiment of the present invention, as shown in FIG. 29, the source line contact plug 18 and the bit line contact plug 17 are connected to the source line contact region 46 and the bit line contact, respectively. The difference from the nonvolatile semiconductor memory device shown in FIG. 1 is that it reaches the buried insulating layer 2 through the region 47.

  When the nonvolatile semiconductor memory device shown in FIG. 29 is manufactured, the opening (contact hole) is formed in the source line contact region 46 and the bit line contact region 47 in the procedure shown in FIGS. 28 (a) and 28 (b). The source line contact plug 17 and the bit line contact plug 18 may be embedded by forming so as to penetrate the buried insulating layer 2. However, the opening (contact hole) does not penetrate the buried insulating layer 2 and reach the support substrate 1.

(Second modification)
As shown in FIG. 30, the nonvolatile semiconductor memory device according to the second modification example of the embodiment of the present invention has a bit on the second select gate transistor STD1 side of the nonvolatile semiconductor memory device shown in FIG. The line contact region 47 is not provided. Even in this case, the source line contact region 46 on the first select gate transistor STS1 side functions as a hole supply source, and the same effect as the nonvolatile semiconductor memory device shown in FIG. 1 can be obtained.

As a method for manufacturing the nonvolatile semiconductor memory device shown in FIG. 30, for example, only n-type impurities are ion-implanted in the procedure shown in FIGS. 25 (a) and 25 (b). Thereafter, a resist film is applied, and the resist film is patterned so as to cover the p ⁻ type impurity diffusion layer 40 b together with the n ⁻ type impurity diffusion layer 41. Using the patterned resist film as a mask, p-type impurities may be ion-implanted only into the p ⁻ -type impurity diffusion layer 40a.

(Third Modification)
In the nonvolatile semiconductor memory device according to the third modification of the embodiment of the present invention, as shown in FIG. 31, the source region, the drain region, and the channel region of the memory cell transistors MT _{11 to} MT _1n are integrated. 1 is different from the nonvolatile semiconductor memory device shown in FIG. 1 in that an n ⁻ type impurity diffusion layer 41 is provided. The n-type impurity densities of the source region, the drain region, and the channel region of the memory cell transistors MT _{11 to} MT _1n are substantially the same.

  In the method of manufacturing the nonvolatile semiconductor memory device shown in FIG. 31, the ion implantation process in FIGS. 23A and 23B and the heat treatment process in FIGS. 24A and 24B are omitted. good. Therefore, the process can be simplified as compared with the nonvolatile semiconductor memory device shown in FIG. 1, and it is suitable for miniaturization.

(Fourth modification)
The nonvolatile semiconductor memory device according to the fourth modification example of the embodiment of the present invention is shown in a plan view in FIG. 32, and cross-sections along cut planes in directions CC and DD in FIG. As shown in the figures, the p ⁺ type source line contact region 43 is disposed adjacent to the n ⁺ type source region 43 of the first select gate transistor STS1 in the gate width direction. The p ⁺ type bit line contact region 47 is disposed adjacent to the n ⁺ type drain region 45 of the second select gate transistor STD1 in the gate width direction. Therefore, the source line contact plug 18 is in contact with the source region 43 without penetrating, and is in contact with the source line contact region 43. The bit line contact plug 17 is in contact with the drain region 45 without penetrating, and is in contact with the bit line contact region 45.

In the method for manufacturing the nonvolatile semiconductor memory device shown in FIGS. 32 to 34, for example, instead of the procedure shown in FIGS. 25A and 25B, an n ⁻ -type impurity diffusion is performed using a lithography technique. The resist film is patterned so as to cover part of the layer 41 and the p ⁻ -type impurity diffusion layers 40a and 40b in the gate width direction. Using the patterned resist film as a mask, p-type impurity ions such as ¹¹ B ⁺ are selectively applied to exposed portions of the p ⁻ -type impurity diffusion layers 40a and 40b at about 10 keV and 1 × 10 ¹⁵ cm ⁻² , for example. inject. The resist film is removed using a registry mover or the like.

Further, a resist film is formed so as to cover a part of the n ⁻ type impurity diffusion layer 41 and the p ⁻ type impurity diffusion layers 40a and 40b that are not implanted with p-type impurity ions by using a lithography technique. Pattern. Thereafter, n-type impurity ions such as ⁷⁵ As ⁺ are selectively implanted into exposed portions of the p ⁻ -type impurity diffusion layers 40a and 40b at, for example, about 5 keV and 1 × 10 ¹⁵ cm ⁻² . The resist film is removed using a registry mover or the like. If heat treatment is performed thereafter, the n ⁺ -type source region 43 and drain region 45, and the p ⁺ -type source line contact region 46 and bit line contact region 47 can be formed adjacent to each other in the gate width direction.

(Fifth modification)
As shown in FIG. 35, the nonvolatile semiconductor memory device according to the fifth modification example of the embodiment of the present invention has the horizontal level of the surface of the source region 43 of the first select gate transistor STS1 as the memory cell transistor MT. ₁₁ is different from the nonvolatile semiconductor memory device shown in FIG. 1 in that it is higher than the horizontal level of the surface of the ₁₁ channel regions 411.

  In the method for manufacturing the nonvolatile semiconductor memory device shown in FIG. 35, after the structure shown in FIGS. 22A and 22B is formed, the first select gate transistor STS1 is formed by photolithography technology and etching technology. Only the gate insulating film 12 on the source region 43 is removed. Then, the sidewall 30 is formed on the source line side of the first select gate transistor STS1 by the CVD method, the photolithography technique, and the etching technique.

Thereafter, Si is selectively epitaxially grown on the exposed SOI layer 3 to form a semiconductor layer (epitaxial growth layer) 31 of about 20 nm, for example, as shown in FIG. Thereafter, similarly to the procedure shown in FIGS. 25A and 25B, ¹¹ B ⁺ is ion-implanted at 10 keV, 1 × 10 ¹⁵ cm ⁻² , for example, and ⁷⁵ As ⁺ is 10 keV, 1 × 10 ¹⁵ cm. ^-2 ion implantation. Since other procedures are substantially the same, redundant description is omitted. As a result, the source region 43 of the first select gate transistor STS1 as shown in FIG. 35 is formed.

  According to the fifth modification, even when the SOI layer 3 is thinned to a thickness that makes ion implantation difficult, the thickness of the SOI layer 3 can be complemented by epitaxial growth. This facilitates the ion implantation process for forming the source line contact region 46 and the bit line contact region 47.

Although in FIG. 35 shows a first select gate transistor STS1 side, Similarly, the second selection gate transistor STD1 side shown in FIG. 1, the channel region of the surface of the drain region 45 of memory cell transistors MT ₁₁ It may be higher than the surface of 411.

(Sixth Modification)
In the nonvolatile semiconductor memory device according to the sixth modification of the embodiment of the present invention, the source line contact plug 18 is not in direct contact with the source region 43 and the source line contact region 46, as shown in FIG. 1 is different from the nonvolatile semiconductor memory device shown in FIG. 1 in that the source region 43 and the source line contact region 46 are electrically connected via the silicide region (silicide electrode) 32.

  In the method for manufacturing the nonvolatile semiconductor memory device shown in FIG. 37, as shown in FIG. 38, after forming a side wall 30x on the source region 43 side of the select gate electrodes 13a and 15a, the gate insulating film 12 is formed. To selectively remove part of. Subsequently, as shown in FIG. 39, a metal film 33 of nickel (Ni) or the like is deposited to a thickness of, for example, about 15 nm by a vacuum evaporation method or the like. Thereafter, in the salicide process, heat treatment is performed at 450 ° C. for 30 seconds. At this time, Si and Ni in the source region 43 react to change to NiSi, and a silicide region (silicide electrode) 32 is formed as shown in FIG. Thereafter, if only unreacted Ni is selectively removed and the source line contact plug 18 is formed on the silicide region 32, the nonvolatile semiconductor memory device shown in FIG. 37 can be realized.

  Furthermore, as shown in FIG. 41, the silicide region (silicide electrode) 32 may reach the buried insulating layer 2. In the method of manufacturing the nonvolatile semiconductor memory device shown in FIG. 41, for example, when the thickness of the SOI layer 3 is 30 nm, a metal film 33 such as Ni is deposited by 20 nm in the procedure shown in FIG. For example, the SOI layer 3 is all silicided. As a result, the nonvolatile semiconductor memory device shown in FIG. 41 can be realized.

  37 and 41 show the first select gate transistor STS1 side, but the bit line contact plug 17 is connected to the drain region 45 and the second select gate transistor STD1 side shown in FIG. The bit line contact region 47 may not be directly in contact, but may be electrically connected to the drain region 45 and the bit line contact region 47 through a silicide region (silicide electrode).

(Other embodiments)
As mentioned above, although this invention was described by embodiment, it should not be understood that the description and drawing which form a part of this indication limit this invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art. For example, although the hole accumulation layers 48a and 48b and the hole inversion layer 49 are shown in FIG. 6, it is a matter of course that an electron accumulation layer and an inversion layer are formed if they are of the opposite conductivity type. Further, as shown in FIG. 42, the surface layer portion of the SOI layer 3 may be shaved.

In the nonvolatile semiconductor memory device shown in FIG. 1, the impurity density (for example, about 1 × 10 ¹⁸ cm ⁻³ ) of the channel region 44 of the second select gate transistor STD1 is equal to the channel of the second select gate transistor STD1. It may be higher than the impurity density of the region 44 (for example, about 1 × 10 ¹⁷ cm ⁻³ ). In this case, in the procedure shown in FIGS. 12A and 12B, the region of the SOI layer 3 in which the first and second select gate transistors STS1 and STD1 are formed together with the memory cell transistor formation region is masked. What is necessary is just to perform each ion implantation from which a dose amount differs.

In the embodiment, n-type polysilicon is used as the gate electrodes 13 and 15 of the memory cell transistors MT _{11 to} MT _1n and the gate electrodes 13a, 13b, 15a and 15b of the selection gate transistors STS1 and STD1, and the memory cell is used. The case where the transistors MT _{11 to} MT _1n operate as a depletion type FET and the select gate transistors STS1 and STD1 operate as an enhancement type FET has been described as an example. Here, the materials of the gate electrodes 13 and 15 of the memory cell transistors MT _{11 to} MT _1n and the gate electrodes 13a, 13b, 15a and 15b of the selection gate transistors STS1 and STD1 are changed, and the work function of the gate electrode material is adjusted. With this method, the memory cell transistors MT _{11 to} MT _1n can operate as non-depletion type FETs, and the select gate transistors STS1 and STD1 can operate as non-enhancement type FETs. In that case, an operation equivalent to that described here can be realized by changing the bias condition applied to each electrode when performing operations such as writing, reading, and batch erasing of memory signals. .

Further, in the embodiment, m × n memory cell transistors MT _{11 to} MT _1n , MT _{21 to} MT _2n ,..., MT _{m1 to} MT _mn are shown. The cell array may be formed of cell transistors. In the embodiment, the binary NAND flash memory has been described. However, the present invention can also be applied to a multi-value NAND flash memory having three or more values. As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

FIG. 3 is a cross-sectional view in the column direction (cross-sectional view in the AA direction in FIG. 2) showing an example of the cell array of the nonvolatile semiconductor memory device according to the embodiment of the present invention. 1 is a plan view showing an example of a cell array of a nonvolatile semiconductor memory device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view in the row direction (cross-sectional view in the BB direction in FIG. 2) showing an example of the cell array of the nonvolatile semiconductor memory device according to the embodiment of the present invention. 3 is an equivalent circuit showing an example of a cell array of the nonvolatile semiconductor memory device according to the embodiment of the present invention. 4 is a timing chart of the erase operation of the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 6 is a cross-sectional view showing an example of the erase operation of the cell array in the nonvolatile semiconductor memory device according to the embodiment of the present invention. It is a graph which shows hole concentration distribution of the non-volatile semiconductor memory device which concerns on embodiment of this invention. 4 is a graph showing a potential during an erasing operation of the nonvolatile semiconductor memory device according to the embodiment of the present invention. 4 is a timing chart of a write operation of the nonvolatile semiconductor memory device according to the embodiment of the present invention. 4 is a flowchart of a write operation of the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 11A is a process cross-sectional view in the column direction (process cross-sectional view in the direction AA in FIG. 2) illustrating an example of a method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 11B is a process cross-sectional view in the row direction (process cross-sectional view in the BB direction in FIG. 2) showing an example of a method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 12A is a process cross-sectional view in the column direction subsequent to FIG. 11A of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 12B is a process cross-sectional view in the row direction subsequent to FIG. 11B of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 13A is a process sectional view in the column direction subsequent to FIG. 12A of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 13B is a process cross-sectional view in the row direction subsequent to FIG. 12B of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 14A is a process cross-sectional view in the column direction subsequent to FIG. 13A of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 14B is a process cross-sectional view in the row direction subsequent to FIG. 13B of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 15A is a process sectional view in the column direction subsequent to FIG. 14A of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 15B is a process sectional view in the row direction subsequent to FIG. 14B of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 16A is a process cross-sectional view in the column direction subsequent to FIG. 15A of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 16B is a process sectional view in the row direction subsequent to FIG. 15B of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 17A is a process sectional view in the column direction subsequent to FIG. 16A of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 17B is a process cross-sectional view in the row direction subsequent to FIG. 16B of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 18A is a process cross-sectional view in the column direction subsequent to FIG. 17A of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 18B is a process sectional view in the row direction subsequent to FIG. 17B of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 19A is a process cross-sectional view in the column direction subsequent to FIG. 18A of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 19B is a process cross-sectional view in the row direction subsequent to FIG. 18B of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 20A is a process cross-sectional view in the column direction subsequent to FIG. 19A of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 20B is a process cross-sectional view in the row direction subsequent to FIG. 19B of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 21A is a process cross-sectional view in the column direction subsequent to FIG. 20A of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 21B is a process sectional view in the row direction subsequent to FIG. 20B of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 22A is a process cross-sectional view in the column direction subsequent to FIG. 21A of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 22B is a process sectional view in the row direction subsequent to FIG. 21B of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 23A is a process sectional view in the column direction subsequent to FIG. 22A of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 23B is a process sectional view in the row direction following FIG. 22B of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 24A is a process sectional view in the column direction subsequent to FIG. 23A of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 24B is a process cross-sectional view in the row direction subsequent to FIG. 23B of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 25A is a process cross-sectional view in the column direction subsequent to FIG. 24A of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 25B is a process sectional view in the row direction subsequent to FIG. 24B of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 26A is a process sectional view in the column direction subsequent to FIG. 25A of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 26B is a process sectional view in the row direction subsequent to FIG. 25B of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 27A is a process cross-sectional view in the column direction subsequent to FIG. 26A of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 27B is a process sectional view in the row direction subsequent to FIG. 26B of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 28A is a process cross-sectional view in the column direction subsequent to FIG. 27A of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 28B is a process sectional view in the row direction subsequent to FIG. 27B of the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention. It is sectional drawing of the column direction which shows an example of the cell array of the non-volatile semiconductor memory device which concerns on the 1st modification of embodiment of this invention. It is sectional drawing of the column direction which shows an example of the cell array of the non-volatile semiconductor memory device which concerns on the 2nd modification of embodiment of this invention. It is sectional drawing of the column direction which shows an example of the cell array of the non-volatile semiconductor memory device which concerns on the 3rd modification of embodiment of this invention. It is a top view which shows an example of the cell array of the non-volatile semiconductor memory device which concerns on the 4th modification of embodiment of this invention. FIG. 36 is a cross-sectional view in the column direction (cross-sectional view in the direction CC of FIG. 32) showing an example of a cell array of the nonvolatile semiconductor memory device in accordance with the fourth modification example of the embodiment of the present invention. FIG. 36 is a cross-sectional view in the column direction (cross-sectional view in the DD direction in FIG. 32) showing an example of a cell array of the nonvolatile semiconductor memory device in accordance with the fourth modification example of the embodiment of the present invention. It is sectional drawing of the column direction which shows an example of the cell array of the non-volatile semiconductor memory device which concerns on the 5th modification of embodiment of this invention. It is process sectional drawing of the column direction which shows an example of the manufacturing method of the non-volatile semiconductor memory device which concerns on the 5th modification of embodiment of this invention. It is sectional drawing of the column direction which shows an example of the cell array of the non-volatile semiconductor memory device which concerns on the 6th modification of embodiment of this invention. It is process sectional drawing of the column direction which shows an example of the manufacturing method of the non-volatile semiconductor memory device which concerns on the 6th modification of embodiment of this invention. FIG. 39 is a process cross-sectional view subsequent to FIG. 38 of the method for manufacturing the nonvolatile semiconductor memory device according to the sixth modification example of the embodiment of the present invention. FIG. 40 is a process cross-sectional view subsequent to FIG. 39 of the method for manufacturing the nonvolatile semiconductor memory device according to the sixth modification example of the embodiment of the present invention. It is sectional drawing of the column direction which shows another example of the manufacturing method of the non-volatile semiconductor memory device which concerns on the 6th modification of embodiment of this invention. It is sectional drawing of the column direction which shows an example of the cell array of the non-volatile semiconductor memory device concerning other embodiment of this invention. It is sectional drawing of the column direction which shows the cell array of the non-volatile semiconductor memory device which concerns on a comparative example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Support substrate 2 ... Embedded insulating layer (BOX layer)
3. Semiconductor layer (SOI layer)
DESCRIPTION OF SYMBOLS 5 ... Mask film 6 ... Element isolation insulating film 7 ... Groove part 8 ... Opening part 12 ... Gate insulating film 13 ... Floating gate electrode (1st polysilicon layer)
13a, 15a, 13b, 15b ... selection gate electrode 14 ... interelectrode insulating film 15 ... control gate electrode (second polysilicon layer)
DESCRIPTION OF SYMBOLS 17 ... Bit line contact plug 18 ... Source line contact plug 27 ... Interlayer insulating film 29a, 29b ... Opening 30 ... Side wall 31 ... Semiconductor layer (epitaxial growth layer)
40a, 40b ... p ^- type impurity diffusion layer 41 ... n ^- type impurity diffusion layer 42,44 ... channel region 43 ... source region 45 ... drain region 46 ... source line contact region 47 ... bit line contact region 48a, 48b ... Hole accumulation layer 49 ... hole inversion layer 411 to 41n ... channel region 421 to 42 (n + 1) ... source and drain regions

Claims (5)

A plurality of memory cell transistors each including a channel region of a first conductivity type in contact with the buried insulating layer and arranged in a column direction;
A first select gate transistor comprising a channel region of a second conductivity type adjacent to one end of the array of the memory cell transistors and in contact with the buried insulating layer;
A second conductive type source line contact region electrically connected to the second conductive type channel region and having a higher impurity density than the channel region;
A source line contact plug electrically connected to the source region of the first conductivity type of the first select gate transistor and electrically connected to the source line contact region ;
A hole inversion layer or an electron inversion layer is formed at the interface between the channel region, the source region, and the drain region of each of the plurality of memory cell transistors at the time of collective erasing of the plurality of memory cell transistors; and A NAND-type nonvolatile semiconductor memory device , wherein a hole accumulation layer or an electron accumulation layer is formed at the buried insulating layer side interface of the channel region of the first select gate transistor . A second select gate transistor comprising a second conductivity type channel region adjacent to the other end of the memory cell transistor array;
A second conductive type bit line contact region electrically connected to the channel region of the second select gate transistor and having a higher impurity density than the channel region;
2. A bit line contact plug electrically connected to the drain region of the first conductivity type of the second select gate transistor and electrically connected to the bit line contact region. The non-volatile semiconductor memory device described in 1.   3. The nonvolatile semiconductor memory device according to claim 2, wherein the channel region of the first select gate transistor has a lower impurity density of the second conductivity type than the channel region of the second select gate transistor.   4. The nonvolatile semiconductor memory device according to claim 1, wherein a surface of a source region of the first select gate transistor is higher than a surface of a channel region of the memory cell transistor. 5.   The nonvolatile semiconductor memory device according to claim 1, wherein the source line contact plug reaches the buried insulating layer.

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