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JP4483566B2 - Light emitting device - Google Patents

Light emitting device Download PDF

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JP4483566B2
JP4483566B2 JP2004367735A JP2004367735A JP4483566B2 JP 4483566 B2 JP4483566 B2 JP 4483566B2 JP 2004367735 A JP2004367735 A JP 2004367735A JP 2004367735 A JP2004367735 A JP 2004367735A JP 4483566 B2 JP4483566 B2 JP 4483566B2
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light emitting
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JP2006173534A (en
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勝紀 小島
実 廣瀬
真央 神谷
浩一 五所野尾
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Toyoda Gosei Co Ltd
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    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

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Description

本発明は、発光装置に用いられる発光素子に関するものである。特に、マウント部材にフリップチップ実装する発光素子の観測面側への光取り出しを向上させた発光装置に関する。   The present invention relates to a light emitting element used in a light emitting device. In particular, the present invention relates to a light-emitting device that improves light extraction to the observation surface side of a light-emitting element that is flip-chip mounted on a mount member.

窒化物半導体を層構造に含む発光ダイオードは、高輝度純緑色発光LED、青色発光LEDとして、フルカラーLEDディスプレイ、交通信号灯、バックライトなど、様々な分野で広く利用されている。   A light-emitting diode including a nitride semiconductor in a layer structure is widely used as a high-luminance pure green light-emitting LED or blue light-emitting LED in various fields such as a full-color LED display, a traffic signal lamp, and a backlight.

これらのLEDは、一般に、サファイアなどの基板上にn型窒化物半導体層、活性層、p型窒化物半導体層が順に積層された構造となっている。さらに、p型窒化物半導体層上にはp側電極が配置され、n型窒化物半導体層上にはn側電極が配置されている。たとえば、p側電極とn側電極とを同一面側に設ける場合は、p型窒化物半導体層上にp側電極が配置されると共に、p型窒化物半導体層、活性層、およびn型窒化物半導体層の一部がエッチングなどにより除去され、露出したn型窒化物半導体層上にn側電極が配置された構成となる。さらに、光取り出しを向上させることを目的として、LEDの構造として様々なものが提案されている(例えば特許文献1及び2)。
特開2004−6662 特開2004−221529
These LEDs generally have a structure in which an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer are sequentially stacked on a substrate such as sapphire. Furthermore, a p-side electrode is disposed on the p-type nitride semiconductor layer, and an n-side electrode is disposed on the n-type nitride semiconductor layer. For example, when the p-side electrode and the n-side electrode are provided on the same surface side, the p-side electrode is disposed on the p-type nitride semiconductor layer, and the p-type nitride semiconductor layer, the active layer, and the n-type nitridation are provided. A part of the physical semiconductor layer is removed by etching or the like, and the n-side electrode is arranged on the exposed n-type nitride semiconductor layer. Further, various LED structures have been proposed for the purpose of improving light extraction (for example, Patent Documents 1 and 2).
JP20046662 JP2004-221529

しかしながら、従来の構造では、フリップ実装された発光素子側面に達する光が効率よく取り出せないという問題点があった。   However, the conventional structure has a problem that light reaching the side surface of the light-emitting element that is flip-mounted cannot be extracted efficiently.

そこで、本発明はフリップ実装された半導体発光素子側面に達する光を効率よく光を取り出すことが出来る発光装置を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a light emitting device that can efficiently extract light reaching a side surface of a flip-mounted semiconductor light emitting element.

以上の目的を達成するために、本発明に係る発光装置は、p層、発光層及びn層が積層され、前記p層と電気的に接続しているp電極及び前記n層と電気的に接続しているn電極が同一面に形成さている半導体発光素子と、前記半導体発光素子は前記p電極及び前記n電極のそれぞれに電気的に接続する回路を有するマウント部材にフリップ実装し、前記半導体発光素子は、前記p層から前記n層までの斜面を有し、前記斜面は前記発光層から発光した光を拡散させながら発光観測面側に全反射させる表面凹凸構造からなることを特徴としている。 In order to achieve the above object, a light-emitting device according to the present invention includes a p-layer , a light-emitting layer, and an n-layer stacked, and electrically connected to the p-electrode and the n-layer that are electrically connected to the p-layer. A semiconductor light emitting device in which n electrodes to be connected are formed on the same surface side , and the semiconductor light emitting device is flip-mounted on a mount member having a circuit electrically connected to each of the p electrode and the n electrode. The semiconductor light emitting device has an inclined surface from the p layer to the n layer, and the inclined surface has a surface uneven structure that totally reflects the light emitted from the light emitting layer to the light emission observation surface side while diffusing the light. It is a feature.

本発明に係る発光装置は、フリップ実装された発光素子側面に達する光が効率よく取り出せることができる。   The light-emitting device according to the present invention can efficiently extract light reaching the side surface of the light-emitting element that is flip-mounted.

本発明に係る発光装置に配置される発光素子を構成する各半導体層としては種々の窒化物半導体を用いることができる。具体的には、有機金属気相成長法(MOCVD)、ハイドライド気相成長法(HVPE)などにより基板上にInAlGa1−X−YN(0≦X、0≦Y、X+Y≦1)等の半導体を複数形成させたものが好適に用いられる。また、その層構造としては、MIS接合、PIN接合やPN接合を有したホモ構造、ヘテロ構造あるいはダブルへテロ構成のものが挙げられる。また、各層を超格子構造としたり、活性層を量子効果が生ずる薄膜に形成させた単一量子井戸構造や多重量子井戸構造とすることもできる。 Various nitride semiconductors can be used as each semiconductor layer constituting the light emitting element disposed in the light emitting device according to the present invention. Specifically, In X Al Y Ga 1- XYN (0 ≦ X, 0 ≦ Y, X + Y ≦) is formed on the substrate by metal organic vapor phase epitaxy (MOCVD), hydride vapor phase epitaxy (HVPE), or the like. A semiconductor in which a plurality of semiconductors such as 1) are formed is preferably used. In addition, the layer structure includes a homo structure having a MIS junction, a PIN junction or a PN junction, a hetero structure, or a double hetero structure. Each layer may have a superlattice structure, or may have a single quantum well structure or a multiple quantum well structure in which an active layer is formed in a thin film in which a quantum effect is generated.

発光素子は、一般的には、特定の基板上に各半導体層を成長させて形成されるが、その際、基板としてサファイア等の絶縁性基板を用いる。この場合、通常、p側電極およびn側電極はいずれも半導体層上の同一面側に形成されることになる。もちろん、最終的に基板を除去した上で、フリップチップ実装することもできる。なお、基板はサファイアに限定されず、スピネル、SiC、GaN、GaAs等、公知の部材を用いることができる。   The light-emitting element is generally formed by growing each semiconductor layer on a specific substrate. At this time, an insulating substrate such as sapphire is used as the substrate. In this case, normally, both the p-side electrode and the n-side electrode are formed on the same surface side on the semiconductor layer. Of course, it is also possible to perform flip-chip mounting after finally removing the substrate. The substrate is not limited to sapphire, and a known member such as spinel, SiC, GaN, or GaAs can be used.

以下、図面を参照しながら、本発明に係る実施の形態を窒化物半導体発光素子について説明する。ただし、以下に示す実施の形態は、本発明の技術思想を具体化するための発光装置を例示するものであって、本発明は発光装置を以下のものに特定しない。   Embodiments according to the present invention will be described below with reference to the drawings for nitride semiconductor light emitting devices. However, the embodiment described below exemplifies a light emitting device for embodying the technical idea of the present invention, and the present invention does not specify the light emitting device as follows.

(実施の形態1)
図1に、本発明の実施例に係るIII族窒化物系化合物半導体素子100の模式的な平面図を、図2にはその断面図を示す。また、図3には、そのIII族窒化物系化合物半導体素子100を用いた発光装置の断面図を示す。
(Embodiment 1)
FIG. 1 is a schematic plan view of a group III nitride compound semiconductor device 100 according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view thereof. FIG. 3 is a cross-sectional view of a light emitting device using the group III nitride compound semiconductor element 100.

III族窒化物系化合物半導体素子100は、次の構成を有する発光素子である。図1に示す様に、一辺300μmの幅を有しており、発光素子周囲にジグザグな形状を有した溝150を有しており、その溝150の一部にn電極140を形成し、また中央のジグザグ形状をした島状部分に、ほぼ全面に厚膜な反射p電極110配置している。   The group III nitride compound semiconductor device 100 is a light emitting device having the following configuration. As shown in FIG. 1, each side has a width of 300 μm, a groove 150 having a zigzag shape around the light emitting element, an n-electrode 140 is formed in a part of the groove 150, and A thick reflective p-electrode 110 is disposed on almost the entire surface of the central zigzag island.

次に図2に示すように、厚さ約300μmのサファイア基板101の上に、窒化アルミニウム(AlN)から成る膜厚約15nmのAlNバッファ層102が成膜され、その上に膜厚約500nmのノンドープのGaN層103が成膜され、その上にシリコン(Si)を1×1018/cm3ドープしたGaNから成る膜厚約5μmのn型コンタクト層104(高キャリア濃度n+層)が形成されている。 Next, as shown in FIG. 2, an AlN buffer layer 102 made of aluminum nitride (AlN) and having a thickness of about 15 nm is formed on a sapphire substrate 101 having a thickness of about 300 μm. A non-doped GaN layer 103 is formed, and an n-type contact layer 104 (high carrier concentration n + layer) having a film thickness of about 5 μm made of GaN doped with silicon (Si) at 1 × 10 18 / cm 3 is formed thereon. Has been.

また、このn型コンタクト層104の上には、シリコン(Si)を1×1018/cm3でドープしたAl0.15Ga0.85Nから成る膜厚約25nmのn型クラッド層105が形成されている。更にその上には、膜厚約3nmのノンドープIn0.2Ga0.8Nから成る井戸層と膜厚約20nmのノンドープGaNから成る障壁層とを3ペア積層して多重量子井戸構造の発光層106が形成されている。 On the n-type contact layer 104, an n-type cladding layer 105 having a thickness of about 25 nm made of Al 0.15 Ga 0.85 N doped with silicon (Si) at 1 × 10 18 / cm 3 is formed. . Further thereon, three pairs of a well layer made of non-doped In 0.2 Ga 0.8 N having a thickness of about 3 nm and a barrier layer made of non-doped GaN having a thickness of about 20 nm are stacked to form a light emitting layer 106 having a multiple quantum well structure. Has been.

更に、この発光層106の上には、Mgを2×1019/cm3ドープした膜厚約25nmのp型Al0.15Ga0.85Nから成るp型クラッド層(第1のp層)107が形成されている。p型クラッド層107の上には、Mgを8×1019/cm3ドープした膜厚約100nmのp型GaNから成るp型コンタクト層(第2のp層)108が形成されている。 Further, a p-type cladding layer (first p layer) 107 made of p-type Al 0.15 Ga 0.85 N having a film thickness of about 25 nm doped with 2 × 10 19 / cm 3 of Mg is formed on the light emitting layer 106. Has been. On the p-type cladding layer 107, a p-type contact layer (second p layer) 108 made of p-type GaN having a thickness of about 100 nm doped with 8 × 10 19 / cm 3 of Mg is formed.

又、p型コンタクト層(第2のp層)108の上には金属蒸着による反射p電極110が、n型コンタクト層104上にはn電極140が形成されている。反射p電極110は、膜厚約300nmのロジウム(Rh)より成る第1層と、このロジウム膜に接合する膜厚約10nmのチタン(Ti)と膜厚約500nmの金(Au)より成る第2層とで構成されている。   A reflective p-electrode 110 formed by metal deposition is formed on the p-type contact layer (second p-layer) 108, and an n-electrode 140 is formed on the n-type contact layer 104. The reflective p-electrode 110 includes a first layer made of rhodium (Rh) having a thickness of about 300 nm, a first layer made of titanium (Ti) having a thickness of about 10 nm and a gold (Au) having a thickness of about 500 nm. It consists of two layers.

多層構造のn電極140は、n型コンタクト層104の一部露出された部分の上から、膜厚約20nmのバナジウム(V)より成る第1層と膜厚約100nmのアルミニウム(Al)より成る第2層、膜厚約10nmのチタン(Ti)から成る第3層、膜厚約500nmの金(Au)からなる第4層とを積層させることにより構成されている。

上記の構成のIII族窒化物系化合物半導体素子100は次のように製造された。III族窒化物系化合物半導体素子100は、有機金属気相成長法(以下「MOVPE」と略す)により製造された。用いられたガスは、アンモニア(NH3)、キャリアガス(H2及びN2)、トリメチルガリウム(Ga(CH33)(以下「TMG」と記す)、トリメチルアルミニウム(Al(CH33)(以下「TMA」と記す)、トリメチルインジウム(In(CH33)(以下「TMI」と記す)、シラン(SiH4)とシクロペンタジエニルマグネシウム(Mg(C552)(以下「CP2Mg」と記す)である。
The n-electrode 140 having a multilayer structure is composed of a first layer made of vanadium (V) with a thickness of about 20 nm and aluminum (Al) with a thickness of about 100 nm from above a part of the n-type contact layer 104 that is partially exposed. The second layer, a third layer made of titanium (Ti) with a thickness of about 10 nm, and a fourth layer made of gold (Au) with a thickness of about 500 nm are stacked.

The group III nitride compound semiconductor device 100 having the above-described configuration was manufactured as follows. Group III nitride compound semiconductor device 100 was manufactured by metal organic vapor phase epitaxy (hereinafter abbreviated as “MOVPE”). The gases used were ammonia (NH 3 ), carrier gas (H 2 and N 2 ), trimethylgallium (Ga (CH 3 ) 3 ) (hereinafter referred to as “TMG”), trimethylaluminum (Al (CH 3 ) 3 (Hereinafter referred to as “TMA”), trimethylindium (In (CH 3 ) 3 ) (hereinafter referred to as “TMI”), silane (SiH 4 ) and cyclopentadienyl magnesium (Mg (C 5 H 5 ) 2 ) (Hereinafter referred to as “CP 2 Mg”).

まず、有機洗浄及び熱処理により洗浄したA面を主面とした単結晶のサファイア基板101をMOVPE装置の反応室に載置されたサセプタに装着する。次に、常圧でH2を反応室に流しながら温度1100℃でサファイア基板101をベーキングした。 First, a single crystal sapphire substrate 101 whose main surface is an A surface cleaned by organic cleaning and heat treatment is mounted on a susceptor mounted in a reaction chamber of an MOVPE apparatus. Next, the sapphire substrate 101 was baked at a temperature of 1100 ° C. while flowing H 2 into the reaction chamber at normal pressure.

次に、サファイア基板101の温度を400℃に低下させ、H2、NH3及びTMAを供給してAlNバッファ層102を約15nmの膜厚に形成した。 Next, the temperature of the sapphire substrate 101 was lowered to 400 ° C., and H 2 , NH 3 and TMA were supplied to form the AlN buffer layer 102 with a thickness of about 15 nm.

次に、サファイア基板101の温度を1150℃に保持し、H2、NH3、TMGを供給して、その上にノンドープGaN層103を形成した。次に、H2、NH3、TMG、シランを供給して、その上にシリコン(Si)を1×1018/cm3ドープしたGaNから成る膜厚約5μmのn型コンタクト層104(高キャリア濃度n+層)を形成した。 Next, the temperature of the sapphire substrate 101 was maintained at 1150 ° C., H 2 , NH 3 , and TMG were supplied, and the non-doped GaN layer 103 was formed thereon. Next, H 2 , NH 3 , TMG and silane are supplied, and n-type contact layer 104 (high carrier) having a film thickness of about 5 μm made of GaN doped with silicon (Si) at 1 × 10 18 / cm 3 thereon. Density n + layer).

この後、H2、NH3、TMG、TMA、シランの供給量を制御して、シリコン(Si)を1×1018/cm3でドープしたAl0.15Ga0.85Nから成る膜厚約25nmのn型クラッド層105を形成した。 Thereafter, the supply amount of H 2 , NH 3 , TMG, TMA, and silane is controlled, and an n 0.15 Ga 0.85 N film made of Al 0.15 Ga 0.85 N doped with silicon (Si) at 1 × 10 18 / cm 3 is formed. A mold cladding layer 105 was formed.

次に、サファイア基板101の温度を825℃にまで低下させて、N2又はH2、NH3、TMG及びTMIの供給量を制御して、膜厚約3nmのノンドープIn0.2Ga0.8Nから成る井戸層と膜厚約20nmのノンドープGaNから成る障壁層とを3ペア積層して多重量子井戸構造の発光層106が形成した。 Next, the temperature of the sapphire substrate 101 is lowered to 825 ° C., and the supply amount of N 2 or H 2 , NH 3 , TMG, and TMI is controlled to be made of non-doped In 0.2 Ga 0.8 N with a film thickness of about 3 nm. A light emitting layer 106 having a multiple quantum well structure was formed by laminating three pairs of well layers and barrier layers made of non-doped GaN having a thickness of about 20 nm.

次に、サファイア基板101の温度を1050℃に保持し、N2又はH2、NH3、TMG、TMA及びCP2Mgを制御しながら供給して、Mgを2×1019/cm3ドープした膜厚約25nmのp型Al0.15Ga0.85Nから成るp型クラッド層(第1のp層)107を形成した。次にN2又はH2、NH3、TMG及びCP2Mgを制御しながら供給して、Mgを8×1019ドープした膜厚約100nmのp型GaNから成るp型コンタクト層(第2のp層)108を形成した。
以上の結晶成長工程を経たサファイア基板(以下ウェハと呼ぶ)について、ウェハ全面にフォトレジストを塗布し、フォトリソグラフィによりIII族窒化物系化合物半導体素子100の最外周部がジグザグの形状となるようにフォトレジストを除去して窓を形成し、また同時に、n電極140を形成する部分のフォトレジストを除去して窓を形成した。
Next, the temperature of the sapphire substrate 101 is maintained at 1050 ° C., and N 2 or H 2 , NH 3 , TMG, TMA and CP 2 Mg are supplied while being controlled, and Mg is doped 2 × 10 19 / cm 3 . A p-type cladding layer (first p layer) 107 made of p-type Al 0.15 Ga 0.85 N having a thickness of about 25 nm was formed. Next, N 2 or H 2 , NH 3 , TMG and CP 2 Mg are supplied while being controlled, and a p-type contact layer made of p-type GaN having a thickness of about 100 nm doped with 8 × 10 19 Mg (the second type) p layer) 108 was formed.
With respect to the sapphire substrate (hereinafter referred to as a wafer) that has undergone the above crystal growth process, a photoresist is applied to the entire surface of the wafer, and the outermost periphery of the group III nitride compound semiconductor device 100 is formed in a zigzag shape by photolithography. The photoresist was removed to form a window, and at the same time, the portion of the photoresist where the n-electrode 140 was formed was removed to form a window.

続いて、フォトレジストで覆われていない窓部分のIII族窒化物系化合物半導体p型コンタクト層(第2のp層)108、p型クラッド層107、活性層106、n型クラッド層105、およびn型コンタクト層104の一部を、反応性イオンエッチングによってα=45度の角度を有する凸凹側面160を形成するようにエッチングして、III族窒化物系化合物半導体素子100の最外周部がジグザグの形状となるようにn型コンタクト層104を露出させ、また同時に、n電極140を形成する部分のn型コンタクト層104を露出させた。
次に、ウェハ全面にフォトレジストを塗布し、フォトリソグラフィにより反射p電極110を形成する部分のフォトレジストを除去して窓を形成し、p型コンタクト層(第2のp層)108を露出させた。続いて、ウェハ全面にロジウム(Rh)を300nm蒸着した。
Subsequently, the group III nitride compound semiconductor p-type contact layer (second p-layer) 108, the p-type cladding layer 107, the active layer 106, the n-type cladding layer 105, and the window portion not covered with the photoresist, A part of the n-type contact layer 104 is etched by reactive ion etching so as to form an uneven side surface 160 having an angle of α = 45 degrees, and the outermost peripheral portion of the group III nitride compound semiconductor device 100 is zigzag-shaped. The n-type contact layer 104 was exposed so that the shape of the n-type contact was formed, and at the same time, the portion of the n-type contact layer 104 where the n-electrode 140 was formed was exposed.
Next, a photoresist is applied to the entire surface of the wafer, a portion of the photoresist where the reflective p-electrode 110 is formed is removed by photolithography, a window is formed, and the p-type contact layer (second p-layer) 108 is exposed. It was. Subsequently, rhodium (Rh) was deposited to 300 nm on the entire surface of the wafer.

この後、フォトレジストおよびフォトレジスト上のロジウム(Rh)を除去し、p型コンタクト層108上に反射p電極110としてロジウム(Rh)膜を形成した。
次に、ウェハ全面にフォトレジストを塗布し、フォトリソグラフィによりn電極140を形成する部分のフォトレジストを除去して窓を形成し、n型コンタクト層104を露出させた。続いて、ウェハ全面に膜厚約20nmのバナジウム(V)、膜厚約100nmのアルミニウム(Al)の順に、連続して蒸着した。この後、フォトレジストとともにフォトレジスト上のバナジウム(V)とアルミニウム(Al)の積層膜を除去し、n型コンタクト層104上にn電極140としてバナジウム(V)/アルミニウム(Al)積層膜を形成し、次に、N雰囲気で500℃、4分程度の熱処理を行う。
Thereafter, the photoresist and rhodium (Rh) on the photoresist were removed, and a rhodium (Rh) film was formed on the p-type contact layer 108 as the reflective p-electrode 110.
Next, a photoresist was applied to the entire surface of the wafer, a portion of the photoresist where the n-electrode 140 was to be formed was removed by photolithography, a window was formed, and the n-type contact layer 104 was exposed. Subsequently, vanadium (V) having a film thickness of about 20 nm and aluminum (Al) having a film thickness of about 100 nm were successively deposited on the entire surface of the wafer. Thereafter, the vanadium (V) and aluminum (Al) laminated film on the photoresist is removed together with the photoresist, and a vanadium (V) / aluminum (Al) laminated film is formed on the n-type contact layer 104 as the n electrode 140. Next, heat treatment is performed at 500 ° C. for about 4 minutes in an N 2 atmosphere.

次に、ウェハ全面にフォトレジストを塗布し、フォトリソグラフィによりn電極140の部分とp電極110の部分のフォトレジストを除去して窓を形成し、n電極140とp電極110を露出させた。続いて、ウェハ全面に膜厚約10nmのチタン(Ti)と膜厚約500nmの金(Au)の順に蒸着した。   Next, a photoresist was applied to the entire surface of the wafer, and the photoresist was removed from the n-electrode 140 portion and the p-electrode 110 portion by photolithography to form a window, and the n-electrode 140 and the p-electrode 110 were exposed. Subsequently, titanium (Ti) having a film thickness of about 10 nm and gold (Au) having a film thickness of about 500 nm were sequentially deposited on the entire surface of the wafer.

この後、フォトレジストとともにフォトレジスト上のチタン(Ti)と金(Au)の積層膜を除去し、n電極140上および反射p電極110上に厚膜電極130としてチタン(Ti)/金(Au)積層膜を形成した。   Thereafter, the laminated film of titanium (Ti) and gold (Au) on the photoresist is removed together with the photoresist, and titanium (Ti) / gold (Au) is formed as a thick film electrode 130 on the n electrode 140 and the reflective p electrode 110. ) A laminated film was formed.

その後、個々の発光素子部分をダイシングにより分離する。   Thereafter, the individual light emitting element portions are separated by dicing.

以上の様にして、半導体層側と反対側のサファイア側から光を取り出すフリップチップ型のIII族窒化物系化合物半導体素子100を製造した。
次に、図3には、上記にて製造した半導体素子100を用いた発光装置200を示している。このIII族窒化物系化合物半導体素子100をリフレクタ部220を有する樹脂ケース210の凹部中央に金バンプ240を介して固定し、樹脂ケース210に形成されたp側電極211とIII族窒化物系化合物半導体素子100の反射p電極110と、又、樹脂ケースに形成されたn側電極212とIII族窒化物系化合物半導体素子100のn電極140をそれぞれ金バンプ240で電気的に接続固定した。そして、樹脂ケースの凹部に透明材料であるシリコン樹脂等の封止材料230を充填し、III族窒化物系化合物半導体素子100を保護した発光装置200を製造した。
In the manner as described above, the flip chip type group III nitride compound semiconductor device 100 in which light is extracted from the sapphire side opposite to the semiconductor layer side was manufactured.
Next, FIG. 3 shows a light emitting device 200 using the semiconductor element 100 manufactured as described above. The group III nitride compound semiconductor element 100 is fixed to the center of the recess of the resin case 210 having the reflector portion 220 via a gold bump 240, and the p-side electrode 211 formed on the resin case 210 and the group III nitride compound are formed. The reflective p-electrode 110 of the semiconductor element 100, the n-side electrode 212 formed on the resin case, and the n-electrode 140 of the group III nitride compound semiconductor element 100 were electrically connected and fixed by gold bumps 240, respectively. And the sealing material 230, such as a silicone resin which is a transparent material, was filled in the recessed part of the resin case, and the light-emitting device 200 which protected the group III nitride compound semiconductor element 100 was manufactured.

本発明の実施の形態1に係る発光装置200によれば、III族窒化物系化合物半導体素子100の溝150の側面160にであるジグザグとなる凹凸を形成するため、側面160にて光が拡散され、かつ、側面160の角度α=45度であるため、側面160に到達した光は、拡散されながら全反射し、発光素子のサファイア側へ導かれ、発行素子外へ取り出される。そして、溝150の反対側にも、同じ角度(α=45度)で形成された反射面となるジグザグとなる凹凸面が存在するため、発光面端面から漏れた光が拡散されるため、効率よく発光観測面側に光を取り出すことが可能となる。   According to the light emitting device 200 according to Embodiment 1 of the present invention, light is diffused on the side surface 160 in order to form the zigzag unevenness on the side surface 160 of the groove 150 of the group III nitride compound semiconductor element 100. In addition, since the angle α of the side surface 160 is 45 degrees, the light reaching the side surface 160 is totally reflected while being diffused, guided to the sapphire side of the light emitting element, and extracted outside the issuing element. Further, since there is a zigzag uneven surface serving as a reflection surface formed at the same angle (α = 45 degrees) on the opposite side of the groove 150, light leaked from the end surface of the light emitting surface is diffused. It is possible to extract light to the emission observation surface side well.

なお、実施の形態に示したIII族窒化物系化合物半導体素子100の形状には、特に限らず、例えば、発光素子100に設けられる溝150のジグザクは、波型に置き換えることが出来、溝150側面160の角度αは、45度に限らず、30度以上で50度未満が好ましく、さらに言えば、40度以上45度が好ましい。なぜなら、30度より角度が小さくなると、発光素子での発光面面積が少なくなり、発光面積が稼げなくなる問題点があり、50度を越える角度では、光が全反射しなくなり、発光素子の下側に取り出される恐れがあるためである。
(実施の形態2)
図42に、本発明の実施の形態2に係るIII族窒化物系化合物半導体素子300の模式的な平面図を示す。
Note that the shape of the group III nitride compound semiconductor device 100 shown in the embodiment is not particularly limited. For example, the zigzag of the groove 150 provided in the light emitting element 100 can be replaced with a wave shape. The angle α of the side surface 160 is not limited to 45 degrees, but is preferably 30 degrees or more and less than 50 degrees, and more preferably 40 degrees or more and 45 degrees. This is because if the angle is smaller than 30 degrees, the light emitting surface area of the light emitting element is reduced and the light emitting area cannot be obtained. If the angle exceeds 50 degrees, the light is not totally reflected, and the lower side of the light emitting element. This is because there is a risk of being taken out.
(Embodiment 2)
FIG. 42 shows a schematic plan view of a group III nitride compound semiconductor device 300 according to the second embodiment of the present invention.

III族窒化物系化合物半導体素子300はの周囲の残余部320と中心の島状部分310を連結する連結部330が形成されていることを除きIII族窒化物系化合物半導体素子100と同様に製造した。   The group III nitride compound semiconductor device 300 is manufactured in the same manner as the group III nitride compound semiconductor device 100 except that a connecting portion 330 is formed to connect the remaining portion 320 around the periphery of the group III nitride compound semiconductor device 300 and the central island-shaped portion 310. did.

本発明の実施の形態2に係るIII族窒化物系化合物半導体素子300によれば、連結部分330が形成されるため、同一基板上で形成される多数の発光素子のp層側が素子分離するまで電気的に接続しているため、個々の発光素子となる部分で荷電することがないため、pn界面が静電気破壊されにくい効果がある。   According to the group III nitride compound semiconductor device 300 according to the second embodiment of the present invention, since the connecting portion 330 is formed, until the p-layer side of many light emitting devices formed on the same substrate is separated. Since they are electrically connected, they are not charged at the portions that become individual light emitting elements, and therefore, there is an effect that the pn interface is not easily destroyed by static electricity.

図1は本発明の実施の形態1にかかる半導体発光素子の平面図である。FIG. 1 is a plan view of a semiconductor light emitting element according to a first embodiment of the present invention. 図2は本発明の実施の形態1にかかる半導体発光素子の断面図である。FIG. 2 is a cross-sectional view of the semiconductor light emitting element according to the first embodiment of the present invention. 図3は本発明の実施の形態1にかかる発光装置の断面図である。FIG. 3 is a sectional view of the light emitting device according to the first embodiment of the present invention. 図4は本発明の実施の形態2にかかる半導体発光素子の平面図である。FIG. 4 is a plan view of a semiconductor light emitting element according to the second embodiment of the present invention.

符号の説明Explanation of symbols

100、300 発光素子
120 p電極
140 n電極
150 溝
160 凹凸側面
200 発光装置
100, 300 Light emitting element 120 p electrode 140 n electrode 150 groove 160 uneven surface 200 light emitting device

Claims (5)

発光装置において、
p層、発光層及びn層が積層され、前記p層と電気的に接続しているp電極及び前記n層と電気的に接続しているn電極が同一面に形成さている半導体発光素子と、
前記半導体発光素子は前記p電極及び前記n電極のそれぞれに電気的に接続する回路を有するマウント部材にフリップ実装し、
前記半導体発光素子は、前記p層から前記n層までの斜面を有し、前記斜面は前記発光層から発光した光を拡散させながら発光観測面側に全反射させる表面凹凸構造からなる、
ことを特徴とする発光装置。
In the light emitting device,
p layer, emission layer and n-layer are laminated semiconductor in which the p-layer and the p electrode and the n layer and electrically connected to and n electrodes are electrically connected are formed on the same side A light emitting element;
The semiconductor light emitting element is flip-mounted on a mount member having a circuit electrically connected to each of the p electrode and the n electrode,
The semiconductor light emitting element has an inclined surface from the p layer to the n layer, and the inclined surface has a surface uneven structure that totally reflects the light emitted from the light emitting layer to the light emission observation surface side while diffusing the light .
A light emitting device characterized by that.
前記半導体発光素子の前記斜面は、溝状に形成されていることを特徴とする請求項1記載の発光装置。   The light emitting device according to claim 1, wherein the slope of the semiconductor light emitting element is formed in a groove shape. 前記凹凸構造は、表裏方向に伸びたのこぎり歯状であることを特徴とする請求項1又は2記載の発光装置。   The light emitting device according to claim 1, wherein the concavo-convex structure has a sawtooth shape extending in a front and back direction. 前記n電極は、側面が斜面により形成されたメサ状形状であることを特徴とする請求項1から3のいずれかに記載の発光装置。   4. The light emitting device according to claim 1, wherein the n electrode has a mesa shape with side surfaces formed by inclined surfaces. 5. 前記半導体発光素子の前記斜面は、50度以下30度以上であることを特徴とする請求項1から4のいずれかに記載の発光装置。   The light emitting device according to any one of claims 1 to 4, wherein the slope of the semiconductor light emitting element is 50 degrees or less and 30 degrees or more.
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