JP4450380B2 - Semiconductor integrated circuit with built-in memory - Google Patents

Description

  The present invention relates to a technique effective for use in a semiconductor integrated circuit with a built-in memory (hereinafter referred to as a logic / memory mixed LSI) in which a logic circuit and a memory circuit are mounted on a single semiconductor chip. .

  Conventionally, as a technique for developing a logic / memory mixed LSI that requires a memory with a large storage capacity, a memory power supply generation circuit and a test circuit together with a so-called memory circuit including a peripheral circuit such as a memory array and a decoder having a predetermined storage capacity There is a method of configuring an LSI by designing a so-called memory macro cell including a memory and mounting a required number of the memory macro cells (for example, Japanese Patent Application Laid-Open No. 11-110963, Japanese Patent Application Laid-Open No. 11-96766, Japanese Patent Application Laid-Open No. Issue).

  Employing such a design technique facilitates the design of a logic / memory mixed LSI. Note that the memory power supply generation circuit has a voltage higher than the power supply voltage VDD, such as a word line selection voltage, a data line precharge voltage, a memory cell substrate voltage, and a reference voltage used as a reference for generating these voltages, and a ground potential. This is a circuit that generates a voltage or the like lower than VSS.

  However, in the design method as described above, it is easy to ensure the necessary storage capacity, but there are a plurality of memory power generation circuits and test circuits that are essentially required to be provided in the chip. Therefore, the chip area becomes larger than necessary, and the power consumption increases. Regarding power consumption, power consumption during standby is particularly a problem.

  In addition, if a memory power generation circuit is provided for each memory macrocell, a plurality of memory power generation circuits are distributed on the chip, and a clock generation circuit in each power supply circuit is provided. Since the oscillator circuits operate separately, it is difficult to simulate the circuit operation, and an unfavorable situation may occur such as an unstable operation due to interference.

  Furthermore, if a plurality of memory power generation circuits are distributed on the chip, the reference voltages generated by the reference voltage circuits in each memory power generation circuit are shifted from each other due to manufacturing variations, and the entire chip is desired. It became clear that there was a problem that the operation of could not be expected.

  An object of the present invention is to provide a semiconductor integrated circuit with a built-in memory with a small chip area and low power consumption.

  Another object of the present invention is to provide a semiconductor integrated circuit with a built-in memory that can easily simulate a circuit operation, does not become unstable, and allows the entire chip to perform a desired operation. It is in.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows.

  That is, when developing a semiconductor integrated circuit with a built-in memory, a memory power generation circuit and a memory circuit excluding the power generation circuit are designed as separate macrocells in advance to obtain a desired storage capacity. The number of memory macrocells to be mounted is determined and these are arranged side by side on the chip, and the macrocell including the power generation circuit is arranged as one or two cells common to the plurality of memory macrocells. It is arranged at the end.

  Here, preferably, the memory macro cells are arranged so that the respective word lines are in the same direction. When two power supply macrocells are used, the power supply macrocells are arranged on both the upper and lower sides and the left and right sides so as to sandwich the memory macrocell rows arranged as described above. Further, the power supply macrocell may be provided with a common test circuit for a plurality of memory macrocells.

  According to the above means, a common power supply macrocell is provided for a plurality of memory macrocells, and the voltage generated there is supplied to the memory macrocell. Therefore, a conventional power supply circuit is provided for each memory macrocell. Compared with the method, the chip area is reduced, and the power consumption of the entire chip can be reduced. In addition, since there is one power supply circuit and the same voltage is supplied to each memory macrocell, it is easy to simulate the circuit operation, and the operation does not become unstable due to interference of multiple oscillator signals. There is no fear that the generated voltage varies and the entire chip does not perform a desired operation.

  Also, a wiring for supplying a voltage generated in the power generation circuit from the macro cell comprising the power generation circuit to the memory macro cell (hereinafter referred to as a memory power supply wiring) and a wiring for supplying a signal output from the test circuit (hereinafter referred to as a power supply circuit) (Referred to as DFT signal wiring) is arranged in a region where a guard ring provided at the periphery of the chip is formed in order to prevent moisture from entering. At this time, preferably, the wiring for supplying the reference voltage is arranged so as to be surrounded by the power supply wiring, the DFT signal wiring, etc. arranged in the guard ring region.

  When a memory power supply generation circuit and a test circuit are provided in common for a plurality of memory macrocells, wiring for supplying voltages and signals generated by these circuits is not provided for memory macrocells and logic circuit sections in the conventional general design method. Since it runs above, there is a risk that the area of the original signal line may be narrowed, but by arranging it in the guard ring area, it is possible to avoid the area where the original signal line is arranged from becoming narrow. Further, the wiring for supplying the reference voltage can be shielded by surrounding it with the wiring used for the guard ring, and the reference voltage can be stabilized without providing a separate shielding structure.

FIG. 1 is a block diagram showing an embodiment of a logic / memory mixed LSI to which the present invention is applied. FIG. 2 is a block diagram illustrating a configuration example of the memory macrocell. FIG. 3 is an explanatory diagram showing a first embodiment of a layout configuration of a logic / memory mixed LSI to which the present invention is applied. FIG. 4 is an explanatory diagram showing a second embodiment of the layout configuration of the logic / memory mixed LSI to which the present invention is applied. FIG. 5 is an explanatory diagram showing an example of how to increase the storage capacity in the logic / memory mixed LSI according to the second embodiment. FIG. 6 is an explanatory diagram showing a third embodiment of the layout configuration of the logic / memory mixed LSI to which the present invention is applied. FIG. 7 is an explanatory diagram showing an example of how to increase the storage capacity in the logic / memory mixed LSI of the third embodiment. FIG. 8 is an explanatory diagram showing a fourth embodiment of the layout configuration of the logic / memory mixed LSI to which the present invention is applied. FIG. 9 is an explanatory diagram showing an embodiment in which the present invention is applied to a multichip module. FIG. 10 is an enlarged plan sectional view showing a part of a guard ring region (a corner portion of the chip) where wiring for supplying a voltage from the power source & DFT macro cell to the memory macro cell is formed. FIG. 11 is a sectional side view showing a sectional structure of the guard ring region.

  FIG. 1 shows a block configuration of an embodiment of a logic / memory mixed LSI to which the present invention is applied.

  In FIG. 1, reference numeral 100 denotes a semiconductor chip such as single crystal silicon, 200 denotes a logic circuit portion formed on the semiconductor chip, 300A to 300H denote memory macrocells, and 400 denotes a power supply & DFT macrocell including a power generation circuit and a test circuit. is there. As shown in FIG. 1, in this embodiment, a voltage and a signal generated by one common power source & DFT macro cell 400 are supplied to a plurality of memory macro cells 300A to 300H, respectively. The power supply & DFT macrocell 400 includes a test circuit 410, a reference voltage circuit 420, a VPP generation circuit 430, and a VBB generation circuit 440.

  Each of the memory macrocells 300A to 300H includes one or more memory mats in which a plurality of memory cells are arranged in a matrix, and the selection terminals of the memory cells in the same row are commonly connected to each memory mat. A plurality of word lines (WL) are arranged in parallel to each other, and the data input / output terminals of the memory cells in the same column are connected in common, and the plurality of data lines (DL) are arranged in a direction perpendicular to the word lines. They are arranged in parallel. Since the memory circuit having such a configuration is the same as a memory mat of a general-purpose SRAM or DRAM, illustration and detailed description thereof are omitted.

  The VPP generation circuit 430 includes a charge pump circuit and the like, and generates a plurality of VPP voltages that generate a boosted word line selection voltage VPP such as 3.3 V based on a power supply voltage VDD such as 1.5 V from the outside. The circuit 431, the VPP oscillator 432 that generates a clock signal necessary for the boosting operation of the VPP voltage generation circuit 431, and the VPP voltage generated by the VPP voltage generation circuit 431 and the reference voltage circuit 420, for example, 0.75V And a VPP sensor circuit 433 including an error amplifier that controls the oscillation frequency of the VPP oscillator 432 by comparing with the reference voltage VREF, and generates a VPP voltage having a desired potential based on the reference voltage VREF. It supplies to the macrocells 300A-300H.

  Similarly, the VBB generation circuit 440 includes a charge pump circuit and the like, for example, a plurality of VBB voltage generation circuits 441 that generate a reduced memory substrate voltage VBB such as −0.7 V, and a boost operation of the VBB voltage generation circuit 441. The VBB oscillator 442 that generates an oscillation signal necessary for the VBB, the VBB voltage generated by the VBB voltage generation circuit 441 and the reference voltage VREF supplied from the reference voltage circuit 420 are compared, and the oscillation frequency of the VBB oscillator 442 is controlled. A VBB detection circuit (VBB sensor) 443 composed of an error amplifier or the like is used to generate a VBB voltage having a desired potential based on the reference voltage VREF and supply it to the memory macrocells 300A to 300H.

  Although not shown in FIG. 1, voltages generated by the power source & DFT macrocell 400 and supplied to the memory macrocells 300A to 300H include the voltage VBLR for precharging the data line, the information charge in the memory cell. There is a plate voltage VPL applied to a common electrode called a memory cell plate provided as one terminal of the storage capacitor element, and the voltage generated by the common power source & DFT macro cell 400 is similarly applied to the memory macro cell 300A. ˜300H.

  The memory macrocells 300A to 300H each include a memory mat section 310 in which memory cells are spread, an input / output buffer 311 for inputting / outputting addresses, data, and control signals to / from the logic circuit section 200, and a row for designating a word line WL. A row decoder 312 that decodes an address, a word driver 313 that selectively drives a word line according to a decoding result, a sense amplifier 314 that is connected to the data line DL and amplifies a signal on the data line, and a column that decodes a column address that specifies the data line The decoder 315 includes a main amplifier 316 that amplifies the read signal of the sense amplifier selected by the column decoder 315, a memory control circuit 317 that controls the inside of the memory macrocell, and the like. When the word line is composed of a main word line and a sub word line connected thereto, the word driver 313 is also composed of a main word driver and a sub word driver.

  As shown in FIG. 2, the word line selection voltage VPP is supplied to the word driver 313 in each memory macrocell 300, and the memory cell substrate voltage VBB is supplied to a well region as a substrate of the memory mat 310. Although not shown, the voltage VBLR for precharging the data line is supplied to the sense amplifier 316 and the memory cell plate voltage VPL is supplied to the memory mat 310. Note that the embodiment shown in FIG. 2 shows a concept, and denies that the voltages VPP and VBB generated by the power source & DFT macrocell 400 are supplied to other than the circuit as shown. Not what you want.

  The test circuit 410 generates and supplies a signal for setting a circuit inside the memory macro cell 300 to a state suitable for the test. The DFT signal generated by the test circuit 410 is supplied to most circuits in the memory macrocell 300. Each embodiment of the present invention can also be applied to a case where the test circuit 410 includes an ALPG that generates a test pattern and is configured to be self-testable.

  3 to 9 show layout configurations of the memory / logic mixed LSI of FIG. In the first embodiment of the layout of the logic / memory mixed LSI to which the present invention is applied, as shown in FIG. 3, the logic circuit section 200 is arranged at substantially the center of the chip 100 and both sides thereof are A plurality of memory macrocells 300 are arranged, and the power supply & DFT macrocell 400 is arranged at the end (upper end in the figure) of the chip opposite to the logic circuit unit 200 with one memory macrocell 300A to 300D interposed therebetween. Thereby, the wiring length used for transmission and reception of signals between the logic circuit unit 200 and the memory macro cell 300 is shorter than the layout in which the power supply & DFT macro cell 400 is arranged between the memory macro cell 300 and the logic circuit unit 200. Thus, the delay time of the signal is shortened and high speed operation is possible.

  In this embodiment, in the memory macro cell 300, the internal word line WL is parallel to the arrangement direction of the memory macro cells 300A to 300D (horizontal direction in the figure), and the data line DL is orthogonal to the arrangement direction of the memory macro cells 300A to 300D. Are arranged to be. As a result, the word line WL is orthogonal to the arrangement direction of the memory macrocells 300A to 300D, and the data line DL is arranged between the logic circuit unit 200 and the memory macrocell 300 as compared with the arrangement in which the data line DL is parallel to the arrangement direction of the memory macrocells 300A to 300D. The data input / output line I / O used for signal transmission / reception is shortened, the signal delay time is shortened, and data can be written and read at high speed.

  Furthermore, in this embodiment, a region 500 in which a voltage or signal generated by the power supply & DFT macro cell 400 is provided along the peripheral edge of the chip and a structure called a guard ring for preventing intrusion of moisture or the like is formed. The memory macrocells 300 are configured to be supplied to the memory macrocells 300 by wirings arranged in the memory cells.

  More specifically, a basic wiring is arranged in a ring shape in the guard ring region 500, and a word in the memory macro cell 300 is arranged between wirings arranged on opposite sides (left and right in FIG. 3) of the basic wiring. A plurality of branch wirings 501 are provided in parallel with the line WL, and a voltage or DFT can be applied to a desired location in the memory macrocell 300 through a through hole or a contact hole provided in an appropriate part of the route of the branch wiring 501. A signal is supplied.

  In this way, by adopting a system in which a desired voltage is supplied to each memory macro by the branch wiring 501 arranged in parallel with the word line WL, the signal between the logic circuit unit 200 and the memory macro cell 300 is transmitted. The branch wiring 501 can be provided without reducing the degree of freedom in wiring design of the data input / output line I / O used for transmission / reception. This is because, in a semiconductor integrated circuit employing a multilayer wiring technique, wirings orthogonal to each other are often formed by different conductive layers. In FIG. 3, one wiring for supplying the signal generated by the test circuit 410 to each memory macrocell 300 is shown, but this does not exclude the case of a plurality of signal wirings.

  As described above, in the embodiment of FIG. 3, the common power source & DFT macro cell 400 is provided for the plurality of memory macro cells 300, and the generated voltage is distributed to the memory macro cells 300. Compared to the conventional method in which a power supply circuit and a test circuit are provided for each memory macrocell, the chip area can be reduced and the power consumption of the entire chip can be reduced. In addition, since there is one power supply circuit and the same voltage is supplied to each memory macrocell, it is easy to simulate the circuit operation, and the operation does not become unstable due to interference of multiple oscillator signals. There is no fear that the generated voltage varies and the entire chip does not perform a desired operation.

  Further, since the voltage generated by the power source & DFT macro cell 400 is supplied to each memory macro cell 300 by the wiring 500 arranged in the guard ring region, a signal line for transmitting a signal between the logic circuit unit 200 and the memory macro cell 300 The area is not narrowed. Of the voltages generated in the power source & DFT macrocell 400, the word line selection voltage VPP requires the largest current supply capability. If the wiring for supplying this voltage is long, the voltage may drop due to wiring resistance. However, in the embodiment of FIG. 3, the VPP generation circuit 430 for generating the word line selection voltage VPP is divided into two in the power supply & DFT macrocell 400 provided in a concentrated manner, and the test circuit 410 and the VREF generation circuit are divided. 420 and the VBB generation circuit 440 are arranged on both sides of the circuit. Therefore, the wiring length to the target memory macrocell is the shortest when VPP is fed, and there is an advantage that the voltage drop due to the wiring resistance can be reduced.

  FIG. 4 shows a second embodiment of a layout of a logic / memory mixed LSI to which the present invention is applied. The layout of this embodiment is different from the layout of FIG. 3 in that the VPP generation circuit 430 ′ and the VBB generation circuit 440 ′ are also provided on the opposite side (lower end in the figure) of the chip across the logic circuit portion 200 and the memory macrocell 300. The power source & DFT macro cell 400 ′ having the same voltage and the same type of voltage generated in each power source & DFT macro cell 400 are commonly connected to corresponding ones of the wirings provided in the guard ring region 500. It is a point.

  Note that the VPP generation circuit 430 ′ and the VBB generation circuit 440 ′ receive the reference voltage VREF generated by the VREF generation circuit 420 of the power supply & DFT macrocell 400 on the opposite side (upper end in the figure), and each receive a desired boosted voltage VPP. And VBB. Other configurations are the same as those in FIG.

  As shown in FIG. 4, in this embodiment, there is one VREF generation circuit 420, and boosted voltages VPP and VBB are generated and generated by two power supplies & DFT macrocell 400 based on the same reference voltage VREF. Since the same type of voltage is commonly connected to the same wiring, even if there is a manufacturing variation in the two power supply & DFT macrocells 400, almost the same level of voltage is supplied to each memory macrocell 300. Become. As a result, it becomes possible to avoid a state in which a desired operation cannot be expected as the whole chip. In addition, since the same level of voltage is supplied to each memory macro cell, it is easy to simulate circuit operation, operation does not become unstable due to interference of signals from a large number of oscillators, and the generated voltage varies. There is no fear that the entire chip will not perform a desired operation.

  As shown in FIG. 4, when the VPP generation circuit 430 and the VBB generation circuit 440 are provided on the opposite sides, respectively, the circuits on the opposite sides are controlled so as to perform a boost operation with clocks whose phases are complementary to each other. It is desirable to do. When the booster circuit is configured with a charge pump, the generated voltage will have ripples (pulsations), but the ripple will be reduced by placing the generated voltages whose cycles are mutually complementary in the same wiring. This is because a more stable voltage can be supplied.

  Further, in the embodiment of FIGS. 3 and 4, a plurality of memory macrocells 300 are arranged on the chip such that the word lines are in the same direction. Therefore, when it is desired to increase the storage capacity of the memory built in the chip, the number of word lines of each memory macro cell is increased, or when the memory macro cell is composed of a plurality of memory mats, the memory is arranged in the data line direction. By increasing the number of mats, the power supply & DFT macrocell 400 can be handled without changing.

  That is, there are two methods for increasing the storage capacity of the memory macrocell: a method of increasing the number of word lines (memory rows) and a method of increasing the number of data lines (memory columns), as shown in FIGS. If a memory macrocell with an increased number of data lines is used in the layout, the width of the memory macrocells 300A to 300D and the width of the power supply & DFT macrocell 400 are not matched, resulting in a useless area.

  In order to eliminate such a useless area, it is necessary to redesign the power source & DFT macro cell 400. However, the number of word lines of the memory macro cell is increased or the number of memory mats is increased in the data line direction. In this way, the number of word lines can be increased without changing the power supply & DFT macro cell 400. However, a design method in which the VPP generation circuit 430 and the VBB generation circuit 440 provided in the power supply & DFT macrocell 400 are designed with a large power supply capability in advance, or the number of memory macrocells activated simultaneously is limited. It is necessary to adopt. This is because the load on the power supply circuit increases as the number of word lines increases.

  Note that designing the VPP generation circuit 430 and the VBB generation circuit 440 with a large power supply capability beforehand means that the test is performed in parallel in a plurality of memory macrocells in the test mode in which the test is performed using the test circuit 410 or the like. Therefore, in a chip designed under such a concept, an increase in design burden and an increase in chip area accompanying the application of this embodiment are substantially achieved. It can be regarded as not.

  FIG. 5 shows, as an example, a configuration in which the storage capacity of the entire chip is increased by increasing the number of memory mats of each memory macro cell. In FIG. 5, each of the memory mats is indicated by a symbol MAT, and among these, the one indicated by a broken line is indicated by a memory mat provided in each macro clocell in FIG. What is an increased memory mat. In this way, by increasing the number of memory mats in the data line direction, the length of the memory macro cell column in the word line direction does not change. Therefore, it is not necessary to change the design of the power source & DFT macro cell 400, and the power source & DFT in FIG. The macro cells 400 and 400 ′ can be used as they are.

  FIG. 6 shows a third embodiment of the layout of the logic / memory mixed LSI to which the present invention is applied. The layout of this embodiment is different from the layout of FIG. 4 in that the test circuit 410, the VREF generation circuit 420, and the VPP generation are arranged so as to be orthogonal to the left and right ends of the chip, ie, the word line, across the logic circuit portion 200 and the memory macrocell 300. A power source & DFT macro cell 400 having a circuit 430 and a power source & DFT macro cell 400 ′ having a VPP generation circuit 430 ′ and a VBB generation circuit 440 are provided.

  In this embodiment also, the VPP generation circuit 430 ′ and the VBB generation circuit 440 in the power supply & DFT macro cell 400 ′ are generated by the VREF generation circuit 420 of the power supply & DFT macro cell 400 on the opposite side (right end in the figure). Receiving VREF, it is configured to generate boosted voltages VPP and VBB, respectively. Other configurations are the same as those in FIG.

  The embodiment of FIG. 6 has a configuration in which a plurality of memory macrocells 300 are arranged side by side on a chip so that their word lines are in the same direction, and power supply & DFT macrocells 400 and 400 'are arranged on both sides thereof. Therefore, when it is desired to increase the storage capacity of the memory built in the chip, the number of data lines in each memory macrocell is increased, or when the memory macrocell is composed of a plurality of memory mats, the word line direction is increased. By increasing the number of memory mats or the number of memory macrocells in the arrangement direction of the memory macrocells 300, it is possible to cope without changing the power supply & DFT macrocell 400.

  That is, as described above, there are two methods for increasing the storage capacity of the memory: a method of increasing the number of word lines (memory rows) and a method of increasing the number of data lines (memory columns), as shown in FIG. In such a layout, if the number of word lines in the memory macrocell is increased, the width of the power source & DFT macrocell 400 and the width of the memory macrocell 300 are not matched, resulting in a useless area.

  In order to eliminate such a useless area, it is necessary to redesign the power source & DFT macro cell 400. However, the number of data mats, the number of memory mats in the word line direction, or the arrangement direction of the memory macro cells 300 is not suitable. By increasing the number of memory macrocells, the storage capacity can be increased without changing the power supply & DFT macrocell 400. However, as in the embodiment of FIG. 5, the VPP generation circuit 430 and the VBB generation circuit 440 provided in the power supply & DFT macrocell 400 are designed with a large power supply capability in advance, or are memory macrocells activated simultaneously. It is necessary to adopt a design method that limits the number of

  Note that when the number of data lines in the memory macrocell is increased or the number of mats is increased, it is necessary to redesign the memory macrocell. Therefore, increasing the number of memory macrocells is the method with the least design burden.

  As an example, FIG. 7 shows a configuration in which the storage capacity of the entire chip is increased by increasing the number of memory macrocells in the arrangement direction of the memory macrocells 300. In this way, by increasing the number of memory macrocells in the arrangement direction of the memory macrocells 300, the length of the memory macrocells in the data line direction does not change. Therefore, it is not necessary to change the design of the power supply & DFT macrocell 400, and the power supply of FIG. The & DFT macrocell 400 can be used as it is. However, when each memory macrocell is composed of a plurality of memory mats, even if the number of memory mats in each macrocrocell is increased in the word line direction, the power source & DFT macrocell 400 is not changed in the design. The storage capacity of the built-in memory can be increased.

  Whether the number of memory mats or the number of memory macrocells is increased in order to increase the storage capacity is also related to the original shape of the memory macrocell, that is, the ratio of the length to the length. Specifically, when the length of the memory macrocell in the word line direction is shorter than the length in the data line direction as shown in FIG. 6, the width of the chip does not increase so much even if the number of memory macrocells is increased. If the length of the memory macrocell in the word line direction is longer than the length in the data line direction, increasing the number of memory macrocells may cause the chip width to become extremely long. It is considered better to increase the number of mats.

  Next, another embodiment of the layout of the logic / memory mixed LSI to which the present invention is applied will be described with reference to FIGS. The same circuits and parts as those in FIG.

In the embodiment of FIG. 8, the power supply & DFT macrocell 400 is arranged at one place (a part of the logic circuit unit 200 in the figure) instead of being arranged along the side of the chip. In such a layout, although there is a slight disadvantage that the variation in the length of the power supply line from the VPP generation circuit 430 to each memory macro cell is larger than that in the embodiment of FIG. Since the circuit is provided as a common circuit for the memory macrocell, the chip area can be reduced and the power consumption of the entire chip can be reduced as compared with the conventional method in which the power supply & DFT macrocell is provided for each memory macrocell. In addition, when changing the storage capacity of the memory, whether the direction of the word line or the direction of the data line is changed, it is not necessary to change the power supply & DFT macrocell by redesigning the logic circuit section. An effect is obtained.

  In the embodiment of FIG. 9, the power source & DFT macrocell 400 in the embodiment of FIG. 3 is configured as a separate chip 600 instead of being provided on the logic / memory mixed LSI chip, and is composed of ceramic or the like together with the logic / memory mixed LSI chip 100. The chip is mounted in one package 700, and chips are connected by bonding wires 800 to constitute a multichip module.

  Although this embodiment has a demerit that the resistance of the wiring for supplying a voltage such as VPP to the memory macrocell 300 and the volume of the device are slightly larger than those of the embodiment of FIG. 3, a power supply & DFT macrocell is provided for each memory macrocell. The power consumption of the entire module can be reduced as compared with the conventional method provided, and the chip area can be reduced, so that the chip yield can be improved and the cost can be reduced.

  Next, the structure of the wiring 500 provided in the guard ring region will be described with reference to FIGS. FIG. 10 is an enlarged plan sectional view showing a part of the guard ring region (the corner portion of the chip), FIG. 11 is a diagram showing a sectional structure of the guard ring region, and FIG. 10 is taken along line BB in FIG. FIG. 11 shows a cross section taken along line AA in FIG. 10 and 11, the illustration of the insulating film interposed between the conductive layers constituting the wiring is omitted.

  Reference numeral 510 denotes a guard ring. The guard ring 510 has a plurality of conductive layers 511 to 517 formed so as to be substantially aligned in the height direction, and an edge of the chip on an insulating film between the conductive layers 511 to 517. It is formed in a wall shape by conductors (vias) 521 to 527 filled in contact holes continuously formed in parallel directions, and has a function of preventing moisture and the like from entering from the outside of the chip. A ground potential VSS is applied to the guard ring 510, and the guard ring 510 also serves as a power supply line that applies a substrate potential to the semiconductor chip 100.

  The uppermost conductive layer 537 inside the guard ring 510 and the lower conductive layer 536 are wirings for supplying the word line selection voltage VPP generated by the power supply & DFT macro cell 400 to the memory macro cell. A plurality of wirings 545 formed by a conductive layer immediately below the conductive layer 526 supplying VPP is a wiring for transmitting a signal generated by the DFT circuit, and a wiring 555 inside thereof is generated by the power supply & DFT macrocell 400. This is a wiring for supplying the memory cell substrate voltage VBB to the memory macro cell.

  In the conductive layer immediately below the DFT wiring 545, a wiring 563 to which the ground potential VSS is applied and a wiring 543 for transmitting a signal generated by the DFT circuit are provided. Further, a wiring for supplying the reference voltage VREF generated by the power source & DFT macrocell 400 to the VPP generation circuit 530 and the VBB generation circuit 540 between the VSS wiring 563 and the conductive layer 513 constituting the guard ring 510. 573 is arranged. Under the VREF wiring 573, a conductive layer 512 constituting the guard ring 510 is extended to the lower side of the wiring 573. As described above, the VREF wiring 573 is surrounded by the card ring 510 to which the ground potential VSS is applied, the wiring 563, the extended portion of the conductive layer 512, and further the DFT wirings 543 and 545. Further, it is possible to prevent noise from being applied to the VREF wiring 573 due to the coupling capacitance between the wirings.

  Above the DFT wiring 543 made of the same conductive layer as the VREF wiring 573, there is a wiring 574 for transmitting the voltage VREF generated by the VREF generation circuit formed on the substrate surface to the VREF wiring 573. Is provided. This wiring 574 is connected to diffusion layers 581d and 582d as drain regions of MOSFETs 581 and 582 constituting the VREF generation circuit on the substrate surface through lower conductive layers 575, 576 and 577.

  If a V-shaped cover formed of a conductive layer 514 that is formed of the same conductive layer as the wiring 574 and forms the guard ring 510 is provided above the VREF wiring 573 except for the formation portion of the wiring 574, Desirable results can be obtained for noise prevention. In FIG. 10, reference numeral VIA indicates a via made of a conductor filled in a contact hole connecting the upper and lower wirings, and reference numeral 585 in FIG. 11 indicates fluctuations in the power supply voltage. This is a decoupling capacity for suppression.

  Further, a protective film 590 made of PIQ (polyimide insulating film) is formed on the top of the chip, and supplies the memory macrocell with the voltages VPP and VBB generated by the guard ring 510 and the power source & DFT macrocell 400. The wirings 537, 536, 545, 555, 543, and 542 are arranged so as not to protrude outward from the protective film 590 made of this PIQ. In other words, the protective film 590 is formed to the vicinity of the edge of the chip so as to completely cover the wirings 537, 536, 545, 555, 543, and 542. As a result, it is possible to more reliably prevent the wiring formed in the chip peripheral portion from being damaged during chip assembly.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor.

  For example, in the above embodiment, the memory power generation circuit that generates the voltage supplied to the memory macro cell and the test circuit that generates the test signal are configured as one macro cell. It is also possible to configure the test circuit as a separate macro cell. The present invention can also be applied to an LSI having only a memory power generation circuit and no test circuit.

  Although the case where the present invention is applied to a logic / memory mixed LSI having a logic circuit portion and a memory has been described above, the present invention includes an LSI having an analog circuit in addition to the logic circuit portion and the memory, a memory, and an analog circuit. It can also be used for LSIs.

Claims (5)

A memory integrated semiconductor integrated circuit in which a logic circuit and a plurality of memory macrocells are mounted,
Each of the plurality of memory macrocells includes a memory mat portion having a plurality of memory cells provided at intersections of a plurality of word lines and a plurality of data lines, an address, data including a row address and a column address. And an input / output buffer for inputting / outputting a control signal, a row decoder for decoding the row address designating one of the plurality of word lines, and among the plurality of word lines according to a decoding result of the row decoder A word driver for driving one; a sense amplifier connected to the plurality of data lines for amplifying signals of the plurality of data lines; and a column address for designating a data line included in the plurality of data lines. A column decoder and a read signal of the sense amplifier connected to the data line selected by the column decoder A main amplifier for amplifying, and a control circuit for controlling the memory macro cell,
A memory power generation circuit for generating a voltage required for the plurality of memory macro cells is disposed on a semiconductor substrate as a circuit common to the plurality of memory macro cells,
The voltage generated by the memory power generation circuit is configured to be supplied to each memory macro cell through a wiring formed in a guard ring region provided at a peripheral portion of the semiconductor substrate. A memory integrated semiconductor integrated circuit.   The voltage generated by the memory power generation circuit and supplied to the plurality of memory macrocells is commonly connected to the first voltage that gives the selection level of the word line and the input / output terminals of the memory cells in the same column. 2. The semiconductor integrated circuit with built-in memory according to claim 1, wherein the second integrated voltage is a second voltage for applying a precharge voltage of the data line.   A test circuit that generates a signal to be supplied to each memory macro cell during the test of the memory macro cell is a new memory macro cell that is removed from the memory macro cell, and the test circuit is integrated with the memory power generation circuit. 3. The circuit according to claim 1, wherein a signal generated by the test circuit is supplied to each of the new memory macrocells by a wiring formed in the guard ring region. Any one of the semiconductor integrated circuits with a built-in memory.   The memory power generation circuit includes a reference voltage generation circuit that generates a third voltage serving as a reference for generating the first voltage and the second voltage on any one side of the semiconductor substrate, and the reference voltage generation circuit 4. The semiconductor integrated circuit with built-in memory according to claim 3, wherein the reference voltage generated in step (1) is supplied to the memory power generation circuit on the other side by wiring formed in the guard ring region.   The wiring for supplying the reference voltage is arranged so as to be surrounded by a wiring for supplying a fixed potential formed in the guard ring region and a wiring for supplying a signal generated by the test circuit. Item 5. The semiconductor integrated circuit with built-in memory according to Item 4.

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