JP4302683B2 - Surge absorber - Google Patents

Description

  The present invention relates to a surge absorbing element.

  Semiconductor devices such as ICs and LSIs are destroyed by high-pressure static electricity or their characteristics deteriorate. For this reason, surge absorbing elements such as varistors are used in semiconductor devices as a countermeasure against static electricity.

  By the way, surge absorbing elements such as varistors have a stray capacitance component and a stray induction component. For this reason, if a surge absorber is applied to a circuit that handles high-speed signals, the high-speed signals are deteriorated. In order to apply a surge absorbing element to a circuit that handles a high-speed signal, deterioration of the rising characteristic and delay characteristic of the high-speed signal is inevitable unless the stray capacitance component of the surge absorbing element is reduced. However, if the stray capacitance component of the surge absorbing element is reduced, the control voltage of the surge absorbing element is increased and the energy tolerance is reduced.

A surge absorption element including an inductor and two varistors is known as a surge absorption element that reduces the influence of stray capacitance components (see, for example, Patent Document 1). The surge absorber described in Patent Document 1 includes a parallel circuit including a first varistor and an inductor, a second varistor electrically connected in series to the parallel circuit, a second varistor, and the parallel circuit. Input / output electrodes and ground electrodes connected to both ends of the series circuit.
JP 2001-60838 A

  However, in the surge absorbing element described in Patent Document 1, since the band-pass filter is configured by the stray capacitance of the first varistor and the inductor, it is difficult to achieve impedance matching over a wide band. Therefore, sufficient characteristics cannot be realized for high-speed signals.

  An object of the present invention is to provide a surge absorbing element excellent in impedance matching even for high-speed signals.

  A surge absorbing element according to the present invention includes a first terminal electrode, a second terminal electrode, and a third terminal electrode, and a first inner conductor and a second inner conductor that are coupled with each other in a polarity-inverted manner. One end of the first inner conductor is connected to the first terminal electrode, one end of the second inner conductor is connected to the second terminal electrode, the other end of the first inner conductor and the second inner electrode The inductor connected to the other end of the conductor, the first inner electrode connected to the other end of the first inner conductor and the other end of the second inner conductor, and the third terminal electrode A surge absorber having a second internal electrode, a first DC resistance component connected between the first terminal electrode and the first internal electrode, and greater than the first DC resistance component And a resistance portion having a second DC resistance component connected between the first internal electrode and the second terminal electrode. And features.

  In the surge absorbing element according to the present invention, the inductor portion has a first inner conductor and a second inner conductor that are coupled with each other in a polarity-reversed manner. For this reason, it is possible to cancel the influence of the stray capacitance component by appropriately setting the induction coefficient of the inductor portion with respect to the stray capacitance component of the surge absorbing portion. As a result, an input impedance with a flat frequency characteristic can be realized over a wide band.

  The present invention further includes a resistance section having a first DC resistance component and a second DC resistance component that is larger than the first DC resistance component. As a result, the impedance of the surge absorbing element, in particular, the circuit portion between the surge absorbing part and the second terminal electrode becomes relatively large. For this reason, the circuit portion between the surge absorber and the second terminal electrode is protected against high-frequency components of electrostatic pulses generated when the human body and the terminal of the electronic device are in contact with each other, such as ICs and LSIs. The impedance is relatively higher than that of the element. As a result, when the protected element is connected to the second terminal electrode, the passage of the electrostatic pulse to the protected element can be suppressed, and the electrostatic pulse can be effectively guided to the surge absorbing portion. The protection level of (Electrostatic Discharge) can be increased.

  Preferably, the combined DC resistance component of the first DC resistance component and the second DC resistance component is set to be greater than 0Ω and 7.5Ω or less.

  Incidentally, there is a differential transmission method as one of methods for transmitting digital signals between electronic devices. The differential transmission system is a system in which digital signals in opposite directions are input to a pair of lines, and radiation noise generated from the signal line and external noise can be canceled by differential transmission. Since the noise is reduced by canceling out the external noise, the signal can be transmitted with a small amplitude. Further, since the signal has a small amplitude, the rise and fall times of the signal are shortened, and the signal transmission speed is increased. There is an advantage that is realized.

  Interface standards using this differential transmission method include USB (Universal Serial Bus), IEEE 1394, LVDS (Low Voltage Differential Signaling), DVI (Digital Video Interface), HDMI (High-Definition Multimedia Interface), and the like. Among these, HDMI is an interface that enables transmission of more digital signals, and is a source device (for example, a DVD player or a set-top box) and a sink device (for example, a digital TV or a projector). Etc.) is a high-speed interface that enables transmission of uncompressed digital signals. According to HDMI, a video signal and an audio signal can be transmitted at a high speed with a single cable.

  In a high-speed interface such as HDMI, the structure of the IC itself is becoming vulnerable to ESD in order to achieve high speed. For this reason, the request | requirement of the ESD countermeasure in high-speed transmission system IC is increasing.

  However, when a surge absorbing element as an ESD countermeasure component is inserted into a transmission line, a problem arises in that a signal transmitted through the transmission line, particularly a high frequency (200 MHz or higher) or a high-speed pulse signal is reflected and attenuated. found. This is because when the surge absorbing element is inserted into the transmission line, the characteristic component at the position where the surge absorbing element is inserted in the transmission line is lowered due to the capacitance component of the surge absorbing element, and impedance matching is performed at that position. This is due to the absence. If there is a portion of the transmission line that is not impedance matched, a high frequency component of the signal is reflected at the mismatched portion of the characteristic impedance, resulting in a return loss. As a result, the signal is greatly attenuated. In addition, unnecessary radiation may be generated in the transmission line due to reflection, which may cause noise. In HDMI, the specified value (TDR standard) of the characteristic impedance of the transmission line is defined as 100Ω ± 15% (High-Definition Multimedia Interface Specification Version 1.1).

  From the above, in the differential transmission method in which digital signals in opposite directions are input to a pair of lines, impedance matching is achieved if the characteristic impedance of one line is within the range of 50 ± 7.5Ω. It will be. Therefore, by setting the combined direct current resistance component of the first direct current resistance component and the second direct current resistance component to be greater than 0Ω and equal to or less than 7.5Ω, the surge absorbing element is connected to the transmission line of the differential transmission method such as HDMI. Even when it is inserted, impedance matching can be achieved.

  Preferably, the first DC resistance component is formed by the first inner conductor, and the second DC resistance component is formed by the second inner conductor. In this case, it is not necessary to separately provide a resistor or the like for configuring the resistance portion, the configuration of the element is simplified, and the element can be reduced in size.

  Preferably, the combined DC resistance component of the DC resistance component of the first inner conductor and the DC resistance component of the second inner conductor is set to be greater than 0Ω and 7.5Ω or less. In this case, as described above, impedance matching can be achieved even when a surge absorbing element is inserted into a transmission line of a differential transmission method such as HDMI.

  Preferably, a capacitor portion having a capacitance component connected between the first terminal electrode and the second terminal electrode is further provided. Thereby, it is possible to flexibly set the induction coefficient of the inductor unit and the capacitance of the capacitor component of the capacitor unit with respect to the stray capacitance component of the surge absorbing unit.

  Preferably, the capacitance component of the capacitor unit is formed by the first inner conductor and the second inner conductor. In this case, there is no need to separately provide an internal electrode or the like for constituting the capacitor portion, the structure of the element is simplified, and the element can be reduced in size.

  Preferably, the inductor section is configured by laminating an inductor layer in which the first inner conductor is formed and an inductor layer in which the second inner conductor is formed, and the surge absorbing section is configured by the first inner electrode. The varistor layer formed with the varistor layer formed with the second internal electrode is laminated, and the first internal conductor and the second internal conductor are viewed from the lamination direction of the inductor layer. The first internal electrode and the second internal electrode include regions that overlap each other when viewed from the stacking direction of the varistor layers. In this case, regions overlapping each other when viewed from the lamination direction of the inductor layer in the first inner conductor and the second inner conductor are capacitively coupled, and the above-described capacitance component is formed by the regions. . Thereby, it is not necessary to separately provide an internal electrode or the like for constituting the capacitor portion, the structure of the element is simplified, and the element can be reduced in size. Further, the surge absorbing part can be a varistor.

  More preferably, each varistor layer contains ZnO as a main component, and contains, as an additive, at least one element selected from the group consisting of rare earth and Bi, Co, and each inductor layer contains ZnO as a main component. , Co is not substantially contained. In this case, the element bodies of the varistor layer and the inductor layer are mainly composed of the same material (ZnO). Therefore, even when these are integrally sintered, stress or the like based on the difference in volume change rate of the element body during sintering hardly occurs between the two layers. Thereby, peeling between the surge absorbing portion and the inductor portion is greatly reduced. In addition, the material constituting the inductor layer, that is, the material containing ZnO as a main component and substantially not containing Co is ZnO alone or the constituent material of the varistor layer (ZnO is rare earth or Bi, Co). In comparison with a material having a high dielectric constant and a low dielectric constant. Therefore, an inductor layer including such a material has excellent inductor characteristics.

  Preferably, the first terminal electrode, the second terminal electrode, and the third terminal electrode are formed on the outer surface of the element body including the inductor portion, the surge absorbing portion, and the resistance portion, and the first internal electrode The other end of the conductor, the other end of the second inner conductor, and the first inner electrode are connected through an outer conductor formed on the outer surface of the element body. In this case, the other end of the first inner conductor, the other end of the second inner conductor, and the first inner electrode can be connected easily and reliably.

  Preferably, the first terminal electrode is an input terminal electrode, the second terminal electrode is an output terminal electrode, and the first inner conductor and the second inner conductor are positively coupled.

  Preferably, a plurality of first terminal electrodes, second terminal electrodes, third terminal electrodes, first internal conductors, second internal conductors, first internal electrodes, and second internal electrodes are provided. In this case, an array of surge absorbing elements can be realized.

  ADVANTAGE OF THE INVENTION According to this invention, the surge absorption element excellent in impedance matching also with respect to a high-speed signal can be provided. Further, according to the present invention, the ESD protection level by the surge absorbing element can be increased.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted. In the description, the terms “upper” and “lower” may be used, which correspond to the vertical direction of each figure.

(First embodiment)
First, based on FIG.1 and FIG.2, the structure of surge absorption element SA1 which concerns on 1st Embodiment is demonstrated. FIG. 1 is a schematic perspective view showing a surge absorbing element according to the first embodiment. FIG. 2 is an exploded perspective view for explaining the configuration of the element body included in the surge absorbing element according to the first embodiment.

  As shown in FIG. 1, the surge absorbing element SA1 includes an element body 1, a first terminal electrode 3, a second terminal electrode 5, a third terminal electrode 7, and an external conductor 9. The element body 1 has a rectangular parallelepiped shape. For example, the length is set to about 1 mm, the width is set to about 0.5 mm, and the height is set to about 0.3 mm. The first terminal electrode 3 and the second terminal electrode 5 are respectively formed at end portions in the longitudinal direction of the element body 1. The third terminal electrode 7 and the external conductor 9 are respectively formed on the side surface of the element body 1 so as to face each other. The first terminal electrode 3 functions as an input terminal electrode of the surge absorbing element SA1. The second terminal electrode 5 functions as an output terminal electrode of the surge absorbing element SA1. The third terminal electrode 7 functions as a ground terminal electrode of the surge absorbing element SA1.

  As shown in FIG. 2, the element body 1 includes an inductor portion 10 and a surge absorbing portion 20. The element body 1 has a structure in which the surge absorbing portion 20, the inductor portion 10, and the protective layer 50 are laminated in order from the bottom.

  The inductor section 10 includes a first inner conductor 11 and a second inner conductor 13 that are coupled to each other with the polarity reversed. The inductor section 10 is configured by laminating an inductor layer 15 in which the first inner conductor 11 is formed and an inductor layer 17 in which the second inner conductor 13 is formed.

  One end of the first inner conductor 11 is drawn out to one side of the inductor layer 15 so as to be exposed on one end face (end face on which the first terminal electrode 3 is formed) of the element body 1. One end of the first inner conductor 11 is physically and electrically connected to the first terminal electrode 3. One end of the second inner conductor 13 is drawn out to one side of the inductor layer 17 so as to be exposed at the other end face of the element body 1 (end face on which the second terminal electrode 5 is formed). One end of the second inner conductor 13 is physically and electrically connected to the second terminal electrode 5. The other end of the first inner conductor 11 and the other end of the second terminal electrode 5 are exposed on the same side surface of the element body 1 (side surface on which the outer conductor 9 is formed) of the inductor layers 15 and 17. Each is pulled out to one side. The other end of the first inner conductor 11 and the other end of the second terminal electrode 5 are physically and electrically connected to the outer conductor 9 formed on the side surface of the element body 1. The other end of the first inner conductor 11 and the other end of the second terminal electrode 5 are electrically connected through the outer conductor 9.

  The first inner conductor 11 and the second inner conductor 13 include regions 11a and 13a that overlap each other when viewed from the stacking direction of the inductor layers 15 and 17, respectively. The first inner conductor 11 and the second inner conductor 13 are capacitively coupled in the regions 11a and 13a. The first inner conductor 11 and the second inner conductor 13 may be connected not by the outer conductor 9 as described above but by a through-hole conductor or the like formed inside the element body 1. Although it does not specifically limit as a electrically conductive material contained in the 1st inner conductor 11 and the 2nd inner conductor 13, It is preferable to consist of Pd or an Ag-Pd alloy.

  Each inductor layer 15 and 17 is made of a ceramic material mainly composed of ZnO. The ceramic material constituting the inductor layers 15 and 17 may contain a metal element such as rare earth (for example, Pr), K, Na, Cs, and Rb in addition to ZnO. Among these, it is particularly preferable to add a rare earth. By adding rare earth, the difference in volume change rate between the inductor layers 15 and 17 and the varistor layers 25 and 27 described later can be easily reduced. In addition, the inductor layers 15 and 17 may further contain Cr, Ca, or Si for the purpose of improving the bondability with the surge absorber 20 described later. These metal elements contained in the inductor layers 15 and 17 can exist in various forms such as simple metals and oxides. A preferable content of the additive contained in the inductor layers 15 and 17 is preferably 0.02 mol% or more and 2 mol% or less in the total amount of ZnO contained in the inductor layers 15 and 17. The content of these metal elements can be measured using, for example, an inductively coupled high frequency plasma emission spectrometer (ICP).

  Each inductor layer 15 and 17 is substantially free of Co contained in varistor layers 25 and 27 described later. Here, the “substantially not contained” state refers to a state in which these elements are not intentionally contained as raw materials when the inductor layers 15 and 17 are formed. For example, when these elements are included unintentionally due to diffusion from the surge absorbing portion 20 to the inductor portion 10 or the like, this corresponds to a “substantially not contained” state. Note that the inductor layers 15 and 17 may further contain other metal elements or the like for the purpose of further improving characteristics as long as the above-described conditions are satisfied.

  The surge absorber 20 includes a first internal electrode 21 and a second internal electrode 23. The surge absorber 20 is configured by laminating a varistor layer 25 in which a first internal electrode 21 is formed and a varistor layer 27 in which a second internal electrode 23 is formed.

  The first internal electrode 21 has a straight line type pattern and extends along the short side direction of the varistor layer 25. One end of the first internal electrode 21 is drawn out to one side of the varistor layer 25 so as to be exposed on the side surface (side surface on which the external conductor 9 is formed) of the element body 1. The other end of the first internal electrode 21 is not exposed on the side surface (side surface on which the third terminal electrode 7 is formed) of the element body 1 and is in a position drawn from the side surface. One end of the first inner electrode 21 is physically and electrically connected to the outer conductor 9 formed on the side surface of the element body 1. The other end of the first inner conductor 11, the other end of the second inner conductor 13, and one end of the first inner electrode 21 are electrically connected through the outer conductor 9.

  The second internal electrode 23 has a straight line type pattern and extends along the short direction of the varistor layer 27. One end of the second internal electrode 23 is drawn to one side of the varistor layer 27 so as to be exposed on the side surface of the element body 1 (the side surface on which the third terminal electrode 7 is formed). The other end of the second internal electrode 23 is not exposed on the side surface (side surface on which the external conductor 9 is formed) of the element body 1 and is in a position drawn from the side surface. One end of the second internal electrode 23 is physically and electrically connected to the third terminal electrode 7 formed on the side surface of the element body 1.

  The first internal electrode 21 and the second internal electrode 23 include regions 21 a and 23 a that overlap each other when viewed from the stacking direction of the varistor layers 25 and 27. Accordingly, the regions 21 a and 23 a overlapping the first internal electrode 21 and the second internal electrode 23 in the varistor layers 25 and 27 function as regions that develop the varistor 63 characteristics. Although it does not specifically limit as a electrically conductive material contained in the 1st internal electrode 21 and the 2nd internal electrode 23, It is preferable to consist of Pd or an Ag-Pd alloy.

  Each varistor layer 25, 27 is made of a ceramic material mainly composed of ZnO. This ceramic material further contains, as an additive, at least one element selected from the group consisting of rare earths and Bi, Co. Here, since the varistor layers 25 and 27 contain Co in addition to the rare earth, the varistor layers 25 and 27 have excellent voltage nonlinear characteristics, that is, varistor characteristics, and also have a high dielectric constant (ε). In other words, since the inductor layers 15 and 17 described above do not contain Co, they do not have varistor characteristics, have a low dielectric constant, and have a high resistivity, so that they are extremely suitable as a constituent material for the inductor section 10. It has special characteristics. The ceramic material constituting the varistor layers 25 and 27 may further contain Al as an additive. When Al is included, the varistor layers 25 and 27 have low resistance. The rare earth contained as an additive is preferably Pr.

  These additive metal elements can be present in the form of simple metals or oxides in the varistor layers 25 and 27. The varistor layers 25 and 27 may further contain metal elements other than those described above (for example, Cr, Ca, Si, K, etc.) as additives for the purpose of further improving the characteristics.

  The first inner conductor 11 has a first DC resistance component. The first DC resistance component is inserted between the first terminal electrode 3 and the first internal electrode 21. That is, the first DC resistance component is connected between the first terminal electrode 3 and the first internal electrode 21, one end of which is electrically connected to the first terminal electrode 3 and the other end is connected. It is electrically connected to the first internal electrode 21.

  The second inner conductor 13 has a second DC resistance component. The second DC resistance component is inserted between the first internal electrode 21 and the second terminal electrode 5. That is, the second DC resistance component is connected between the first internal electrode 21 and the second terminal electrode 5, one end of which is electrically connected to the first internal electrode 21 and the other end is connected. It is electrically connected to the second terminal electrode 5.

  The second DC resistance component of the second inner conductor 13 is set to be larger than the first DC resistance component of the first inner conductor 11. The combined DC resistance component of the first DC resistance component and the second DC resistance component is set to be greater than 0Ω and 7.5Ω or less. In the present embodiment, the first DC resistance component of the first inner conductor 11 is set to about 0.5Ω, and the second DC resistance component of the second inner conductor 13 is about 4.5Ω. Is set. Therefore, the combined DC resistance component of the first DC resistance component and the second DC resistance component is about 5Ω.

  The protective layer 50 is a layer made of a ceramic material, and protects the inductor unit 10. The constituent material of the protective layer 50 is not particularly limited, and various ceramic materials and the like can be applied. However, a material containing ZnO as a main component is preferable from the viewpoint of reducing peeling from the above-described laminated structure.

  The first terminal electrode 3, the second terminal electrode 5, the third terminal electrode 7, and the outer conductor 9 are electrically connected to a metal such as Pd constituting the inner conductors 11 and 13 and the inner electrodes 21 and 23. It is preferable that it consists of a metal material which can be connected well. For example, Ag has good electrical connectivity with the internal conductors 11 and 13 and the internal electrodes 21 and 23 made of Pd, and also has good adhesion to the end face of the element body 1. It is suitable as a material.

  On the surfaces of the first terminal electrode 3, the second terminal electrode 5, the third terminal electrode 7, and the outer conductor 9, a Ni plating layer (not shown), a Sn plating layer (not shown), and the like are sequentially formed. Yes. These plated layers are formed mainly for the purpose of improving solder heat resistance and solder wettability when the surge absorbing element SA1 is mounted on a substrate or the like by solder reflow.

  Next, a circuit configuration of the surge absorbing element SA1 having the above-described configuration will be described with reference to FIGS. FIG. 3 is a diagram for explaining a circuit configuration of the surge absorbing element according to the first embodiment. FIG. 4 is a diagram showing an equivalent circuit of the circuit configuration shown in FIG.

  As described above, the first inner conductor 11 and the second inner conductor 13 include regions 11a and 13a that overlap each other when viewed from the stacking direction of the inductor layers 15 and 17, respectively. Are capacitively coupled. For this reason, the surge absorbing element SA1 has a capacitive component 61 formed by the first inner conductor 11 and the second inner conductor 13, as shown in FIG. The capacitive component 61 is connected between the first terminal electrode 3 and the second terminal electrode 5.

  The first inner conductor 11 has an inductance component and a first DC resistance component 62a connected in series. The second inner conductor 13 has an inductance component and a second DC resistance component 62b connected in series. Thereby, as shown in FIG. 3, the surge absorbing element SA1 has a DC resistance component 62 (first DC resistance component 62a and second DC resistance component 62 formed by the first inner conductor 11 and the second inner conductor 13). Of the DC resistance component 62b). The DC resistance component 62 is electrically connected between the first terminal electrode 3 and the second terminal electrode 5. As described above, the second DC resistance component 62b is larger than the first DC resistance component 62a.

  Here, “polarity reversal coupling” means that the winding start of the inductance component corresponding to the first inner conductor 11 is the first terminal electrode 3 side, as shown in FIG. When the winding start of the corresponding inductance component is on the side connected to the first inner conductor 11 (in this embodiment, the outer conductor 9 side), the first inner conductor 11 and the second inner conductor 13 It means that the bond is “positive”. That is, “polarity reversal coupling” means that a current flows into the first inner conductor 11 from the first terminal electrode 3 side, and the second inner conductor 13 is connected to the first inner conductor 11 (this embodiment). In FIG. 5, current flows from the outer conductor 9 side), and means that the magnetic flux generated in the first inner conductor 11 and the magnetic flux generated in the second inner conductor 13 are strengthened to each other.

  In the surge absorber SA1, the first internal electrode 21, the second internal electrode 23, and the regions 21a and 23a overlapping the first internal electrode 21 and the second internal electrode 23 in the varistor layers 25 and 27 are included. One varistor 63 is formed. As shown in FIG. 3, the varistor 63 is electrically connected between a connection point (the outer conductor 9) between the first inner conductor 11 and the second inner conductor 13 and the third terminal electrode 7. Connected.

  As shown in FIG. 4, the first inner conductor 11 and the second inner conductor 13 that are coupled to each other with the polarity reversed are connected to each other by a first inductance component 65, a second inductance component 67, and a third inductance component 69. Can be converted to The first inductance component 65 and the second inductance component 67 are connected in series between the first terminal electrode 3 and the second terminal electrode 5. The third inductance component 69 is connected between a connection point between the first inductance component 65 and the second inductance component 67 connected in series and the varistor 63. When the induction coefficient of each of the inner conductors 11 and 13 is Lz and the coupling coefficient between the inner conductors 11 and 13 is Kz, the induction coefficients of the first inductance component 65 and the second inductance component 67 are (1 + Kz) Lz, The induction coefficient of the third inductance component 69 is −KzLz.

  As shown in FIG. 4, the varistor 63 can convert the variable resistor 71 and the stray capacitance component 73 connected in parallel between the third inductance component 69 and the third terminal electrode 7. The variable resistor 71 normally has a large resistance value, and the resistance value decreases when a high voltage surge is applied. In the varistor 63, a high-speed signal with a small amplitude can be approximated only by the stray capacitance component 73.

The input impedance Zin of the surge absorbing element SA1 shown in FIG. 4 is expressed by the following equation (1). Here, the capacitance of the capacitance component 61 is Cs, and the capacitance of the stray capacitance component 73 of the varistor 63 is Cz. Since the direct current resistance has little influence on the impedance, formulas for the capacitance component and the inductance component are considered.

上記（２）式及び（３）式からも分かるように、内部導体１１，１３間の結合係数Ｋｚを任意に選べるため、柔軟性の高い回路設計が可能となる。 In the equation (1), if the capacitance Cs of the capacitance component 61 is set so as to satisfy the following equation (2), the input impedance Zin does not depend on the frequency characteristics. When the capacitance Cs of the capacitance component 61 is set to the following equation (2) and the induction coefficient Lz of each internal conductor is set as shown in the following equation (3), the input impedance Zin is matched with the characteristic impedance Zo. Can do.

As can be seen from the above equations (2) and (3), the coupling coefficient Kz between the inner conductors 11 and 13 can be arbitrarily selected, so that a highly flexible circuit design is possible.

  Therefore, according to the present embodiment, the surge absorbing element SA1 can be a surge absorbing element that is excellent in impedance matching even for high-speed signals while protecting a semiconductor device or the like from high-voltage static electricity.

  Incidentally, the varistor 63 also includes a stray inductance component 75 as shown in FIG. Normally, the resistance value of the variable resistor 71 is large, and the resistance value decreases when a high voltage surge is applied. However, the stray capacitance component 73 and the stray inductance component 75 exist. For this reason, when the surge absorbing element SA1 is added to the input side of a semiconductor device that handles a high-speed signal as an input signal, it causes deterioration of the high-speed signal. In order to apply the surge absorbing element SA1 to a circuit that handles high-speed signals, it is preferable to reduce the influence of not only the stray capacitance component 73 but also the stray inductance component 75.

ただし、ＫｚＬｚ≧Ｌｅである。このように設計すると、サージ吸収素子ＳＡ１に浮遊容量成分７３と浮遊インダクタンス成分７５が含まれていても、入力インピーダンスＺｉｎを特性インピーダンスＺｏに整合させることができる。 As can be seen from the equivalent circuit shown in FIG. 4, the floating inductance component 75 of the varistor 63 can be canceled by using the third inductance component 69 having a negative induction coefficient. However, since it appears to be the same as the state where the coupling is reduced, the coupling coefficient Kz and the induction coefficient Lz are left as they are, and the capacitance Cs of the capacitive component 61 is expressed by the following equation (4). Here, the induction coefficient of the floating inductance component 75 is Le.

However, KzLz ≧ Le. With this design, even if the surge absorbing element SA1 includes the stray capacitance component 73 and the stray inductance component 75, the input impedance Zin can be matched with the characteristic impedance Zo.

  Next, a method for manufacturing the surge absorbing element SA1 according to the first embodiment will be described with reference to FIG. FIG. 6 is a flowchart for explaining a process of manufacturing the surge absorbing element according to the first embodiment.

  In manufacturing the surge absorbing element SA1, first, a paste containing a ceramic material as a raw material for the inductor layers 15 and 17 and the varistor layers 25 and 27 is manufactured (step S101). Specifically, the paste for forming the varistor layers 25 and 27 has at least one element selected from the group consisting of rare earths (for example, Pr) and Bi as an additive with respect to ZnO as a main component, in addition to Co. If necessary, it can be prepared by adding Al, Cr, Ca, Si, K or the like so as to have a desired content after firing, and adding and mixing these binders. The metal element in this case can be added as an oxide, for example.

  The paste for forming the inductor layers 15 and 17 is made by adding a metal element such as rare earth or Bi as an additive to ZnO as a main component, and further adding and mixing a binder or the like as necessary. It can be prepared. Unlike the paste for forming the varistor layers 25 and 27, Co is not added to the paste for forming the inductor layers 15 and 17. The said metal element can be added with the form of compounds, such as an oxide, an oxalate, and carbonate, for example. These addition amounts are adjusted so that the metal element has the desired content as described above in the element body 1 after firing as described later.

  These pastes are applied on a plastic film or the like by a doctor blade method or the like and then dried to form a green sheet made of a ceramic material (step S102). Thus, the required number of green sheets for forming inductor layers 15 and 17 (hereinafter referred to as “inductor sheets”) and green sheets for forming varistor layers 25 and 27 (hereinafter referred to as “varistor sheets”) are respectively obtained. Get one by one. In the formation of the green sheet, the plastic film or the like may be peeled off from each sheet immediately after application and drying, or may be peeled off immediately before lamination as will be described later. In this green sheet forming step, together with these sheets, a green sheet for forming the protective layer 50 containing ZnO is formed by the same method as described above.

  Next, a conductor paste for forming the first and second inner conductors 11 and 13 or the first and second inner electrodes 21 and 23 on the inductor sheet or the varistor sheet is applied to each sheet. Screen printing is performed to obtain a desired pattern (step S103). Thereby, each sheet provided with a conductive paste layer having a desired pattern is obtained. Here, the first and second inner conductors 11 and 13 obtained by firing the conductor paste layer having a desired pattern for obtaining the first and second inner conductors 11 and 13 in a later step. Are formed so as to have the desired DC resistance component described above. Examples of the conductor paste include a conductor paste containing Pd or an Ag—Pd alloy as a main component.

  Subsequently, the varistor sheets provided with the conductive paste layers respectively corresponding to the first and second internal electrodes 21 and 23 are sequentially laminated (step S104). Subsequently, an inductor sheet provided with a conductive paste layer corresponding to each of the first and second inner conductors 11 and 13 is sequentially laminated thereon (step S105). Further, a green sheet for forming the protective layer 50 is further stacked on these laminated structures, and these are pressure-bonded to obtain a laminated body that is a precursor of the element body 1.

  Thereafter, the obtained laminate is cut into chips so as to have a desired size, and then the chip is baked at a predetermined temperature (for example, 1000 to 1400 ° C.) to obtain the element body 1 (step S106). ). Subsequently, Li is diffused from the surface of the obtained element body 1 to the inside thereof. Here, a Li compound is attached to the surface of the obtained element body 1 and then heat treatment or the like is performed. A sealed rotating pot can be used for adhesion of the Li compound. The Li compound is not particularly limited, but Li diffuses from the surface of the element body 1 to the vicinity of the first and second inner conductors 11 and 13 and the first and second inner electrodes 21 and 23 by heat treatment. Examples of such compounds include Li oxides, hydroxides, chlorides, nitrates, borates, carbonates, and oxalates. Note that this Li diffusion step is not necessarily required in manufacturing the surge absorbing element SA1.

  Then, after transferring the paste containing silver as a main component to the side surface of the Li diffused element body 1 and baking it, the first terminal electrode 3, the second terminal electrode 5, The third terminal electrode 7 and the external conductor 9 are respectively formed to obtain the surge absorbing element SA1 (step S107). The plating can be performed by electroplating. For example, Cu and Ni and Sn, Ni and Sn, Ni and Au, Ni and Pd and Au, Ni and Pd and Ag, or Ni and Ag can be used. .

  As described above, in the first embodiment, the inductor unit 10 includes the first inner conductor 11 and the second inner conductor 13 that are coupled to each other by polarity inversion. For this reason, it is possible to cancel the influence of the stray capacitance component 73 by appropriately setting the induction coefficient of the inductor portion 10 with respect to the stray capacitance component 73 of the surge absorber 20. As a result, an input impedance with a flat frequency characteristic can be realized over a wide band.

  Further, the first embodiment further includes a resistance unit having a first DC resistance component 62a and a second DC resistance component 62b that is larger than the first DC resistance component 62a. Thereby, the impedance of the circuit portion between the surge absorbing element SA1, in particular, the surge absorbing portion 20 (varistor 63) and the second terminal electrode 5 becomes relatively large. For this reason, the circuit portion between the surge absorber 20 (varistor 63) and the second terminal electrode 5 is designed to prevent high frequency components of electrostatic pulses generated when the human body and the terminal of the electronic device are in contact with each other. And a relatively higher impedance than the protected element such as LSI. As a result, when a protected element is connected to the second terminal electrode 5, the passage of the electrostatic pulse to the protected element can be suppressed, and the electrostatic pulse can be effectively guided to the surge absorber 20 (varistor 63). The protection level of ESD (Electrostatic Discharge) by the surge absorbing element can be increased.

  In the first embodiment, the combined DC resistance component of the first DC resistance component 62a and the second DC resistance component 62b is set to be greater than 0Ω and 7.5Ω or less. Accordingly, impedance matching can be achieved even when the surge absorbing element SA1 is inserted into a transmission line of a differential transmission method such as HDMI.

  In the first embodiment, the first DC resistance component 62 a is formed by the first inner conductor 11, and the second DC resistance component 62 b is formed by the second inner conductor 13. In this case, it is not necessary to separately provide a resistor or the like for configuring the resistance portion, the configuration of the element SA1 can be simplified, and the element SA1 can be reduced in size. In the first embodiment, the combined DC resistance component of the first DC resistance component 62a of the first inner conductor 11 and the second DC resistance component 62b of the second inner conductor 13 is greater than 0Ω. .5Ω or less is set.

  In the first embodiment, a capacitor unit having a capacitance component 61 is further provided. Thereby, the induction coefficient of the inductor unit 10 and the capacitance of the capacitance component 61 of the capacitor unit 40 can be set flexibly with respect to the stray capacitance component 73 of the surge absorbing unit 20.

  The surge absorbing element SA1 of the first embodiment can be a surge absorbing element SA1 that is more excellent in impedance matching for high-speed signals while protecting semiconductor devices and the like from high-voltage static electricity.

  In the first embodiment, the capacitance component 61 included in the capacitor unit 40 is formed by the first inner conductor 11 and the second inner conductor 13. Accordingly, it is not necessary to separately provide an internal electrode or the like for configuring the capacitor unit 40, the configuration of the device is simplified, and the device can be reduced in size.

  In the first embodiment, the inductor section 10 is configured by laminating an inductor layer 15 in which the first inner conductor 11 is formed and an inductor layer 17 in which the second inner conductor 13 is formed. The one inner conductor 11 and the second inner conductor 13 include regions 11 a and 13 a that overlap each other when viewed from the stacking direction of the inductor layers 15 and 17. Thereby, in the first inner conductor 11 and the second inner conductor 13, the regions 11 a and 13 a overlapping each other when viewed from the lamination direction of the inductor layers 15 and 17 are capacitively coupled, and the regions 11 a and 13 a The capacitive component 61 described above is formed. Accordingly, it is not necessary to separately provide an internal electrode or the like for configuring the capacitor portion, the configuration of the surge absorbing element SA1 can be simplified, and the surge absorbing element SA1 can be downsized.

  In the first embodiment, the surge absorber 20 is configured by laminating a varistor layer 25 in which a first internal electrode 21 is formed and a varistor layer 27 in which a second internal electrode 23 is formed, The first internal electrode 21 and the second internal electrode 23 include regions that overlap each other when viewed from the stacking direction of the varistor layers 25 and 27. Thereby, the surge absorber 20 can be constituted by the varistor 63.

  In the first embodiment, the inductor layers 15 and 17 constituting the inductor portion 10 and the varistor layers 25 and 27 constituting the surge absorbing portion 20 are both made of a ceramic material mainly composed of ZnO. For this reason, the difference of the volume change which arises at the time of baking is very small in the inductor part 10 and the surge absorption part 20. FIG. Therefore, even if these are fired at the same time, it is difficult for strain or stress to occur between them. As a result, the obtained surge absorbing element SA1 is extremely unlikely to peel off compared to the conventional surge absorbing element SA1 in which the inductor portion 10 and the surge absorbing portion 20 are formed of different materials.

  As described above, the inductor layers 15 and 17 are made of a ceramic material containing ZnO as a main component and substantially not containing Co as an additive. Such a material has a resistivity sufficiently high as a constituent material of the inductor. Specifically, it tends to have a resistivity exceeding 1 MΩ suitable as an inductor material. For this reason, the inductor unit 10 can exhibit excellent inductor characteristics despite containing ZnO as a main component, which is insufficient in terms of resistivity by itself.

  In the first embodiment, the other end of the first inner conductor 11, the other end of the second inner conductor 13, and the first inner electrode 21 are connected through the outer conductor 9. Thereby, the other end of the 1st internal conductor 11, the other end of the 2nd internal conductor 13, and the 1st internal electrode 21 can be connected easily and reliably.

  There are the following methods for adjusting the first DC resistance component 62a of the first inner conductor 11 and the second DC resistance component 62b of the second inner conductor 13 to the desired values described above. The width, thickness, line length, etc. of the first and second inner conductors 11 and 13 are adjusted. The resistivity is adjusted by selecting a metal material contained in the conductor paste for forming the first and second inner conductors 11 and 13. The density of the first and second inner conductors 11 and 13 is adjusted by adjusting the blending ratio of the metal material contained in the conductor paste or by adjusting the particle size of the metal material.

(Second Embodiment)
Next, based on FIG.7 and FIG.8, the structure of surge absorber SA2 which concerns on 2nd Embodiment is demonstrated. FIG. 7 is a schematic perspective view showing the surge absorbing element according to the second embodiment. FIG. 8 is an exploded perspective view for explaining the configuration of the element body included in the surge absorbing element according to the second embodiment. The surge absorber SA2 according to the second embodiment includes a first terminal electrode 3, a second terminal electrode 5, a third terminal electrode 7, a first inner conductor 11, a second inner conductor 13, and a first terminal electrode 3. The number of internal electrodes 21, second internal electrodes 23, and external conductors 9 is different from the surge absorbing element SA1 according to the first embodiment.

  As shown in FIG. 7, the surge absorbing element SA2 includes an element body 1. The element body 1 has a rectangular parallelepiped shape. For example, the length is set to about 1.4 mm, the width is set to about 1.0 mm, and the height is set to about 0.5 mm. The surge absorbing element SA2 includes a plurality (two in the present embodiment) of the first terminal electrode 3, the second terminal electrode 5, the third terminal electrode 7, and the external conductor 9, respectively. The first terminal electrode 3, the second terminal electrode 5, and the third terminal electrode 7 are formed on the side surface of the element body 1 so as to face each other. The outer conductors 9 are respectively formed at the ends of the element body 1 in the longitudinal direction.

  As shown in FIG. 8, the inductor section 10 has a plurality of first internal conductors 11 and a plurality of second internal conductors 13 (two in the present embodiment) that are coupled to each other in a reverse polarity. . The first inner conductors 11 are spaced apart from each other on the inductor layer 15 so as to be electrically insulated from each other. The second inner conductors 13 have a predetermined interval on the inductor layer 17 so as to be electrically insulated from each other.

  The DC resistance component of each second inner conductor 13 is larger than the DC resistance component of each first inner conductor 11. The combined DC resistance component of the DC resistance component of each first inner conductor 11 and the DC resistance component of each second inner conductor 13 is set to be greater than 0Ω and 7.5Ω or less. In the surge absorbing element SA2, the inductor unit 10 has a DC resistance component that is greater than 0Ω and equal to or less than 15Ω. In the present embodiment, the DC resistance component of each first inner conductor 11 is set to about 0.5Ω, and the DC resistance component of each second inner conductor 13 is also set to about 4.5Ω. Therefore, in the surge absorbing element SA2, the inductor unit 10 has a DC resistance component of about 10Ω.

  As shown in FIG. 8, the surge absorber 20 includes a plurality of first internal electrodes 21 and a plurality of second internal electrodes 23 (two in the present embodiment).

  The first internal electrodes 21 are spaced apart from each other on the varistor layer 25 so as to be electrically insulated from each other. Each first internal electrode 21 includes a first electrode portion 31 and a second electrode portion 33. The first electrode portion 31 overlaps with a first electrode portion 35 of a second internal electrode 23 described later when viewed from the stacking direction of the varistor layers 25 and 27. The first electrode portion 31 has a substantially rectangular shape. The second electrode portion 33 is drawn out from the first electrode portion 31 so as to be exposed on the side surface (side surface on which the external conductor 9 is formed) of the element body 1 and functions as a lead conductor. Each first electrode portion 31 is electrically connected to the outer conductor 9 through the second electrode portion 33. The second electrode portion 33 is formed integrally with the first electrode portion 31.

  Each second internal electrode 23 includes a first electrode portion 35 and a second electrode portion 37. The first electrode portion 35 is formed so as to overlap the first electrode portion 31 of the first internal electrode 21 when viewed from the stacking direction of the varistor layers 25 and 27. The first electrode portions 35 each have a substantially rectangular shape. The second electrode portions 37 are respectively drawn out from the first electrode portions 35 so as to be exposed on both side surfaces (both side surfaces on which the third terminal electrodes 7 are formed) of the element body 1. Function. Each first electrode portion 35 is electrically connected to the second terminal electrode 5 through the second electrode portion 37. The second electrode portion 37 is formed integrally with the first electrode portion 35.

  As shown in FIG. 9, the second internal electrodes 23 may have a predetermined interval on the varistor layer 27 so as to be electrically insulated from each other. In this case, as shown in FIG. 8, each second electrode portion 37 is exposed from each first electrode portion 35 to the side surface of the element body 1 (the side surface on which the third terminal electrode 7 is formed). Respectively.

  In the surge absorber 20, the first electrode portion 31, the first electrode portion 35, and the region overlapping the first electrode portion 31 and the first electrode portion 35 in the varistor layers 25 and 27, provide one A varistor will be constructed.

  As described above, also in the second embodiment, as in the first embodiment, the semiconductor device and the like can be protected from high-voltage static electricity, and impedance matching for high-speed signals can be further improved.

  Also in the second embodiment, similarly to the first embodiment, the passage of the electrostatic pulse to the protected element can be suppressed, and the electrostatic pulse can be effectively guided to the surge absorber 20 (varistor 63). The ESD protection level by the surge absorbing element SA2 can be increased.

  In the second embodiment, the first terminal electrode 3, the second terminal electrode 5, the third terminal electrode 7, the first inner conductor 11, the second inner conductor 13, the first inner electrode 21, And a plurality of second internal electrodes 23. Thereby, the surge absorbing element SA2 in the form of an array can be realized.

(Third embodiment)
Next, based on FIG. 10, the structure of the surge absorption element which concerns on 3rd Embodiment is demonstrated. FIG. 10 is an exploded perspective view for explaining the configuration of the element body included in the surge absorbing element according to the third embodiment. The surge absorbing element according to the third embodiment is different from the surge absorbing element SA1 according to the first embodiment with respect to the configuration of the capacitor unit 40.

  The surge absorbing element of the third embodiment is similar to the surge absorbing element SA1 shown in FIG. 1, and the element body 1, the first terminal electrode 3, the second terminal electrode 5, the third terminal electrode 7, and the external A conductor 9 is provided. As shown in FIG. 10, the element body 1 includes an inductor portion 10, a surge absorbing portion 20, and a capacitor portion 40. The element body 1 has a structure in which the surge absorbing portion 20, the inductor portion 10, the capacitor portion 40, and the protective layer 50 are laminated in order from the bottom.

  The DC resistance component of each second inner conductor 13 is larger than the DC resistance component of each first inner conductor 11. The combined DC resistance component of the DC resistance component of each first inner conductor 11 and the DC resistance component of each second inner conductor 13 is set to be greater than 0Ω and 7.5Ω or less. In the surge absorbing element according to the third embodiment, the inductor section 10 has a DC resistance component that is greater than 0Ω and equal to or less than 15Ω. In the present embodiment, the DC resistance component of each first inner conductor 11 is set to about 0.5Ω, and the DC resistance component of each second inner conductor 13 is also set to about 4.5Ω. Therefore, in the surge absorbing element according to the third embodiment, the inductor unit 10 has a DC resistance component of about 10Ω.

  The capacitor unit 40 includes a third internal electrode 41 and a fourth internal electrode 43. The capacitor unit 40 is configured by laminating an insulator layer 45 in which a third internal electrode 41 is formed and an insulator layer 47 in which a fourth internal electrode 43 is formed.

  The third internal electrode 41 includes a first electrode portion 41a and a second electrode portion 41b. The first electrode portion 41a overlaps with a first electrode portion 43a of a fourth internal electrode 43, which will be described later, when viewed from the stacking direction of the insulator layers 45 and 47. The first electrode portion 41a has a substantially rectangular shape. The second electrode portion 41b is drawn out from the first electrode portion 41a so as to be exposed at one end face of the element body 1 (the end face on which the first terminal electrode 3 is formed), and functions as a lead conductor. . The first electrode portion 41a is electrically connected to the first terminal electrode 3 through the second electrode portion 41b. The second electrode portion 41b is formed integrally with the first electrode portion 41a.

  The fourth internal electrode 43 includes a first electrode portion 43a and a second electrode portion 43b. The first electrode portion 43 a overlaps the first electrode portion 41 a of the third internal electrode 41 when viewed from the stacking direction of the insulator layers 45 and 47. The first electrode portion 43a has a substantially rectangular shape. The second electrode portion 43b is drawn out from the first electrode portion 43a so as to be exposed at the other end face of the element body 1 (end face on which the second terminal electrode 5 is formed), and functions as a lead conductor. . The first electrode portion 43a is electrically connected to the second terminal electrode 5 through the second electrode portion 43b. The second electrode portion 43b is formed integrally with the first electrode portion 43a.

  The first electrode portion 41 a of the third internal electrode 41 and the first electrode portion 43 a of the fourth internal electrode 43 are capacitively coupled, and the third internal electrode 41 and the fourth internal electrode 43 A capacitive component 61 is formed. As a result, the capacitor unit 40 has a capacitance component 61 connected between the first terminal electrode 3 and the second terminal electrode 5.

  Each of the insulator layers 45 and 47 is a layer made of a ceramic material. The constituent materials of the insulator layers 45 and 47 are not particularly limited, and various ceramic materials and the like can be applied. However, from the viewpoint of reducing peeling from the above-described laminated structure, a material containing ZnO as a main component is preferable. .

  As described above, in the third embodiment, as in the first embodiment, the semiconductor device and the like can be protected from high-voltage static electricity, and impedance matching for high-speed signals can be further improved.

  Also in the third embodiment, similarly to the first embodiment, the passage of the electrostatic pulse to the protected element can be suppressed, and the electrostatic pulse can be effectively guided to the surge absorber 20 (varistor 63). The ESD protection level by the surge absorbing element SA3 can be increased.

(Fourth embodiment)
Next, based on FIG. 11, the structure of the surge absorption element which concerns on 4th Embodiment is demonstrated. FIG. 11 is an exploded perspective view for explaining the configuration of the element body included in the surge absorbing element according to the fourth embodiment. The surge absorbing element according to the fourth embodiment is different from the surge absorbing element SA2 according to the second embodiment with respect to the configurations of the inductor section 10 and the surge absorbing section 20.

  The surge absorber of the fourth embodiment is the same as the surge absorber SA2 shown in FIG. 7, and the element body 1, the first terminal electrode 3, the second terminal electrode 5, the third terminal electrode 7, and the outside. A plurality of conductors 9 are provided (two in this embodiment).

  The inductor section 10 includes a plurality of inductor layers 15 (in this embodiment, two layers) each having an inductor layer 15 in which the first inner conductor 11 is formed and an inductor layer 17 in which the second inner conductor 13 is formed. The inductor section 10 is configured by laminating an inductor layer 15 and an inductor layer 17 so as to be paired one by one.

  The DC resistance component of each second inner conductor 13 is larger than the DC resistance component of each first inner conductor 11. The combined DC resistance component of the DC resistance component of each first inner conductor 11 and the DC resistance component of each second inner conductor 13 is set to be greater than 0Ω and 7.5Ω or less. In the surge absorbing element according to the fourth embodiment, the inductor section 10 has a DC resistance component that is greater than 0Ω and equal to or less than 15Ω. In the present embodiment, the DC resistance component of each first inner conductor 11 is set to about 0.5Ω, and the DC resistance component of each second inner conductor 13 is also set to about 4.5Ω. Therefore, in the surge absorbing element according to the fourth embodiment, the inductor unit 10 has a DC resistance component of about 10Ω.

  The inductor section 10 includes a plurality (two layers in this embodiment) of insulating layers (dummy layers) 19 in which no internal conductor is formed. The insulator layer 19 is located between the first inductor layer pair constituted by the inductor layer 15 and the inductor layer 17 and the second inductor layer pair constituted by the inductor layer 15 and the inductor layer 17. The insulator layer 19 includes a second internal conductor 13 formed on the inductor layer 17 constituting the first inductor layer pair and a first internal layer formed on the inductor layer 15 constituting the second inductor layer pair. This is a layer for suppressing polarity reversal coupling with the conductor 11. The constituent material of the insulator layer 19 is not particularly limited, and various ceramic materials can be applied. However, from the viewpoint of reducing the separation from the above-described laminated structure, the inductor layers 15 and 17 and ZnO are similarly used. A material containing as a main component is preferable.

  A plurality (two layers in this embodiment) of insulating layers (dummy layers) 51 in which no internal conductor is formed are located under the inductor portion 10. An insulator layer (dummy layer) in which no internal conductor is formed may be located between the inductor layer 15 and the inductor layer 17 constituting the first inductor layer pair. Further, an insulator layer (dummy layer) in which no internal conductor is formed may be located between the inductor layer 15 and the inductor layer 17 constituting the second inductor layer pair.

  In the surge absorbing element of the fourth embodiment, when the length and width of the element body 1 are the same as that of the surge absorbing element SA2 of the second embodiment, that is, the areas of the inductor layers 15 and 17 are the same, It is possible to set a large coil area by the first inner conductor 11 and the second inner conductor 13. As a result, in the surge absorbing element of the fourth embodiment, the induction coefficient (inductance value) can be increased as compared with the surge absorbing element SA2 of the second embodiment.

  The surge absorber 20 has a plurality of first internal electrodes 21 and a plurality of second internal electrodes 23 (two in this embodiment). A plurality of insulator layers (dummy layers) in which no internal conductor is formed are located between the inductor portion 10 and the surge absorbing portion 20. A plurality of insulator layers (dummy layers) 28 and 29 on which no internal conductor is formed are located above and below the surge absorber 20 so as to sandwich the surge absorber 20. The constituent materials of the insulator layers 28 and 29 are not particularly limited, and various ceramic materials and the like can be applied. From the viewpoint of reducing separation from the above-described laminated structure, similarly to the varistor layers 25 and 27, A material containing ZnO as a main component is preferable. Between the varistor layer 25 and the varistor layer 27, an insulator layer (dummy layer) in which no internal conductor is formed may be located.

  The first internal electrodes 21 are spaced apart from each other on the varistor layer 25 so as to be electrically insulated from each other. The second internal electrodes 23 are spaced apart from each other on the varistor layer 27 so as to be electrically insulated from each other. Each first internal electrode 21 includes a first electrode portion 31 and a second electrode portion 33. Each second internal electrode 23 includes a first electrode portion 35 and a second electrode portion 37. The first electrode portion 31 overlaps the first electrode portion 35 when viewed from the stacking direction of the varistor layers 25 and 27. The first electrode portion 31 and the first electrode portion 35 each have a substantially trapezoidal shape.

  In the surge absorber of the fourth embodiment, the area of the portion where the first electrode portion 31 and the first electrode portion 35 overlap each other is set larger than that of the surge absorber SA2 of the second embodiment. . Thereby, equivalent series resistance (ESR) and equivalent series inductance (ESL) can be achieved. The predetermined interval between the first internal electrodes 21 is set to a value that can suppress the occurrence of the crosstalk in consideration of the crosstalk between the first internal electrodes 21. The predetermined interval between the second internal electrodes 23 is also set to a value that can suppress the occurrence of the crosstalk in consideration of crosstalk between the second internal electrodes 23.

  As described above, in the fourth embodiment, as in the first embodiment, the semiconductor device and the like can be protected from high-voltage static electricity, and impedance matching for high-speed signals can be further improved.

  Also in the fourth embodiment, similarly to the first embodiment, it is possible to suppress the passage of the electrostatic pulse to the protected element and to effectively guide the electrostatic pulse to the surge absorber 20 (varistor 63). The ESD protection level by the surge absorbing element can be increased.

  In the fourth embodiment, the first terminal electrode 3, the second terminal electrode 5, the third terminal electrode 7, the first inner conductor 11, the second inner conductor 13, the first inner electrode 21, And a plurality of second internal electrodes 23. Thereby, the surge absorption element made into the array form is realizable.

  The preferred embodiments of the present invention have been described above. However, the present invention is not necessarily limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

  The DC resistance components of the first inner conductor 11 and the second inner conductor 13 are not limited to the values described above, and the DC resistance component of the second inner conductor 13 is more than the DC resistance component of the first inner conductor 11. And the combined DC resistance component of the DC resistance component of the first inner conductor 11 and the DC resistance component of the second inner conductor 13 is greater than 0Ω and 7.5Ω or less. The DC resistance component of the first inner conductor 11 may be 0Ω.

  In the embodiment described above, the first DC resistance component 62a is formed by the first inner conductor 11, and the second DC resistance component 62b is formed by the second inner conductor 13, but this is not limitative. Absent. For example, the first DC resistance component 62a may be formed by a resistor connected in series to the first inner conductor 11, and the second DC resistance component 62b is connected in series to the second inner conductor 13. You may form by a body.

  As long as the surge absorbing element of the present invention can constitute the above-described equivalent circuit or a device having the same function, the laminated structure, the formation position of the electrode, and the like can be arbitrarily changed. That is, in the above-described embodiment, the structure in which the inductor unit 10 is provided on the surge absorbing unit 20 is illustrated. However, for example, the inductor unit 10 may be sandwiched between a pair of surge absorbing units 20. Further, the positional relationship between the terminal electrodes 3 to 7 and the outer conductor 9 may be arbitrarily changed. Even in the case of having these structures, the surge absorbing element SA1 having excellent effects as described above can be obtained.

  In the present embodiment, the varistor 63 is used as the surge absorber 20, but is not limited thereto. As the surge absorber 20, a capacitor, a PN junction (for example, a Zener diode, a silicon surge clamper, etc.), a gap discharge element, or the like may be used.

  The number of laminated layers of the inductor unit 10, the surge absorber 20, the capacitor unit 40, and the protective layer 50 is not necessarily limited to the above-described embodiment. That is, for example, the number of turns in the coil pattern may be further increased by repeatedly laminating the inductor layers 15 and 17 in which the inner conductor is formed. Further, the varistor layers 25 and 27 on which the internal electrodes are formed may be further repeatedly laminated. The number of stacked layers can be appropriately adjusted according to the desired characteristics of the surge absorbing element.

  By the way, when the inner conductor is laminated in the inductor portion 10 of the surge absorbing element, when the material constituting the inductor layers 15 and 17 has a high dielectric constant, the inner conductors adjacent in the laminating direction are coupled to each other. Parasitic capacitance is generated between the conductors. Therefore, in the configuration in which the inner conductor is laminated in the inductor portion 10, it tends to be difficult to apply to high frequency applications. From such a viewpoint, it is preferable that the inductor layers 15 and 17 have a low dielectric constant. Specifically, the relative dielectric constant is preferably 50 or less.

It is a schematic perspective view which shows the surge absorption element which concerns on 1st Embodiment. It is a disassembled perspective view for demonstrating the structure of the element | base_body contained in the surge absorption element which concerns on 1st Embodiment. It is a figure for demonstrating the circuit structure of the surge absorption element which concerns on 1st Embodiment. It is a figure which shows the equivalent circuit of the circuit structure shown by FIG. It is a figure which shows the equivalent circuit of a varistor. It is a flowchart for demonstrating the process of manufacturing the surge absorption element which concerns on 1st Embodiment. It is a schematic perspective view which shows the surge absorption element which concerns on 2nd Embodiment. It is a disassembled perspective view for demonstrating the structure of the element | base_body contained in the surge absorption element which concerns on 2nd Embodiment. It is a disassembled perspective view for demonstrating the structure of the modification of the element | base_body contained in the surge absorption element which concerns on 2nd Embodiment. It is a disassembled perspective view for demonstrating the structure of the element | base_body contained in the surge absorption element which concerns on 3rd Embodiment. It is a disassembled perspective view for demonstrating the structure of the element | base_body contained in the surge absorption element which concerns on 4th Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Element body, 3 ... 1st terminal electrode, 5 ... 2nd terminal electrode, 7 ... 3rd terminal electrode, 9 ... External conductor, 10 ... Inductor part, 11 ... 1st internal conductor, 13 ... 1st 3, 15, 17, inductor layer, 20, surge absorber, 21, first internal electrode, 23, second internal electrode, 25, 27, varistor layer, 40, capacitor unit, 41, third. Internal electrode, 43 ... 4th internal electrode, 45, 47 ... insulator layer, 50 ... protective layer, 62a ... first DC resistance component, 62b ... second DC resistance component, 63 ... varistor, SA1, SA2 ... Surge absorbing element.

Claims (9)

A surge absorbing element,
A first terminal electrode, a second terminal electrode, and a third terminal electrode;
A first inner conductor and a second inner conductor that are coupled to each other with the polarity reversed, and one end of the first inner conductor is connected to the first terminal electrode; An inductor having one end connected to the second terminal electrode and the other end of the first inner conductor connected to the other end of the second inner conductor;
A first internal electrode connected to the other end of the first internal conductor and the other end of the second internal conductor; and a second internal electrode connected to the third terminal electrode. A surge absorber,
A first DC resistance component connected between the first terminal electrode and the first internal electrode; a first DC resistance component that is greater than the first DC resistance component and the first internal electrode and the second terminal; A resistance portion having a second DC resistance component connected between the electrodes;
A capacitor unit having a capacitance component connected between the first terminal electrode and the second terminal electrode ,
The inductor portion is configured by laminating an inductor layer in which the first inner conductor is formed and an inductor layer in which the second inner conductor is formed;
The surge absorbing portion is configured by laminating a varistor layer in which the first internal electrode is formed and a varistor layer in which the second internal electrode is formed,
The first inner conductor and the second inner conductor include a region where the first inner conductor and the second inner conductor overlap each other when viewed from the lamination direction of the inductor layer,
The first internal electrode and the second internal electrode include a region where they overlap each other when viewed from the stacking direction of the varistor layer,
Each of the varistor layers contains ZnO as a main component, and contains, as an additive, at least one element selected from the group consisting of rare earths and Bi, Co.
Each inductor layer contains ZnO as a main component, contains rare earth as an additive, does not substantially contain Co ,
A surge absorbing element, wherein an input impedance of the surge absorbing element is matched with a characteristic impedance .   2. The surge absorbing element according to claim 1, wherein a combined DC resistance component of the first DC resistance component and the second DC resistance component is set to be greater than 0Ω and equal to or less than 7.5Ω.   The surge absorbing element according to claim 1, wherein the first DC resistance component is formed by the first inner conductor, and the second DC resistance component is formed by the second inner conductor. .   The combined DC resistance component of the DC resistance component of the first inner conductor and the DC resistance component of the second inner conductor is set to be greater than 0Ω and 7.5Ω or less. The surge absorber described. Surge absorber according to claim 1, capacitance component the capacitor unit has, characterized in that formed between the first inner conductor by said second internal conductor. The first terminal electrode, the second terminal electrode, and the third terminal electrode are formed on an outer surface of an element body including the inductor portion, the surge absorbing portion, and the resistance portion,
The other end of the first inner conductor, the other end of the second inner conductor, and the first inner electrode are connected through an outer conductor formed on the outer surface of the element body. The surge absorbing element according to claim 1. The first terminal electrode is an input terminal electrode;
The second terminal electrode is an output terminal electrode;
The surge absorbing element according to claim 1, wherein the first inner conductor and the second inner conductor are positively coupled.   The first terminal electrode, the second terminal electrode, the third terminal electrode, the first internal conductor, the second internal conductor, the first internal electrode, and the second internal electrode The surge absorption element according to claim 1, wherein a plurality of surge absorption elements are provided.   The surge absorber according to claim 1, wherein the content of the additive contained in the inductor layer is 0.02 mol% or more and 2 mol% or less in the total amount of ZnO contained in the inductor layer.

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