JP4394835B2 - High-speed on-chip voltage generator for low power integrated circuits - Google Patents

Description

【００５３】
上記のトランジスタの大きさとキャパシタのパラメータは、特定の半導体装置の必要により設計された特定の実現の代表例である。明らかに、これらのトランジスタの相対的な大きさと部品の変化はある状況に対して適当であろう。しかし、これらは例示の回路の動作をより詳細に理解するための基礎として与えられた。
【００５４】
従って、フラッシュメモリ及び他のメモリ装置のための読出し動作に使用するのに公的な２モード電圧ブースト回路が開示された。回路はまた、正確な遮断レベルでもって高速ブーストが望ましい他の環境でも好適である。例えば、さまざまなレベルのセルの読出しについてワード線電圧上に大変厳しいマージンに依存する複数レベル・セルには正確な遮断レベルは特別に重要である。
【００５５】
本発明の好ましい実施の形態の詳細な説明が例示的な説明目的でなされた。本発明を開示した正確な形式に限定する意図又は網羅的な意図ではない。明らかに、当業者には多くの修正や変形が容易である。
【図面の簡単な説明】
【図１】 本発明のオンチップ電圧供給回路を含む集積回路メモリ装置のブロック図。
【図２】 図１のシステムで使用される本発明のワード線ブースト回路のブロック図。
【図３】 本発明の作用を説明するために使用されるタイミング図。
【図４】 本発明によるブースト回路の好ましい実施の形態の回路図。
【図５】 図４のブースト回路により使用される遷移信号を発生するために使用される論理の回路図。
【図６】 図４の回路との組合せて使用される電圧レベル検出器の回路図。
【図７】 図４の回路と共に使用される第２電圧レベル検出器の回路図。
【図８】 図４の回路と共に使用される予備充電回路の回路図。
【図９】 図４の回路と共に使用される第２予備充電回路の回路図。[0001]
Background art
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an on-chip voltage generation technique for generating on-chip a voltage outside the range of power supply voltage supplied to the chip, and more particularly, the read-out necessary for the power supply voltage to detect data in the memory. The present invention relates to the generation of word line voltages on low power memory devices such as flash memory, mask ROM, and SRAM that are lower than the potential.
[0002]
Conventional technology
Traditionally, integrated circuits have been manufactured to operate with a power supply voltage of about 5 volts within a specified range of ± 10%. Of course, other power supply voltages are also used. The current trend is to design integrated circuits to operate at lower supply voltages for many applications. In general, lower voltages result in lower power operation of the device and can be easily supplied with batteries in smaller devices. For example, one of the low power supply voltages that has emerged as standard specifies that it operates in the range of about 2.7 to about 3.6 volts. Other standards around lower voltages have also been developed.
[0003]
However, on-chip circuits are often designed to operate at higher voltages for several purposes. For example, in memory devices such as flash memory, word lines that supply gate voltages to memory cells are often designed to operate with a read voltage of 4 volts or higher. Therefore, the low power supply voltage is insufficient to directly supply an on-chip voltage that is sufficiently high to drive the word line. This problem is addressed by including a charge pump or other voltage supply booster on the integrated circuit to provide a higher operating voltage on the chip. See, for example, US Pat. No. 5,511,026, Booted and regulated gate power supply with reference tracking for multiple density and low power memory. The '026 patent describes an integrated circuit memory having a charge pump configured to supply a word line voltage at a level higher than the power supply potential. In addition, the '026 patent allows multiple word line voltages for multi-level / memory devices to be provided between memory cell states with a larger operating margin than is normally available using standard power supply potentials. It describes the use of an on-chip charge pump to provide.
[0004]
One problem associated with conventional approaches of on-chip charge pumps for these purposes arises from the difficulty of generating well-tuned output levels without sacrificing speed. Well-regulated levels are especially important in multi-level memory devices or low voltage devices that operate with a narrow margin of read voltage. However, it is preferable to read at high speed. The time required to stabilize the charge pump output to a well regulated level contributes a significant portion of the delay for read operations or operations that require the output generated by the charge pump for operation.
[0005]
Accordingly, it would be desirable to provide an on-chip voltage supply circuit for use in an integrated circuit that operates at high speed and provides more accurate control of the on-chip voltage.
[0006]
Disclosure of the invention
The present invention provides an on-chip voltage generation circuit suitable for use in an integrated circuit having a low power supply voltage (for example, 2.7 to 3.6 volts) such as a flash memory device. In accordance with one aspect of the present invention, an integrated circuit having a supply voltage input capable of receiving a supply potential within a pre-specified range of voltages, wherein the on-state is higher than the supply voltage within the pre-specified range. Characterized as an integrated circuit that includes components on the integrated circuit that use the chip voltage. A voltage boost circuit is coupled to the supply voltage input and a boost signal that boosts the on-chip voltage to a node on the integrated circuit in response to the boost signal transition. The voltage boost circuit is responsive to the first mode for boosting the on-chip voltage with a first speed boost up to a first threshold, and after reaching the first threshold, is turned on with a second speed boost. A second mode for boosting the chip voltage. In a preferred system, the second speed boost is slower than the first speed boost. The detection circuit is coupled to a node on the integrated circuit that receives the on-chip voltage and a voltage boost circuit. The detection circuit provides a signal to the voltage boost circuit when the node reaches the first threshold value, and provides a signal to the voltage boost signal circuit when the node reaches the second threshold value. According to one aspect of the present invention, the first threshold is reached in 5 nanoseconds or less. More preferably, it is 2 nanoseconds or less of the transition of the boost signal.
[0007]
According to one aspect of the invention, the detection circuit includes a first detector that provides a first control signal to the voltage boost circuit within a first time interval when the node reaches a first threshold. During the first time interval, the voltage boost circuit continues to boost at the first speed. A second detector is coupled to the node and provides a second control signal to the voltage boost circuit within a second time interval during which the node reaches a second threshold. During the second time interval, the voltage boost circuit continues to boost at the second rate so that the on-chip voltage on the node increases less during the second time interval than during the first time interval. This slower increase during the time interval between the signal of the voltage boost circuit and the detection of the second threshold of the second detector is more accurate in response to the passage of the second threshold. Allows to control off. This allows a very fast boost of the difference in the initial part of the voltage pumping in response to signal transitions while maintaining an accurate cut-off.
[0008]
According to another aspect of the invention, the voltage boost circuit includes a capacitor and a drive circuit coupled to one terminal of the capacitor. The drive circuit provides a transition to the capacitor by supplying current at a first rate during the first mode, and supplies current at a second rate during the second mode. In one approach, the drive circuit includes an inverter whose input is connected to receive a boost signal and whose output is coupled to a capacitor. The inverter is coupled to any one of the first and second power supply terminals having first and second power supply terminals and a first mode supply current at a first speed and a second mode supply current at a second speed. Current source. In this way, the rate of increase of the voltage on the capacitor can be controlled in the first and second modes to set pumping at faster and slower rates.
[0009]
According to another aspect of the invention, the voltage boost circuit includes a first stage and a second stage. The first stage includes a capacitor having first and second terminals, and a diode having an anode coupled to the second terminal capacitor and a cathode coupled to a node on the integrated circuit. A driver is coupled to the first terminal of the capacitor and provides a first transition signal to the first capacitor. The second stage includes a second capacitor having a first terminal coupled to a node on the integrated circuit. A second driver is coupled to the second terminal of the second capacitor and provides a boost signal transition to the second terminal of the capacitor in accordance with the operation of the two modes described above.
[0010]
In one aspect of the invention, the circuit also includes a first precharge circuit coupled to the anode of the diode in the first stage and a second precharge circuit coupled to the cathode of the diode.
[0011]
In addition, the circuit according to the preferred embodiment includes on-chip logic capable of generating a first transition signal and a boost signal transition.
[0012]
The present invention is particularly suitable for implementation on an integrated circuit memory including an array of memory cells of multiple word lines and multiple bit lines. A set of word line drive circuits is coupled to the plurality of word lines and uses a word line voltage that is higher than a pre-specified range of supply voltage inputs. The logic detects an event on the integrated circuit, such as an address signal transition, and generates a boost signal transition. The voltage boost circuit and detection circuit described above are included on the chip to boost the voltage on the word line. According to one aspect of the invention, an integrated circuit memory includes an array of ROM cells. In another aspect, the array of memory cells includes floating gate memory cells such as flash memory.
[0013]
Hereinafter, other aspects and advantages of the present invention will become apparent by describing embodiments of the present invention with reference to the drawings.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
The embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 shows an entire flash memory device incorporating an on-chip voltage supply circuit for generating a read mode word line voltage. That is, FIG. 1 shows an integrated circuit. The integrated circuit includes a supply voltage input 10 that can receive a supply voltage VDD. In one embodiment, the supply voltage is between 2.7 and 3.6 volts. A ground input 11 is provided. There are input and output pins on the integrated circuit including address input 12, control signal inputs such as chip enable input 13 and output enable input 14, and data input / output pins 15.
[0015]
The integrated circuit includes a flash memory array 16 that includes floating gate transistors and an array of ROM cells, such as masked ROM cells, or other memory cells. The array 16 includes a plurality of word lines represented by arrows 17, for example. The word lines are word line detector section 0, word line detector section 1, word line detector section 2, word line detector section 3, word line detector section 4, word line detector section 5, word line in this example. It is driven by a word line decoder having a plurality of sections including a line detector section 6 and a word line detector section 7. The column decoder and data input / output circuit 18 is coupled to a plurality of bit lines represented by arrows 19 in the array 16. Column decoder 18 and word line decoder 20 are controlled by the address received from address input 12. Each address can be characterized as including a row address on line 21 and a column address on line 22 driving word line decoder 20 and column decoder 18, respectively. A word line spare decoder 23 coupled to the address line 12 is also included. The word line spare decoder 23 generates a selection control signal SEL (0-7) on the line 24 which is supplied to the word line decoder sections 0-7, respectively. In this example, the three upper bits of the row address portion of the address on line 12 are used to control word line spare decoder 23 and to select a particular word line decoder section from word line decoder 20.
[0016]
Mode logic 26 is included on the chip. Mode logic 26 receives the chip enable and chip select signals on lines 13 and 14 as well as other signals for control of mode operation of the flash memory. The flash memory device includes a read mode, a program mode, an erase mode, and other modes suitable for specific implementation of program and erase operations. The read control signal on line 40 is generated by mode control logic 26. A program and erase mode word line voltage pump 28 is included on the chip. For read mode, read mode word line voltage booth and circuit 29 are included. In accordance with the present invention, read mode word line voltage boost circuit 29 includes a high speed multi-stage boost circuit. The output of the read mode word line boost circuit 29 includes the word line voltage AVX (0-7) on line 30 for each word line detector section. In accordance with the present invention, read mode word line voltage boost circuit 29 is responsive to the level of AVX 30. The read mode word line voltage boost circuit 29 responds to the address transition detection circuit 33. The address transition detection circuit 33 generates a signal on the line 35 indicating the address transition.
[0017]
Therefore, as shown in FIG. 1, the present invention is applied to word line voltage generation for a read mode of a flash memory device. The present invention is particularly suitable for a flash memory having a low power supply voltage, for example, in the range of 2.7 to 3.6 volts. The present invention is also suitable for other devices and ROM arrays that require a boosted voltage on a node, such as node 30 on an integrated circuit.
[0018]
FIG. 2 shows a block diagram of a word line voltage boost circuit according to the present invention. The circuit receives an address as an input on the integrated circuit and provides an address transition detection signal ATS on line 201 as an output, a first address transition detection pulse ATD1ST on line 202, and a second address on line 203. An address transition detection circuit 200 that provides a transition detection pulse is included. The second pulse ATD2ND on line 203 is connected to the first stage boost drive circuit and logic block 204 including the pump capacitor C1. The pump capacitor is connected to the diode of diode 205. The cathode of the diode 205 is connected to a node 206 where the voltage AVX is generated. The second stage boost drive circuit and logic block 207 is also connected to receive the pulse ATD2ND on line 203 and to receive the address transition detection signal ATD on line 201. The output of second stage block 207 provides the boost signal on line 208 to capacitor C2. The second terminal of the capacitor is coupled to node 206. First level detector 209 and second level detector 210 are coupled to node 206 and generate first control signal CT1 on line 211 and second control signal CT1SP on line 212, respectively. These signals are provided to the second stage block 207 to control the charge rate of capacitor C2 in response to the boost signal transition on line 208.
[0019]
  The word line voltage generator in FIG. 2 also includes a first precharge circuit 215 and a second precharge circuit 216. First and second precharge circuits 215, 216 precharge the anode of diode 205 and node 206 to near the supply potential to facilitate the boost process. On line 217Chip enable CEL signal, Control signals including enable enable signal ENRDYB on line 218 and enable address transition detect signal ENATD on line 219 are supplied to the precharge circuit. In addition, the precharge circuit is responsive to a first address transition pulse ATD1ST on line 202.
[0020]
FIG. 3 is a timing chart of the level of the AVX signal on the node 206 and the address transition detection signal.
[0021]
In FIG. 3, the address input to the address transition detection signal is shown on the trace 300. An address transition detection signal on line 201 is shown on trace 301. A first address transition detection pulse ATD1ST is shown on the trace 302. A second address transition detection pulse ATD2ND is shown on the trace 303. On trace 304 the level of voltage AVX on node 206 is shown.
[0022]
In this example, the level of the AVX signal on line 304 starts at a supply voltage level of approximately VDD as shown at point 310. At time 311, the address changes at the input of the integrated circuit. This transitions the address transition detection signal to a high state at time 311 and transitions to a low state at time 312. In this example, the interval of the ATD signal on line 301 between times 311 and 312 is about 20 nanoseconds. Address transition detection circuit 200 generates a first pulse that starts at time 311 and ends at time 313 as indicated by the ATD1ST signal on line 302. The ATD2ND signal transitions to a high state at time 313 and transitions to a low state at time 314 close to time 312.
[0023]
Node AVX boost begins at time 311 with a precharge caused by the ATD1ST pulse. In trace 304 of FIG. 3, this precharge does not reflect any change in the level of the AVX signal. However, if the AVX signal was not precharged to the VDD level before the ATD signal, that level would have been raised to near VDD. The precharge circuit also preconditions to boost capacitor C1 above the VDD level.
[0024]
At the rising edge of the ATD2ND signal at time 313, the first stage boost pump causes a transition on capacitor C1. This boosts the anode of diode 205 above the level of node 206 and induces an increase in the AVX signal as indicated by region 315 between times 313 and 312.
[0025]
At the falling edge of the ATD signal at time 312, the second stage boost pump begins a fast transition of the boost signal 208 at the steep region 316 of the trace 304 immediately after time 312. At time 317, voltage level detector B210 detects that the AVX signal has crossed the first threshold. This immediately switches the second stage boost pump to a slower speed boost as shown in region 319 of trace 304 shortly after time 317.
[0026]
At time 318, level detector A 209 detects that voltage level AVX has reached the final threshold and generates control signal CT1 on line 211. This stops the boost speed of the second stage pump.
[0027]
In this example, the interval between fast boost times 312 and 317 is about 2 nanoseconds or less, or about 5 nanoseconds or less. The slower boost time interval in trace 319 between times 317 and 318 is about 10 nanoseconds or less, or about 20 nanoseconds or less.
[0028]
The overall slower boost rate during interval 319 allows more time for the feedback circuit to more accurately control the final level of the AVX signal. The faster boost speed during interval 316 significantly speeds up the boost process without sacrificing cut-off level accuracy.
[0029]
4, 5, 6, 7, 8, and 9 provide detailed circuit diagrams of the voltage boost circuit in the preferred embodiment of the present invention. FIG. 4 shows a first stage pump and a second stage pump. The first stage pump receives a second pulse ATD2ND on line 400. This signal is supplied to the first terminal of the capacitor C1 through the inverter 401, the inverter 402, the inverter 403, and the inverter 404. Therefore, at the rising edge of pulse ATD2ND on line 400, the signal on the first terminal of capacitor C1 transitions from a low value to a high value. The second terminal of the capacitor C1 is connected to the anode of the diode 405. The cathode of the diode 405 is connected to a node 406 where the AVX voltage is generated.
[0030]
The second stage of the pump includes a second pulse ATD2ND on line 400 and an address transition detection signal ATD on line 410. These signals are supplied as inputs to NOR gate 411, which provides the input to inverter 412. The output of the inverter 412 is supplied as a reset input of the set / reset SR latch 413 and one input of the NOR gate 414. The active low chip enable signal CEB 415 is supplied to the setting input of the SR latch 413. The output of the SR latch is the second input of NOR gate 414. The output of NOR gate 414 drives inverter 416, which then drives inverter 417. Inverter 417 provides inputs to inverter 418 and inverter 419. The output of inverter 419 is coupled to the first terminal of capacitor 420. The second terminal capacitor 420 is connected to the source of the n-channel transistor 421. The drain of the n-channel transistor 421 is connected to the supply potential VDD. The gate of transistor 421 receives control signal ENATD on line 422. The capacitor 420 is connected to the anode of the diode 423. The cathode of the diode 423 is connected to the node 406. A control signal on line 422 pulls the anode of diode 423 to the supply potential level during operation of the pump circuit. The circuit including transistor 421, capacitor 420, and inverter 419, coupled to node 406 via diode 423, operates with precharge capacity. When the ENATD signal is low, CEB sets latch 413, causing a transition on the output of inverter 419. This boosts node 406 through capacitor 420 and diode 423 to a precharge level to assist the precharge function.
[0031]
Boost is enabled via inverter 418 when the address transition detect enable signal is high. The inverter 418 drives the two-mode inverter 425. The output of the two-mode inverter is a boost signal on line 426 coupled to capacitor C2. A second node of the capacitor C2 is supplied to the terminal 406. Two-mode drive circuit 425 has a power supply terminal connected to a current source circuit including transistors 428, 429, 430 and 431. In this example, transistors 428 and 429 are p-channel transistors having a width of 3 microns and a length of 5 microns. The gates and drains of transistors 428 and 429 are each coupled together in a diode configuration. Each n-well of the transistor is coupled to a source. These transistors provide a weak pull-up to the power supply terminal of the drive circuit 425 to prevent it from floating.
[0032]
  Transistors 430 and 431 set two boost speed boost signals on line 426. In this example, transistor 430 is approximately 5 minutes the width of transistor 431 (eg, 50 microns).1And has a length of about 0.5 microns. Transistor 430 is a p-channel transistor having control signal CT1 coupled to its gate. Transistor 431 is a p-channel transistor having control signal CT1SP coupled to its gate. Transistor 431 has a width of about 5 times the width of transistor 430 (eg, 250 microns) and a length of about 0.5 microns. Thus, transistor 431 controlled by CT1SP is much stronger than transistor 430 controlled by CT1. The drains of transistors 430 and 431 are both coupled to the power supply terminal of drive inverter 425. When both CT1 and CT1SP are low, a fast boost is generated in boost signal 426 as reflected in the interval between times 312 and 317 in trace 304 in FIG. When the control signal CT1SP becomes high, the transistor 431 is turned off and is driven only by the transistor 430, and the speed of boost is substantially reduced. This reflects the slow speed boost during interval 319 between times 317 and 318 of trace 304 in FIG.
[0033]
The boost rate of the signal in node 426 is directly reflected across capacitor C2 on node 406 in the manner shown by trace 304 in FIG.
[0034]
The CT1 and CT1SP control signals for the gate of transistor 430 are generated by the level detector shown in FIGS. The ATD1ST pulse and the ATD2ND pulse are generated by the circuit shown in FIG.
[0035]
The precharge circuit shown in FIGS. 8 and 9 used for setting the boost operation of the circuit is coupled to the boost circuit. A first precharge circuit 490 is coupled to the anode of diode 405. A second precharge circuit 491 is coupled to the cathode node 406 of the diode 405.
[0036]
The ENRDYB, CEL, CEB, and ENATD control signals are control signals generated with standard design logic.
[0037]
In FIG. 5, ATD1ST and ATD2ND signals are generated in response to an address transition detection ATD signal on line 500. The ATD signal is generated, for example, as described in US patent application Ser. No. 08 / 751,513 “Address Transition Detection Circuit” filed Nov. 15, 1996 by the inventor, In Liu et al. Upon transition of the address signal, an ATD pulse of about 20 nanoseconds is generated in the preferred system as shown in FIG. This signal is applied to a one-shot circuit comprising a NAND gate 501 and an inverter 502. Input ATD signal line 500 is connected to the input of inverter 502 and one of NAND gates 501. The output of the inverter 502 is connected to the second input of the NAND gate 501. The output of the NAND gate 501 is supplied to the inverter 503. The output of inverter 503 provides the ATD1ST signal on line 436. The ATD1ST signal is supplied to a second one-shot circuit including an inverter 504 and a NOR gate 505. The ATD1ST signal is connected to the input of the inverter 504 whose output is connected to the input of the NOR gate 505. The ATD1ST signal is connected to the second input of the NOR gate 505. The output of the NOR gate 505 is connected to the set input of the SR latch 506. In addition, the output of NOR gate 505 is connected as one input to NOR gate 507. The output of the NOR gate 507 is connected to the reset input of the SR latch 506. The Q output of SR latch 506 is connected to inverter 508, which in turn drives inverter 509. The output of inverter 509 is the ATD2ND signal on line 400.
[0038]
The first level detector shown in FIG. 6 generates a CT1SP signal. The second level detector shown in FIG. 7 generates the CT1 signal. The CT1SP signal triggers at a lower AVX level than the CT1 signal. The detector of FIG. 6 is enabled by the output of a NOR gate 600 that receives as input the CEB signal on line 601, the ATD1ST signal on line 436, and the CT1 signal on line 700. The output of the NOR gate 600 is connected to the gate of the transistor 603 via the inverter 602. The output of the inverter 600 is connected to the gate of the transistor 604. When the output of NOR gate 600 is high, transistor 604 is turned on and transistor 603 turns off enabling of the level detector circuit.
[0039]
  The level detector circuit includes a first current leg that receives an AVX signal from node 406 as an input. This node is a p-channel transistor605N-well and source. The gate and drain of p-channel transistor 605 are connected to the n-well and source of p-channel transistor 606. The gate and drain of the transistor 606 are connected to the drain of the transistor 604. The source of transistor 604 is connected to the gate and drain of n-channel transistor 607. n-channel transistor607The source of is connected to ground.
[0040]
The second current leg of the level detector includes a first node connected to the power supply potential VDD. The p-channel transistor 610 and the p-channel transistor 611 have their sources connected to the supply potential. The gate and drain of the transistor 610 are connected to the drain of the transistor 612. The gate of transistor 611 is connected to the output of inverter 613 which receives as input the SBCTL1 signal on line 614 supplied from the output of inverter 602. Thus, when the SBCTL1 signal is high, the signal on the gate of transistor 611 is low, allowing increased current through the circuit.
[0041]
  The source of transistor 612 is grounded. The gate of transistor 612 is connected to the gate of transistor 607 by a current mirror method. The gate of the transistor 612 and the gate of the transistor 607 are connected to the drain of the transistor 603. Node NISP on the drain of transistor 612 is connected as the input of inverter 615. The output of inverter 615 is connected to the S input of SR latch 616. The reset input of SR latch 616 is connected to receive the ATD1ST signal on line 436. The Q output of the SR latch 616 is connected to an inverter 617 that drives an inverter 618. The output of inverter 618 is control signal CT1SP on line 620. In operation, when the signal AVX increases, the current increases through the current mirror leg of the detector. Transistor610When the current increases through, the voltage NISP drops. When voltage NISP drops below the trip point of inverter 615, latch 616 is set to generate the CT1SP signal.
[0042]
FIG. 7 shows a level detector for generating the CT1 signal. This level detector is enabled by the output of a NOR gate 701 that receives the CEB signal on line 601 and the ATD1ST on line 436. The output of NOR gate 701 is connected to the gate of n-channel transistor 702 and the input of inverter 703. The input of inverter 703 is connected to the gate of n-channel transistor 704. The drain of the transistor 704 is connected to the node 705. The source of transistor 704 is connected to ground. Thus, the circuit is enabled by turning off transistor 704 and turning on transistor 702 when the output of NOR gate 701 goes high. In addition, the output of inverter 703 generates a control signal SBCTL that is supplied to the input of inverter 706. A high level at the input of inverter 706 turns on transistor 707.
[0043]
The level detector includes a first current leg connected to voltage AVX on node 406. Node 406 is connected to the source and n-well of p-channel transistor 708. The gate and drain of transistor 708 are coupled to the source and n-well of p-channel transistor 709. The gate and drain of the transistor 709 are connected to the source and n well of the transistor 710 and the source and n well of the transistor 711. The gate of transistor 710 is connected to receive control signal CT1 on line 700. The gate and drain of transistor 711 and the drain of the transistor are connected to the gate and drain of n-channel transistor 712. The source of transistor 712 is connected to the gate and drain of triple well n-channel transistor 713. The isolation well of transistor 713 is connected to AVX node 406. The p-well and source of the transistor 713 are connected to the drain of the transistor 702. The source of the transistor 702 is connected to the drain and gate of the transistor 714 at a node 705. The source of transistor 714 is connected to ground.
[0044]
The second current leg of the level detector includes a transistor 707 with its source connected to the supply potential and its drain connected to the drain of transistor 715. The source of transistor 715 is connected to ground. The gate of the transistor 715 is connected to the node 705 in common with the transistor 714. In addition, transistor 716 has its source connected to the supply potential and its drain connected to the drain of transistor 715.
[0045]
The circuit operates in the manner described above for FIG. 6 except for the high threshold. That is, when the voltage level AVX increases, the current increases through the current mirror leg. When the current reaches a certain level, the voltage on node NI of the input of inverter 717 reaches the trip point of the inverter. The output of the inverter 717 is connected to the set input of the SR latch 718. The Q output of SR latch 718 is connected to inverter 719 which in turn drives inverter 720. The output of inverter 720 is the CT1 signal on line 700. The reset input of SR latch 718 receives the ATD1ST signal on line 436.
[0046]
Transistor 710 operates to turn off when the CT1 signal goes high. This reduces the current through the level detector and saves circuit power.
[0047]
The level detection circuit described here constitutes a preferred embodiment. There are various levels of detection circuit techniques used by the present invention. In accordance with the present invention, when the AVX voltage level rapidly increases during the first stage of pumping, the detection of AVX level shifts using the circuits of FIGS. 6 and 7 or other types of level detectors. It can be seen that a delay of a fraction of a nanosecond contained is a significantly more accurate interruption. The ability to adjust the timing of these detectors to 1 nanosecond or less to cut off the boost level of the AVX signal at a preferred predetermined level, according to the present invention, boosts when the level reaches the desired cutoff. It is solved by reducing the speed. In this way, the relative timing of the CT1SP signal and the arrival of the final boost level are not very critical. According to the present invention, a rapid boost is possible but an overshoot condition is avoided.
[0048]
FIG. 8 shows the first precharge circuit 490. It receives as input signals an enabling ATD signal on line 435 and a first ATD pulse ATD1ST on line 436. These signals are supplied as inputs to the NAND gate 437 and the output of the gate 437 drives the inverter 438. The output of the inverter 438 is connected to the source and drain of the capacitor connection transistor 439. The gate of transistor 439 is connected to the gate of n-channel transistor 440. The source of n-channel transistor 440 is connected to line 432 that is coupled to the anode of diode 405. The drain of the transistor 440 is connected to the supply potential VDD. The gate of transistor 440 is biased by a circuit including a p-channel transistor 441 having a source connected to supply potential VDD, a gate connected to control signal ENRDYB on line 442, and a drain connected to the anode of diode 443. Is done. The cathode of the diode 443 is connected to the gate of the transistor 440. Transistor 444 has its drain connected to the gate of transistor 440 and its source connected to ground. The gate of transistor 444 is connected to control signal CEL on line 445. In addition, transistor 446 has its drain connected to the gate of transistor 440 and its source connected to ground. The gate of transistor 446 is connected to the control signal ENRDYB signal on line 442. In operation, the gate of transistor 440 is determined at a level determined by a voltage drop below the supply potential across transistor 441 and diode 443 in response to a low signal at the ENRDYB terminal on line 442. When the control signal CEL on line 445 goes high, the node is connected to ground. Similarly, when control signal ENRDYB goes high, the node is connected to ground through transistor 446.
[0049]
In addition, the precharge circuit includes a transistor 450 with the gate and drain coupled to the supply potential and the source connected across the line 430 to the anode of the diode 405. The diode-connected transistor 450 maintains the node level at a threshold drop below VDD as a starting point. In response to the ATD1ST pulse, the gate of transistor 440 is boosted, raising the anode of diode 405 to the VDD level to compensate for the threshold drop across transistors 440 and 450.
[0050]
FIG. 9 shows a second precharge circuit, which is similar to the first precharge circuit. It receives its input ENATD on line 435 and the ATD1ST signal on line 436. These signals are supplied as inputs to a NAND gate 457. Gate 457 drives inverter 458. The inverter 458 is connected to the source and drain of the capacitor connection transistor 459. Gate transistor 459 is connected to the gate of transistor 460. The gate of transistor 460 is also biased by a circuit including a p-channel transistor 461 having a source connected to supply potential VDD and a drain connected to gate transistor 460 through diode 462. Transistors 463 and 464 are n-channel transistors with their drains connected to the gate of transistor 460 and their sources connected to ground. The gate of transistor 463 receives the CEL control signal on line 445. The gate of transistor 461 and the gate of transistor 464 receive control signal ENRYDB on line 442 as an input.
[0051]
The second precharge circuit includes a transistor 470 whose gate and drain are connected to the supply potential VDD and whose source is connected to the node 406 on the line 431.
[0052]
In the circuit of this example, the parameters and relative sizes of the circuit components in FIGS. 4 to 9 are represented in the following table.
table

[0053]
The transistor sizes and capacitor parameters described above are representative of specific implementations designed according to the needs of specific semiconductor devices. Obviously, the relative size and component variations of these transistors may be appropriate for certain situations. However, these were provided as a basis for a more detailed understanding of the operation of the exemplary circuit.
[0054]
Accordingly, a public two-mode voltage boost circuit has been disclosed for use in read operations for flash memory and other memory devices. The circuit is also suitable in other environments where a fast boost is desired with an accurate cutoff level. For example, the exact cutoff level is particularly important for multi-level cells that rely on very tight margins on the word line voltage for reading various levels of cells.
[0055]
The detailed description of the preferred embodiment of the present invention has been made for purposes of illustration. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in this art.
[Brief description of the drawings]
FIG. 1 is a block diagram of an integrated circuit memory device including an on-chip voltage supply circuit of the present invention.
FIG. 2 is a block diagram of the word line boost circuit of the present invention used in the system of FIG.
FIG. 3 is a timing diagram used to explain the operation of the present invention.
FIG. 4 is a circuit diagram of a preferred embodiment of a boost circuit according to the present invention.
5 is a circuit diagram of the logic used to generate the transition signal used by the boost circuit of FIG.
6 is a circuit diagram of a voltage level detector used in combination with the circuit of FIG.
7 is a circuit diagram of a second voltage level detector used with the circuit of FIG.
8 is a circuit diagram of a precharge circuit used with the circuit of FIG.
9 is a circuit diagram of a second precharge circuit used with the circuit of FIG.

Claims (14)

In an integrated circuit comprising components on an integrated circuit having a supply voltage input capable of receiving a supply voltage within a predetermined voltage range and using an on-chip voltage higher than the predetermined range,
A voltage boost circuit coupled to a supply voltage input and a boost signal that boosts an on-chip voltage to a node on the integrated circuit in response to a boost signal transition, the voltage boost circuit being first in response to the transition. A first mode in which the on-chip voltage is boosted at a first speed of boost to a threshold, and a second mode in which the on-chip voltage is boosted at a second speed of boost after the first threshold to a second threshold; A voltage boost circuit, wherein the second speed is slower than the first speed;
Combined with a node on the integrated circuit and a voltage boost circuit, provides a signal to the voltage boost circuit when the node reaches a first threshold, and signals to the voltage boost circuit when the node reaches a second threshold anda detection circuit for supplying,
The detection circuit comprises:
A first detection coupled to the node that provides a first control signal to the voltage boost circuit while the voltage boost circuit continues to boost at a first rate within a first time interval when the node reaches a first threshold. Circuit,
The on-chip voltage at the node supplies the second control signal to the voltage boost circuit while the voltage boost circuit continues to boost at the second rate within the second time interval when the node reaches the second threshold. An integrated circuit including a second detection circuit coupled to the node, wherein the second detection circuit is configured to increase less than the first time interval during the time interval . Voltage boost circuit
A capacitor having a first terminal and a second terminal coupled to a node of the integrated circuit;
A drive coupled to the second terminal of the capacitor that provides a transition to the second terminal of the capacitor by supplying current at the first speed during the first mode and supplying current at the second speed during the second mode. Circuit,
The integrated circuit according to claim 1, comprising: The drive circuit is
An inverter having an input connected to receive the boost signal, an output coupled to the second terminal of the capacitor, and first and second power supply terminals;
A current source coupled to one of the first and second power supply terminals having a first mode supply current at a first speed and having a second mode supply current at a second speed;
The integrated circuit according to claim 2 . Voltage boost circuit
A first capacitor having a first terminal and a second terminal, a diode having an anode coupled to the second terminal of the capacitor, a cathode coupled to a node of the integrated circuit, and a first transition signal supplied to the first capacitor A first circuit comprising: a drive circuit coupled to a first terminal of the capacitor to be coupled;
A second capacitor having a first terminal and a second terminal coupled to a node on the integrated circuit; coupled to a second terminal of the second capacitor to supply current at a first rate during the first mode; and A second stage comprising: a second drive circuit that provides a boost signal transition to the second terminal of the capacitor by supplying current at a second rate during the mode;
The integrated circuit according to claim 1, comprising: A first precharge circuit coupled to the anode of the diode, and a second precharge circuit coupled to the first terminal of the second capacitor and a node for precharging the node to the start voltage before the first transition signal. The integrated circuit according to claim 4 . The integrated circuit of claim 4 , including logic responsive to the event to generate a transition between the first transition signal and the boost signal.   2. The integrated circuit of claim 1, wherein the boost circuit reaches the first threshold within 5 nanoseconds after the boost signal transition.   The integrated circuit of claim 1, wherein the boost circuit reaches the first threshold in 2 nanoseconds or less after the boost signal transitions. An array of memory cells;
A plurality of word lines coupled to a row of memory cells in the array;
A plurality of bit lines coupled to a column of memory cells in the array;
A set of word line drive circuits coupled to a plurality of word lines for driving a word line voltage from the node on the integrated circuit onto a selected word line;
Logic to detect an event on the integrated circuit and generate a boost signal transition;
The integrated circuit of claim 1 comprising: An integrated circuit memory having a supply voltage input capable of receiving a supply voltage within a predetermined range of voltages, comprising:
An array of memory cells;
At least one address input;
A plurality of word lines coupled to a row of memory cells in the array;
A plurality of bit lines coupled to a column of memory cells in the array;
A set of word line driving circuits coupled to the plurality of word lines for driving a word line voltage higher than a predetermined range of supply voltage onto a selected word line from a node on the integrated circuit;
Detecting an event on the integrated circuit, a precharge signal, a first transition of the boost signal after the precharge signal in response to the transition of the at least one address input, a second transition of the boost signal after the first transition; The first and second precharge circuits are responsive to the precharge signal; and
A voltage boost circuit coupled to the supply voltage input and receiving a boost signal and boosting an on-chip voltage to a node on the integrated circuit, the voltage boost circuit comprising:
A first capacitor having a first terminal and a second terminal, a diode having an anode coupled to the second terminal of the capacitor, a cathode coupled to a node of the integrated circuit, and a first transition is provided to the first capacitor. A first stage including a drive circuit coupled to the first terminal of the capacitor;
A second capacitor having a first terminal and a second terminal coupled to a node on the integrated circuit and a second capacitor coupled to the second terminal of the second capacitor to supply current at a first rate until a first threshold is reached And a second drive circuit for providing a second transition of the boost signal to the second terminal of the capacitor by supplying current at a second rate until a second threshold is reached, and Is reached in the second transition in less than 5 nanoseconds, the second speed is slower than the first speed, the second stage,
A first precharge circuit coupled to the anode of the diode; a second precharge circuit coupled to a node that precharges the first terminal and node of the second capacitor to a starting voltage prior to the first transition signal;
Combined with a node on the integrated circuit and a voltage boost circuit, provides a signal to the voltage boost circuit when the node reaches a first threshold, and signals to the voltage boost circuit when the node reaches a second threshold And a detection circuit for supplying the detection circuit,
A first detection coupled to the node that provides a first control signal to the voltage boost circuit while the voltage boost circuit continues to boost at a first rate within a first time interval when the node reaches a first threshold. Circuit,
The word line voltage at the node supplies the second control signal to the voltage boost circuit while the voltage boost circuit continues to boost at the second rate within the second time interval when the node reaches the second threshold. A second detection circuit coupled to the node, wherein the second detection circuit is configured to increase less than the first time interval during the time interval;
Integrated circuit including. A second drive circuit,
An inverter having an input connected to receive the boost signal, and an output coupled to the second terminal of the second capacitor and the first and second power supply terminals;
A current source coupled to one of the first and second power supply terminals having a first mode supply current at a first speed and having a second mode supply current at a second speed;
The integrated circuit of claim 10 comprising: The integrated circuit of claim 10 , wherein the array of memory cells includes ROM cells. The integrated circuit of claim 10 , wherein the array of memory cells comprises floating gate memory cells. 11. The integrated circuit of claim 10 , wherein the boost circuit reaches the first threshold in 2 nanoseconds or less after the boost signal transition.

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