JP2003517719A - High-speed on-chip voltage generator for low power integrated circuits - Google Patents

Abstract

To provide an on-chip voltage generation circuit used in an integrated circuit such as a flash memory device having a low power supply voltage capable of generating an on-chip voltage quickly and accurately. SOLUTION: The voltage generation circuit includes first and second level detectors (209 and 210) and a boost drive circuit (204), and the voltage generation circuit responds to the output of the detector by the first and second level detectors. Pump charge at speed.

Description

Detailed Description of the Invention

[0001] BACKGROUND Technical Field The present invention belongs invention relates to on-chip voltage generation techniques for generating a voltage outside the power supply voltage range supplied to the chip on the chip, and more particularly, the power supply voltage is in memory Flash memory, mask RO that is lower than the read potential required to detect the data of
M and the generation of word line voltages on low power memory devices such as SRAMs.

Prior Art Traditionally, integrated circuits have been manufactured to operate with a power supply voltage of about 5 volts within a specified range of ± 10%. Of course, other power supply voltages are also used. The current trend is to design integrated circuits to operate at lower supply voltages for many applications. In general, lower voltages result in lower power operation of the device and can be easily battery powered in small devices. For example, one of the emerging low power supply voltages specifies that it will operate in the range of about 2.7 to about 3.6 volts. Other standards around lower voltage have also been developed.

However, on-chip circuits are often designed to operate at higher voltages for several purposes. For example, in memory devices such as flash memory, the word lines that provide the gate voltage to the memory cells are often designed to operate at read voltages of 4 volts or higher. Therefore, the low power supply voltage is not sufficient to directly supply a high enough on-chip voltage to drive the word line. This problem is addressed by including a charge pump or other voltage supply booster on the integrated circuit to provide a higher operating voltage on the chip. See, for example, US Pat. No. 5,511,026, "Booted and Regulated Gate Power Supply with Reference Tracking for Multiple Density and Low Power Memory". The '026 patent is a charge / voltage converter configured to supply a word line voltage at a level higher than the power supply potential.
An integrated circuit memory with a pump is described. In addition, the '026 patent provides multiple word line voltages for a multi-level / memory device such that using a standard power supply potential provides more operating margin between memory cell states than is normally available. It describes the use of on-chip charge pumps to provide.

One related to conventional approaches of on-chip charge pumps for these purposes
One problem arises from the difficulty of producing well regulated output levels without sacrificing speed. Well regulated levels are especially important in multi-level per cell memory devices or low voltage devices operating with a narrow margin of read voltage. However, it is preferable to read at high speed. The time required to stabilize the charge pump output to a well regulated level contributes a significant portion of the delay to the read operation or operations that require the output generated by the charge pump for the operation.

Therefore, it is desirable to provide an on-chip voltage supply circuit for use in integrated circuits that operates at high speed and provides more accurate control of the on-chip voltage.

DISCLOSURE OF THE INVENTION The present invention is a low power supply voltage (eg, 2.7 to 3.
An on-chip voltage generating circuit suitable for use in an integrated circuit having 6 volts) is provided. According to one aspect of the invention, an integrated circuit having a supply voltage input capable of receiving a supply potential within a prespecified range of voltages, the integrated circuit having a higher on-voltage than the supply voltage within the prespecified range. It is characterized as an integrated circuit that includes components on the integrated circuit that use the chip voltage. A voltage boost circuit is coupled to the supply voltage input and a boost signal that boosts an on-chip voltage to a node on the integrated circuit in response to the transition of the boost signal. The voltage boost circuit has a first mode of boosting the on-chip voltage with a first speed boost to a first threshold in response to the transition and a second mode of boosting after reaching the first threshold. A second mode of boosting the chip voltage. In the preferred system, the second speed boost is slower than the first speed boost. The detection circuit is coupled to a node on the integrated circuit that receives the on-chip voltage and the voltage boost circuit. The detection circuit provides a signal to the voltage boost circuit when the node reaches the first threshold and a signal to the voltage boost signal circuit when the node reaches the second threshold. According to one aspect of the invention, the first threshold is 5
Reached in nanoseconds or less. More preferably, it is 2 nanoseconds or less of the transition of the boost signal.

According to one aspect of the invention, the detection circuit includes a first detector that provides a first control signal to the voltage boost circuit within a first time interval at which the node reaches a first threshold.
During the first time interval, the voltage boost circuit continues to boost at the first rate. A second detector is coupled to the node and provides a second control signal to the voltage boost circuit within the second time interval for the node to reach the second threshold. During the second time interval, the voltage boost circuit continues to boost at the second rate such that the on-chip voltage on the node increases less during the second time interval than during the first time interval. This slower increase during the time interval between the signal of the voltage boost circuit and the detection of the second threshold of the second detector is
It enables more precise control of the turn-off of the voltage boost circuit in response to the passage of the threshold value. It responds to signal transitions while maintaining an accurate cutoff,
Allows a very fast boost of the initial difference in voltage pumping.

According to another aspect of the invention, a voltage boost circuit includes a capacitor and a drive circuit coupled to one terminal of the capacitor. The drive circuit provides a transition to the capacitor by supplying current at a first rate during the first mode and supplies current at a second rate during the second mode. In one approach, the drive circuit includes an inverter whose input is connected to receive the boost signal and whose output is coupled to the capacitor. An inverter is coupled to the first and second power supply terminals and to any one of the first and second power supply terminals having a first mode supply current at a first speed and a second mode supply current at a second speed. And a current source that has been set. In this way, the rate of increase of the voltage on the capacitor can be controlled in the first and second modes to set pumping at faster and slower rates.

According to another aspect of the invention, a voltage boost circuit includes a first stage and a second stage. First
The stage has a capacitor having first and second terminals, a diode having an anode coupled to the second terminal capacitor and a cathode coupled to a node on the integrated circuit;
including. A driver is coupled to the first terminal of the capacitor and provides a first transition signal to the first capacitor. The second stage includes a second capacitor having a first terminal coupled to a node on the integrated circuit. A second driver is coupled to the second terminal of the second capacitor and provides a boost signal transition to the second terminal of the capacitor according to the two modes of operation described above.

In one aspect of the invention, the circuit also includes a first precharge circuit coupled to the anode of the diode in the first stage and a second precharge circuit coupled to the cathode of the diode.

In addition, the circuit according to the preferred embodiment includes on-chip logic capable of generating the first transition signal and the transition of the boost signal.

The present invention is particularly suitable for implementation on an integrated circuit memory including an array of memory cells of a plurality of word lines and a plurality of bit lines. A set of word line driver circuits is coupled to the plurality of word lines and uses a word line voltage higher than a prespecified range of supply voltage inputs. The logic detects an event on the integrated circuit, such as an address signal transition, and generates a boost signal transition. The voltage boost circuit and the detection circuit described above are included on the chip to perform the voltage boost of the word line. According to one aspect of the invention, an integrated circuit memory includes an array of ROM cells. In another aspect, the array of memory cells includes floating gate memory cells such as flash memory.

Other aspects and advantages of the present invention will become apparent from the following description of the embodiments of the present invention with reference to the drawings.

[0014] With reference to Embodiment FIGS. 1 to 9 of the invention, a detailed description of embodiments of the present invention. FIG. 1 shows an entire flash memory device incorporating an on-chip voltage supply circuit for generating a read mode word line voltage. That is, FIG. 1 shows an integrated circuit. The integrated circuit includes a supply voltage input 10 capable of receiving a supply voltage VDD. The supply voltage for one embodiment is 2.7 to 3.6 volts. A ground input 11 is provided. There are control signal inputs such as address inputs 12, chip enable inputs 13 and output enable inputs 14, and input and output pins including data input / output pins 15 on the integrated circuit.

The integrated circuit includes a floating gate transistor and an array of ROM cells, such as mask ROM cells, or a flash memory array 16 including other memory cells. Array 1
6 includes a plurality of word lines indicated by arrow 17, for example. The word lines are word line detector section 0, word line detector section 1, word line detector section 2, word line detector section 3, word line detector section 4, word line detector section 5, word in this example. It is driven by a word line decoder having a plurality of sections including a line detector section 6 and a word line detector section 7. In addition, the column decoder and data input / output circuit 18 has an arrow 19 in the array 16.
Connected to a plurality of bit lines represented by. The column decoder 18 and word line decoder 20 are controlled by the address received from the address input 12. The addresses can be characterized as including a row address on line 21 and a column address on line 22, which drive word line decoder 20 and column decoder 18, respectively.
Also included is a word line spare decoder 23 coupled to address line 12. The word line preliminary decoder 23 generates the selection control signal SEL (0-7) on the line 24 which is supplied to the word line decoder section 0-7, respectively. In this example, the three upper bits of the row address portion of the address on line 12 control word line predecoder 23 and are used to select a particular word line decoder section from word line decoder 20.

Mode logic 26 is included on the chip. The mode logic 26 receives the chip enable and chip select signals on lines 13 and 14 as well as other signals for controlling the mode operation of the flash memory. Flash memory devices include read mode, program mode, erase mode, and other modes suitable for the particular implementation of program and erase operations. The read control signal on line 40 is generated by the mode control logic 26. A program and erase mode word line voltage pump 28 is included on the chip. For read mode, a read mode word line voltage booth and circuit 29 is included. According to the present invention, the read mode word line voltage boost circuit 2
9 includes a high speed multi-stage boost circuit. Read mode word line boost circuit 29
The outputs of the include the word line voltages AVX (0-7) on line 30 for each word line detector section. According to the present invention, the read mode word line voltage boost circuit 29 responds to the level of the AVX 30. Further, the read mode word line voltage boost circuit 29 responds to the address transition detection circuit 33. The address transition detection circuit 33 generates a signal on the line 35 indicating an address transition.

Therefore, as shown in FIG. 1, the present invention is applied to word line voltage generation for a read mode of a flash memory device. The invention is particularly applicable to, for example, 2.7 to 3
． Suitable for flash memory with low power supply voltage in the range of 6 volts. The invention is also suitable for other devices and ROM arrays that require a boosted voltage on a node such as node 30 on an integrated circuit.

FIG. 2 shows a block diagram of a word line voltage boost circuit according to the present invention. The circuit receives the address as an input on the integrated circuit and provides as an output an address transition detection signal ATS on line 201 and on line 202 a first address transition detection pulse A
An address transition detection circuit 200 is provided which provides TD1ST and provides a second address transition detection pulse on line 203. The second pulse ATD2ND on line 203 is connected to the first stage boost drive circuit including pump capacitor C1 and logic block 204. The pump capacitor is connected to the diode of diode 205. The cathode of diode 205 is connected to node 206 where voltage AVX is generated. The second stage boost drive circuit and logic block 207 also includes line 203
Receive pulse ATD2ND above and address transition detect signal A on line 201
Connected to receive TD. The output of the second stage block 207 is the line 208.
The above boost signal is provided to capacitor C2. The second terminal of the capacitor is node 2
It is connected to 06. First level detector 209 and second level detector 210 are coupled to node 206 and produce a first control signal CT1 on line 211 and a second control signal CT1SP on line 212, respectively. These signals are provided to the second stage block 207 to control the charging rate of capacitor C2 in response to the boost signal transition on line 208.

The word line voltage generator in FIG. 2 also includes a first precharge circuit 215 and a second precharge circuit 216. First and second precharge circuits 215, 216 precharge the anode of diode 205 and node 206 to near the supply potential to facilitate the boost process. Control signals including a chip enable active low CEL signal on line 217, an enable ready signal ENRDYB on line 218, and an enable address transition detect signal ENATD on line 219 are provided to the precharge circuit. In addition, the precharge circuit responds to the first address transition pulse ATD1ST on line 202.

FIG. 3 is a timing chart of the AVX signal level and the address transition detection signal on the node 206.

In FIG. 3, the address input to the address transition detect signal is shown on trace 300. The address transition detect signal on line 201 is shown on trace 301.
The first address transition detection pulse ATD1ST is shown on the trace 302. The second address transition detection pulse ATD2ND is shown on the trace 303. The level of voltage AVX on node 206 is shown on trace 304.

In this example, the level of the AVX signal on line 304 starts at a supply voltage level of approximately VDD, as shown at point 310. At time 311, the address changes at the input of the integrated circuit. It transitions the address transition detect signal high at time 311 and low at time 312. In this example, time 31
The spacing of the ATD signal on line 301 between 1 and 312 is about 20 nanoseconds. Address transition detection circuit 200 generates a first pulse that begins at time 311 and ends at time 313, as indicated by the ATD1ST signal on line 302. ATD2ND
The signal transitions to a high state at time 313 and a low state at time 314, which is close to time 312.

Boosting node AVX begins at time 311 with precharge caused by the ATD1ST pulse. In trace 304 of FIG. 3, this precharge does not reflect any changes in the level of the AVX signal. However, if the AVX signal is AT
If it was not precharged to VDD level before D signal, its level is VD
It would have been lifted to near D. The precharge circuit also connects capacitor C1 to V
Precondition to boost above the DD level.

At the rising edge of the ATD2ND signal at time 313, the first stage boost pump produces a transition on capacitor C1. This boosts the anode of diode 205 above the level of node 206, and region 31 between times 313 and 312.
Induces an increase in AVX signal as indicated by 5.

At the falling edge of the ATD signal at time 312, the second stage boost pump is turned on at time 312.
A fast transition 316 of the boost signal 208 begins in the abrupt region 316 of the trace 304 immediately after. At time 317, the voltage level detector B210 detects that the AVX signal has crossed the first threshold. This switches the second stage boost pump to a slower speed boost, as shown in area 319 of trace 304, shortly after time 317.

At time 318, the level detector A 209 detects that the voltage level AVX has reached the final threshold and generates the control signal CT 1 on the line 211. This stops the boost speed of the second stage pump.

In this example, the interval between the fast boost times 312 and 317 is less than about 2 nanoseconds, or less than about 5 nanoseconds. Trace 31 between times 317 and 318
The slower boost time interval in 9 is less than about 10 nanoseconds, or less than about 20 nanoseconds.

The overall slower boost rate during interval 319 allows more time for feedback circuitry to more accurately control the final level of the AVX signal. Interval 31
The faster boost speed in 6 significantly speeds up the boost process without sacrificing cutoff level accuracy.

4, 5, 6, 7, 8 and 9 provide detailed circuit diagrams of the voltage boost circuit in the preferred embodiment of the present invention. FIG. 4 shows a first stage pump and a second stage pump. The first stage pump receives the second pulse ATD2ND on line 400. This signal is supplied to the first terminal of the capacitor C1 via the inverter 401, the inverter 402, the inverter 403, and the inverter 404. Thus, at the rising edge of pulse ATD2ND on line 400, the signal on the first terminal of capacitor C1 transitions from a low value to a high value. The second terminal of the capacitor C1 is connected to the anode of the diode 405. The cathode of diode 405 is connected to node 406 where the AVX voltage is generated.

The second stage of the pump includes a second pulse ATD2ND on line 400 and an address transition detect signal ATD on line 410. These signals are provided as inputs to NOR gate 411, which in turn provides inputs to inverter 412. The output of the inverter 412 is the reset input of the set / reset SR latch 413 and the NOR gate 414.
Is supplied as one input of. Active low chip enable signal CEB 415 is provided to the set input of SR latch 413. The output of the SR latch is NOR gate 4
14 second input. The output of NOR gate 414 drives inverter 416, which in turn drives inverter 417. Inverter 417 provides inputs to inverter 418 and inverter 419. The output of inverter 419 is coupled to the first terminal of capacitor 420. The second terminal capacitor 420 is connected to the source of the n-channel transistor 421. The drain of n-channel transistor 421 is connected to supply potential VDD. The gate of the transistor 421 is the line 422.
Receive the above control signal ENATD. In addition, the capacitor 420 is a diode 423.
Connected to the anode of. The cathode of diode 423 is connected to node 406. The control signal on line 422 pulls the anode of diode 423 to the supply potential level during operation of the pump circuit. Node 406 through diode 423
The circuit including transistor 421, capacitor 420, and inverter 419 coupled to operate in precharge capacity. When the ENATD signal is low, CEB sets latch 413, causing a transition on the output of inverter 419. This is capacitor 4
20 and diode 423 to boost node 406 to the precharge level to assist the precharge function.

Boost is enabled through inverter 418 when the address transition detect enable signal is high. Inverter 418 drives bimode inverter 425. The output of the 2-mode inverter is the boost signal on line 426 which is coupled to capacitor C2. The second node of the capacitor C2 is supplied to the terminal 406. The two-mode drive circuit 425 has a power supply terminal connected to a current source circuit including transistors 428, 429, 430, and 431. In this example, transistors 428 and 429 consist of p-channel transistors having a width of 3 microns and a length of 5 microns. The gates and drains of transistors 428 and 429 are each coupled together in a diode configuration. The n-wells of the transistors are each coupled to the source. These transistors provide a weak pull-up to the power supply terminal of the drive circuit 425 to prevent it from floating.

Transistors 430 and 431 set the boost signal on line 426 at two boost rates. In this example, transistor 430 is transistor 431.
Has a width of about one-fifth of the width (eg, 50 microns) and has a length of about 0.5 microns. Transistor 430 is a p-channel transistor with control signal CT1 coupled to its gate. The transistor 431 has a control signal CT1.
A p-channel transistor with SP coupled to its gate. Transistor 431 has a width of about 5 times the width of transistor 430 (eg, 250 microns) and a length of about 0.5 microns. Therefore, the transistor 431 controlled by CT1SP is much stronger than the transistor 430 controlled by CT1. The drains of transistors 430 and 431 are both coupled to the power supply terminal of drive inverter 425. When both CT1 and CT1SP are low, trace 304 in FIG.
Generating a fast boost during boost signal 426 as reflected in the interval between times 312 and 317 during. When the control signal CT1SP goes high, the transistor 431 turns off and is driven only by the transistor 430, substantially reducing the boost speed. This reflects a slow speed boost during the interval 319 between times 317 and 318 of trace 304 in FIG.

The boost rate of the signal in node 426 is directly reflected across capacitor C2 on node 406 in the manner shown by trace 304 in FIG.

The CT1 and CT1SP control signals for the gate of transistor 430 are generated by the level detector shown in FIGS. 6 and 7. ATD1ST pulse and ATD2
The ND pulse is generated by the circuit shown in FIG.

The precharge circuit shown in FIGS. 8 and 9 used for setting the boost operation of the circuit is coupled to the boost circuit. A first precharge circuit 490 is coupled to the anode of diode 405. The second precharge circuit 491 is the diode 40.
5 cathode node 406.

The ENRDYB, CEL, CEB, and ENATD control signals are control signals generated by standard design logic.

In FIG. 5, the ATD1ST and ATD2ND signals are generated in response to the address transition detect ATD signal on line 500. The ATD signal may be used, for example, by the inventor, In Liu et al. In US patent application Ser.
, 513 “Address transition detection circuit”. Upon transition of the address signal, an ATD pulse of approximately 20 nanoseconds is generated in the preferred system as shown in FIG. This signal is applied to the NAND gate 501 and the inverter 502.
It is added to the one-shot circuit consisting of. The input ATD signal line 500 is an inverter 5
02 input and one of the NAND gates 501. The output of the inverter 502 is connected to the second input of the NAND gate 501. NAND gate 501
Is output to the inverter 503. The output of the inverter 503 is ATD on line 436.
Supply 1ST signal. The ATD1ST signal is supplied to the inverter 504 and the NOR gate 50.
5 is supplied to the second one-shot circuit including 5. The ATD1ST signal is connected to the input of the inverter 504 whose output is connected to the input of the NOR gate 505. Also, AT
The D1ST signal is connected to the second input of NOR gate 505. NOR gate 5
The output of 05 is connected to the set input of the SR latch 506. In addition to this, N
The output of OR gate 505 is connected as one input to NOR gate 507. The output of NOR gate 507 is connected to the reset input of SR latch 506. The Q output of SR latch 506 is connected to inverter 508, which in turn
Drive 9 The output of inverter 509 is the ATD2ND signal on line 400.

The first level detector shown in FIG. 6 produces a CT1SP signal. The second level detector shown in FIG. 7 produces a CT1 signal. The CT1SP signal triggers on a lower level AVX than the CT1 signal. The detector of FIG. 6 is enabled by the output of NOR gate 600 which receives as input the CEB signal on line 601, the ATD1ST signal on line 436, and the CT1 signal on line 700. The output of NOR gate 600 is connected to the gate of transistor 603 via inverter 602. The output of the inverter 600 is also connected to the gate of the transistor 604. NOR gate 600
When the output is high, transistor 604 is turned on and transistor 603 turns off the enablement of the level detector circuit.

The level detector circuit includes a first current leg that receives the AVX signal from node 406 as an input. This node is connected to the n-well and source of p-channel transistor 604. The gate and drain of p-channel transistor 605 are connected to the n-well and source of p-channel transistor 606. The gate and drain of the transistor 606 are connected to the drain of the transistor 604. The source of transistor 604 is connected to the gate and drain of n-channel transistor 607. The source of the n-channel transistor is connected to ground.

The second current leg of the level detector includes a first node connected to the power supply potential VDD. P-channel transistor 610 and p-channel transistor 611 have their sources connected to the supply potential. The gate and drain of the transistor 610 are connected to the drain of the transistor 612. Transistor 611
Is connected to the output of inverter 613 which receives as input the SBCTL1 signal on line 614 which is supplied from the output of inverter 602. Thus, when the SBCTL1 signal is high, the signal on the gate of transistor 611 is low, allowing increased current through the circuit.

The source of the transistor 612 is grounded. The gate of transistor 612 is connected to the gate of transistor 607 in a current mirror manner. The gate of the transistor 612 and the gate of the transistor 607 are connected to the drain of the transistor 603. The node NISP on the drain of transistor 612 is connected as the input of inverter 615. The output of the inverter 615 is connected to the S input of the SR latch 616. The reset input of SR latch 616 is ATD1 on line 436.
Connected to receive the ST signal. The Q output of the SR latch 616 is the inverter 61.
8 is connected to an inverter 617. The output of inverter 618 is control signal CT1SP on line 620. In operation, when the signal AVX increases, the current increases through the current mirror leg of the detector. The voltage NISP drops as the current increases through transistors 610 and 611. The voltage NISP is the inverter 61.
When falling below the trip point of 5, latch 616 is set to generate the CT1SP signal.

FIG. 7 shows a level detector for generating the CT1 signal. This level detector is enabled by the output of NOR gate 701 which receives the CEB signal on line 601 and the ATD1ST on line 436. The output of NOR gate 701 is connected to the gate of n-channel transistor 702 and the input of inverter 703. The input of inverter 703 is connected to the gate of n-channel transistor 704.
The drain of the transistor 704 is connected to the node 705. Transistor 70
The source of 4 is connected to ground. Thus, when the output of NOR gate 701 goes high, the circuit is enabled by turning off transistor 704 and turning on transistor 702. In addition to this, the output of the inverter 703 produces the control signal SBCTL which is supplied to the input of the inverter 706. A high level at the input of inverter 706 turns on transistor 707.

The level detector includes a first current leg connected to the voltage AVX on node 406. Node 406 is connected to the source of p-channel transistor 708 and the n-well. The gate and drain of transistor 708 are coupled to the source and n-well of p-channel transistor 709. Transistor 70
The gate and drain of 9 are connected to the source and n-well of the transistor 710 and the source and n-well of the transistor 711, respectively. The gate of transistor 710 is connected to receive the control signal CT1 on line 700. The gate and drain of transistor 711 and the drain of the transistor are connected to the gate and drain of n-channel transistor 712. The source of transistor 712 is connected to the gate and drain of triple well n-channel transistor 713. The isolation well of transistor 713 is connected to AVX node 406. The p well and source of the transistor 713 are the transistor 702.
Connected to the drain of. The source of transistor 702 is connected to the drain and gate of transistor 714 at node 705. The source of transistor 714 is connected to ground.

The second current leg of the level detector includes a transistor 707 having its source connected to the supply potential and its drain connected to the drain of transistor 715. The source of transistor 715 is connected to ground. The gate of the transistor 715 is connected to the node 705 in common with the transistor 714. In addition to this, transistor 7
16 has its source connected to the supply potential and its drain connected to the drain of transistor 715.

The circuit operates in the manner described above for FIG. 6, except for the high threshold. That is, as the voltage level AVX increases, the current increases through the current mirror legs. When the current reaches a certain level, the voltage on node NI at the input of inverter 717 reaches the trip point of the inverter. The output of the inverter 717 is connected to the set input of the SR latch 718. The Q output of SR latch 718 is connected to inverter 719, which in turn drives inverter 720. The output of inverter 720 is CT1 on line 700.
It is a signal. The reset input of SR latch 718 receives the ATD1ST signal on line 436.

The transistor 710 operates to turn off when the CT1 signal goes high. This reduces the current through the level detector and saves circuit power.

The level detection circuit described here constitutes a preferred embodiment. There are various levels of detection circuit approaches used in accordance with the present invention. According to the present invention, when the voltage level of the AVX increases rapidly during the first stage pumping, it is possible to detect the level shift of the AVX using the circuit of FIGS. 6 and 7 or another type of level detector. It can be seen that a delay on the order of a fraction of a nanosecond included is a significantly accurate cutoff. The ability to adjust the timing of these detectors to 1 nanosecond or less in order to block the boost level of the AVX signal at the preferred predetermined level, according to the present invention, boosts when the level reaches the desired block. It is solved by reducing the speed. In this way, the relative timing of the CT1SP signal and the arrival of the final level of boost are less critical. The present invention allows a rapid boost, but avoids overshoot conditions.

FIG. 8 shows the first precharge circuit 490. It receives the line 435 as an input signal.
It receives the enable ATD signal above and the first ATD pulse ATD1ST on line 436. These signals are provided as inputs as inputs to NAND gate 437, the output of gate 437 driving inverter 438. The output of the inverter 438 is connected to the source and drain of the capacitor connection transistor 439. The gate of transistor 439 is connected to the gate of n-channel transistor 440. The source of n-channel transistor 440 is connected to line 432 which is coupled to the anode of diode 405. The drain of the transistor 440 is connected to the supply potential VDD. The gate of the transistor 440 is
The source is connected to the supply potential VDD and the gate is the control signal ENRDY on line 442.
B is connected and the drain is biased by a circuit including a p-channel transistor 441 connected to the anode of diode 443. The cathode of the diode 443 is connected to the gate of the transistor 440. Transistor 444 has its drain connected to the gate of transistor 440 and its source connected to ground. The gate of transistor 444 is the control signal C on line 445.
It is connected to EL. In addition, transistor 446 has its drain connected to the gate of transistor 440 and its source connected to ground. The gate of transistor 446 is connected to the control signal ENRDYB signal on line 442. In operation, the gate of transistor 440 is ENRDYB on line 442.
In response to a low signal on the terminal, the level is determined by the voltage drop below the supply potential across transistor 441 and diode 443. When the control signal CEL on line 445 goes high, the node is connected to ground. Similarly, the control signal EN
When RDYB goes high, the node is connected to ground through transistor 446.

In addition to this, the precharge circuit has a gate and a drain coupled to the supply potential,
The source includes a transistor 450 connected across line 430 to the anode of diode 405. This diode-connected transistor 450 has a starting point
Keep the node level at a threshold drop below VDD. In response to the ATD1ST pulse, the gate of transistor 440 is boosted, pulling the anode of diode 405 to VDD level to compensate for the threshold drop across transistors 440 and 450.

A second precharge circuit is shown in FIG. 9 and is similar to the first precharge circuit. It receives its input ENATD on line 435 and the ATD1ST signal on line 436.
These signals are supplied as inputs to the NAND gate 457. Gate 457 drives inverter 458. The inverter 458 is a capacitor-connected transistor 45.
9 is connected to the source and drain. Gate transistor 459 is connected to the gate of transistor 460. The gate of transistor 460 is also biased by a circuit including p-channel transistor 461 having its source connected to supply potential VDD and its drain connected to gate transistor 460 via diode 462. Transistors 463 and 464 are n-channel transistors with their drains connected to the gate of transistor 460 and their sources connected to ground. The gate of transistor 463 is C on line 445.
Receive an EL control signal. The gate of transistor 461 and the gate of transistor 464 receive as input the control signal ENRYDB on line 442.

The second precharge circuit includes a transistor 470 having its gate and drain connected to the supply potential VDD and its source connected to the node 406 on line 431.

In the circuit of this example, the parameters and relative sizes of the circuit components of FIGS. 4 to 9 are given in the table below. table

The transistor size and capacitor parameters above are representative of particular implementations designed to the needs of a particular semiconductor device. Obviously, the relative size and component variations of these transistors may be appropriate for some situations. However, these were provided as a basis for a more detailed understanding of the operation of the exemplary circuit.

Accordingly, an official bimodal voltage boost circuit for use in read operations for flash memory and other memory devices has been disclosed. The circuit is also suitable in other environments where a fast boost with a precise cutoff level is desired. For example, accurate cut-off levels are of particular importance for multi-level cells, which rely on very tight margins on the word line voltage for reading different levels of cells.

The detailed description of the preferred embodiments of the present invention has been made for purposes of illustration. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Obviously, many modifications and variations will be readily apparent to those of ordinary skill in the art.

[Brief description of drawings]

[Figure 1]   FIG. 3 is a block diagram of an integrated circuit memory device including the on-chip voltage supply circuit of the present invention.

[Fig. 2]   2 is a block diagram of the word line boost circuit of the present invention used in the system of FIG.

[Figure 3]   FIG. 5 is a timing diagram used to explain the operation of the present invention.

[Figure 4]   FIG. 3 is a circuit diagram of a preferred embodiment of a boost circuit according to the present invention.

5 is a schematic diagram of the logic used to generate the transition signals used by the boost circuit of FIG.

[Figure 6]   FIG. 5 is a circuit diagram of a voltage level detector used in combination with the circuit of FIG. 4.

[Figure 7]   FIG. 5 is a circuit diagram of a second voltage level detector used with the circuit of FIG. 4.

[Figure 8]   FIG. 5 is a circuit diagram of a precharge circuit used with the circuit of FIG. 4.

[Figure 9]   FIG. 5 is a circuit diagram of a second precharge circuit used with the circuit of FIG. 4.

─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Chen Ken-Hui             Taiwan 412 Thailand-Chun Thali Chen             -Kun Road Number 139 (72) Inventor Ho Tien-Shin             Taiwan 231 Taipei County Shin             -Tien Chun-Cheng Rhodes             Treat 230-1 3 F (72) Inventor Lee Yi Long             Taiwan 300 Shin Gwang-Furo             DSC Second Lane 155               Array 10 Number 13-33 F (72) Inventor Shio Tsin-Hay             Taiwan 305 Shinchu Country Shin             -Puchun-Cheng Road 595 (72) Inventor One Ray-Lin             United States California             94539 Fremont Wichita Dora             Eve 709 F term (reference) 5B015 HH01 HH03 JJ21 KA22 KB63                       KB73 KB86 QQ11                 5B025 AD03 AD05 AD10 AE05                 5F038 BG05 BG08 EZ20

Claims (27)

[Claims] 1. An integrated circuit comprising a component on an integrated circuit having an input supply voltage capable of receiving a supply voltage within a predetermined voltage range and using an on-chip voltage higher than this predetermined range, A voltage boost circuit coupled to a supply voltage input and a boost signal that boosts an on-chip voltage to a node on an integrated circuit in response to a transition of the boost signal, the voltage boost circuit first responsive to the transition. A first mode for boosting the on-chip voltage at a first speed of boost to a threshold and a second mode for boosting the on-chip voltage at a second speed of the boost after a first threshold to a second threshold. Have a second
The speed is slower than the first speed and is coupled to the voltage boost circuit and the node on the integrated circuit and the voltage boost circuit to signal the voltage boost circuit when the node reaches the first threshold, and the node to the second speed. A detection circuit that signals a voltage boost circuit when a threshold is reached; 2. The detection circuit has a first voltage boost circuit within a first time interval during which the node reaches a first threshold value.
A first detection circuit coupled to the node for providing a first control signal to the voltage boost circuit while continuing to boost at a speed, and a voltage boost circuit within a second time interval for the node to reach a second threshold Is the second
Providing a second control signal to the voltage boost circuit while continuing to boost at a rate such that the on-chip voltage at the node increases during the second time interval by less than the first time interval; 2. The integrated circuit according to claim 1, including two detection circuits. 3. The voltage boost circuit includes a capacitor having a first terminal and a second terminal coupled to a node of the integrated circuit, and providing current at a first rate during the first mode and during the second mode. The integrated circuit of claim 1, further comprising: a drive circuit coupled to the second terminal of the capacitor, which provides a transition to the second terminal of the capacitor by supplying current at a second rate. 4. A inverter having a drive circuit having an input connected to receive a boost signal, an output coupled to a second terminal of a capacitor, and first and second power supply terminals. 4. A current source coupled to one of the first and second power supply terminals having a first mode supply current at a speed and a second mode supply current at a second speed. Integrated circuit. 5. A diode, the voltage boost circuit having a first capacitor having a first terminal and a second terminal, an anode coupled to the second terminal of the capacitor and a cathode coupled to a node of the integrated circuit. A first stage including a drive circuit coupled to a first terminal of the capacitor supplying a first transition signal to the first capacitor; and a first stage having a first terminal and a second terminal coupled to a node on the integrated circuit. Two capacitors and a second terminal of the second capacitor coupled to the second terminal of the capacitor by supplying current at a first rate during the first mode and supplying current at a second rate during the second mode. The integrated circuit of claim 1, further comprising a second drive circuit that provides a transition of the boost signal. 6. A first precharge circuit coupled to the anode of the diode, and a second precharge circuit coupled to the second terminal of the first capacitor and a node for precharging the node to a starting voltage prior to the first transition signal. The integrated circuit of claim 5, comprising a circuit. 7. The integrated circuit of claim 5, including logic responsive to an event to generate a transition of the first transition signal and a boost signal. 8. The boost circuit is configured to perform a first operation within 5 nanoseconds or less after transition of the boost signal.
The integrated circuit of claim 1, wherein a threshold is reached. 9. The integrated circuit of claim 1, wherein the boost circuit reaches the first threshold in about 2 nanoseconds or less after the transition of the boost signal. 10. An integrated circuit memory having a supply voltage input capable of receiving a supply voltage within a predetermined range of voltages, the array of memory cells coupled to a row of memory cells of the array. Driving word lines, bit lines coupled to columns of memory cells in an array, and word line voltages higher than a supply voltage in a predetermined range onto a word line selected from a node on the integrated circuit. A set of word line drive circuits coupled to a plurality of word lines, logic to detect an event on the integrated circuit and generate a boost signal transition, and a boost voltage signal coupled to the supply voltage input. A voltage boost circuit that receives and boosts an on-chip voltage to a node on an integrated circuit in response to a transition of the boost signal, the voltage boost circuit being responsive to the transition to a first threshold. A first mode of boosting the on-chip voltage at a first speed of strike and a second mode after a first threshold
A second mode for boosting an on-chip voltage at a second speed of boost to a threshold, the second speed being slower than the first speed, and a node on the integrated circuit and the voltage boost circuit. An integrated circuit that couples and signals the voltage boost circuit when the node reaches the first threshold and signals the voltage boost circuit when the node reaches the second threshold. 11. The integrated circuit of claim 10, wherein the integrated circuit comprises at least one address input, the logic including circuitry for generating a transition of the boost signal in response to a transition on the at least one address input. 12. The detection circuit has a first voltage boost circuit within a first time interval during which the node reaches a first threshold value.
A first detection circuit coupled to the node for providing a first control signal to the voltage boost circuit while continuing to boost at a speed, and a voltage boost circuit within a second time interval for the node to reach a second threshold Is the second
Providing a second control signal to the voltage boost circuit while continuing to boost at a rate such that the word line voltage at the node increases less than the first time interval during the second time interval; 11. The integrated circuit according to claim 10, including two detection circuits. 13. The voltage boost circuit includes a capacitor having a first terminal and a second terminal coupled to a node of the integrated circuit, and providing current at a first rate during the first mode and during the second mode. 11. The integrated circuit of claim 10, further comprising: a drive circuit coupled to the second terminal of the capacitor that provides a transition to the second terminal of the capacitor by supplying current at a second rate. 14. An inverter having a drive circuit having an input connected to receive a boost signal, an output coupled to a second terminal of a capacitor, and first and second power supply terminals. 14. A current source coupled to one of the first and second power supply terminals having a first mode supply current at a speed and a second mode supply current at a second speed. Integrated circuit. 15. A diode, the voltage boost circuit having a first capacitor having a first terminal and a second terminal, an anode coupled to the second terminal of the capacitor and a cathode coupled to a node of the integrated circuit. A first stage including a drive circuit coupled to a first terminal of the capacitor supplying a first transition signal to the first capacitor; and a first stage having a first terminal and a second terminal coupled to a node on the integrated circuit. Two capacitors and a second terminal of the second capacitor coupled to the second terminal of the capacitor by supplying current at a first rate during the first mode and supplying current at a second rate during the second mode. The integrated circuit of claim 10, further comprising a second stage including a second drive circuit that provides a transition of the boost signal. 16. A circuit comprising at least one address input, the logic generating a first transition signal transition and a transition in a boost signal after the first transition signal in response to a transition of the at least one address input. The integrated circuit of claim 15 including. 17. A first precharge circuit coupled to the anode of the diode,
16. The integrated circuit of claim 15, comprising a second terminal of the first capacitor and a second precharge circuit coupled to the node to precharge the node to a starting voltage prior to the first transition signal. 18. A precharge signal, a first transition signal after the precharge signal, and a boost signal after the first transition signal in response to a transition of the at least one address input, the logic including at least one address input. The integrated circuit of claim 17, wherein the first and second precharge circuits are responsive to the precharge signal. 19. The integrated circuit of claim 10, wherein the array of memory cells comprises ROM cells. 20. The integrated circuit of claim 10, wherein the array of memory cells comprises floating gate memory cells. 21. The integrated circuit of claim 10, wherein the boost circuit reaches the first threshold in less than 5 nanoseconds after the boost signal transitions. 22. The integrated circuit of claim 10, wherein the boost circuit reaches the first threshold in about 2 nanoseconds or less after the transition of the boost signal. 23. An integrated circuit memory having a supply voltage input capable of receiving a supply voltage within a predetermined range of voltages, the array of memory cells, at least one address input, and the array of memories. A plurality of word lines coupled to a row of cells, a plurality of bit lines coupled to a column of memory cells in an array, and a word line voltage higher than a predetermined range supply voltage from a node on an integrated circuit. A set of word line drive circuits coupled to multiple word lines that drive on selected word lines, and detect events on the integrated circuit to respond to precharge signals and at least one address input transition And a logic for generating a first transition of the boost signal after the precharge signal and a second transition of the boost signal after the first transition, and for the first and second precharge circuits to respond to the precharge signal. A voltage boost circuit coupled to the voltage input and receiving the boost signal to boost an on-chip voltage to a node on the integrated circuit, the voltage boost circuit including a first capacitor having a first terminal and a second terminal, The second of this capacitor
A first circuit comprising a diode having an anode coupled to a terminal and a cathode coupled to a node of the integrated circuit; and a drive circuit logically coupled to a first terminal of the capacitor for providing the first transition to the first capacitor. A second capacitor having a first terminal and a second terminal coupled to a node on the integrated circuit, and a first terminal coupled to the second terminal of the second capacitor until reaching the first threshold. A second drive circuit for supplying a second transition of the boost signal to a second terminal of the capacitor by supplying current at a speed and supplying a current at a second speed until a second threshold is reached; A second stage in which the first threshold reaches less than the second threshold of 5 nanoseconds and the second speed is slower than the first speed; and a first precharge circuit coupled to the anode of the diode, First before the first transition signal A second pre-charge circuit coupled to the second terminal of the capacitor and the node to pre-charge the node to the starting voltage, and a node on the integrated circuit and the voltage boost circuit, when the node reaches the first threshold value. A detection circuit for signaling the voltage boost circuit and for signaling the voltage boost circuit when the node reaches the second threshold, the detection circuit having a first time when the node reaches the first threshold. A first detection circuit coupled to the node that provides a first control signal to the voltage boost circuit while the voltage boost circuit continues to boost at a first rate within the interval; and the node reaches a second threshold Providing a second control signal to the voltage boost circuit while the voltage boost circuit continues to boost at the second rate within the second time interval, the word line voltage at the node being greater than the first time interval during the second time interval. An integrated circuit including a second detection circuit coupled to the node, the second detection circuit being configured to increase at least. 24. An inverter having a second drive circuit connected to receive the boost signal and having an input and an output coupled to the second terminal of the second capacitor and the first and second power supply terminals. A current source coupled to one of the first and second power supply terminals having a first mode supply current at a first speed and having a second mode supply current at a second speed. 23. The integrated circuit according to 23. 25. The integrated circuit of claim 23, wherein the array of memory cells comprises ROM cells. 26. The integrated circuit of claim 23, wherein the array of memory cells comprises floating gate memory cells. 27. The integrated circuit of claim 23, wherein the boost circuit reaches the first threshold in about 2 nanoseconds or less after the transition of the boost signal.