JP4344560B2 - 半導体チップおよびこれを用いた半導体装置 - Google Patents
半導体チップおよびこれを用いた半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 117
- 229910000679 solder Inorganic materials 0.000 claims abstract description 47
- 239000004020 conductor Substances 0.000 claims abstract description 27
- 238000007772 electroless plating Methods 0.000 claims abstract description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 84
- 238000000034 method Methods 0.000 claims description 53
- 239000010931 gold Substances 0.000 claims description 42
- 239000000758 substrate Substances 0.000 claims description 22
- 230000017525 heat dissipation Effects 0.000 claims description 15
- NWONKYPBYAMBJT-UHFFFAOYSA-L zinc sulfate Chemical compound [Zn+2].[O-]S([O-])(=O)=O NWONKYPBYAMBJT-UHFFFAOYSA-L 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims 1
- 238000007747 plating Methods 0.000 abstract description 67
- 230000002093 peripheral effect Effects 0.000 abstract description 10
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 238000005304 joining Methods 0.000 description 6
- 238000005476 soldering Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009429 electrical wiring Methods 0.000 description 2
- 238000002149 energy-dispersive X-ray emission spectroscopy Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Die Bonding (AREA)
- Electrodes Of Semiconductors (AREA)
Description
図5は、従来のケース構造型の半導体装置の断面図である。
なお、接続導体は、半導体チップの表面電極と絶縁基板上に構成された第2の回路パターンとに接合されるリードフレームと、半導体チップの表面電極と接合し、一端を外部電極としてモジュール外部に露出させる外部電極用端子を含む、はんだ接合によって半導体チップ表面電極に接合される導体を言う。
本発明の実施の形態の半導体チップ1は、ベアチップ2の表面側にAl膜で形成されたAl電極3が積層されており、Al電極3の側面には、周辺耐圧構造4を形成するポリイミド膜が成膜される。
このような無電解Ni/Auめっき工程を経て2層電極膜が形成された半導体チップ1は、Al電極3の上に選択的に電極膜が形成されており、周辺耐圧構造4部に電極膜が形成されることがない。このため、半導体チッププロセスにおいて行われていたNi/Au層のエッチング工程を省くことができ、プロセスを簡単にすることができる。
上記の説明のように、ベアチップ2にAl電極3と周辺耐圧構造4が形成された状態で、無電解Ni/Auめっき工程が開始される。すなわち、表面電極にアルミワイヤがボンディングされる従来の半導体チップがウェハ状態あるいはダイシング後のチップ状態のときに、無電解Ni/Auめっき工程に入る。
続いて、第2工程の脱脂、第4工程の酸エッチングが実施され、Al電極3の表面の汚れと、Al酸化膜が除去される。
第6工程でジンケートを行う浴に半導体チップを浸漬することで、イオン化傾向によりAlが溶出し、代わりに選択的に亜鉛(Zn)がAl電極3表面に析出する(置換めっき)。その後、ZnとNiを置換する。
続く第10工程では、Niめっき層5表面の酸化を防止するために、上記説明のような置換めっきを用いてNiめっき層5の上にAuめっき層6を成膜する。
このように、従来の工程に無電解Ni/Auめっき工程を追加することで、周辺耐圧構造4を形成するポリイミド膜状には金属が堆積することなく、半導体チップ1の表面Al電極3上にはんだ接合に必要なNiめっき層5およびAuめっき層6の2層電極膜を成膜することが可能となる。
図3は、本発明の実施の形態の半導体チップが実装される半導体装置の構造を示す断面図である。
絶縁基板15は、セラミックなどの絶縁板の両面に金属層を形成したものであり、絶縁層15bを挟んで下側(半導体チップ非搭載面)に金属層15a、上側(半導体チップ搭載面)に金属層15c、15dを具備する構造をとる。半導体チップが接合される側の面の金属層(15c、15d)は、所定の回路パターンとして形成されている。
また、半導体チップ1の表面側は、はんだ層12cを介して熱伝導性と導電性を備えたリードフレーム20aに接合する。図の例では、リードフレーム20aは、放熱効率を上げるため、半導体チップ1の表面を覆うような形状を備えているが、半導体チップ1の表面に形成された均一な2層電極膜により、信頼性の高いはんだ接合配線が確保される。リードフレーム20aのもう一方は、絶縁基板15の表面に形成された第2回路パターン15dに接合し、これによって電気的な配線経路が構成される。また、リードフレーム20bは、外部電極用端子14との配線経路としても用いられる。
図4は、めっき層形成後のNiめっき層とはんだ接合後のNiめっき層の厚さの関係を示している。図は、横軸がはんだ接合前、すなわち、無電解めっき法によって形成されたNiめっき層の厚さ(図では初期Niめっき厚さ)を表しており、縦軸がはんだ接合後のNiめっき層の厚さを示している。
2 ベアチップ
3 アルミニウム(Al)電極
4 周辺耐圧構造
5 Niめっき層
6 Auめっき層
12a、12b、12c はんだ層
14 外部電極用端子
15 絶縁基板
15a 金属層
15b 絶縁層
15c 金属層(第1回路パターン)
15d 金属層(第2回路パターン)
16 放熱ベース
17 ケース
20a、20b リードフレーム
Claims (3)
- 裏面電極が絶縁基板上に構成された回路パターンに接合され、表面電極が接続導体に接合される半導体チップにおいて、
前記表面電極を形成するアルミニウム(Al)層の上に、ニッケル(Ni)層と前記ニッケル(Ni)層の上に積層される金(Au)層の2層をジンケート法による無電解めっき法で成膜して熱伝導率を均一にした電極膜と、
前記電極膜上に形成され、放熱経路を構成する接続導体と前記電極膜とを接合する鉛フリーはんだ層と、
を有することを特徴とする半導体チップ。 - 前記ニッケル(Ni)層は、前記無電解めっき法によって3マイクロメートル(μm)以上の厚さに成膜することを特徴とする請求項1記載の半導体チップ。
- 裏面電極が絶縁基板上に構成された回路パターンに接合され、表面電極が接続導体に接合される半導体チップを実装した半導体装置において、
前記半導体チップの前記表面電極を形成するアルミニウム(Al)層の上に、ニッケル(Ni)層と前記ニッケル(Ni)層の上に積層される金(Au)層の2層をジンケート法による無電解めっき法で成膜して熱伝導率を均一にした電極膜と、
前記電極膜上に形成される鉛フリーはんだ層と、
を有し、前記表面電極が前記電極膜及び前記はんだ層を介して放熱経路を構成する接続導体と接合されることを特徴とする半導体装置。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8492256B2 (en) | 2010-04-14 | 2013-07-23 | Fuji Electric Co., Ltd. | Method of manufacturing semiconductor apparatus |
US9666437B2 (en) | 2013-09-27 | 2017-05-30 | Fuji Electric Co., Ltd. | Method for manufacturing semiconductor device |
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JP5452130B2 (ja) | 2009-08-20 | 2014-03-26 | 株式会社デンソー | 半導体装置の製造方法 |
JP5463845B2 (ja) * | 2009-10-15 | 2014-04-09 | 三菱電機株式会社 | 電力半導体装置とその製造方法 |
JP6083109B2 (ja) * | 2012-01-18 | 2017-02-22 | 富士電機株式会社 | 半導体装置 |
WO2016163319A1 (ja) | 2015-04-06 | 2016-10-13 | 三菱電機株式会社 | 半導体素子及びその製造方法 |
CN109791880A (zh) * | 2016-10-13 | 2019-05-21 | 三菱电机株式会社 | 半导体装置的制造方法 |
JP6651271B2 (ja) * | 2017-02-15 | 2020-02-19 | 三菱電機株式会社 | 半導体素子及びその製造方法 |
JP7334435B2 (ja) | 2019-03-22 | 2023-08-29 | 富士電機株式会社 | 半導体装置および半導体装置の検査方法 |
WO2020208998A1 (ja) * | 2019-04-10 | 2020-10-15 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
CN112002770B (zh) * | 2020-08-20 | 2022-04-12 | 上海航天电子通讯设备研究所 | 一种电极预置焊料的光导开关及制作方法 |
JP2024104885A (ja) * | 2023-01-25 | 2024-08-06 | ミネベアパワーデバイス株式会社 | 電子部品及び電子部品の製造方法 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8492256B2 (en) | 2010-04-14 | 2013-07-23 | Fuji Electric Co., Ltd. | Method of manufacturing semiconductor apparatus |
US9666437B2 (en) | 2013-09-27 | 2017-05-30 | Fuji Electric Co., Ltd. | Method for manufacturing semiconductor device |
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