JP4219675B2 - Voltage limiter circuit and semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM).
[0002]
[Prior art]
As one means for achieving high integration of an EEPROM, there is known a method of storing multi-value data in one memory cell by providing a plurality of threshold voltages of one memory cell. The operation of the EEPROM is as follows.
[0003]
As shown in FIG. 6, the EEPROM memory cell includes a first MOS transistor having a high concentration region 38 as a source region and a high concentration region 37 as a drain region, a high concentration region 37 as a source region, and a high concentration region 36 as a source region. The drain region is a second MOS transistor. To erase data, the select gate 32 and the control gate 33 are set to an erase voltage, and the P-type substrate 39, the drain line 31 and the source line 35 are set to 0V. As a result, electrons are sent to the floating gate 34 from the drain line or the source line through the high concentration region 38, and the threshold voltage of the first transistor becomes 0 V or higher.
[0004]
Data is written by setting the select gate and drain lines to the write voltage, setting the control gate of the first transistor to 0 V, and setting the source line to a floating state, so that the electrons in the floating gate are formed below the select gate. To the drain line, and the threshold voltage of the first transistor becomes 0 V or less.
[0005]
In an EEPROM that stores binary data, a write voltage or 0 V is applied to the drain line of the memory cell in accordance with data 0 or 1 during a write operation.
[0006]
In an EEPROM that stores multilevel data in one memory cell, a write control voltage corresponding to the write data is applied to the drain line of the selected memory cell during a write operation. Thereby, it is possible to control the amount of electrons flowing out of the floating gate during the write operation, and to provide a plurality of threshold voltages of the selection transistor.
[0007]
In the EEPROM as described above, it is necessary to prepare a plurality of write potentials to be applied to the control gate. For this reason, it is necessary to prepare a circuit that generates a plurality of write voltages for each memory cell and holds the potential (see, for example, Patent Document 1).
[0008]
[Patent Document 1]
JP 09-251786 (5-6 tribute, FIG. 1)
[0009]
[Problems to be solved by the invention]
However, when such a circuit increases in the number of memory cells to be simultaneously written, it is necessary to prepare a circuit for holding a write voltage and a circuit for controlling the held charge for each memory cell. It will be enormous.
[0010]
An object of the present invention is to provide a nonvolatile semiconductor memory device that applies a plurality of write voltages to a memory cell without preparing a circuit for holding such a write voltage.
[0011]
[Means for Solving the Problems]
The voltage limiter circuit according to the present invention includes a first input terminal to which an output of the voltage generation circuit is input, a second input terminal to which a reference voltage is input, an output of the voltage generation circuit, and the reference voltage. And a first voltage limiter having a first output terminal for outputting a signal. And receiving a third input terminal to which the output of the voltage generation circuit is input, a fourth input terminal to which the reference voltage is applied, an output of the voltage generation circuit and an input of the reference voltage. A second voltage limiter having a second output terminal for outputting a signal. Further, the first voltage limiter includes a first MOS transistor having a drain and a gate connected to the first input terminal and a substrate potential connected to the second input terminal, a first MOS transistor, A second MOS transistor of the same conductivity type, having a drain and a source connected to the source of the first MOS transistor, and a substrate potential and a gate connected to the second input terminal. Further, a signal at a connection point between the first MOS transistor and the second MOS transistor is output to the first output terminal. Further, the second voltage limiter has a third conductivity type that is the same as that of the first MOS transistor in which a drain and a gate are connected to the third input terminal and a substrate potential is connected to the fourth input terminal. The fourth MOS transistor has the same conductivity type as the third MOS transistor, the drain and the source are connected to the source of the third MOS transistor, and the substrate potential and the gate are connected to the fourth input terminal. MOS transistors. Furthermore, a signal at a connection point between the third MOS transistor and the fourth MOS transistor is output to the second output terminal.
[0012]
Further, the first MOS transistor and the third MOS transistor have the same conductivity type.
[0013]
Further, the film pressure of the gate oxide film of the second MOS transistor is different from the film thickness of the gate oxide film of the fourth MOS transistor.
[0014]
Further, the film thickness of the gate oxide film of the first MOS transistor is different from the film thickness of the gate oxide film of the third MOS transistor.
[0015]
The voltage limiter circuit according to the present invention includes a first input terminal to which an output of the voltage generation circuit is input, a second input terminal to which a reference voltage is input, an output of the voltage generation circuit, and the reference And first and second output terminals for receiving signals and outputting signals. A first MOS transistor having a drain and a gate connected to the first input terminal and a substrate potential connected to the second input terminal; and the same conductivity type as the first MOS transistor; A second MOS transistor having a drain and a gate connected to a source of the first MOS transistor and a substrate potential connected to the second input terminal; and the same conductivity type as the first MOS transistor; A third MOS transistor having a drain and a source connected to a source of the second MOS transistor and a substrate potential and a gate connected to the second input terminal. Further, a signal at a connection point between the first MOS transistor and the second MOS transistor is output to the first output terminal, and the connection between the second MOS transistor and the third MOS transistor is provided. A point signal is output to the first output terminal.
[0016]
Here, the reference voltage of the voltage limiter circuit according to the present invention is 0V.
[0017]
Further, the semiconductor memory device according to the present invention is configured to receive the voltage limiter circuit, the memory array in which the memory cells are arranged in a grid, and the output of the voltage limiter circuit to receive the select gate and the control of the memory cell. A word driver that outputs a signal for controlling a gate; and a bit line control circuit that receives the output of the voltage limiter circuit and controls the drain line of the memory cell.
[0018]
In order to achieve the above-described object, in the nonvolatile semiconductor memory device according to the present invention, when multi-value data is written into the memory cell, a plurality of voltages to be supplied to the memory cell corresponding to each multi-value data are supplied. This is realized by the surface breakdown of a MOS transistor having a gate oxide film thickness of.
[0019]
In order to achieve the above object, in the nonvolatile semiconductor memory device according to the present invention, when multi-value data is written into the memory cell, a voltage to be supplied to the memory cell corresponding to each multi-value data is reduced. This is realized by the surface breakdown of one MOS transistor and the voltage drop of a plurality of saturation-connected MOS transistors.
[0020]
In order to achieve the above object, in the nonvolatile semiconductor memory device according to the present invention, when writing multi-value data to the memory cell, a plurality of voltages for supplying the memory cell corresponding to each multi-value data are supplied. A non-volatile semiconductor memory device characterized by being realized by a surface breakdown of a MOS transistor having a gate oxide film thickness and a drop voltage of a plurality of saturation-connected MOS transistors.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0022]
FIG. 1 is a block diagram of an EEPROM for storing multivalued data in one memory cell representing the first embodiment of the present invention.
[0023]
As shown in FIG. 1, a bit line control circuit 5 and a word driver 6 are provided for a memory array 7 in which memory cells are arranged in a grid pattern. The word driver controls the select gates and control gates of the memory cells in the memory array according to the output of the address input buffer 8. The bit line control circuit controls the drain lines of the memory cells in the memory array according to the outputs of the address input buffer and the data input / output buffer 4.
[0024]
When performing the write operation, the power source boosted by the high voltage generation circuit 1 is converted into a desired voltage by the voltage limiter 3 and the voltage limiter 2 set to a voltage lower than the voltage limiter 3, and then the first voltage limiter. Are supplied to the word driver and the bit line control circuit. The second voltage limiter is supplied to the bit line control circuit.
[0025]
FIG. 2 shows a part of the configuration of the memory array of FIG. When a write operation is performed at an address designated by the address input buffer, the output of the first voltage limiter and 0 V are applied to the pair of select gates and control gates by the word driver, respectively. The bit line control circuit selects the drain line according to the data to be written, and the output of the first voltage limiter, the output of the second voltage limiter, or 0 V is applied to the selected drain line.
[0026]
FIG. 3 shows the configuration of the voltage limiter. The output of the high voltage generation circuit is input to the terminal 10 and input to the drains and gates of the N-channel MOS transistors M1 and M3 connected in saturation in the first voltage limiter 3 and the second voltage limiter 2, respectively. The source of M1 is connected to the source and drain of the N-channel MOS transistor M2, and to the output terminal 12 of the first voltage limiter 3. The gate of the N-channel MOS transistor M2 is connected to the 0V terminal 13. On the other hand, the source of M3 is connected to the source and drain of an N-channel MOS transistor M4 whose gate oxide film thickness is smaller than that of M2, and to the output terminal 11 of the second voltage limiter 2. The gate of the N-channel MOS transistor M4 is connected to the 0V terminal 13. The substrate potentials of the transistors M1 to M4 are connected to the 0V terminal 13, respectively.
[0027]
Since the gate of M2 is fixed at 0 V, when the potential of the source and drain rises, surface breakdown occurs at a specific potential, and current flows from the source and drain to the substrate. Due to this phenomenon, the terminal 12 does not exceed the surface breakdown voltage of M2, and operates as a voltage limiter.
[0028]
M4 operates in the same manner as M2, but since the gate oxide film thickness is thin, surface breakdown occurs at a voltage lower than M2. Thereby, the terminal 11 can obtain a voltage lower than that of the terminal 12.
[0029]
FIG. 4 is a block diagram of an EEPROM voltage limiter representing a second embodiment of the present invention, which stores multilevel data in one memory cell.
[0030]
The voltage limiter in the first embodiment can be used when the write voltage is not sufficient.
[0031]
The output of the high voltage generation circuit is input to the terminal 10 and connected to the drain and gate of the N channel MOS transistor M5 connected in saturation of the voltage limiter 14. The source of M5 is connected to the drain and gate of the N channel MOS transistor M6 connected in saturation and the output 15 of the third voltage limiter. The substrate potentials of the transistors M5 to M7 are connected to the 0V terminal 13, respectively.
[0032]
The source of M6 is connected to the source and drain of M7 whose gate is fixed at 0V and the output 16 of the fourth voltage limiter. The output of the fourth voltage limiter is the surface breakdown voltage of M7. The output of the third voltage limiter can be higher than the output voltage of the fourth voltage limiter by the threshold voltage of M6. By supplying the output of the third voltage limiter to the word driver and the bit line control circuit, and supplying the output of the fourth voltage limiter to the bit line control circuit, a higher voltage than the first embodiment with respect to the write voltage. realizable.
[0033]
If necessary, three or more N channel MOS transistors connected in saturation may be connected in series.
[0034]
FIG. 5 is a block diagram of an EEPROM voltage limiter for storing multivalued data in one memory cell, representing a third embodiment of the present invention.
[0035]
This is input to the output terminal 10 of the high voltage generation circuit, and is connected to the drain and gate of the N-channel MOS transistor M8 connected in saturation in the fourth voltage limiter 17. The source of M8 is connected to the drain and gate of the N channel MOS transistor M9 connected in saturation and the output 19 of the fifth voltage limiter. The source of M9 is connected to the source and drain of M10 whose gate is fixed at 0V and the output 22 of the sixth voltage limiter. The output of the sixth voltage limiter is the surface breakdown voltage of M10. It is obvious that the output of the fifth voltage limiter is higher than the output voltage of the sixth voltage limiter by the threshold voltage of M9. The output terminal 10 of the high voltage generation circuit is also connected to the drain and gate of the N-channel MOS transistor M11 connected in saturation in the fifth voltage limiter 18. The source of M11 is connected to the drain and gate of the N channel MOS transistor M12 connected in saturation and the output 20 of the seventh voltage limiter.
[0036]
The source of M12 is connected to the source and drain of M13 whose gate oxide film thickness is thinner than that of M10 whose gate is fixed at 0V and the output 21 of the eighth voltage limiter. The substrate potentials of the transistors M8 to M13 are connected to the 0V terminal 13, respectively.
[0037]
The output of the eighth voltage limiter is the surface breakdown voltage of M13. It is obvious that the output of the seventh voltage limiter is higher than the output of the eighth voltage limiter by the threshold voltage of M12. The output voltage of the sixth voltage limiter is supplied to the word driver and the bit line control circuit, and the output of the fifth voltage limiter, the output of the seventh voltage limiter, and the output of the eighth voltage limiter are supplied to the bit line control circuit. By doing so, it is possible to obtain a voltage higher than that of the above-described embodiment with respect to the write voltage.
[0038]
If necessary, three or more N channel MOS transistors connected in saturation may be connected in series.
[0039]
【The invention's effect】
The present invention relates to a non-volatile semiconductor memory device that stores multi-value data, and can easily realize a plurality of write voltages required for writing multi-value data into a memory cell, and a circuit that holds the write voltage Therefore, a highly integrated nonvolatile semiconductor memory device can be provided.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing an example of an EEPROM that stores multi-value data.
FIG. 2 is a configuration diagram showing an example of an EEPROM memory array;
FIG. 3 is a configuration diagram showing a configuration of a voltage limiter according to the first embodiment of the present invention.
FIG. 4 is a configuration diagram showing a configuration of a voltage limiter according to a second embodiment of the present invention.
FIG. 5 is a configuration diagram showing a configuration of a voltage limiter according to a third embodiment of the present invention.
FIG. 6 is a cross-sectional view schematically showing an example of an EEPROM memory cell.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 High voltage generation circuit 2 Voltage limiter 3 Voltage limiter 4 Data input / output buffer 5 Bit line control circuit 6 Word driver 7 Memory array 8 Address input buffer 9 Source line 10 Output terminal 11 of the high voltage generation circuit Output of the second voltage limiter 12 Output of the first voltage limiter 130 0V terminal 14 Third voltage limiter 15 Output of the third voltage limiter 16 Output of the fourth voltage limiter 17 Fourth voltage limiter 18 Fifth voltage limiter 19 Output of voltage limiter 20 Output of seventh voltage limiter 21 Output of eighth voltage limiter 22 Output of sixth voltage limiter 31 Drain line 32 Select gate 33 Control gate 34 Floating gate 35 Source line 36 High concentration region 37 High concentration Region 38 High concentration region 39 P-type substrate

Claims (7)

A first input terminal to which an output of the voltage generation circuit is input, a second input terminal to which a reference voltage is input, an output of the voltage generation circuit and an input of the reference voltage, and outputs a signal A first voltage limiter having a first output terminal;
A third input terminal to which an output of the voltage generation circuit is input; a fourth input terminal to which the reference voltage is applied; and an output of the voltage generation circuit and an input of the reference voltage to receive a signal. A second voltage limiter having a second output terminal for outputting,
The first voltage limiter is:
A first MOS transistor having a drain and a gate connected to the first input terminal and a substrate potential connected to the second input terminal;
A second MOS transistor having the same conductivity type as the first MOS transistor, a drain and a source connected to the source of the first MOS transistor, and a substrate potential and a gate connected to the second input terminal; Have
A signal at a connection point between the first MOS transistor and the second MOS transistor is output to the first output terminal;
The second voltage limiter is:
A third MOS transistor having the same conductivity type as the first MOS transistor, the drain and gate of which are connected to the third input terminal and the substrate potential is connected to the fourth input terminal;
A fourth MOS transistor having the same conductivity type as the third MOS transistor, a drain and a source connected to the source of the third MOS transistor, and a substrate potential and a gate connected to the fourth input terminal; Have
A voltage limiter circuit, wherein a signal at a connection point between the third MOS transistor and the fourth MOS transistor is output to the second output terminal. A first input terminal to which an output of the voltage generation circuit is input;
A second input terminal to which a reference voltage is input;
First and second output terminals for receiving an output of the voltage generation circuit and an input of the reference voltage and outputting a signal;
A first MOS transistor having a drain and a gate connected to the first input terminal and a substrate potential connected to the second input terminal;
A second MOS transistor having the same conductivity type as the first MOS transistor, a drain and a gate connected to the source of the first MOS transistor, and a substrate potential connected to the second input terminal;
A third MOS transistor having the same conductivity type as the first MOS transistor, a drain and a source connected to the source of the second MOS transistor, and a substrate potential and a gate connected to the second input terminal; Have
A signal at a connection point between the first MOS transistor and the second MOS transistor is output to the first output terminal;
A voltage limiter circuit, wherein a signal at a connection point between the second MOS transistor and the third MOS transistor is output to the first output terminal.   3. The voltage limiter circuit according to claim 1, wherein the reference voltage is 0V.   2. The voltage limiter circuit according to claim 1, wherein conductivity types of the first MOS transistor and the third MOS transistor are the same.   5. The voltage limiter circuit according to claim 4, wherein a film pressure of the gate oxide film of the second MOS transistor is different from a film thickness of the gate oxide film of the fourth MOS transistor.   5. The voltage limiter circuit according to claim 4, wherein a film pressure of the gate oxide film of the first MOS transistor is different from a film thickness of the gate oxide film of the third MOS transistor. The voltage limiter circuit according to claim 1 or 2,
A memory array in which memory cells are arranged in a grid, and
A word driver that receives the output of the voltage limiter circuit and outputs a signal for controlling a select gate and a control gate of the memory cell;
A semiconductor memory device, comprising: a bit line control circuit that receives the output of the voltage limiter circuit and controls the drain line of the memory cell.

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