JP4282777B2 - Semiconductor device substrate and semiconductor device manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a BGA (Ball Grid Array) type semiconductor device substrate on which a semiconductor chip is mounted, a semiconductor device, and a method for manufacturing the same. The present invention relates to a semiconductor device and a manufacturing method thereof.
[0002]
[Prior art]
Recently, portable electronic devices such as notebook computers, handy video devices, and mobile phones have been widely sold. For this reason, there is an increasing demand for downsizing and higher functionality of a semiconductor device substrate when the semiconductor device is mounted in these electronic devices.
[0003]
Such a substrate for a semiconductor device includes a BGA type substrate on which a semiconductor chip such as an LSI can be mounted. Specifically, for example, a substrate disclosed in Japanese Patent Application Laid-Open No. 8-37345 is known. ing. Note that a semiconductor device that can be mounted on a mother board or the like of an external element is manufactured by mounting a semiconductor chip on a semiconductor device substrate and sealing with resin.
[0004]
FIG. 8 is a cross-sectional view showing a configuration of a semiconductor device using the semiconductor device substrate. In this semiconductor device, a copper-clad laminate for a printed wiring board is used as a base substrate 31, and a plurality of holes 32 are formed in a substantially matrix shape by mechanical processing using a drill in the base substrate 31.
[0005]
Next, of the copper layers on both surfaces of the base substrate 31, patterning is performed by photolithography so that the upper copper layer becomes the wiring pattern 33 and the other copper layer becomes the electrode terminal (hereinafter referred to as land electrode) 34. Is done.
[0006]
When a pattern that cannot be formed by a single layer is provided as the wiring pattern 33 because of high density and complexity, it is necessary to increase the wiring density by arranging the wiring pattern 33 in multiple layers. In the multilayer of the wiring pattern 33, after the insulating layer 35 is formed on the surface including the lower wiring pattern 33, a conductive layer (copper layer) is similarly formed, and this conductive layer is patterned to form a new wiring pattern 33. It is said.
[0007]
At this time, in order to establish conduction between the upper and lower wiring patterns 33, a through hole 36 is formed in the insulating layer 35, and both the wiring patterns 33 are conducted through the conductive layer formed in the through hole 36. At this time, the insulating layer 35 is preferably made of a material that can be patterned by a photolithography method so that the through hole 36 can be formed in a desired portion, and for example, a photosensitive resin is appropriate.
[0008]
In addition, after the formation of the wiring pattern 33 of each layer, Au plating is applied to the surface of the wiring pattern 33 of the uppermost layer, so that the connection (wire bonding) suitability with the semiconductor chip 37 is improved.
[0009]
[Problems to be solved by the invention]
However, in the semiconductor device substrate as described above, a drilling process is performed on the base substrate 31 to make the wiring pattern 33 and the land electrode 34 conductive. However, in general, drilling is not suitable for fine drilling, so this type of substrate for a semiconductor device has no problem when applied to a product with a normal integration degree. Therefore, it is not suitable for applications that require high integration.
[0010]
The base substrate 31 functions as a support substrate in the step of forming the insulating layer 35 to which a photosensitive resin or the like is applied. That is, since the base substrate 31 is required to have a certain degree of rigidity (thickness), as described above, there is no problem as a normal product, but it is not suitable for applications that require further thinning. It has become.
[0011]
Further, since the copper layer on the lower surface side of the base substrate 31 is patterned and the land electrode 34 is formed, the lower surface of the base substrate 31 is uneven.
Due to the unevenness, fixing by vacuum suction or the like becomes somewhat difficult. Therefore, steps such as formation of the insulating layer 35, patterning of the wiring pattern 33, formation of the through hole 36, and gold plating of the surface of the uppermost wiring pattern 33 are performed. There is a problem that automating is somewhat difficult. Further, since the land electrode 34 protrudes by the thickness of the copper layer, there is a possibility that defects such as scratches may occur during the manufacturing process and the mounting process of the semiconductor chip 37.
[0012]
The present invention has been made in consideration of the above-mentioned circumstances, is high-density and thin, can be fixed securely during the manufacturing process, etc., and is less likely to cause defects such as damage to land electrodes, and has high reliability. It is an object of the present invention to provide a semiconductor device substrate, a semiconductor device, and a method of manufacturing the same that can be realized.
[0017]
[Means for Solving the Problems]
  Claim 1The invention corresponding to the first step of forming a first insulating layer formed by curing a resin on a sheet-like copper alloy, and the first insulating layerpluralA second step of forming a land electrode formation hole;EachOn the upper surface of the sheet-like copper alloy exposed from the land electrode formation hole, an electrolytic gold plating layer having a thickness of 0.1 μm to 5 μm is formed by electrolytic gold plating using the sheet-like copper alloy as an electrode.pluralThe third step of forming the etching stopper layer and the electrolytic nickel plating processEachOn the etching stopper layerpluralBy the fourth step of forming the electrolytic nickel plating layer and the electrolytic copper plating treatment,EachOn the electrolytic nickel plating layerpluralBy forming the electrolytic copper plating layer, the frontEachEtching stopper layer, frontEachElectrolytic nickel plating layer and frontEachConsists of electrolytic copper plating layerpluralA fifth step of forming land electrodes, and on and before the first insulating layer;EachA sixth step of forming a second insulating layer formed by curing a resin on the land electrode; andEachA seventh step of forming a via hole forming hole reaching the land electrode, an eighth step of forming a copper layer filling the via hole by electrolytic copper plating, and the second insulating layer on the copper layer and the second insulating layer. A ninth step of smoothing by buffing the layer, and after the smoothing, on the copper layer and the second insulating layer by copper platingEachLine area andEach connectionA tenth step of integrally forming a connection electrode; an eleventh step of attaching a protective dry film on the second insulating layer, on the wiring layers and on the connection electrodes; and A method of manufacturing a substrate for a semiconductor device, comprising: a twelfth step of removing the copper alloy by etching after a film is attached; and a thirteenth step of peeling the dry film. .
[0019]
  And claims2The invention corresponding to the first step of forming a first insulating layer formed by curing a resin on a sheet-like copper alloy, and the first insulating layerpluralA second step of forming a land electrode formation hole;EachOn the upper surface of the sheet-like copper alloy exposed from the land electrode formation hole, an electrolytic gold plating layer having a thickness of 0.1 μm to 5 μm is formed by electrolytic gold plating using the sheet-like copper alloy as an electrode.pluralThe third step of forming the etching stopper layer and the electrolytic nickel plating processEachOn the etching stopper layerpluralBy the fourth step of forming the electrolytic nickel plating layer and the electrolytic copper plating treatment,EachOn the electrolytic nickel plating layerpluralBy forming the electrolytic copper plating layer, the frontEachEtching stopper layer, frontEachElectrolytic nickel plating layer and frontEachConsists of electrolytic copper plating layerpluralA fifth step of forming land electrodes, and on and before the first insulating layer;EachA sixth step of forming a second insulating layer formed by curing a resin on the land electrode; andEachA seventh step of forming a via hole forming hole reaching the land electrode, an eighth step of forming a copper layer filling the via hole by electrolytic copper plating, and the second insulating layer on the copper layer and the second insulating layer. A ninth step of smoothing by buffing the layer, and after the smoothing, on the copper layer and the second insulating layer by copper platingEachLine area andEach connectionA tenth step of manufacturing a substrate for a semiconductor device by integrally forming a connection electrode;Each connectionAn eleventh step of mounting a semiconductor chip on the upper surface of the substrate for a semiconductor device by connecting to a connection electrode, and a twelfth step of resin-sealing at least the semiconductor chip and its connection portion to each of the connection electrodes And a thirteenth step of removing the copper alloy by etching after the resin sealing.
[0020]
  Claims3In the invention corresponding to the first step of forming a resist layer on a sheet-like copper alloy, the resist layerpluralA second step of forming a land electrode formation hole;EachOn the upper surface of the sheet-like copper alloy exposed from the land electrode formation hole, a solder plating layer having a thickness of 3 μm to 5 μm is formed by electrolytic solder plating using the sheet-like copper alloy as an electrode.pluralThe third step of forming the etching stopper layer and the electrolytic copper plating processEachOn the etching stopper layerpluralBy forming the electrolytic copper plating layer, the frontEachEtching stopper layer and frontEachConsists of electrolytic copper plating layerpluralA fourth step of forming a land electrode; a fifth step of stripping the resist layer after the formation of the land electrode; and on and before the sheet-like copper alloy.EachA sixth step of forming an insulating layer formed by curing a resin on the land electrode; andEachA seventh step of forming a via hole forming hole reaching the land electrode, an eighth step of forming a copper layer filling the via hole by electrolytic copper plating, and the copper layer and the insulating layer. A ninth step of smoothing by buffing, and after the smoothing, on the copper layer and the insulating layer by copper platingEachLine area andEach connectionA tenth step of integrally forming a connection electrode; an eleventh step of attaching a protective dry film on the insulating layer, the wiring layers, and the connection electrodes; and attaching the dry film. A method of manufacturing a substrate for a semiconductor device, comprising: a twelfth step of removing the copper alloy by etching and a thirteenth step of peeling off the dry film.
[0022]
  Claims4In the invention corresponding to the first step of forming a resist layer on a sheet-like copper alloy, the resist layerpluralA second step of forming a land electrode formation hole;EachOn the upper surface of the sheet-like copper alloy exposed from the land electrode formation hole, a solder plating layer having a thickness of 3 μm to 5 μm is formed by electrolytic solder plating using the sheet-like copper alloy as an electrode.pluralThe third step of forming the etching stopper layer and the electrolytic copper plating processEachOn the etching stopper layerpluralBy forming the electrolytic copper plating layer, the frontEachEtching stopper layer and frontEachConsists of electrolytic copper plating layerpluralA fourth step of forming a land electrode; a fifth step of stripping the resist layer after the formation of the land electrode; and on and before the sheet-like copper alloy.EachA sixth step of forming an insulating layer formed by curing a resin on the land electrode; andEachA seventh step of forming a via hole forming hole reaching the land electrode, an eighth step of forming a copper layer filling the via hole by electrolytic copper plating, and the copper layer and the insulating layer. A ninth step of smoothing by buffing, and after the smoothing, on the copper layer and the insulating layer by copper platingEachLine area andEach connectionA tenth step of manufacturing a substrate for a semiconductor device by integrally forming a connection electrode;EachAn eleventh step of mounting a semiconductor chip on the upper surface of the semiconductor device substrate by connecting to a connection electrode, and a twelfth step of resin-sealing at least the semiconductor chip and a connection portion to each of the connection electrodes. And a thirteenth step of removing the copper alloy by etching after the resin sealing.
(Terminology) Next, supplementary explanation will be given on the materials applied to the present invention as described above.
[0023]
The insulating layer is formed by curing a liquid resin applied by screen printing or curtain coating. As the liquid resin, an epoxy resin, a polyimide resin, an acrylic resin, or the like is applicable. In addition, as the liquid resin, it is preferable to use a photosensitive resin from the viewpoint of easily processing via holes and the like with high accuracy. However, even if a non-photosensitive resin is used, it can be formed into a desired shape by fine processing using an excimer laser or the like.
[0024]
Further, the substrate for a semiconductor device may have either a structure capable of mounting one semiconductor chip or a structure capable of mounting two or more semiconductor chips.
Further, the substrate for a semiconductor device may have a multilayer structure in which the printed circuit portion has the number of layers required for wiring, for example, a power supply layer and a ground layer are provided.
[0025]
The land electrode is formed of the above-described materials such as Au, Pt, Ni, Pd, solder, and Cu paste at least on the surface, and these materials may be used alone, as an alloy, or as a multilayer structure. . That is, for example, a Ni layer or a Ni—Au alloy layer is used as the surface layer (also referred to as an etching stopper layer). Moreover, you may provide Ni layer or a Ni-Pd alloy layer as those foundation | substrates, for example.
[0026]
The etching stopper layer serves as a stopper when the sheet-like metal material is removed by etching. For example, when the metal material is copper and ferric chloride is used, Au, Pd, or the like is used. In the case of using a persulfate etching solution such as ammonium persulfate or potassium persulfate, or an etching solution comprising an alkaline aqueous solution mainly composed of a copper ammonium complex ion, solder or the like is used.
[0027]
The material of the etching stopper layer is preferably one that has a strong adhesion to the wiring material and is not easily corroded by the etching solution, and can be easily formed on a metal material. Specifically, it is appropriately selected depending on the relationship between the metal material and the etching solution.
[0028]
The material of the etching stopper layer is preferably a material having high wettability relative to a material (for example, solder) used for connection to a printed wiring board or the like of an external element.
The method for forming the etching stopper layer includes plating, vapor deposition, sputtering, and the like, which can be selected as appropriate.
[0029]
Gold is preferable because it has a high stopper effect with respect to various etching solutions and can directly protect the surface of the terminal.
Moreover, the solder can be easily formed by plating, is inexpensive and is preferable. In this case, if the metal material is a copper alloy, the copper alloy is etched and the solder layer becomes a stopper layer when etching is performed using an alkaline etching solution mainly composed of copper ammonium complex ions.
[0030]
As the sheet-like metal material, for example, copper, a copper alloy, or an iron-Ni alloy represented by 42 alloy (42 wt% Ni, balance Fe) can be used. This is preferable in that it has excellent thermal conductivity and low electrical resistance.
[0031]
The thickness of the sheet-like metal material is required to be thick enough to function as a support substrate and not so thick as to be easily removed by etching, for example, within a range of about 0.15 mm to 0.35 mm. It is preferable that it exists in.
[0032]
In the via formation step, filling the via hole by plating is preferable from the viewpoint of preventing the formation of bubbles in the via hole. Specifically, it is possible to perform electroplating in which a metal material is energized, and the via hole can be filled with a simple process.
[0033]
In the process of forming a conductor circuit composed of a wiring region and a connection electrode on a via, an electrolytic Cu plating such as a conventional subtractive method, a semi-additive method or a full additive method can be applied, but the via is already formed. Therefore, a conductor circuit can be easily formed.
[0034]
As the subtractive method, for example, electroless plating or sputtering can be used. Specifically, for example, after forming a thin copper layer having a thickness of 0.2 μm, electrolytic copper plating having a thickness of 10 μm is applied to the entire surface. A resist (eg, PMER; trade name: manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied and dried, and then the steps of exposure, development, etching, and resist stripping are performed. Further, as the resist, a negative photosensitive resist is desirable. For example, a resist called a trade name PMER can be used. As a coating method, dipping, screen printing, spin coating, or the like can be used as appropriate.
[0035]
As the semi-additive method, for example, electroless plating or sputtering can be used. Specifically, for example, after forming a thin copper layer having a thickness of 0.2 μm, a resist (eg, PMER) is applied and dried. After that, exposure and development are performed, and electrolytic copper plating with a thickness of 10 μm is applied to the pattern region that becomes the wiring region and the connection electrode. Further, after the resist is removed, the thin copper layer is removed by etching.
[0036]
  As a full additive method, for example, after applying a catalyst and forming a resist, a wiring region and a connection electrode are formed by electroless plating.
  As a method for connecting the semiconductor chip to the semiconductor device substrate, there are wire bonding, bumps, and the like. Further, at least the semiconductor chip and the connection portion between the semiconductor chip and the semiconductor device substrate are sealed with resin, and then the metal material is etched.
(Function)
  Therefore, in the invention corresponding to claim 1, the insulating layer is formed by taking the above-described means.CuredSince it is made of resin, the drilling process with a drill can be omitted, so a high-density pattern and a thin shape can be realized, and the surface of each land electrode is positioned almost flush with the surface of the insulating layer. It can be reliably fixed during the process, and it is difficult to cause defects such as damage to the land electrode, and high reliability can be realized.
[0037]
Also,eachSince the land electrode is coated with a sheet-like metal material, the electrode surface is protected until the completion of the semiconductor device on which the semiconductor chip is mounted, and it is difficult to cause defects such as scratches, thereby further improving the reliability. be able to.
[0040]
  Also, Claims1In the invention corresponding to the above, an insulating layer is selectively formed on the sheet-like copper alloy, and then an etching stopper layer to be the surface of each land electrode is formed. Since the insulating layer is formed again, each via, each wiring region, and each connection electrode are formed, the insulating layer is formed again, each via, each wiring region, each connection electrode is formed, and the copper alloy is removed by etching. ,SemiconductorThe body device substrate can be easily and reliably manufactured, and the stability of the manufacturing process can be improved.
[0042]
  And claims2In the invention corresponding to the above, an insulating layer is selectively formed on the sheet-like copper alloy, and then an etching stopper layer to be the surface of each land electrode is formed. Form the insulating layer again, form each via, each wiring region and each connection electrode, connect the semiconductor chip to each connection electrode, resin-seal the semiconductor chip, etc., and remove the copper alloy by etching,HalfThe conductor device can be easily and reliably manufactured, and the stability of the manufacturing process can be improved.
[0043]
  Claims3In the invention corresponding to the above, a resist layer and each land electrode forming hole are formed on a sheet-like copper alloy, an etching stopper layer and each land electrode are formed, the resist layer is peeled off, and then the insulating layer is sequentially insulated. Forming a layer, forming each via, each wiring region and each connection electrode, and then sequentially forming an insulating layer, forming each via, each wiring region and each connection electrode, and removing the copper alloy by etching SoHalfA substrate for a conductor device can be manufactured easily and reliably, the stability of the manufacturing process can be improved, and a higher resolution resist can be used to selectively form an etching stopper layer. A fine pattern can be formed with high density.
[0045]
  Claims4In the invention corresponding to the above, a resist layer and each land electrode forming hole are formed on a sheet-like copper alloy, an etching stopper layer and each land electrode are formed, the resist layer is peeled off, and then the insulating layer is sequentially insulated. Forming a layer, forming each via, each wiring region and each connection electrode, connecting a semiconductor chip to each connection electrode, sealing the semiconductor chip, etc., and removing the copper alloy by etching,HalfThe conductor device can be manufactured easily and reliably, the stability of the manufacturing process can be improved, and when the etching stopper layer is selectively formed, by using a high-resolution resist, the density can be further increased. A fine pattern can be formed.
[0046]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a cross-sectional view showing a configuration of a substrate for a semiconductor device according to a first embodiment of the present invention. The substrate for a semiconductor device includes an insulating layer 1 formed by curing a liquid resin, a plurality of connection electrodes 2 formed on one surface of the insulating layer 1 and arranged to be connectable to a semiconductor chip, and the insulating layer 1. A plurality of wiring regions 3 formed on one surface and individually connected to each connection electrode 2, the surface is positioned substantially in the same plane as the surface of the insulating layer 1, and the side surface is covered with the insulating layer 1 A plurality of land electrodes 4 formed in the other surface of the insulating layer 1 and arranged to be connectable to external elements, and a plurality of vias 5 individually connecting the land electrodes 4 and the wiring regions 2. I have.
[0047]
Further, the surface formed of each wiring region 3 and the insulating layer 1 is covered with a protective layer 6 except on the connection electrode 2.
Here, the insulating layer 1 is formed by applying and drying a liquid insulating resin. As the insulating resin, an epoxy resin-based or acrylic resin-based insulating resin or the like can be applied.
[0048]
Each connection electrode 2 has a plating layer 2a formed on the surface for good connection to a semiconductor chip. In the plating layer 2a, the base on the conductive layer (copper layer) is a Ni layer, and an Au layer is formed on the Ni layer.
[0049]
Each land electrode 4 has a plating layer 4a as an etching stopper layer formed on the surface thereof. Here, the plating layer 4a has the same layer structure as the plating layer 2a described above. In addition, each plating layer 2a, 4a is good also as another layer structure.
[0050]
Next, a method for manufacturing such a semiconductor device substrate will be described.
First, the sheet-like 0.2 mm thick copper alloy 10 is cleaned. After drying, a dry film (not shown) as an acid-resistant tape is attached to the entire back surface of the copper alloy 10. Thereafter, a photosensitive insulating resin (DPR-105; trade name: manufactured by Asahi Chemical Research Co., Ltd.) to be the insulating layer 1 is printed on the surface of the copper alloy 10 by screen printing.
[0051]
The photosensitive insulating resin is exposed and developed in a pattern corresponding to the land electrode 4 formation position, whereby the insulating layer at the land electrode 4 formation position is removed with a hole diameter of 0.6 mm. As shown in (a), an insulating layer 1a having a thickness of 20 μm is selectively formed.
[0052]
Subsequently, an electrolytic gold plating process is performed using the copper alloy 10 as an electrode, and an Au layer having a thickness of 0.5 μm is formed on the copper alloy 10 surrounded by the insulating layer 1a. Since the Au layer becomes a stopper layer when the copper alloy 10 is removed by etching in the final step, the thickness is about 0.1 μm to 5 μm so as not to have pinholes and to have sufficient etching resistance. It is preferable that the thickness is about 0.3 μm to 1 μm.
[0053]
Next, an electrolytic nickel plating process for imparting good adhesion to the subsequent copper plating is performed to form a nickel layer having a thickness of 2 μm on the Au layer, and as shown in FIG. Then, a plating layer 4a made of an Au layer and a Ni layer is formed.
[0054]
Further, such a copper alloy 10 is immersed in a copper sulfate plating solution and subjected to an electrolytic copper plating process, whereby a 10 μm thick copper layer 11 is formed as shown in FIG.
[0055]
Again, the photosensitive insulating resin used as the insulating layer 1 is printed by screen printing. This insulating resin is exposed and developed corresponding to a pattern that partially exposes the plating layer 4a on the surface of each land electrode, so that the insulating layer in the central portion at the position where the land electrode 4 is formed has a hole diameter of 0.08 mm. As a result, the via hole 12 is formed, and as shown in FIG. 3A, the insulating layer 1 having a thickness of 40 μm is formed together with the insulating layer 1a having a thickness of 20 μm.
[0056]
Next, an electrolytic copper plating process is performed using the copper alloy 10 as an electrode, and a copper plating layer having a thickness of 20 μm is formed in the via hole 12. Thus, the via hole 12 is filled with the copper layer to form the via 5. The Thereafter, the upper surface of the via hole 12 and the surface of the insulating layer 1 are buffed and smoothed.
[0057]
Subsequently, electroless copper plating is applied to the entire surface with a thickness of 0.5 μm, and electrolytic plating is applied with a thickness of 10 μm to form a 10.5 μm thick copper layer on the entire surface.
Further, a photosensitive liquid resist (PMER; trade name: manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied by immersion to a thickness of 10 μm on both sides. The liquid resist is exposed, developed and patterned in correspondence with the pattern for forming the connection electrode 2 and the wiring region 3.
[0058]
Thereafter, the copper layer is selectively etched and removed, and the resist on the back surface is peeled off together with the dry film, so that the connection electrode 2 and the wiring region 3 are formed as shown in FIG. It becomes.
[0059]
Resin of the same material as the insulating resin is screen-printed on the wiring region 3 as the protective layer 6, exposed and developed corresponding to a pattern exposing the connection electrode 2 to the semiconductor chip, and the resin on the connection electrode 2. Is removed.
[0060]
On the connection electrode 2, nickel plating is applied to a thickness of 2 μm and gold plating is applied to a thickness of 0.3 μm by electroless plating. That is, as shown in FIG. 3C, a plating layer 2 a composed of a Ni layer and an Au layer is formed on the connection electrode 2. The structure shown in FIG. 3C is a semiconductor device substrate that can be shipped.
[0061]
Subsequently, a protective dry film is attached to the circuit forming surface composed of the protective layer 6, the wiring region 3, and the connection electrode 2 (not shown), and then the copper alloy 10 is removed by etching. At this time, the Au layer of the plating layer 4a becomes an etching stopper layer, and only the copper alloy 10 is removed. Then, the dry film is peeled off, and the semiconductor device substrate is completed as shown in FIG.
[0062]
As described above, according to the first embodiment, since the insulating layer 1 is formed from a liquid resin, a drilling step by a drill can be omitted, so that a high-density pattern and a thin shape can be realized. Since the surface of the insulating layer 1 is positioned substantially on the same plane as the surface of the insulating layer 1, it can be securely fixed during the manufacturing process and the like, and the land electrode 4 is not easily damaged, and high reliability is achieved. Can be made.
[0063]
Further, since build-up is performed on the sheet-like copper alloy 10 and then the copper alloy 10 is removed, even when the thickness is reduced, it can be easily manufactured with high reliability.
In the case of shipping with the structure shown in FIG. 3C, each land electrode 4 is covered with a sheet-like copper alloy 10, so that the surface of the land electrode 4 remains until just before completion of the semiconductor device on which the semiconductor chip is mounted. It is protected and hardly causes defects such as scratches, so that the reliability can be further improved.
[0064]
Furthermore, since the surface of each land electrode 4 is formed of a material that functions as an etching stopper layer, the above-described effects can be easily and reliably achieved.
In addition, as a manufacturing process, the insulating layer 1a is selectively formed on the sheet-like copper alloy 10, and then the plating layer 4a to be the surface of each land electrode 4 is formed. 4, the insulating layer 1 is formed again, each via 5, each wiring region 3 and each connection electrode 2 are formed, and the copper alloy 10 is removed by etching. Therefore, a semiconductor device substrate having the above-described effects can be obtained. It can be manufactured easily and reliably, and the stability of the manufacturing process can be improved.
(Second Embodiment)
Next, a semiconductor device substrate according to a second embodiment of the present invention will be described.
[0065]
FIG. 4 is a cross-sectional view showing the configuration of the substrate for a semiconductor device. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. Only different parts will be described here.
[0066]
That is, the substrate for a semiconductor device according to the present embodiment is a modification of the manufacturing method of the first embodiment, and forms a plating layer 4a (a solder layer 4b in FIG. 4) on each land electrode 4. After that, the manufacturing method for forming the insulating layer 1 is the same as the structure shown in FIG.
[0067]
The difference in structure is that a solder layer 4b is formed instead of the Au layer and Ni layer of the plating layer 4a.
Next, a method for manufacturing such a semiconductor device substrate will be described.
[0068]
First, the sheet-like 0.2 mm thick copper alloy 10 is cleaned. After drying, a dry film (not shown) is attached to the back surface of the copper alloy 10. Thereafter, a photosensitive liquid resist (PMER; trade name: manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied to the surface of the copper alloy 10 by immersion so as to have a thickness of 25 μm. The coating thickness of the liquid resist needs to be thicker than the land electrode 4 to be formed later, and is preferably about 25 to 50 μm, for example.
[0069]
This liquid resist is exposed and developed in accordance with the pattern of the land electrode 4 formation position, whereby the land electrode 4 formation position portion is removed with a hole diameter of 0.6 mm, and FIG. ), A 20 μm thick resist layer 13 is selectively formed.
[0070]
Subsequently, electrolytic solder plating is performed using the copper alloy 10 as an electrode, and a solder layer 4b having a thickness of 3 μm is formed on the copper alloy 10 surrounded by the resist layer 13 as shown in FIG. Since the solder layer 4b serves as a stopper layer when the copper alloy 10 is removed by etching in the final process, the solder layer 4b is formed to have a thickness of about 3 μm to 5 μm so as not to have pinholes and to have sufficient etching resistance. It is preferable.
[0071]
The land electrode 4 may be reinforced by performing electrolytic copper plating on the solder layer 4b to form a copper layer having a thickness of about 15 μm.
Next, as shown in FIG. 5C, the resist 13 is peeled off.
[0072]
Subsequently, in the same manner as described above, a photosensitive insulating resin (DPR-105; trade name: manufactured by Asahi Chemical Research Co., Ltd.) to be the insulating layer 1 is printed by screen printing. This insulating resin is exposed and developed corresponding to a pattern that partially exposes each land electrode 4, whereby the insulating layer in the central portion at the position where the land electrode 4 is formed is removed with a hole diameter of 0.08 mm. A via hole 12 is formed, and an insulating layer 1 having a thickness of 40 μm is formed as shown in FIG.
[0073]
Electrolytic copper plating is performed using the copper alloy 10 as an electrode, and a copper plating layer having a thickness of 20 μm is formed in the via hole 12. Thus, the via hole is filled with the copper layer to form the via 5. Thereafter, the upper surface of the via hole 12 and the surface of the insulating layer 1 are buffed and smoothed.
[0074]
Subsequently, electroless plating is applied to the entire surface with a thickness of 0.5 μm, and electrolytic plating is applied with a thickness of 10 μm to form a copper layer with a thickness of 10.5 μm on the entire surface.
Furthermore, a photosensitive liquid resist (PMER) is applied to both surfaces with a thickness of 10 μm by dipping. This liquid resist is exposed, developed and patterned corresponding to a pattern for forming the connection electrode 2 and the wiring region 3.
[0075]
Thereafter, the copper layer is selectively removed by etching using ferric chloride, and the resist on the back surface is peeled off together with the dry film. As shown in FIG. The wiring region 3 is formed.
[0076]
Resin of the same material as the insulating resin is screen-printed on the wiring region 3 as the protective layer 6, exposed and developed corresponding to a pattern exposing the connection electrode 2 to the semiconductor chip, and the resin on the connection electrode 2. Is removed.
[0077]
On the connection electrode 2, nickel plating is applied with a thickness of 2 μm and gold plating with a thickness of 0.3 μm by electroless plating. As shown in FIG. Layer 2a is formed. The structure shown in FIG. 5F is a semiconductor device substrate that can be shipped.
[0078]
Subsequently, a protective dry film is affixed to the circuit forming surface composed of the protective layer 6, the wiring region 3, and the connection electrode 2 (not shown), and then the copper alloy 10 is removed by etching. At this time, the solder layer 4b becomes an etching stopper layer, and only the copper alloy is removed. Then, the dry film is peeled off, and the semiconductor device substrate is completed as shown in FIG.
[0079]
As described above, according to the second embodiment, in addition to the effects of the first embodiment, as a manufacturing process, the solder layer 4 b and each land electrode 4 are selectively formed on the sheet-like copper alloy 10. After the formation, the insulating layer 1 is sequentially formed, the vias 5, the wiring regions 3 and the connection electrodes 2 are formed, and the copper alloy 10 is removed by etching, so that the effect of the first embodiment can be obtained. The semiconductor device substrate can be manufactured easily and reliably, the stability of the manufacturing process can be improved, and when the solder layer 4b is selectively formed, the use of a high resolution resist further increases A high-density and fine pattern can be formed.
(Third embodiment)
Next, a semiconductor device according to a third embodiment of the present invention will be described.
[0080]
FIG. 6 is a cross-sectional view showing the configuration of this semiconductor device. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. Only different parts will be described here. That is, the semiconductor device according to the present embodiment is a modification of the first or second embodiment, and is electrically connected to each connection electrode 2 as shown in FIG. 6 with respect to the device shown in FIG. The semiconductor chip 21 is provided, and at least the semiconductor chip 21 and its connection portion to each connection electrode 2 are sealed with an insulating resin 22.
[0081]
Note that FIG. 3C in the first embodiment and FIG. 5F in the second embodiment have the same contents, so only the process in FIG. 3C is taken as an example here. This embodiment will be described so as to continue the process thereafter.
[0082]
Next, a method for manufacturing such a semiconductor device will be described.
After the step shown in FIG. 3C, the semiconductor chip 21 is mounted on the semiconductor chip mounting portion in the center of the substrate, and the semiconductor chip 21 and the connection electrode 2 are connected via the bonding wires 23 as shown in FIG. Connected.
[0083]
Subsequently, the mounting surface of the semiconductor chip is sealed with an insulating resin 22 such as an epoxy resin, as shown in FIG.
Further, as shown in FIG. 7C, the copper alloy 10 is removed by etching. At this time, since the Au layer in the plating layer 4a of the land electrode 4 serves as an etching stopper, the inside of the land electrode 4, the vias 5 and the like are not removed, and only the copper alloy 10 is removed.
[0084]
As described above, according to the third embodiment, the semiconductor chip 21 is connected to the semiconductor device substrate according to the first embodiment, and the semiconductor chip 21 and its connecting portion are resin-sealed. Due to the operational effects of the first embodiment, high density and thinning can be expected, and high functionality can be expected.
[0085]
In addition, as a manufacturing process from the beginning, the insulating layer 1a is selectively formed on the sheet-like copper alloy 10, and then the plating layer 4a to be the surface of each land electrode 4 is formed. Sequentially, the land electrode 4 is formed, the insulating layer 1 is formed again, each via 5, each wiring region 3 and each connection electrode 2 are formed, and the semiconductor chip 21 is connected to each connection electrode 2, and the semiconductor chip 21 and the like Since the copper alloy 10 is removed by etching, the semiconductor device having the above-described effects can be manufactured easily and reliably, and the stability of the manufacturing process can be improved.
[0086]
Although detailed description is avoided in the present embodiment, when a semiconductor device is manufactured by continuing the post-process of FIG. 5F, the manufacturing process will be described from the beginning on the sheet-like copper alloy 10, The solder layer 4b and each land electrode 4 are selectively formed, and then the insulating layer 1 is sequentially formed, each via 5, each wiring region 3 and each connection electrode 2 are formed, and a semiconductor is formed on each connection electrode 2. Since the chip 21 is connected, the semiconductor chip 21 and the like are resin-sealed, and the copper alloy 10 is removed by etching, the semiconductor device having the effects of this embodiment can be easily and reliably manufactured. Stability can be improved. Furthermore, when the solder layer 4b is selectively formed, a high-resolution resist can be used to form a finer pattern with higher density.
(Other embodiments)
In the third embodiment, the semiconductor device is manufactured by mounting the semiconductor chip 21 and finally removing the copper alloy 10 after the step shown in FIG. 3C or FIG. However, the present invention is not limited to this, and the semiconductor chip 21 and the connection electrode 2 are connected via the bonding wire 23 after the step of removing the copper alloy 10 shown in FIG. 3D or FIG. Even if the semiconductor device having the structure shown in FIG. 6 is manufactured by adding a process and a process in which the mounting surface of the semiconductor chip 21 is sealed with the insulating resin 22, the present invention is implemented in the same manner. An effect can be obtained.
In addition, the present invention can be implemented with various modifications without departing from the gist thereof.
[0087]
【The invention's effect】
  As described above, according to the invention of claim 1, the insulating layer isCuredSince it is made of resin, the drilling process with a drill can be omitted, so a high-density pattern and a thin shape can be realized, and the surface of each land electrode is positioned almost flush with the surface of the insulating layer. It is possible to provide a substrate for a semiconductor device that can be reliably fixed during the process and the like, and is less likely to cause defects such as damage to a land electrode, and can realize high reliability.
[0088]
Also,eachSince the land electrode is covered with a sheet-like metal material, the electrode surface is protected until the completion of the semiconductor device on which the semiconductor chip is mounted, and it is difficult to cause defects such as scratches, thereby further improving the reliability. A substrate for a semiconductor device can be provided.
[0091]
  And claims1According to the invention, an insulating layer is selectively formed on a sheet-like copper alloy, and thereafter an etching stopper layer that becomes the surface of each land electrode is formed. Since the insulating layer is formed again, each via, each wiring region and each connection electrode are formed, and the copper alloy is removed by etching.HalfA substrate for a semiconductor device can be easily and reliably manufactured, and a method for manufacturing a substrate for a semiconductor device that can improve the stability of the manufacturing process can be provided.
[0093]
  And claims2According to the invention, an insulating layer is selectively formed on a sheet-like copper alloy, and thereafter an etching stopper layer that becomes the surface of each land electrode is formed. Form the insulating layer again, form each via, each wiring region and each connection electrode, connect the semiconductor chip to each connection electrode, resin-seal the semiconductor chip, etc., and remove the copper alloy by etching,HalfA conductor device can be easily and reliably manufactured, and a method for manufacturing a semiconductor device that can improve the stability of the manufacturing process can be provided.
[0094]
  Claims3According to the invention, a resist layer and each land electrode forming hole are formed on a sheet-like copper alloy, an etching stopper layer and each land electrode are formed, the resist layer is peeled off, and then the insulating layers are sequentially insulated. Forming a layer, forming each via, each wiring region and each connection electrode, and removing the copper alloy by etching,HalfA substrate for a conductor device can be manufactured easily and reliably, the stability of the manufacturing process can be improved, and a higher resolution resist can be used to selectively form an etching stopper layer. It is possible to provide a method for manufacturing a substrate for a semiconductor device capable of forming a fine pattern with a high density.
[0096]
  Claims4According to the invention, a resist layer and each land electrode forming hole are formed on a sheet-like copper alloy, an etching stopper layer and each land electrode are formed, the resist layer is peeled off, and then the insulating layers are sequentially insulated. Forming a layer, forming each via, each wiring region and each connection electrode, connecting a semiconductor chip to each connection electrode, sealing the semiconductor chip, etc., and removing the copper alloy by etching,HalfThe conductor device can be manufactured easily and reliably, the stability of the manufacturing process can be improved, and when the etching stopper layer is selectively formed, by using a high-resolution resist, the density can be further increased. A method of manufacturing a semiconductor device capable of forming a fine pattern can be provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration of a substrate for a semiconductor device according to a first embodiment of the invention.
FIG. 2 is a process sectional view for explaining the manufacturing method according to the embodiment;
3 is a process cross-sectional view for explaining the manufacturing method in the same embodiment; FIG.
FIG. 4 is a cross-sectional view showing a configuration of a semiconductor device substrate according to a second embodiment of the present invention.
FIG. 5 is a process sectional view for explaining the manufacturing method according to the embodiment;
FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment of the present invention.
FIG. 7 is a process cross-sectional view for explaining the manufacturing method in the same embodiment;
FIG. 8 is a cross-sectional view showing a configuration of a semiconductor device using a conventional substrate for a semiconductor device.
[Explanation of symbols]
1, 1a ... Insulating layer
2 ... Connection electrode
2a, 4a ... plating layer
3 ... Wiring area
4 ... Land electrode
4b ... Solder layer
5 ... Bahia
6 ... Protective layer
10 ... Copper alloy
11 ... Copper layer
12 ... Bahia Hall
13 ... resist layer
21 ... Semiconductor chip
22 ... Insulating resin
23 ... Bonding wire

Claims (4)

A first step of forming a first insulating layer formed by curing a resin on a sheet-like copper alloy; a second step of forming a plurality of land electrode formation holes in the first insulating layer; the upper surface of the front Symbol said sheet-like copper alloy is exposed from each land electrode forming holes, the sheet of the copper alloy by electrolytic gold plating treatment for the electrode, a thickness of the electroless gold plating layer of 5μm from 0.1μm a third step of forming a plurality of etching stopper layer made by electroless nickel plating, a fourth step of forming a plurality of electrolytic nickel plating layer before Symbol the etching stopper layer by electrolytic copper plating process, by forming a plurality of electrolytic copper plating layer prior Symbol the electroless nickel plating layer, a plurality of lands electrostatic consisting previous SL each etch stopper layer, before Symbol the electroless nickel plating layer and prior Symbol the electrolytic copper plating layer A fifth step of forming a pole, on the first insulating layer and prior Symbol each land electrode, a sixth step of the resin to form a second insulating layer formed by curing, the second the insulating layer, and a seventh step of forming a via hole formed hole before Symbol reaching the respective land electrodes by electrolytic copper plating treatment, an eighth step of forming a copper layer filling the via hole, the copper layer a ninth step of smoothing by buffing the top and the second insulating layer above, after the smoothing, the copper plating, the wiring area on the copper layer and the second insulating layer and a tenth step of forming integrally the respective connection electrodes, the second insulating layer, the respective wiring layer and the upper connection electrodes, and the eleventh step of attaching a dry film for protecting Then, after attaching the dry film, the copper alloy is removed by etching. Step and the 13th step and the method of manufacturing a substrate for a semiconductor device characterized by containing the peeling off the dry film. A first step of forming a first insulating layer formed by curing a resin on a sheet-like copper alloy; a second step of forming a plurality of land electrode formation holes in the first insulating layer; the upper surface of the front Symbol said sheet-like copper alloy is exposed from each land electrode forming holes, the sheet of the copper alloy by electrolytic gold plating treatment for the electrode, a thickness of the electroless gold plating layer of 5μm from 0.1μm a third step of forming a plurality of etching stopper layer made by electroless nickel plating, a fourth step of forming a plurality of electrolytic nickel plating layer before Symbol the etching stopper layer by electrolytic copper plating process, by forming a plurality of electrolytic copper plating layer prior Symbol the electroless nickel plating layer, a plurality of lands electrostatic consisting previous SL each etch stopper layer, before Symbol the electroless nickel plating layer and prior Symbol the electrolytic copper plating layer A fifth step of forming a pole, on the first insulating layer and prior Symbol each land electrode, a sixth step of the resin to form a second insulating layer formed by curing, the second the insulating layer, and a seventh step of forming a via hole formed hole before Symbol reaching the respective land electrodes by electrolytic copper plating treatment, an eighth step of forming a copper layer filling the via hole, the copper layer a ninth step of smoothing by buffing the top and the second insulating layer above, after the smoothing, the copper plating, the wiring area on the copper layer and the second insulating layer and eleventh mounting a tenth step of manufacturing a substrate for a semiconductor device by forming each connection electrodes together, the semiconductor chip on the upper surface of the semiconductor device substrate by connecting to the respective connection electrodes And a connection portion to at least the semiconductor chip and each of the connection electrodes And a twelfth step of resin encapsulation, wherein after the resin sealing, a method of manufacturing a semiconductor device characterized by and a thirteenth step of removing the copper alloy by etching. On a sheet-like copper alloy, a first step and a second step of forming a plurality of land electrodes formed hole in the resist layer, the sheet prior Symbol exposed from the land electrode formed holes for forming a resist layer A third step of forming a plurality of etching stopper layers made of a solder plating layer having a thickness of 3 μm to 5 μm on the upper surface of the copper alloy having a sheet shape by electrolytic solder plating using the sheet-like copper alloy as an electrode; by electrolytic copper plating, by forming a plurality of electrolytic copper plating layer prior Symbol the etching stopper layer, the second to form a pre-Symbol plurality of land electrodes made of the etching stopper layer and before Symbol the electrolytic copper plating layer 4 of a step, after the formation of the land electrodes, wherein a fifth step of removing the resist layer, on said sheet-like copper alloy and prior Symbol each land electrode, an insulating layer resin is being cured A sixth step of forming a said insulating layer, and a seventh step of forming a via hole formed hole before Symbol reaching the respective land electrodes by electrolytic copper plating, a copper layer filling the via hole An eighth step of performing, a ninth step of buffing and smoothing the copper layer and the insulating layer, and after the smoothing, by copper plating on the copper layer and the insulating layer a tenth step of forming each wiring region and the connection electrodes together, the insulating layer, wherein each wiring layer and the upper connection electrodes, eleventh step of attaching a dry film for protecting And a twelfth step of removing the copper alloy by etching after the bonding of the dry film and a thirteenth step of peeling the dry film. Production method. On a sheet-like copper alloy, a first step and a second step of forming a plurality of land electrodes formed hole in the resist layer, the sheet prior Symbol exposed from the land electrode formed holes for forming a resist layer A third step of forming a plurality of etching stopper layers made of a solder plating layer having a thickness of 3 μm to 5 μm on the upper surface of the copper alloy having a sheet shape by electrolytic solder plating using the sheet-like copper alloy as an electrode; by electrolytic copper plating, by forming a plurality of electrolytic copper plating layer prior Symbol the etching stopper layer, the second to form a pre-Symbol plurality of land electrodes made of the etching stopper layer and before Symbol the electrolytic copper plating layer 4 of a step, after the formation of the land electrodes, wherein a fifth step of removing the resist layer, on said sheet-like copper alloy and prior Symbol each land electrode, an insulating layer resin is being cured A sixth step of forming a said insulating layer, and a seventh step of forming a via hole formed hole before Symbol reaching the respective land electrodes by electrolytic copper plating, a copper layer filling the via hole An eighth step of performing, a ninth step of buffing and smoothing the copper layer and the insulating layer, and after the smoothing, by copper plating on the copper layer and the insulating layer a tenth step of manufacturing a substrate for a semiconductor device by forming each wiring region and the connection electrodes together, a pre-Symbol semiconductor chip on the upper surface of the semiconductor device substrate by connecting the connection electrodes An eleventh step of mounting, a twelfth step of resin-sealing at least the semiconductor chip and its connection portions to the connection electrodes, and a step of removing the copper alloy by etching after the resin sealing. Including 13 processes. The method of manufacturing a semiconductor device according to.

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