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JP4123131B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP4123131B2
JP4123131B2 JP2003369832A JP2003369832A JP4123131B2 JP 4123131 B2 JP4123131 B2 JP 4123131B2 JP 2003369832 A JP2003369832 A JP 2003369832A JP 2003369832 A JP2003369832 A JP 2003369832A JP 4123131 B2 JP4123131 B2 JP 4123131B2
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semiconductor device
wiring
semiconductor
bumps
circuit board
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JP2004048074A (en
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伸仁 大内
茂 山田
靖 白石
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

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  • Wire Bonding (AREA)

Description

本発明は、歩留まりの低下を抑えつつ、高密度実装化を図ることが可能な半導体装置に関するものである。   The present invention relates to a semiconductor device capable of achieving high-density mounting while suppressing a decrease in yield.

近年における携帯型電子機器の急速な普及には目覚ましいものがある。これに伴って携帯型電子機器に搭載される樹脂封止型半導体装置も薄型・小型・軽量のものが要求されるようになっている。かかる要求に応える高密度化の半導体装置としてチップサイズパッケージと称されるものがある。このチップサイズパッケージの構成の一例を、図12を参照しながら説明する。   The rapid spread of portable electronic devices in recent years is remarkable. Accordingly, a resin-encapsulated semiconductor device mounted on a portable electronic device is required to be thin, small, and lightweight. As a high-density semiconductor device that meets such demands, there is one called a chip size package. An example of the configuration of this chip size package will be described with reference to FIG.

半導体装置820は、図12に示したように、400μm程度の厚みを有する半導体素子1b上に電極パッド6が形成され、電極パッド6に電気的に接続するCu等による配線2が形成されている。半導体素子1bの表面及び配線2は、厚み100μm程度の封止樹脂5によって封止されている。封止樹脂5の表面に露出した配線2の上面にははんだ等によるバンプ3が形成されている。図中符号4は、電極パッド6と配線2とを電気的に接続するCu等による再配線である。   In the semiconductor device 820, as shown in FIG. 12, the electrode pad 6 is formed on the semiconductor element 1b having a thickness of about 400 μm, and the wiring 2 made of Cu or the like electrically connected to the electrode pad 6 is formed. . The surface of the semiconductor element 1b and the wiring 2 are sealed with a sealing resin 5 having a thickness of about 100 μm. Bumps 3 made of solder or the like are formed on the upper surface of the wiring 2 exposed on the surface of the sealing resin 5. Reference numeral 4 in the figure denotes rewiring with Cu or the like for electrically connecting the electrode pad 6 and the wiring 2.

この図12に示した半導体装置820の製造方法を、図13を参照しながら説明する。まず、図13(A)に示したように、半導体素子1b上にCu等による配線2が形成される。なお、図13(A)では、上記電極パッド6及び再配線4は図示していない。そして、図13(B)に示したように、配線2を完全に覆う厚みで半導体素子1bの表面全体を封止樹脂5により封止する。次いで、図13(C)に示したように、表面全体を研削して配線2を表面に露出させた後、図13(D)に示したように、はんだ等によるバンプ3を形成する。さらに、半導体素子1bを個々の半導体装置に切断し分割することによって、半導体装置820が製造される。   A method for manufacturing the semiconductor device 820 shown in FIG. 12 will be described with reference to FIG. First, as shown in FIG. 13A, the wiring 2 made of Cu or the like is formed on the semiconductor element 1b. In FIG. 13A, the electrode pad 6 and the rewiring 4 are not shown. Then, as shown in FIG. 13B, the entire surface of the semiconductor element 1 b is sealed with a sealing resin 5 with a thickness that completely covers the wiring 2. Next, as shown in FIG. 13C, after the entire surface is ground to expose the wiring 2 on the surface, bumps 3 made of solder or the like are formed as shown in FIG. 13D. Furthermore, the semiconductor device 820 is manufactured by cutting and dividing the semiconductor element 1b into individual semiconductor devices.

なお、本件の親出願である特願平11−187658号においては、拒絶理由通知の際に以下の8件の文献が挙げられている。
特開平10−93013号公報 特開平9−181256号公報 特開昭59−117146号公報 特開平10−12810号公報 特開平7−240496号公報 実願平1−144089号(実開平3−83940号)のマイクロフィルム 特願平11−145870号(特開2000−340736号公報) 特願平10−121046号(特開平11−312780号公報)
In Japanese Patent Application No. 11-187658, which is the parent application of the present case, the following eight documents are cited at the time of notification of reasons for refusal.
Japanese Patent Laid-Open No. 10-93013 Japanese Patent Laid-Open No. 9-181256 JP 59-117146 A Japanese Patent Laid-Open No. 10-12810 Japanese Patent Laid-Open No. 7-240696 Microfilm of Japanese Utility Model Application No. 1-144089 (Japanese Utility Model Application No. 3-83940) Japanese Patent Application No. 11-145870 (Japanese Patent Laid-Open No. 2000-340736) Japanese Patent Application No. 10-121046 (Japanese Patent Laid-Open No. 11-31780)

ところで、例えばメモリプロセスとロジックプロセスのように、半導体素子製造のプロセス条件が異なる場合には、これらの異なる複数の機能を一の半導体素子上に形成することは難しい。かかる場合には、各機能の半導体装置を個別に製造しておき、それらをプリント基板上に実装することが行われる。
例えば、2つの半導体装置をプリント基板13に実装する場合について説明する。ここで第1の半導体装置810は、半導体素子811及び金線815が設けられたエポキシ基板816の片面を封止樹脂805により封止し、裏面にはんだ等のバンプ803がエリア状に形成されたBGA(ball grid array)構造と称される半導体装置であり、第2の半導体装置は上述の半導体装置820であり、それぞれ個別に製造されたものである。これら個別に製造された2つの半導体装置810、820の実装を、図14に示したように、プリント基板13の同一平面上で行うと、高密度基板実装を図ることが難しいという問題があった。
By the way, when the process conditions for manufacturing a semiconductor element are different, such as a memory process and a logic process, it is difficult to form these different functions on one semiconductor element. In such a case, semiconductor devices having respective functions are individually manufactured and mounted on a printed board.
For example, a case where two semiconductor devices are mounted on the printed circuit board 13 will be described. Here, in the first semiconductor device 810, one surface of the epoxy substrate 816 provided with the semiconductor element 811 and the gold wire 815 is sealed with a sealing resin 805, and bumps 803 such as solder are formed in an area shape on the back surface. The semiconductor device is called a BGA (ball grid array) structure, and the second semiconductor device is the above-described semiconductor device 820, which are individually manufactured. When mounting these two individually manufactured semiconductor devices 810 and 820 on the same plane of the printed board 13 as shown in FIG. 14, there is a problem that it is difficult to achieve high-density board mounting. .

また、上記問題点を解決するために、図15に示したように、半導体素子1a、1bを積み重ね、金属細線15a、15bを配線14に接続した後に樹脂封止する構成がある。かかる構成によれば、基板実装面積を増加させることなく高密度実装を図ることができる。しかしながら、半導体装置全体の歩留まりの点においては、以下の問題点があった。すなわち、通常、半導体素子はウェハの状態で簡易的な特性チェックがされるが、最終テスト(出荷テスト)は、組立後の半導体装置としてのみ実施がされる。したがって、最終テストの済んでいない2つの半導体素子を搭載して半導体装置を製造すると、半導体装置全体としての歩留まりは2つの半導体素子の歩留まりの積となる。このため高密度実装化に反比例して歩留まりの低下が生じ、コストアップにつながるという課題があった。   In order to solve the above problem, as shown in FIG. 15, there is a configuration in which the semiconductor elements 1 a and 1 b are stacked and the metal thin wires 15 a and 15 b are connected to the wiring 14 and then resin-sealed. According to this configuration, high-density mounting can be achieved without increasing the board mounting area. However, there are the following problems in terms of the yield of the entire semiconductor device. That is, normally, a semiconductor device is subjected to a simple characteristic check in a wafer state, but a final test (shipment test) is performed only as a semiconductor device after assembly. Therefore, when a semiconductor device is manufactured by mounting two semiconductor elements that have not been final tested, the yield of the entire semiconductor device is the product of the yields of the two semiconductor elements. For this reason, there is a problem that the yield is reduced in inverse proportion to the high-density mounting, leading to an increase in cost.

上述の課題を解決するため、本発明によれば、第1の半導体装置と、前記第1の半導体装置に接着剤を介して接合され前記第1の半導体装置とは異なる機能を有する第2の半導体装置とで構成された半導体装置であって、前記第1の半導体装置は、複数のバンプが形成された第1の面を有し、当該複数のバンプが、配線を有するプリント基板の当該配線と接続されるものであり、前記第2の半導体装置は、複数の端子が形成された第2の面を有し、前記第2の面とは反対側の面が前記第1の半導体装置の前記第1の面に対向するように、前記第1の半導体装置の前記第1の面における前記複数のバンプが形成されていない領域上に接着剤を介して接合されており、当該複数の端子が、前記プリント基板の配線と電気的に接続されるものであり、前記複数のバンプの高さは前記第2の半導体装置の高さ以上であり、前記第1の半導体装置の前記バンプと前記第2の半導体装置の前記端子とは、前記プリント基板の前記配線を介して電気的に接続されることを特徴とする半導体装置が提供される。   In order to solve the above-described problem, according to the present invention, a first semiconductor device and a second semiconductor device bonded to the first semiconductor device via an adhesive and having a function different from that of the first semiconductor device. A semiconductor device configured with a semiconductor device, wherein the first semiconductor device has a first surface on which a plurality of bumps are formed, and the plurality of bumps have wirings on the printed circuit board. The second semiconductor device has a second surface on which a plurality of terminals are formed, and a surface opposite to the second surface is the surface of the first semiconductor device. The plurality of terminals are bonded via an adhesive to a region of the first surface of the first semiconductor device where the plurality of bumps are not formed so as to face the first surface. Is electrically connected to the wiring of the printed circuit board. The heights of the plurality of bumps are equal to or higher than the height of the second semiconductor device, and the bumps of the first semiconductor device and the terminals of the second semiconductor device connect the wiring of the printed circuit board. A semiconductor device is provided which is electrically connected through the semiconductor device.

また、上述の課題を解決するため、本発明によれば、第1の半導体装置と、前記第1の半導体装置に接着剤を介して接合され前記第1の半導体装置とは異なる機能を有する第2の半導体装置とで構成された半導体装置であって、前記第1の半導体装置は、表面及び裏面を有する基板と、前記基板の前記表面上に搭載された第1の半導体素子と、前記第1の半導体素子を封止する樹脂と、前記基板の前記裏面上に形成され、かつ、プリント基板上の配線と電気的に接続される複数のバンプとで構成され、前記第2の半導体装置は、前記プリント基板の前記配線と電気的に接続される複数の端子が形成された面とは反対側の面が前記基板の前記裏面に対向するように、前記基板の前記裏面における前記複数のバンプが形成されていない領域上に接着剤を介して接合された第2の半導体素子を有しており、前記複数のバンプの高さは前記第2の半導体素子の高さ以上であり、前記バンプと前記端子とは、前記プリント基板の前記配線を介して電気的に接続されることを特徴とする半導体装置が提供される。   In order to solve the above-described problem, according to the present invention, a first semiconductor device and a first semiconductor device that is bonded to the first semiconductor device via an adhesive and has a function different from that of the first semiconductor device. The first semiconductor device includes a substrate having a front surface and a back surface, a first semiconductor element mounted on the front surface of the substrate, and the first semiconductor device. The second semiconductor device includes: a resin for sealing one semiconductor element; and a plurality of bumps formed on the back surface of the substrate and electrically connected to wiring on the printed circuit board. The plurality of bumps on the back surface of the substrate such that the surface opposite to the surface on which the plurality of terminals electrically connected to the wiring of the printed circuit board is opposed to the back surface of the substrate On the area where no A plurality of bumps having a height equal to or greater than a height of the second semiconductor element, and the bumps and the terminals are the printed circuit board. A semiconductor device is provided which is electrically connected through the wiring.

さらに、上述の課題を解決するため、本発明によれば、第1の半導体装置と、前記第1の半導体装置に接着剤を介して接合され前記第1の半導体装置とは異なる機能を有する第2の半導体装置とで構成された半導体装置であって、前記第1の半導体装置は、複数の電極が形成された第1の面を有する第1の半導体素子と、前記第1の面を封止するように前記第1の半導体素子上に形成された樹脂部と、前記複数の電極上に形成され、かつ、プリント基板上の配線と電気的に接続される複数のバンプで構成され、前記第2の半導体装置は、前記プリント基板上の前記配線と電気的に接続される複数の端子が形成された第2の面を有し、前記第2の面とは反対側の面が前記第1の面に対向するように、前記第1の半導体素子における前記複数のバンプが形成されていない領域上に接着剤を介して接合された第2の半導体素子を有しており、
前記複数のバンプの高さは前記第2の半導体素子の高さ以上であり、前記第1の半導体素子の前記バンプと前記第2の半導体素子の前記端子とは、前記プリント基板の前記配線を介して電気的に接続されることを特徴とする半導体装置が提供される。
Furthermore, in order to solve the above-described problem, according to the present invention, a first semiconductor device and a first semiconductor device bonded to the first semiconductor device via an adhesive and having a function different from that of the first semiconductor device. The first semiconductor device includes a first semiconductor element having a first surface on which a plurality of electrodes are formed, and the first surface being sealed. A resin portion formed on the first semiconductor element to stop, and a plurality of bumps formed on the plurality of electrodes and electrically connected to wiring on a printed circuit board, The second semiconductor device has a second surface on which a plurality of terminals electrically connected to the wiring on the printed board are formed, and a surface opposite to the second surface is the first surface. The plurality of bars in the first semiconductor element so as to face one surface. Flop via the adhesive on a region not formed has a second semiconductor element which are bonded,
The height of the plurality of bumps is equal to or higher than the height of the second semiconductor element, and the bump of the first semiconductor element and the terminal of the second semiconductor element are connected to the wiring of the printed circuit board. A semiconductor device is provided which is electrically connected through the semiconductor device.

本発明の効果として、半導体装置の製造における歩留まり低下の抑制しながら、高密度実装化を図ることが可能な半導体装置の提供が挙げられる。   As an effect of the present invention, provision of a semiconductor device capable of achieving high-density mounting while suppressing a decrease in yield in the manufacture of the semiconductor device can be given.

以下に添付図面を参照しながら、本発明にかかる半導体装置及びその製造方法の好適な実施の形態について詳細に説明する。なお、本明細書及び図面において、実質的に同一の機能構成を有する構成要素については、同一の符号を付することにより重複説明を省略する。   Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

本実施の形態にかかる半導体装置100を、図1を参照しながら説明する。半導体装置100は、図1(A)に示したように、表面にはんだ等のバンプ3が例えば格子状に形成された第1の半導体装置110と、複数の端子2を有し、第1の半導体装置110の表面のバンプ3が形成されていない領域に搭載される第2の半導体装置120とを含んでいる。第1の半導体装置110のバンプ3と第2の半導体装置120の端子2とは、後工程で半導体装置100がプリント基板13に実装される際に、プリント基板13上の配線により、電気的に接続される。
第1の半導体装置110及び第2の半導体装置120の製造方法について、図2及び図3を参照しながら説明する。
A semiconductor device 100 according to the present embodiment will be described with reference to FIG. As shown in FIG. 1A, the semiconductor device 100 includes a first semiconductor device 110 having bumps 3 made of solder or the like formed on the surface thereof, for example, in a lattice shape, and a plurality of terminals 2. And a second semiconductor device 120 mounted on the surface of the semiconductor device 110 where the bumps 3 are not formed. The bump 3 of the first semiconductor device 110 and the terminal 2 of the second semiconductor device 120 are electrically connected by wiring on the printed circuit board 13 when the semiconductor device 100 is mounted on the printed circuit board 13 in a later process. Connected.
A method for manufacturing the first semiconductor device 110 and the second semiconductor device 120 will be described with reference to FIGS.

(第1の半導体装置110)まず、図2を参照しながら、第1の半導体装置110について説明する。まず、図2(A)に示したように、エポキシ基板16の表面に半導体素子1a及び配線14を設ける。そして、図2(B)に示したように、半導体素子1a上の電極と配線14とを金属細線15aにより接続する。その後、図2(C)に示したように、これらエポキシ基板16上の各構成部材を覆うように封止樹脂5で封止する。さらに、エポキシ基板16の裏面にバンプ3を形成する。このエポキシ基板16にはスルーホール17が形成されており、配線4は裏面のバンプ3と電気的に導通している。
バンプ3の高さは、後工程で第1の半導体装置110に搭載する第2の半導体装置120の高さと実質的に同じsか、わずかに高い寸法となっている。また、バンプ3は、後工程で半導体装置100がプリント基板13に実装される際の熱処理により溶融する。
(First Semiconductor Device 110) First, the first semiconductor device 110 will be described with reference to FIG. First, as shown in FIG. 2A, the semiconductor element 1 a and the wiring 14 are provided on the surface of the epoxy substrate 16. Then, as shown in FIG. 2B, the electrode on the semiconductor element 1a and the wiring 14 are connected by a thin metal wire 15a. Thereafter, as shown in FIG. 2C, sealing is performed with a sealing resin 5 so as to cover the constituent members on the epoxy substrate 16. Further, bumps 3 are formed on the back surface of the epoxy substrate 16. A through hole 17 is formed in the epoxy substrate 16, and the wiring 4 is electrically connected to the bump 3 on the back surface.
The height of the bump 3 is substantially the same as the height of the second semiconductor device 120 to be mounted on the first semiconductor device 110 in a later process, or slightly higher. Further, the bump 3 is melted by heat treatment when the semiconductor device 100 is mounted on the printed board 13 in a later process.

(第2の半導体装置120)次いで、図3を参照しながら、第2の半導体装置120の製造方法について説明する。まず、図3(A)に示したように、半導体素子1b上に電気メッキ等により、高さ約50μmのCuの配線2を形成する。次いで、図3(B)に示したように、配線2を完全に覆う厚みで半導体素子1bの表面全体を封止樹脂5bにより封止する。樹脂封止方法はトランスファーモールド法、ポッティング法、印刷法等が用いられる。次いで、図3(C)に示したように、表面全体を研削して配線2を表面に露出させる。
次いで、図3(D)に示したように、後工程で切断し分割する部分に所定の深さで溝9を形成する。溝9の深さは最終的に個々の半導体装置とした場合の半導体素子1bの厚みに基づいて決定する。半導体素子1bの厚みを100μmとする場合、溝は約20μm深く形成し約120μmとする。そして、樹脂部5bの厚みも加えて合計で170μmの深さとなる。
(Second Semiconductor Device 120) Next, a method for manufacturing the second semiconductor device 120 will be described with reference to FIG. First, as shown in FIG. 3A, a Cu wiring 2 having a height of about 50 μm is formed on the semiconductor element 1b by electroplating or the like. Next, as shown in FIG. 3B, the entire surface of the semiconductor element 1b is sealed with a sealing resin 5b with a thickness that completely covers the wiring 2. As the resin sealing method, a transfer molding method, a potting method, a printing method, or the like is used. Next, as shown in FIG. 3C, the entire surface is ground to expose the wiring 2 on the surface.
Next, as shown in FIG. 3D, a groove 9 is formed at a predetermined depth in a portion to be cut and divided in a subsequent process. The depth of the groove 9 is determined based on the thickness of the semiconductor element 1b when the semiconductor device is finally formed. When the thickness of the semiconductor element 1b is 100 μm, the groove is formed to be about 20 μm deep and about 120 μm. And the thickness of the resin part 5b is added and it becomes a depth of 170 micrometers in total.

次いで、裏面研削工程を行う。まず、図3(E)に示したように、溝9が形成された半導体素子1bの樹脂形成面に研削テープ20を貼付する。この研削テープ20は紫外線を照射することによって、粘着力が落ち、簡単に剥がせるものである。次いで、研削テープ20を貼付した面を研削ステージ(図示しない)に吸着により固定する。裏面の研削は、図3(F)に示したように、上述の溝9の底部に達するまで行う。こうして研削テープ12上に個々に分割された半導体装置(第2の半導体装置120)が並ぶ状態となる。
次いで、図3(G)に示したように、研削した面にマウントテープ21が貼付される。そして、研削テープ20は紫外線が照射されて除去される。この第2の半導体装置120がマウントテープ21に並べられた状態で、第1の半導体装置110へと搭載される。
Next, a back grinding process is performed. First, as shown in FIG. 3E, the grinding tape 20 is attached to the resin-formed surface of the semiconductor element 1b in which the grooves 9 are formed. This grinding tape 20 can be easily peeled off by irradiating it with ultraviolet rays. Next, the surface to which the grinding tape 20 is affixed is fixed to a grinding stage (not shown) by suction. The grinding of the back surface is performed until the bottom of the groove 9 is reached as shown in FIG. In this way, the semiconductor devices (second semiconductor device 120) divided individually on the grinding tape 12 are arranged.
Next, as shown in FIG. 3G, the mount tape 21 is attached to the ground surface. Then, the grinding tape 20 is removed by irradiation with ultraviolet rays. The second semiconductor device 120 is mounted on the first semiconductor device 110 in a state of being arranged on the mount tape 21.

第2の半導体装置120の第1の半導体装置120への搭載は、第1の半導体装置110のバンプ3が形成されていない領域に第2の半導体装置120を接着剤115を用いて搭載する。この接着剤115は、第1の半導体装置110に供給しておくこともできるが、マウントテープ21に接着剤115を設けることも可能である。以上の工程により、第1の実施の形態にかかる半導体装置100が製造される。半導体装置100は、後工程により、図1(B)に示したように、プリント基板13に実装される。このとき、第2の半導体装置120の端子2は、プリント基板13にはんだ18により電気的に接続される。ここで、はんだ18は、あらかじめプリント基板13に塗布されているはんだペーストであり、このはんだペーストは、バンプ3及び端子2に対応してそれぞれ形成されている。
以上のように半導体装置100によれば、第2の半導体装置120は、第1の半導体装置110の表面のバンプ3が形成されていない領域に搭載される。そして、第1の半導体装置110及び第2の半導体装置120がそれぞれ最終テスト済みであるため、歩留まりの低下を抑えつつ、高密度実装化を図ることが可能である。
The mounting of the second semiconductor device 120 on the first semiconductor device 120 is performed by mounting the second semiconductor device 120 on the region where the bumps 3 of the first semiconductor device 110 are not formed using the adhesive 115. The adhesive 115 can be supplied to the first semiconductor device 110, but the adhesive 115 can be provided on the mount tape 21. The semiconductor device 100 according to the first embodiment is manufactured through the above steps. The semiconductor device 100 is mounted on the printed circuit board 13 as shown in FIG. At this time, the terminal 2 of the second semiconductor device 120 is electrically connected to the printed circuit board 13 by the solder 18. Here, the solder 18 is a solder paste previously applied to the printed circuit board 13, and this solder paste is formed corresponding to the bump 3 and the terminal 2, respectively.
As described above, according to the semiconductor device 100, the second semiconductor device 120 is mounted on the surface of the first semiconductor device 110 where the bumps 3 are not formed. Since each of the first semiconductor device 110 and the second semiconductor device 120 has been subjected to a final test, high-density mounting can be achieved while suppressing a decrease in yield.

なお、本実施の形態においては、第1の半導体装置110にBGA構造の半導体装置を採用した場合の一例につき説明したが、本発明はこれに限定されない。例えば図4(A)に示したように、第1の半導体装置として、第2の半導体装置120と同様のチップサイズパッケージの第1の半導体装置110’を採用し、半導体装置100’を構成することも可能である。この第1の半導体装置110’は、図4(B)に示したように、上記第1の半導体装置110と同様、第2の半導体装置120を搭載する領域には、電極2及びバンプ3が形成されていない。なお、以下の実施の形態においても同様である。   Note that although an example in which a semiconductor device having a BGA structure is employed as the first semiconductor device 110 has been described in this embodiment, the present invention is not limited to this. For example, as shown in FIG. 4A, the first semiconductor device 110 ′ having the same chip size package as that of the second semiconductor device 120 is adopted as the first semiconductor device, thereby forming the semiconductor device 100 ′. It is also possible. As shown in FIG. 4B, the first semiconductor device 110 ′ has electrodes 2 and bumps 3 in the region where the second semiconductor device 120 is mounted, as in the first semiconductor device 110. Not formed. The same applies to the following embodiments.

本実施の形態にかかる半導体装置200は、上記半導体装置100を改良したものであり、第2の半導体装置220の端子が形成されていない面が第1の半導体装置210の表面と接着剤212により接合されることにより、第1の半導体装置210に搭載される点で上記半導体装置100と共通する。以下に、半導体装置200の改良点につき、図5を参照しながら説明する。なお、略同一の構成要素については同一符号を付すことで詳細な説明を省略する。   The semiconductor device 200 according to the present embodiment is an improvement of the semiconductor device 100, and the surface of the second semiconductor device 220 where the terminals are not formed is formed by the surface of the first semiconductor device 210 and the adhesive 212. By being bonded, it is common to the semiconductor device 100 in that it is mounted on the first semiconductor device 210. Hereinafter, improvements of the semiconductor device 200 will be described with reference to FIG. In addition, about the same component, the detailed description is abbreviate | omitted by attaching | subjecting the same code | symbol.

半導体装置200においては、第1の半導体装置210のバンプ3が形成されていない所定の領域に、第2の半導体装置220の大きさに合わせて浅く平滑に削った凹部(座繰り部)215が形成されている。そして、第2の半導体装置220はこの座繰り部215に搭載される。
半導体装置200は、後工程により、図5(B)に示したように、プリント基板13に実装される。このとき、座繰り部215を形成したことにより第2の半導体装置220とプリント基板13との間に広い空間をとることができるので、図5(B)に示したように、素子間の接続の信頼性を向上させるためのはんだ等のバンプ3bを形成することができる。
以上のように、半導体装置200によれば、第2の半導体装置220を搭載する領域に厚み方向の広い空間を取ることができるので、第2の半導体装置220が多少厚みのあるものであっても搭載することができる。また、この空間にはんだ等のバンプ3bを形成することにより、素子間の接続の信頼性を向上させることが可能である。
In the semiconductor device 200, a recess (a countersink portion) 215 that is shallowly and smoothly cut according to the size of the second semiconductor device 220 is formed in a predetermined region where the bump 3 of the first semiconductor device 210 is not formed. Is formed. Then, the second semiconductor device 220 is mounted on the counterbore part 215.
The semiconductor device 200 is mounted on the printed circuit board 13 as shown in FIG. At this time, since the counterbored portion 215 is formed, a wide space can be provided between the second semiconductor device 220 and the printed circuit board 13, so that connection between elements is performed as shown in FIG. Bumps 3b made of solder or the like for improving the reliability can be formed.
As described above, according to the semiconductor device 200, since a wide space in the thickness direction can be provided in the region where the second semiconductor device 220 is mounted, the second semiconductor device 220 is somewhat thick. Can also be installed. Also, by forming bumps 3b such as solder in this space, it is possible to improve the reliability of connection between elements.

本実施の形態にかかる半導体装置300は、上記半導体装置100を改良したものであり、第2の半導体装置320の端子が形成されていない面が第1の半導体装置310の表面と接着剤により接合されることにより、第1の半導体装置310に搭載される点で上記半導体装置100と共通する。以下に、半導体装置300の改良点につき、図6を参照しながら説明する。なお、略同一の構成要素については同一符号を付すことで詳細な説明を省略する。   The semiconductor device 300 according to the present embodiment is an improvement of the semiconductor device 100, and the surface of the second semiconductor device 320 where the terminals are not formed is bonded to the surface of the first semiconductor device 310 with an adhesive. Thus, the semiconductor device 100 is common to the semiconductor device 100 in that it is mounted on the first semiconductor device 310. Hereinafter, improvements of the semiconductor device 300 will be described with reference to FIG. In addition, about the same component, the detailed description is abbreviate | omitted by attaching | subjecting the same code | symbol.

半導体装置300は、図6(A)に示したように、第2の半導体装置320の裏面と、第1の半導体装置310とを接合する接着剤に、所定の温度以上で接着性を失う低分子接着剤315を用いたことを特徴としている。ここで所定の温度とは、半導体装置300をプリント基板13に実装する際のリフロー等の熱処理時の温度であり、例えば200℃以上で接着性を失う低分子接着剤を用いることができる。
半導体装置300は、後工程により、図6(B)に示したように、プリント基板13に実装される。このとき、低分子接着剤315は接着力を失い、第1の半導体装置310と第2の半導体装置320とは分離される。
以上のように半導体装置300によれば、半導体装置300をプリント基板13に実装する際に、第1の半導体装置310と第2の半導体装置320とを分離して、個別に位置合わせすることができる。かかるセルフアライメント効果により、正確な位置に実装することが可能である。
As shown in FIG. 6A, the semiconductor device 300 is a low adhesive that bonds the back surface of the second semiconductor device 320 and the first semiconductor device 310 at a predetermined temperature or higher. A molecular adhesive 315 is used. Here, the predetermined temperature is a temperature at the time of heat treatment such as reflow when the semiconductor device 300 is mounted on the printed circuit board 13, and for example, a low molecular adhesive that loses adhesion at 200 ° C. or higher can be used.
The semiconductor device 300 is mounted on the printed circuit board 13 as shown in FIG. At this time, the low molecular adhesive 315 loses adhesive force, and the first semiconductor device 310 and the second semiconductor device 320 are separated.
As described above, according to the semiconductor device 300, when the semiconductor device 300 is mounted on the printed circuit board 13, the first semiconductor device 310 and the second semiconductor device 320 can be separated and individually aligned. it can. Due to such a self-alignment effect, mounting at an accurate position is possible.

本参考例1にかかる半導体装置400を、図7を参照しながら説明する。なお、第1の実施の形態にかかる半導体装置100と略同一の構成要素については同一符号を付すことで詳細な説明を省略する。   A semiconductor device 400 according to the first reference example will be described with reference to FIG. In addition, about the component substantially the same as the semiconductor device 100 concerning 1st Embodiment, detailed description is abbreviate | omitted by attaching | subjecting the same code | symbol.

上記半導体装置100では、第2の半導体装置120の端子が形成されていない面が第1の半導体装置110の表面と接着剤115により接合されることにより、第1の半導体装置110に搭載されていた。本参考例1にかかる半導体装置400では、図7(A)に示したように、第2の半導体装置420の端子2が第1の半導体装置410の表面とはんだ415により接合されることにより、第1の半導体装置410に搭載されることを特徴としている。
第1の半導体装置410のバンプ3が形成されたエポキシ基板16の裏面には、バンプ3と第2の半導体装置420の端子2とを電気的に導通させるための配線パターンが形成されている。上記構成によれば、エポキシ基板16の裏面で第1の半導体装置410と第2の半導体装置420とは電気的に接続される。
以上のように半導体装置400によれば、図7(B)に示したように、後工程でプリント基板13に実装する際に、装置全体の端子が増えていないため、容易に実装することが可能である。
The semiconductor device 100 is mounted on the first semiconductor device 110 by bonding the surface of the second semiconductor device 120 on which the terminals are not formed to the surface of the first semiconductor device 110 with an adhesive 115. It was. In the semiconductor device 400 according to the first reference example, as illustrated in FIG. 7A, the terminal 2 of the second semiconductor device 420 is bonded to the surface of the first semiconductor device 410 with the solder 415. It is mounted on the first semiconductor device 410.
A wiring pattern for electrically connecting the bumps 3 and the terminals 2 of the second semiconductor device 420 is formed on the back surface of the epoxy substrate 16 on which the bumps 3 of the first semiconductor device 410 are formed. According to the above configuration, the first semiconductor device 410 and the second semiconductor device 420 are electrically connected on the back surface of the epoxy substrate 16.
As described above, according to the semiconductor device 400, as shown in FIG. 7B, when the device is mounted on the printed circuit board 13 in a subsequent process, the number of terminals of the entire device is not increased. Is possible.

なお、本参考例1においては、第1の半導体装置410にBGA構造の半導体装置を採用した場合の一例につき説明したが、本発明はこれに限定されない。例えば図8(A)に示したように、第1の半導体装置として、第2の半導体装置420と同様のチップサイズパッケージの第1の半導体装置410’を採用し、半導体装置400’を構成することも可能である。この第1の半導体装置410’は、図8(B)に示したように、上記第1の半導体装置410と同様、第2の半導体装置420を搭載する領域には、バンプ3が形成されておらず、端子2が露出している。そして、この第1の半導体装置410’の端子2と、第2の半導体装置420の端子2とが、はんだ415により電気的に接続される。なお、以下の実施の形態においても同様である。   In the first reference example, an example in which a semiconductor device having a BGA structure is employed as the first semiconductor device 410 has been described. However, the present invention is not limited to this. For example, as shown in FIG. 8A, a first semiconductor device 410 ′ having a chip size package similar to that of the second semiconductor device 420 is adopted as the first semiconductor device, thereby forming the semiconductor device 400 ′. It is also possible. As shown in FIG. 8B, the first semiconductor device 410 ′ has bumps 3 formed in the region where the second semiconductor device 420 is mounted, as in the first semiconductor device 410. The terminal 2 is exposed. The terminal 2 of the first semiconductor device 410 ′ and the terminal 2 of the second semiconductor device 420 are electrically connected by solder 415. The same applies to the following embodiments.

本参考例2にかかる半導体装置500は、上記半導体装置400を改良したものであり、第2の半導体装置520の端子が第1の半導体装置510の表面とはんだ514により接合されることにより、第1の半導体装置510に搭載される点で上記半導体装置400と共通する。以下に、半導体装置500の改良点につき、図9を参照しながら説明する。なお、略同一の構成要素については同一符号を付すことで詳細な説明を省略する。   The semiconductor device 500 according to the second reference example is an improvement of the semiconductor device 400, and the terminal of the second semiconductor device 520 is joined to the surface of the first semiconductor device 510 by the solder 514, so that the first It is common to the semiconductor device 400 in that it is mounted on one semiconductor device 510. Hereinafter, improvements of the semiconductor device 500 will be described with reference to FIG. In addition, about the same component, the detailed description is abbreviate | omitted by attaching | subjecting the same code | symbol.

半導体装置500は、図9(A)に示したように、第2の半導体装置510の裏面に、熱伝導性の高い接着部材515が貼付されることを特徴としている。この接着部材515は、図示した例では、所定厚みのシート状をしている。
半導体装置500は、後工程により、図9(B)に示したように、プリント基板13に実装される。このとき、第2の半導体装置520は、接着部材515の接着力によりプリント基板13に安定して固定される。
以上のように半導体装置500によれば、第2の半導体装置520は、熱伝導性の高い接着部材617を介してプリント基板13に接続されているため、第2の半導体装置520の放熱性を向上させることが可能である。
As shown in FIG. 9A, the semiconductor device 500 is characterized in that an adhesive member 515 having high thermal conductivity is attached to the back surface of the second semiconductor device 510. In the illustrated example, the adhesive member 515 has a sheet shape with a predetermined thickness.
The semiconductor device 500 is mounted on the printed circuit board 13 as shown in FIG. At this time, the second semiconductor device 520 is stably fixed to the printed circuit board 13 by the adhesive force of the adhesive member 515.
As described above, according to the semiconductor device 500, since the second semiconductor device 520 is connected to the printed circuit board 13 through the adhesive member 617 having high thermal conductivity, the heat dissipation of the second semiconductor device 520 is improved. It is possible to improve.

本参考例3にかかる半導体装置600は、上記半導体装置400を改良したものであり、第2の半導体装置620の端子が第1の半導体装置610の表面とはんだにより接合されることにより、第1の半導体装置610に搭載される点で上記半導体装置400と共通する。以下に、半導体装置600の改良点につき、図10を参照しながら説明する。なお、略同一の構成要素については同一符号を付すことで詳細な説明を省略する。   The semiconductor device 600 according to the present reference example 3 is an improvement of the semiconductor device 400 described above, and the first semiconductor device 620 is joined to the surface of the first semiconductor device 610 by soldering the first semiconductor device 610. This is common to the semiconductor device 400 in that it is mounted on the semiconductor device 610. Hereinafter, improvements of the semiconductor device 600 will be described with reference to FIG. In addition, about the same component, the detailed description is abbreviate | omitted by attaching | subjecting the same code | symbol.

半導体装置600は、第2の半導体装置620の端子面と、第1の半導体装置610とを接合するはんだに、高融点はんだ615を用いたことを特徴としている。ここで高融点とは、後工程で半導体装置600をプリント基板13に実装する際の温度より高い融点であり、例えば200℃以上の融点を持つ高融点はんだ615を用いることができる。
以上説明したように半導体装置600によれば、プリント基板13への実装時のリフロー等の熱処理を行っても、第2の半導体装置620は、第1の半導体装置610に高融点はんだで接合されているため、安定した基板実装が可能である。
The semiconductor device 600 is characterized in that a high melting point solder 615 is used as solder for joining the terminal surface of the second semiconductor device 620 and the first semiconductor device 610. Here, the high melting point is a melting point higher than the temperature at which the semiconductor device 600 is mounted on the printed circuit board 13 in a later step. For example, a high melting point solder 615 having a melting point of 200 ° C. or higher can be used.
As described above, according to the semiconductor device 600, the second semiconductor device 620 is bonded to the first semiconductor device 610 with the high melting point solder even if heat treatment such as reflow during mounting on the printed circuit board 13 is performed. Therefore, stable board mounting is possible.

本参考例4にかかる半導体装置700を、図11を参照しながら説明する。なお、第1の実施の形態にかかる半導体装置100と略同一の構成要素については同一符号を付すことで詳細な説明を省略する。   A semiconductor device 700 according to the fourth reference example will be described with reference to FIG. In addition, about the component substantially the same as the semiconductor device 100 concerning 1st Embodiment, detailed description is abbreviate | omitted by attaching | subjecting the same code | symbol.

上記半導体装置100では、第2の半導体装置120は、その裏面が第1の半導体装置110の表面と接着剤115により接合されることにより、第1の半導体装置110に搭載されていた。本参考例4にかかる半導体装置700では、図11に示したように、第2の半導体装置720は、その裏面が第1の半導体装置710の表面と封止樹脂715により接合されることにより、第1の半導体装置710に搭載されることを特徴としている。   In the semiconductor device 100, the second semiconductor device 120 is mounted on the first semiconductor device 110 by bonding the back surface of the second semiconductor device 120 to the front surface of the first semiconductor device 110 with the adhesive 115. In the semiconductor device 700 according to the fourth reference example, as illustrated in FIG. 11, the back surface of the second semiconductor device 720 is bonded to the front surface of the first semiconductor device 710 with the sealing resin 715. The semiconductor device is mounted on the first semiconductor device 710.

第1の半導体装置710は、所定のパターン加工が施され、必要に応じて放熱板702が設けられたエポキシ基板16に、半導体素子1aを接着剤により固着する。そして、半導体素子1a上の電極と、エポキシ基板16とを金属細線15aで接続する。エポキシ基板16はその表面で電気的に導通され、第1の半導体装置710の裏面に形成されたバンプ3と電気的に接続されている。   The first semiconductor device 710 is subjected to a predetermined pattern processing, and the semiconductor element 1a is fixed to the epoxy substrate 16 provided with the heat radiating plate 702 as necessary with an adhesive. And the electrode on the semiconductor element 1a and the epoxy board | substrate 16 are connected with the metal fine wire 15a. The epoxy substrate 16 is electrically connected on the front surface and is electrically connected to the bumps 3 formed on the back surface of the first semiconductor device 710.

第2の半導体装置720は、上記第1の半導体装置710の封止樹脂715の直後の封止樹脂715が凝固しないうちに、この封止樹脂715に接するように載置される。封止樹脂715が凝固すると、第1の半導体装置710と第2の半導体装置720とは、一体となって固着される。
以上のように半導体装置700によれば、第2の半導体装置は、第1の半導体装置の樹脂封止部に直接接着されており、接着剤などの別の固着材は不要であるため、工程の簡略化、コスト低減が可能である。
The second semiconductor device 720 is placed in contact with the sealing resin 715 before the sealing resin 715 immediately after the sealing resin 715 of the first semiconductor device 710 is solidified. When the sealing resin 715 is solidified, the first semiconductor device 710 and the second semiconductor device 720 are integrally fixed.
As described above, according to the semiconductor device 700, the second semiconductor device is directly bonded to the resin sealing portion of the first semiconductor device, and another fixing material such as an adhesive is not necessary. Can be simplified and the cost can be reduced.

以上、添付図面を参照しながら本発明にかかる半導体装置及びその製造方法の好適な実施形態について説明したが、本発明はかかる例に限定されない。当業者であれば、特許請求の範囲に記載された技術的思想の範疇内において各種の変更例または修正例に想到し得ることは明らかであり、それらについても当然に本発明の技術的範囲に属するものと了解される。   The preferred embodiments of the semiconductor device and the manufacturing method thereof according to the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to such examples. It will be obvious to those skilled in the art that various changes or modifications can be conceived within the scope of the technical idea described in the claims, and these are naturally within the technical scope of the present invention. It is understood that it belongs.

実施例1にかかる半導体装置の説明図である。1 is an explanatory diagram of a semiconductor device according to Example 1. FIG. 第1の半導体装置の製造方法の説明図である。It is explanatory drawing of the manufacturing method of a 1st semiconductor device. 第2の半導体装置の製造方法の説明図である。It is explanatory drawing of the manufacturing method of a 2nd semiconductor device. 実施例1にかかる半導体装置の応用例の説明図である。FIG. 10 is an explanatory diagram of an application example of the semiconductor device according to Example 1; 実施例2にかかる半導体装置の説明図である。7 is an explanatory diagram of a semiconductor device according to Example 2. FIG. 実施例3にかかる半導体装置の説明図である。FIG. 10 is an explanatory diagram of a semiconductor device according to Example 3. 参考例1にかかる半導体装置の説明図である。7 is an explanatory diagram of a semiconductor device according to Reference Example 1. FIG. 参考例1にかかる半導体装置の応用例の説明図である。12 is an explanatory diagram of an application example of a semiconductor device according to Reference Example 1. FIG. 参考例2にかかる半導体装置の説明図である。It is explanatory drawing of the semiconductor device concerning the reference example 2. FIG. 参考例3にかかる半導体装置の説明図である。It is explanatory drawing of the semiconductor device concerning the reference example 3. FIG. 参考例4にかかる半導体装置の説明図である。It is explanatory drawing of the semiconductor device concerning the reference example 4. FIG. 従来の半導体装置の説明図である。It is explanatory drawing of the conventional semiconductor device. 従来の半導体装置の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the conventional semiconductor device. 従来の半導体装置の問題点の説明図である。It is explanatory drawing of the problem of the conventional semiconductor device. 従来の半導体装置の問題点の説明図である。It is explanatory drawing of the problem of the conventional semiconductor device.

符号の説明Explanation of symbols

1a、1b:半導体素子
2:配線
3、3b:バンプ
5a、5b:封止樹脂
13:プリント基板
14:配線
15:金属配線
16:エポキシ基板
17:スルーホール
100、200、・・・、700、100’、400’:半導体装置
110、210、・・・、710、110’、410’:第1の半導体装置
120、220、・・・、720:第2の半導体装置
115:接着剤
215:座繰り部
315:低分子接着剤
415:はんだ
515:熱伝導性接着部材
615:高融点はんだ
715:封止樹脂
DESCRIPTION OF SYMBOLS 1a, 1b: Semiconductor element 2: Wiring 3, 3b: Bump 5a, 5b: Sealing resin 13: Printed circuit board 14: Wiring 15: Metal wiring 16: Epoxy board 17: Through hole 100, 200, ..., 700, 100 ', 400': Semiconductor devices 110, 210, ..., 710, 110 ', 410': First semiconductor devices 120, 220, ..., 720: Second semiconductor devices 115: Adhesives 215: Countersink 315: Low molecular adhesive 415: Solder 515: Thermally conductive adhesive member 615: High melting point solder 715: Sealing resin

Claims (10)

第1の半導体装置と、前記第1の半導体装置に接着剤を介して接合され前記第1の半導体装置とは異なる機能を有する第2の半導体装置とで構成された半導体装置であって、
前記第1の半導体装置は、複数のバンプが形成された第1の面を有し、当該複数のバンプが、配線を有するプリント基板の当該配線と接続されるものであり、
前記第2の半導体装置は、複数の端子が形成された第2の面を有し、前記第2の面とは反対側の面が前記第1の半導体装置の前記第1の面に対向するように、前記第1の半導体装置の前記第1の面における前記複数のバンプが形成されていない領域上に接着剤を介して接合されており、当該複数の端子が、前記プリント基板の配線と電気的に接続されるものであり、
前記複数のバンプの高さは前記第2の半導体装置の高さ以上であり、
前記第1の半導体装置の前記バンプと前記第2の半導体装置の前記端子とは、前記プリント基板の前記配線を介して電気的に接続されることを特徴とする半導体装置。
A semiconductor device comprising a first semiconductor device and a second semiconductor device bonded to the first semiconductor device via an adhesive and having a function different from that of the first semiconductor device,
The first semiconductor device has a first surface on which a plurality of bumps are formed, and the plurality of bumps are connected to the wiring of a printed circuit board having wiring.
The second semiconductor device has a second surface on which a plurality of terminals are formed, and a surface opposite to the second surface faces the first surface of the first semiconductor device. As described above, the plurality of bumps on the first surface of the first semiconductor device are joined to each other through an adhesive, and the plurality of terminals are connected to the wiring of the printed circuit board. Are electrically connected,
The height of the plurality of bumps is equal to or higher than the height of the second semiconductor device,
The bump of the first semiconductor device and the terminal of the second semiconductor device are electrically connected via the wiring of the printed circuit board.
請求項1記載の半導体装置において、
前記第2の半導体装置は、前記第2の表面を封止する樹脂部を有し、かつ当該樹脂部を含む外形が切断によって形成された切断面によって規定されていることを有することを特徴とする半導体装置。
The semiconductor device according to claim 1,
The second semiconductor device has a resin portion for sealing the second surface, and an outer shape including the resin portion is defined by a cut surface formed by cutting. Semiconductor device.
請求項1〜2のいずれか一つに記載された半導体装置において、
前記第2の半導体装置の前記複数の端子は、はんだによって前記プリント基板の前記配線に接続されることを特徴とする半導体装置。
In the semiconductor device according to claim 1,
The plurality of terminals of the second semiconductor device are connected to the wiring of the printed circuit board by solder.
第1の半導体装置と、前記第1の半導体装置に接着剤を介して接合され前記第1の半導体装置とは異なる機能を有する第2の半導体装置とで構成された半導体装置であって、
前記第1の半導体装置は、
表面及び裏面を有する基板と、
前記基板の前記表面上に搭載された第1の半導体素子と、
前記第1の半導体素子を封止する樹脂と、
前記基板の前記裏面上に形成され、かつ、プリント基板上の配線と電気的に接続される複数のバンプとで構成され、
前記第2の半導体装置は、
前記プリント基板の前記配線と電気的に接続される複数の端子が形成された面とは反対側の面が前記基板の前記裏面に対向するように、前記基板の前記裏面における前記複数のバンプが形成されていない領域上に接着剤を介して接合された第2の半導体素子を有しており、
前記複数のバンプの高さは前記第2の半導体素子の高さ以上であり、
前記バンプと前記端子とは、前記プリント基板の前記配線を介して電気的に接続されることを特徴とする半導体装置。
A semiconductor device comprising a first semiconductor device and a second semiconductor device bonded to the first semiconductor device via an adhesive and having a function different from that of the first semiconductor device,
The first semiconductor device includes:
A substrate having a front surface and a back surface;
A first semiconductor element mounted on the surface of the substrate;
A resin for sealing the first semiconductor element;
It is formed on the back surface of the substrate, and includes a plurality of bumps that are electrically connected to wiring on the printed circuit board,
The second semiconductor device includes:
The plurality of bumps on the back surface of the substrate are arranged such that the surface opposite to the surface on which the plurality of terminals electrically connected to the wiring of the printed circuit board is opposed to the back surface of the substrate. Having a second semiconductor element joined via an adhesive on the unformed region;
The height of the plurality of bumps is greater than or equal to the height of the second semiconductor element,
The bump and the terminal are electrically connected via the wiring of the printed board.
請求項4記載の半導体装置において、
前記第2の半導体素子は、前記複数の端子が形成された面を封止する樹脂部をを有し、かつ当該樹脂部を含む外形が切断によって形成された切断面によって規定されていることを有することを特徴とする半導体装置。
The semiconductor device according to claim 4.
The second semiconductor element has a resin portion that seals a surface on which the plurality of terminals are formed, and an outer shape including the resin portion is defined by a cut surface formed by cutting. A semiconductor device comprising:
請求項4〜5のいずれか一つに記載された半導体装置において、
前記第2の半導体素子の前記複数の端子は、はんだによって前記プリント基板の前記配線に接続されることを特徴とする半導体装置。
The semiconductor device as described in any one of Claims 4-5 WHEREIN:
The plurality of terminals of the second semiconductor element are connected to the wiring of the printed circuit board by solder.
第1の半導体装置と、前記第1の半導体装置に接着剤を介して接合され前記第1の半導体装置とは異なる機能を有する第2の半導体装置とで構成された半導体装置であって、
前記第1の半導体装置は、
複数の電極が形成された第1の面を有する第1の半導体素子と、
前記第1の面を封止するように前記第1の半導体素子上に形成された樹脂部と、
前記複数の電極上に形成され、かつ、プリント基板上の配線と電気的に接続される複数のバンプで構成され、
前記第2の半導体装置は、
前記プリント基板上の前記配線と電気的に接続される複数の端子が形成された第2の面を有し、前記第2の面とは反対側の面が前記第1の面に対向するように、前記第1の半導体素子における前記複数のバンプが形成されていない領域上に接着剤を介して接合された第2の半導体素子を有しており、
前記複数のバンプの高さは前記第2の半導体素子の高さ以上であり、
前記第1の半導体素子の前記バンプと前記第2の半導体素子の前記端子とは、前記プリント基板の前記配線を介して電気的に接続されることを特徴とする半導体装置。
A semiconductor device comprising a first semiconductor device and a second semiconductor device bonded to the first semiconductor device via an adhesive and having a function different from that of the first semiconductor device,
The first semiconductor device includes:
A first semiconductor element having a first surface on which a plurality of electrodes are formed;
A resin portion formed on the first semiconductor element so as to seal the first surface;
Formed of a plurality of bumps formed on the plurality of electrodes and electrically connected to wiring on the printed circuit board;
The second semiconductor device includes:
A second surface on which a plurality of terminals electrically connected to the wiring on the printed circuit board are formed, and a surface opposite to the second surface faces the first surface; And having a second semiconductor element bonded via an adhesive on a region where the plurality of bumps in the first semiconductor element are not formed,
The height of the plurality of bumps is greater than or equal to the height of the second semiconductor element,
The bump of the first semiconductor element and the terminal of the second semiconductor element are electrically connected through the wiring of the printed board.
請求項7記載の半導体装置において、
前記第2の半導体素子は、前記複数の端子が形成された面を封止する樹脂部を有し、かつ当該樹脂部を含む外形が切断によって形成された切断面によって規定されていることを有することを特徴とする半導体装置。
The semiconductor device according to claim 7.
The second semiconductor element has a resin portion that seals a surface on which the plurality of terminals are formed, and an outer shape including the resin portion is defined by a cut surface formed by cutting. A semiconductor device.
請求項7〜8のいずれか一つに記載された半導体装置において、
前記第2の半導体素子の前記複数の端子は、はんだによって前記プリント基板の前記配線に接続されることを特徴とする半導体装置。
The semiconductor device as described in any one of Claims 7-8,
The plurality of terminals of the second semiconductor element are connected to the wiring of the printed circuit board by solder.
請求項7〜9のいずれか一つに記載された半導体装置において、
前記複数のバンプは、前記第1の半導体素子上に搭載された前記第2の半導体素子を取り囲むように配置されていることを特徴とする半導体装置。
The semiconductor device as described in any one of Claims 7-9,
The plurality of bumps are arranged so as to surround the second semiconductor element mounted on the first semiconductor element.
JP2003369832A 2003-10-30 2003-10-30 Semiconductor device Expired - Fee Related JP4123131B2 (en)

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