JP4191206B2 - Image display system and image display apparatus - Google Patents

Description

  The present invention relates to a video interface mechanism for displaying an image on a display panel. More specifically, the present invention relates to a video interface method for driving a plurality of display panels and high-definition panels in a distributed manner, a driving device, a display device, and the like. .

  In general, a display image is processed by a graphics controller of a host device such as a personal computer (PC) and sent to the display device. However, due to recent advances in display devices represented by liquid crystal display (LCD) panels, there has been a large difference in processing capabilities between host devices and display devices. For example, in the LCD panel, high definition of the panel itself has progressed, and conventional XGA (Extended Graphics Array) (1024 × 768 dots), SXGA (Super Extended Graphics Array) (1280 × 1024 dots), SXGA + (1400 × 1050) Dots), UXGA (Ultra Extended Graphics Array) (1600 x 1200 dots), much higher definition QXGA (Quad Extended Graphics Array) (2048 x 1536 dots) and QSXGA (Quad super Extended Graphics Array) (2560 x 2048 dots) ), High-definition (ultra-high-definition) panels having a very large resolution, such as QUXGA (Quad Ultra Extended Graphics Array) (3200 × 2400 dots), are being put into practical use. These high-definition panels far surpass the limit of definition that can be realized by CRT, so that demand is expected more and more in the future. However, on the other hand, the system power and the power of the graphics controller cannot follow the progress of the panel, and the current situation is that sufficient display on the ultra-high definition panel cannot be performed.

For example, the performance of an image processing system represented by a graphics controller is limited to a general display function of about QXGA, and three-dimensional (3D) computer graphics (CG) represented by a video game console for home use. ) Has a low resolution processing capability of about VGA (Video Graphics Array) (640 × 480 dots). In this way, for example, the state-of-the-art video still has a resolution of about VGA, while the panel can produce resolutions several to several tens of times higher, and the disparity in processing power has become prominent. It was.
In recent years, a display device typified by an LCD panel has a smaller frame around the display portion, and so-called tiling that combines a plurality of panels into an enlarged panel has become possible. As a result, it is possible to further increase the resolution as in the case of the ultra-high definition panel, and the difference from the host side appears more remarkably.

  Furthermore, when displaying video data sent from a host PC (host side) on an ultra-high-definition display panel, if the same frame rate is maintained on the display panel side, the higher the definition, the more video You need to increase the transfer rate on the interface. On the other hand, in recent years, the video interface between the host PC and the display system is changed to a low voltage differential such as LVDS (Low Voltage Differential Signaling), TMDS (Transition Minimized Differential Signaling) and GVIF (Gigabit Video InterFace) instead of the conventional analog interface. A so-called digital interface using an operation type digital data transmission system is becoming widespread. Therefore, it is possible to increase these transfer rates by increasing the transfer clock of the digital interface or by doubling (Dual Channel) or quadruple (Quadruple Channel) the number of video interface signals.

Japanese Patent Laid-Open No. 4-40518 JP 7-146671 A

  However, in the above-described method, every time a new ultra-high-definition display panel appears, it is required to realize a transfer rate required by the display panel. In other words, it is required to define a new video interface timing, develop a new LSI that supports a high transfer clock rate, and adopt a new multiple channel structure for the video interface signal, and at the same time, This means that they must be added to a video interface standard such as VESA (Video Electronics Standard Association). In general, the infrastructure for efficiently promoting these new developments and introductions is not well established at present, which means that there will be a demand for ultra-high-definition display panels in the near future. Nevertheless, it is a major factor that hinders the spread of display systems that use it. As long as you stay on the extension of the conventional video interface, these problems will follow each time, and in order to solve them fundamentally, it is necessary to devise a video interface based on a completely different concept from the conventional video interface. .

The present invention has been made in order to solve the technical problems as described above. The object of the present invention is to transfer a large amount of image data from the host to the display direction and vice versa. It is to realize a small amount of data transfer with maximum efficiency.
Another object is to enable transfer error processing during image transfer and to reduce the amount of data transfer related to transfer errors.

For this purpose, the present invention includes an image display system that includes a host that executes an application, a display connected to the host, and an interface that connects the host and the display, and displays an image on the display. This interface is a first interface that performs a large amount of data transfer from the host to the display, and much less than the capacity of the first interface from the display to the host, but not zero. And a second interface for executing a small-capacity data transfer.
Here, large-capacity data transfer is of the order of 100M to 1G BPS (Byte / Sec) when supported by, for example, SXGA, 8 bits / color, and a refresh rate of 60 Hz, and small-capacity data transfer is at most 1.2K or less. It is about 1.8K BPS. The ratio between the two transfer rates is approximately 100,000: 1 to 1,000,000: 1 in this example.

The first interface transfers data in a packet form, and the second interface transfers data used for error handling for the data transferred through the first interface. it can.
In addition, the host transfers image data before development via the first interface, and the display includes a panel memory for developing the image data transferred via the first interface, The transfer error information for the image data developed in the panel memory can be transferred via the second interface.

Here, the first interface may be constituted by a high-speed unidirectional transfer line, and the second interface may be constituted by a low-speed bidirectional transfer line.
On the other hand, physically, it is possible to configure a second interface by using a part of the first interface. According to this, for example, low-speed bidirectional transfer such as DDC (Digital Data Channel) is possible. It is excellent in that there is no need to have a separate line.
The first interface is composed of a bidirectional high-speed transfer line, and transfers data in synchronization with a high-speed clock signal obtained by multiplying the clock signal. The second interface is the first interface. It is also possible to transfer data in synchronism with a clock signal that is not multiplied with respect to the bidirectional high-speed transfer line used in the above. This is preferable in that a multiplier for data transfer at the second interface can be omitted.

On the other hand, when the present invention is grasped from the image display apparatus, the image display apparatus of the present invention receives a panel for displaying an image and packetized image data from a host executing an application through a large-capacity interface. And receiving means for notifying the host of information indicating a transfer error of the image data received by the receiving means to the host via a small-capacity interface that is much smaller capacity than the large-capacity interface. It is characterized by having prepared.
This notification means includes a case where the notification is read from the host side in response to a request from the host side.

Further provided is a panel memory for expanding the image data received by the receiving means, and the notification means collectively notifies transfer error information in a unit for refreshing the panel using the image data expanded in the panel memory. It is characterized by that.
Further, the notification means notifies the information indicating the transfer error when displaying the still image on the panel, and does not notify the information indicating the transfer error when displaying the moving image on the panel. be able to. With this configuration, a still image that does not need to be transferred from the panel to the display each time refresh is performed can be distinguished from a moving image.

According to the present invention, transfer of image data from the host in the display direction and data transfer in the opposite direction can be realized with high efficiency.
Furthermore, even when transfer error processing is performed during image transfer, the amount of data transfer related to transfer errors can be reduced.

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
FIG. 1 is a block diagram showing an embodiment of an image display system to which the present invention is applied. In the figure, reference numeral 10 denotes a host side composed of a personal computer (PC) or the like, and has a role as a driving device for driving the display device in the present embodiment. On the host side 10, reference numeral 11 denotes a graphics controller, and preprocessing of image data is executed by a preprocessor (not shown) included therein. A graphics memory 16 is used for preprocessing of image data. In this embodiment, since it is not necessary to continue refreshing using the graphics controller 11 by distributed processing, the graphics memory 16 is configured with a smaller capacity than the conventional one. Reference numeral 17 denotes a system bus connected to a host system (not shown) that executes an application. Reference numeral 12 denotes a transmitter that transfers image data received from the graphics controller 11 to the display side 30. Reference numeral 50 denotes a digital interface (digital I / F), such as LVDS or TMDS that transfers image data from the host side 10 to the display side 30. This digital I / F 50 is positioned as a high-speed unidirectional operation type video interface. Reference numeral 60 denotes a control signal line, which is a low-speed bidirectional transfer line such as a DDC (Digital Data Channel). The control signal line 60 is used to send and receive control signals. A DDC handler (not shown) provided in the graphics controller 11 and a DDC controller (shown in the figure) provided in a panel control chip (described later) on the display side 30. (Not shown).

  On the other hand, on the display side 30, 35 is a panel control chip having a post processor (not shown) therein, and a plurality of (four in FIG. 1) according to the number of divisions of the panel 40 that actually displays an image. Is provided. Reference numeral 36 denotes a panel memory provided in each panel control chip 35. Reference numeral 31 denotes a receiver which converts image data transferred via the digital I / F 50 and transfers the converted image data to the panel control chip 35. Reference numeral 40 denotes a panel that actually displays an image. In FIG. 1, the panel is divided into four areas and controlled. The panel 40 is composed of a high-definition panel. In order to support this high-definition screen, the panel control chip 35 enables a plurality of parallel processes.

  The characteristic configuration in the present embodiment is that the graphics controller 11 performs data pre-processing and the panel control chip 35 performs post-processing. As a result, the screen generation job on the host side 10 such as mixing image data and refreshing the screen, which has been performed by the graphics controller 11 until now, is transferred to the display device side (display side 30). That is, the graphics controller 11 attaches a tag or image data attribute and error protection to the image data before the development of the image data, that is, the image data before mixing, and the panel control chip 35 first supplies the image data to the panel memory 36. That is, it is decompressed, mixed with image data, and transferred to a refresh circuit (not shown).

Here, in this embodiment, the concept of window is introduced. This window is an area that is meaningful on the image space that the host is aware of, and is a unit of image data transfer processing.
FIG. 12 is an explanatory diagram briefly explaining an example of a transfer method of image data using a packet used in the present embodiment in relation to the above-described window. Assume that an area A and an area B exist as image images by the host application. In the present embodiment, image development work is not performed on the host side 10, and image development work is performed on the display side 30. On the host side 10, for example, a window ID: 4 is set for the area A, and a window ID: 5 is set for the area B. The transfer of the image information to the display side 30 is performed for each area by a packet method. More specifically, in response to a display enable signal, the image signal is transferred in packets in units of areas belonging to a sub-area (described later) such as for each scan. This sub-area may be a rectangular area composed of predetermined pixels. ID information indicating a window ID is added to the image signals by these packets and transferred. For example, if each handler (not shown) in a specific sub-panel is set to process window ID: 4 and window ID: 5, the image information transferred by the packet method and assigned with the window ID is designated. It becomes possible to expand on the sub-panel.

  Here, the bus protocol itself for packetizing and transferring data has been widely adopted to date. A typical example is a serial bus standard defined by the IEEE 1394 standard. This is a connection mode between two PCs or peripheral devices using two twisted pair operation signal lines, and bidirectional transfer of packetized data is half duplex (Half Duplex) communication mode. (A mode in which data transfer is performed only from one of the nodes in the same time zone). It is also possible to extend the basic connection between these two nodes to a cascade (chain connection) type or a tree type to configure a network that spans multiple nodes and transfer data from each node to another node. is there.

However, the packet transfer according to IEEE 1394 assumes an interface in which the data transfer amount in each direction is equal, and therefore the average transfer rate in one direction cannot be increased to the physical limit of the bus. For example, bus arbitration is always required before starting the transfer. Also, in asynchronous transfer (Asynchronous Subaction), which is a typical transfer mode of IEEE 1394, after arbitration, a certain bus master that has acquired a bus transfers an asynchronous packet (Asynchronous Packet) to a bus target that is a slave, and then a certain amount of The Acknowledge Packet must be read back after the time gap. For this reason, the average data transfer rate from the same bus master is lowered.
On the other hand, in the synchronous transfer (Isochronous Subaction), which is another transfer mode, the acknowledge packet is not read back after the bus master sends out the synchronous packet after arbitration, but conversely, any acknowledge packet is also read back. It is not possible to grasp the error situation described later.

Data transfer from the host side 10 toward the display side 30 is now considered when video data is transferred from the PC system or the like on the host side 10 to the display side 30 (or a group of connected display panels). Will be enormous. On the other hand, the data transfer from the display side 30 to the host side 10 (data read from the host side 10) has a display ID, a data transfer error status check, etc., and is generally much smaller than the former. However, 0 is not a good translation.
In the present embodiment, in order to cope with such a problem, it is possible to realize a large-capacity data transfer from the host side 10 to the display side 30, and to efficiently transfer data in the opposite direction with a small capacity. Provides a packet-based video interface.

FIG. 2 is a block diagram illustrating one embodiment of the physical configuration of the video interface.
On the host side 10, the transmitter 12 is provided with a serializer (Encoder / Serializer) 13 and a PLL (Phase Locked Loop) 14. The serializer 13 converts the image data from parallel to serial and passes it to the digital I / F 50. The PLL 14 forms a multiplication clock for parallel-serial conversion of image data.
On the display side 30, the receiver 31 is provided with a deserializer (Decoder / Deserializer) 32 and a PLL 33. The deserializer 32 converts the image data from serial to parallel. The PLL 33 forms a multiplication clock for serial-parallel conversion of image data.

The digital I / F 50 includes a unidirectional high-speed transfer line 51 and a unidirectional transfer line 52. The unidirectional transfer line 52 transfers a clock signal output from the host side 10. The unidirectional high-speed transfer line 51 includes a plurality of data signal lines, and transfers image data output from the host in synchronization with a clock transferred from the unidirectional transfer line 52.
On the other hand, the control signal line 60 includes a bidirectional low-speed transfer line 61 and a clock signal line 62. Panel ID information, error information, and the like are transferred from the display side 30 to the host side 10 via the bidirectional low-speed transfer line 61.

FIG. 3 is a block diagram showing another example of the physical configuration of the video interface. This physical configuration feature is used for data transfer from the display side 30 to the host side 10 by making only the data lines of the unidirectional operation type video interface such as LVDS and TMDS bidirectional. This point is different from the configuration shown in FIG. 1 and FIG. 2R> 2.
The host side 10 is provided with a transceiver 19, and the display side 30 is provided with a transceiver 39. The digital I / F 55 includes two or more bidirectional high-speed transfer lines 57 in addition to the unidirectional high-speed transfer line 56. At this time, the clock signal line 65 remains unidirectional and is used to generate a high-speed clock signal by multiplying the clock signal by the PLL 14 or PLL 33. The bidirectional high-speed transfer line 57 transfers parallel-serial converted image data from the host side 10 to the display side 30 at a high-speed clock rate synchronized with the multiplied clock. For data transfer such as panel ID information and error information from the display side 30 to the host side 10, the clock signal is fed back to one of the bidirectional high-speed transfer lines 57 as it is, and the data to be read is sent to the other bidirectional data. It can be executed by placing it on the high-speed transfer line 57. The graphics controller 11 includes a latch 15 that latches status information read from the display side 30 to take timing. The display side 30 is also provided with a latch 34 for latching status information read from the host side 10.

  Thus, in the video interface shown in FIG. 3, it is necessary to partially extend the conventional operation type interface bidirectionally. However, it is characterized in that a low-speed bidirectional transfer line such as DDC is not required. Normally, when such an operational interface is simply bidirectionalized, the clock line is also bidirectional, and two types of PLLs are required in each direction to create a multiplied clock for parallel-serial conversion of data. It becomes. However, in the present embodiment, it is assumed that the data transfer amount from the display side 30 to the host side 10 is extremely small compared to the opposite direction. Therefore, one of the data lines (digital I / F 55) is used to feed back the clock signal from the host side 10 to the display side 30 and the data to be transferred to the other data line from the display side 30 toward the host side 10 Is on. With this configuration, it is not necessary to make the clock signal line 65 bidirectional, and there is no need to provide a clock source on the display side 30 to serve as a bus master, and data transfer from the display side 30 to the host side 10 can be performed. The host side 10 can perform the read control as a bus master. In addition, since the amount of data in the direction from the display side 30 to the host side 10 is small, there is no need for parallel-serial conversion of data and no extra PLL is required for transfer in this direction.

Note that the data transfer rate from the host side 10 to the display side 30 varies depending on the resolution of the video interface up to which panel the video interface has in real time. Now, assuming that SXGA (1280 x 1024 dots), 8-bit / color panel can be supported at a refresh rate of 60 Hz,
R, G, B 8 bits each → 24 bits Pixel clock 110-120 MHz
So,
24 × 110M / 8 = 330MBPS (Byte / Sec)
24 × 120M / 8 = 360MBPS
Therefore, it is about 330M to 360 MBPS.
In general, the order is about 100M to 1GBPS.

On the other hand, the transfer from the display side 30 to the host side 10 is only confirmation of the error status in the present embodiment, and for each transfer for one window, 1 bit is used for the first mechanism described later, and 5 is used for the second mechanism. -10 bytes. Even if other information is read out, it is about 20 to 30 bytes per frame (60 Hz) refresh. Therefore,
20 x 60 = 1200
30 × 60 = 1800
It is about 1.2K to 1.8K BPS.
For that reason, the ratio between the two transfer rates is about
100,000: 1 to 1 million: 1
It becomes. According to the present embodiment, it is possible to cope with these large-capacity and small-capacity data transfers.

4A and 4B are explanatory diagrams showing an example of a logical configuration (format) of data transfer in the present embodiment. In the present embodiment, packetization is adopted as image data transfer using the digital I / F 50 or 55 in the direction from the host side 10 to the display side 30.
In FIG. 4A, in synchronization with the clock transferred to the unidirectional transfer line 52, the packet enable signal 70 and packetized packet data 71 are transmitted in the unidirectional high-speed transfer lines 51 and 56 and the bidirectional high-speed transfer line 57. Is transferred. In the TMDS specification, a total of 30 bits, 10 bits each for R / G / B, can be transferred. In conventional video data transfer, R (Red) / G (Green) / B (Blue) video data and vertical synchronization (V-sync), horizontal synchronization (H-sync), DE signal indicating data valid, and The other two control signals were serialized and sent. In the present embodiment, using this TMDS specification, 1 bit is secured as a packet enable signal 70 and 24 bits are secured as packet data 71. This packet enable signal 70 indicates a valid packet period of the packet data 71. By using this packet enable signal 70, it becomes possible to transfer packet data 71 of indefinite length having a non-uniform length.

  One packetized packet data 71 includes a header part 72, a body part 73, and a footer part 74. The header portion 72 is provided with a sub area address field (Sub Area Addr Field) 75. Further, the header portion 72 has a start transfer bit (Start Transfer Bit) 79 for identifying whether or not it is a re-transfer and a sync data bit (Sync Data Bit) 80 for indicating a new frame. Have. Moreover, it is possible to indicate that the video is a moving image by using these bits and adding other bits. For example, it is possible to configure so as to omit error processing to be described later by indicating that it is a moving image. The body part 73 has a video data area 76 and an attribute area 77 to which image data is actually transferred. In the present embodiment, as described above, a window that is a meaningful area is defined in the image space conscious of the application on the host side 10 and image data can be transferred in units of the window. It is configured. That is, the image data transferred in the video data area 76 is transferred as, for example, a line unit within a range defined by the window. Further, the attribute area 77 stores address information of a finer sub area (described later), information on the range of the video data in the sub area, scaling factor, and the like.

Here, the sub-area is an area obtained by equally dividing the entire display area of the panel 40 into a certain size, and is a unit that can process an end bit (Comp Bit), which will be described later, when performing error detection. The sub area which is the processing unit is one line unit or one rectangular area unit, and the transfer video data included in one packet is transfer data for display of any one of these sub areas. That is, the maximum number of video data transmitted in one packet is for all pixels in one sub-area, and the minimum number is for one pixel.
The footer unit 74 also includes a transfer error check / correction field (Transfer Error Checking) for checking transfer errors using parity bits, ECC (Error Checking Correcting), and cyclic redundancy check (CRC). / Correcting Field) 78.

  FIG. 4B shows in further detail the structure of the body part 73 and the footer part 74 shown in FIG. In the present embodiment, as shown in FIG. 4B, for example, 24 horizontal parity bits are used as the transfer error check / correction field 78. The video data is divided in units of 24 bits, and a horizontal parity bit is generated by taking an exclusive OR at the same place in each word, and compared with the transfer error check / correction field 78 (Compare). The parity error of the entire video data is output by taking the logical sum of these 24 bits.

Next, the first error handling mechanism in the present embodiment will be described with reference to FIGS. 4A and 4B and FIGS.
In this first mechanism, one line is used as a unit as a sub-area which is a unit for detecting a transfer error.
FIG. 5 shows an example of transfer error processing in the aforementioned format. Reference numeral 90 is a frame buffer memory, and 91 is a window area. The frame buffer memory 90 is physically provided in the panel memory 36 described above. Here, since the logical configuration is described, the frame buffer memory 90 is used for description. Reference numeral 93 denotes an end bit (Comp Bit), which is provided for each sub-area, and is provided for each line in the example of FIG. An AND circuit 94 is configured to output OFF (= LOW) when there is even one sub-area that is not normally terminated. Reference numeral 95 denotes a panel end bit (Panel Comp Bit). The panel end bit 95 is read from the host side 10. In other words, in the present embodiment, a status bit (end bit 93) corresponding to each subarea and indicating the normal end of data transfer to that subarea is provided, and an AND of outputs from all end bits 93 is taken. A status bit (panel end bit 95) indicating the normal end of data transfer as the entire display area is used. The default value of each end bit 93 after power ON reset is ON (= High).
FIG. 6 is an explanatory diagram showing a case where a parity error occurs after the window area 91 is transferred, and the structure of each code is the same as FIG.
FIG. 7 is an explanatory diagram showing a state in which the re-transfer sequence is performed, and the structure of each symbol is the same as that in FIGS.

  First, in order to update the display of a rectangular area (window area 91) with a display, the host side 10 starts transferring video data. At this time, since the sub area group in the minimum range that covers the area is determined, packet data 71 that is packetized in order for each sub area is sequentially transferred. Based on the subarea address field 75 in the header portion 72 of each packet data 71, the display side 30 determines to which subarea the transfer is made, and writes the data to the corresponding frame buffer memory 90.

  When the first packet in the window area 91 to be transferred is transferred, the start transfer bit 79 and the sync data bit 80 in the header portion 72 are turned ON. The sync data bit 80 is used to detect that the first sub-area of the window area 91 has been sent on the display side 30 and to synchronize. The display side 30 also refers to the sub-area address field 75 of the packet data 71 to determine which sub-area the video data sent is for. Further, it is detected that the start transfer bit 79 is ON, and the end bit 93 corresponding to this subarea is turned OFF (= Low). Next, the video data included in the body portion 73 of the packet is written into the frame buffer memory 90 corresponding to the sub area. At the same time, it is determined from the value of the video data and the value of the transfer error check / correction field 78 whether or not a transfer error that cannot be corrected has occurred by a parity check, CRC, or ECC technique. If a transfer error that cannot be corrected does not occur, the end bit 93 is turned ON again. When this uncorrectable transfer error occurs, the end bit 93 is left OFF.

  In the second and subsequent packet transfers in the window area 91, the transfer is performed with the start transfer bit 79 turned on and the sync data bit 80 turned off. As in the first case, the sub-area address field 75 of the packet data 71 is referred to and it is determined to which sub-area the transmitted video data is. Then, it is detected that the start transfer bit 79 is ON, and the end bit 93 corresponding to this subarea is turned OFF (= Low). Next, the video data included in the body portion 73 of the packet data 71 is written into the frame buffer memory 90 corresponding to the sub area. At the same time, it is determined whether or not an uncorrectable transfer error has occurred from the value of the video data and the value of the transfer error check / correction field 78. If this uncorrectable transfer error has not occurred, the end bit 93 is set. Turn on again. When this uncorrectable transfer error occurs, the end bit 93 is left OFF.

Thereafter, when all packets for the window area 91 have been sent, the panel end bit 95 on the display side 30 is checked from the host side 10.
If the checked panel end bit 95 is ON, it is considered that all packet transfers have been completed without error, and the host side 10 ends the transfer sequence of this window area 91.
If the checked panel end bit 95 is OFF, it is assumed that a transfer error has occurred in some sub-area, and the re-transfer sequence of this window area 91 is started.

In the retransfer sequence, the start transfer bit 79 is turned OFF in all packets. When a packet is transferred, the sub-area address field 75 is referred to determine to which sub-area the transmitted video data is, and it is detected that the start transfer bit 79 is OFF. Thus, the end bit 93 corresponding to this subarea is not changed.
Next, when the end bit 93 is OFF, the video data included in the body portion 73 of the packet data 71 is written into the frame buffer memory 90 corresponding to the sub area. At the same time, it is determined whether or not a transfer error that cannot be corrected has occurred from the value of the video data and the value of the transfer error check / correction field 78, and if not, the end bit 93 is turned ON. If it occurs, the end bit 93 remains OFF.
When the end bit 93 is ON, the video data included in the body part 73 of the packet data 71 is not written to the frame buffer memory 90. Further, the result of the transfer error is not reflected on ON / OFF of the end bit 93 but is ignored.
When all the packet transfers of the retransfer sequence are completed, the panel end bit 95 on the display side 30 is checked again from the host side 10. If the checked panel end bit 95 is ON, it is considered that all packet transfers have been completed without error, and the host side 10 ends the transfer sequence of this window area 91. If the panel end bit 95 is OFF, the retransfer sequence is repeated again.

The flow of the error check and retransmission sequence described above will be described again using a specific example.
In FIG. 5, it is assumed that the sub-area is one line of the display screen as described above. In this example, the entire display area of the display has a resolution of QXGA (2048 × 1536 dots). The frame buffer memory 90 assumes the entire display area on the display side 30, and here has the first line to the 1536th line in the vertical direction and the first line to the 2048th column in the horizontal direction. It is assumed that the window area 91 to be displayed is a rectangular area whose vertical direction is from the 101st line to the 500th line and whose horizontal direction is from the 1001st line to the 1500th line. The first packet for video data transfer in this window area 91 is transferred for the 101st line, the second packet is transferred for the 102nd line, and the last 400th packet is for the 500th line. At this time, the video data included in the body portion 73 of each packet data 71 is for 500 pixels from the 1001st column to the 1500th column.

FIG. 6 shows a case where a parity error occurs after the window area 91 is transferred.
Now, in these 400 packet transfers, it is assumed that a parity error has occurred during the transfer of the 10th packet (110th line) and the 100th packet (200th line). Then, at the end of the 10th packet transfer, the end bit 96 for the 110th line is set to “0” (OFF). Further, the end bit 97 for the 200th line is set to “0” (OFF) at the end of the 100th packet transfer. Thus, when the host side 10 reads the panel end bit 95 after the end of the last 400th packet, OFF (= Low) can be read.

FIG. 7 shows a state in which the retransmission sequence is performed.
Recognizing that the panel end bit 95 is OFF (= Low), the host side 10 starts a re-transfer sequence for the same window area 91. In this retransmission sequence, 400 packets from the 101st line to the 500th line are sent again, but it is detected that the end bit 93 is already ON in the packets other than the 110th line and the 200th line. Thus, the frame buffer memory 90 is not overwritten. “X” in FIG. 7 indicates that the overwriting is not performed. Only when two packets for the 110th line and the 200th line are transferred, it is detected that the end bits 96 and 97 are OFF, and the corresponding frame buffer memory 90 is overwritten. If no parity bit is generated at the time of transferring these two packets, all the end bits 93 are turned ON, and the panel end bit 95 is also turned ON. Accordingly, when the host side 10 reads the panel end bit 95 after completion of the last 400th packet transfer in the retransfer sequence, ON (= High) can be read, and thus all transfer sequences for this window area 91 are completed.

In the first mechanism described with reference to FIGS. 5 to 7, one end bit 93 is provided for each subarea of each line of the frame buffer memory 90. It is possible to provide an end bit 93 corresponding to.
According to the first mechanism described above, the error information read by the host side 10 is only 1 bit for each window area transfer, and the interface from the display side 30 to the host side 10 can have a small capacity. Is possible.

Next, the second error handling mechanism in the present embodiment will be described with reference to FIGS. 4A and 4B and FIGS. In this second mechanism, sub-areas, which are units for detecting transfer errors, are divided vertically and horizontally into several bits × several bits, and error handling and retransmission of packets transferred in that unit are performed.
FIG. 8 is a diagram illustrating another example of transfer error processing. In the figure, 99 is a sub-area, and this sub-area 99 is assumed to be a small rectangular area of horizontal 64 pixels × vertical 32 pixels. Reference numeral 100 denotes a window area. Reference numeral 101 denotes an error address register including address information that can identify a packet. Reference numeral 102 denotes a pointer register indicating the number of errors.
FIG. 9 shows a state where a transfer error has occurred when the window area 100 is transferred.
FIG. 10 shows a state in which a new transfer error has occurred when performing retransfer.
FIG. 11 shows a state in which transfer is performed again and the transfer sequence ends.

  As shown in FIG. 8, on the display side 30, a plurality of registers (M: # 0 to # (M−) are stored in the error address register 101 for storing address information and the like of the subarea 99 in which the transfer error has occurred. 1)) It is provided. This M (Max value) is arbitrarily determined in consideration of an error rate in the system system including the host side 10 and the display side 30. The error address register 101 is generally a packet number, but any error number register can be used as long as it can identify the packet. Further, a pointer register 102 that represents pointers to these registers and is incremented by the number of address information stored in the error address register 101 is provided. The pointer register 102 has a default value of “0” after power-on reset.

  When the host side 10 starts to transfer video data in order to update the display of the window area 100 on the display side 30, the minimum unit subarea group covering the window area 100 is determined. And packet data transfer is executed in sequence. Based on the subarea address field 75 in the header portion 72 of each packet data 71, the display side 30 determines to which subarea 99 the transfer is made, and writes the image data in the corresponding frame buffer memory 90.

  At the time of the first packet transfer in the window area 100 to be transferred, the start transfer bit 79 and the sync data bit 80 in the header portion 72 are turned ON. The sync data bit 80 is used to detect that the first sub-area 99 of the window area 100 has been sent on the display side 30 and to synchronize. The display side 30 also detects that the start transfer bit 79 is ON, and initializes the value of the pointer register 102 to “0”. Thereafter, with reference to the sub-area address field 75 of the packet data 71, it is determined to which sub-area 99 the transmitted video data corresponds. Then, the video data included in the body portion 73 of the packet is written into the frame buffer memory 90 corresponding to the sub area 99. At the same time, it is determined from the value of the video data and the value of the transfer error check / correction field 78 whether an uncorrectable transfer error has occurred. If this occurs, for example, the address value of the subarea 99 is recorded in the error address register 101 indicated by the pointer register 102, and the value of the pointer register 102 is incremented by one. If no uncorrectable transfer error occurred, nothing is done.

  In the second and subsequent packet transfers in the window area 100, the start transfer bit 79 and the sync data bit 80 are turned OFF for transfer. As in the first case, the sub-area address field 75 of the packet data 71 is referred to determine to which sub-area 99 the transmitted video data is, and the body portion 73 of the packet data 71 is determined. Is written in the frame buffer memory 90 corresponding to the sub-area. At the same time, it is determined from the value of the video data and the value of the transfer error check / correction field 78 whether an uncorrectable transfer error has occurred. When this occurs, it is determined whether or not the value of the pointer register 102 is equal to or less than M (Max value). If it is equal to or less than M, for example, the address value of the subarea 99 is recorded in the error address register 101 indicated by the pointer register 102, and the value of the pointer register 102 is incremented by one. If the value of the pointer register 102 is M, or if an uncorrectable transfer error has not occurred, nothing is done.

Here, it is assumed that the value of the pointer register 102 at the time when all the packets in the window area 100 have been sent is P (0 ≦ P ≦ M). From the host side 10, the value of the pointer register 102 on the display side 30 is checked.
If the checked value P is P = 0, it is considered that the transfer of all the packets in the window area 100 has been completed without error, and the host side 10 ends the transfer sequence of the window area 100. .
If the checked value P is P ≠ 0, the host side 10 determines that a transfer error has occurred in some subarea 99, and from # 0 (first) to # ( The error address registers 101 up to (P-1) (Pth) are read, and the retransfer sequence of this window area 100 is started.

The retransmission sequence is performed according to the following procedure.
i) In the case of P <M, the host side 10 sends to the display side 30 only packets for P sub-areas 99 indicated by the value of the error address register 101 from # 0 to # (P-1). Transfer sequentially.
ii) In the case of P = M, the host side 10 adds # (P--) in addition to the P sub-areas 99 indicated by the value of the error address register 101 from # 0 to # (P-1). The packets are sequentially transferred to the display side 30 for all sub-areas 99 in the window area 100 having a value larger than the value of the error address register 101 of 1).

  At the time of the first packet transfer in the window area 100 to be transferred, the start transfer bit 79 in the header portion 72 is turned ON. At this time, the sync data bit 80 is OFF. The display side 30 detects that the start transfer bit 79 is ON, and initializes the value of the pointer register 102 to “0”. Thereafter, the video data is written into the frame buffer memory 90 corresponding to the sub area 99 indicated by the sub area address field 75. At the same time, when an uncorrectable transfer error occurs, the address value of the subarea 99 is recorded in the error address register 101 indicated by the pointer register 102, and the value of the pointer register 102 is incremented by one. If no uncorrectable transfer error occurred, nothing is done.

  When the second and subsequent packets are transferred, the start transfer bit 79 in the header portion 72 is turned OFF. Similarly, the display side 30 writes the video data to the frame buffer memory 90 corresponding to the sub area 99 indicated by the sub area address field 75. At the same time, when an uncorrectable transfer error occurs, the address value of the subarea 99 is recorded in the error address register 101 indicated by the pointer register 102, and the value of the pointer register 102 is incremented by one. If no uncorrectable transfer error occurred, nothing is done.

Let P (0 ≦ P ≦ M) be the value of the pointer register 102 when all the packets of the retransfer sequence have been sent. The host side 10 checks the value of the pointer register 102 on the display side 30.
If the checked value P is P = 0, it is considered that all packet transfers in this window area 100 have been completed without error, and the host side 10 ends the transfer sequence of this window area 100. To do.
If the checked value P is P ≠ 0, the host side 10 determines that a transfer error has occurred in some subarea 99, and from # 0 to # (P-1). The error address register 101 is read, and the above retransfer sequence is repeated again.

The processing flow of the error check and re-transfer sequence described above will be specifically described mainly with reference to FIGS.
As in the case described with reference to FIG. 5, the entire display area of the panel 40 in the second error handling mechanism shown in FIG. 8 has a resolution of QXGA (2048 × 1536 dots). Since the sub-area 99 is a small rectangular area of 64 pixels wide × 32 pixels vertical as described above, the entire display area is divided into a total of 1536 sub-areas 99 of 32 horizontal and 48 vertical. There are four error address registers 101, # 0 to # 3.

  As shown in FIG. 8, the window area 100 to be displayed now starts from the eighth sub-area from the left in the horizontal direction and the twelfth sub-area from the top in the vertical direction (the sub-area of (8, 12) in coordinate expression). It is assumed that it is covered by a rectangular area composed of 100 sub-areas 99 from the 17th from the left in the horizontal direction and the 21st subarea from the top in the vertical direction (the subarea of (17, 21) in coordinate expression). That is, the first packet (packet # 1) for video data transfer in the window area 100 is a subarea 99 of coordinates (8, 12), and the second packet (packet # 2) is coordinates (9, This is a subarea 99 of 12). The final 100th packet is a sub-area 99 with coordinates (17, 21).

  As shown in FIG. 9, in the transfer of these 100 packets, the 10th packet (coordinate (17,12) subarea), the 20th packet (coordinate (17,13) subarea), the 30th packet are now transferred. It is assumed that a parity error has occurred during each transfer of the packet (the sub area of coordinates (17, 14)) and the 90th packet (the sub area of coordinates (17, 20)). At the time of the last 100th packet transfer, the value of the pointer register 102 is “4”. This value is read by the host side 10, and subsequently the values of the four error address registers 101 of # 0 to # 3 are read.

  Since the value of the pointer register 102 read into the host side 10 is not “0”, a retransfer sequence is started for the same window area 100. In this retransfer sequence, first, of the 100 subareas 99 that cover the window area 100, four subareas 99 indicated by the read value of the error address register 101 are written into the frame buffer memory 90. Along with these four subareas 99, image data corresponding to all the subareas 99 after the subarea 99 indicated by # 3 of the error address register 101 are transferred in packets and written into the frame buffer memory 90. This is because the value of the read error address register 101 is the MAX value (= 4), and therefore a parity error may occur in the sub-area 99 after # 3.

  As shown in FIG. 10, in this retransmission sequence, it is assumed that a parity error has occurred during the transfer of two subareas at coordinates (10, 21) and coordinates (15, 21). At the end of the last packet transfer, the value of the pointer register 102 is 2. The host side 10 reads this value, and subsequently reads the value of the error address register 101 of # 0 to # 1.

  Since the value of the pointer register 102 read by the host side 10 is not “0” again, the re-transfer sequence is started again for the same window area 100. This time, of the 100 subareas 99 covering the window area 100, the image data of the portion corresponding to the two subareas 99 indicated by the read value of the error address register 101 is packet (two). And is written to the corresponding frame buffer memory 90. At this time, since the value of the read pointer register 102 is “2” and not the maximum value “4”, it is determined that the transfer parity error has occurred only twice.

  As shown in FIG. 11, it is assumed that no parity error has occurred once in this retransmission sequence. At this time, the value of the pointer register 102 remains “0” even at the end of the final second packet transfer. This value is read by the host side 10 and is “0”, so the transfer sequence for this window area 100 is completed.

  According to this second mechanism, it is not necessary to have an end bit 93 for each subarea as in the first mechanism described above, and logic consumption can be prevented. Further, it is excellent in that it is not necessary to transfer packets for all window areas again in the retransfer sequence, and it is only necessary to execute retransfer to the subarea 99 in which a transfer error has occurred.

As described above, according to the present embodiment, it is possible to optimize the video interface mechanism when performing distributed processing of display images on the host side 10 and the display side 30. Therefore, it is possible to solve problems such as a so-called tiled display that uses a plurality of panels as an enlarged display or a display composed of an ultra-high-definition panel.
Further, even when video data is transferred between the host side 10 and the display side 30 using the packet format, error processing can be efficiently executed.

1 is a block diagram showing an embodiment of an image display system to which the present invention is applied. It is a block diagram which shows one Embodiment of the physical structure in a video interface. It is a block diagram which shows another example in the physical structure of a video interface. (a), (b) is explanatory drawing which shows an example of the logical structure (format) of the data transfer in this Embodiment. It is a figure which shows an example of the transfer error process in the above-mentioned format. It is explanatory drawing which shows the case where the parity error after window area 91 transfer has arisen. It is explanatory drawing which shows the state which implemented the re-transfer sequence. It is a figure which shows another example of a transfer error process. It is the figure which showed the state which the transfer error produced when transferring the window area | region 100 in another example. It is a figure which shows the state in which the new transfer error produced when retransfer in another example was implemented. It is the figure which showed the state which implements transfer again in another example, and a transfer sequence is complete | finished. It is explanatory drawing which demonstrated simply an example of the transfer method of the image data using the packet used in this Embodiment regarding the above-mentioned window.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Host side, 11 ... Graphics controller, 12 ... Transmitter, 13 ... Serializer, 14 ... PLL, 15 ... Latch, 16 ... Graphics memory, 17 ... System bus, 19 ... Transceiver, 30 ... Display side, 31 ... Receiver, 32 ... Deserializer, 33 ... PLL, 34 ... Latch, 35 ... Panel control chip, 36 ... Panel memory, 39 ... Transceiver, 40 ... Panel, 50 ... Digital I / F, 51 ... Unidirectional high-speed transfer line , 52 ... Unidirectional transfer line, 55 ... Digital I / F, 56 ... Unidirectional high speed transfer line, 57 ... Bidirectional high speed transfer line, 60 ... Control signal line, 61 ... Bidirectional low speed transfer line, 62 ... Clock signal line , 65 ... clock signal line, 70 ... packet enable signal, 71 ... packet data, 72 ... header part, 73 ... body part, 74 ... footer part, 75 ... Barea address field, 76 ... Video data area, 77 ... Attribute area, 78 ... Transfer error check / correction field, 79 ... Start transfer bit, 80 ... Sync data bit, 90 ... Frame buffer memory, 91 ... Window area, 93 ... End bit, 95 ... Panel end bit, 96, 97 ... End bit, 99 ... Sub-area, 100 ... Window area, 101 ... Error address register, 102 ... Pointer register

Claims (6)

An image display system that includes a host that executes an application, a display connected to the host, and an interface that connects the host and the display, and displays an image on the display.
The interface is
A first interface for performing large-capacity data transfer from the host to the display at a first speed ;
For executing a data transfer of a small capacity that is much smaller than the capacity of the first interface but not zero from the display to the host at a second speed that is slower than the first speed. A second interface,
The first interface packetizes and transfers data, is configured with a bidirectional high-speed transfer line, and transfers data in synchronization with a high-speed clock signal multiplied by a clock signal,
The image display system, wherein the second interface transfers data in synchronization with a clock signal that is not multiplied with respect to the bidirectional high-speed transfer line used for the first interface .   The image display system according to claim 1, wherein the second interface transfers data used for error processing with respect to the data transferred via the first interface. The host transfers image data before development via the first interface,
The display includes a panel memory for expanding the image data transferred via the first interface, and information on transfer errors for the image data expanded on the panel memory is displayed on the second interface. The image display system according to claim 1, wherein the image display system transfers the data via the image display system. Said first interface, together configured to include a high-speed unidirectional transfer line,
The image display system according to claim 1, wherein the second interface includes a low-speed bidirectional transfer line. A panel for displaying images,
Receiving means for receiving packetized image data from a host executing an application through a high- speed interface of a first speed ;
The information indicating the transfer error of the image data received by the receiving means is transmitted through the interface of the second speed slower than the first speed of the small capacity that is much smaller capacity than the interface of the large capacity. Notification means for notifying the host ,
The notifying means notifies the information indicating the transfer error when displaying a still image on the panel, and does not notify the information indicating the transfer error when displaying a moving image on the panel. An image display device. A panel memory for expanding the image data received by the receiving means;
6. The image display apparatus according to claim 5 , wherein the notifying unit collectively notifies transfer error information in a unit for refreshing the panel using the image data expanded in the panel memory.

Images