JP4190518B2 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- JP4190518B2 JP4190518B2 JP2005183851A JP2005183851A JP4190518B2 JP 4190518 B2 JP4190518 B2 JP 4190518B2 JP 2005183851 A JP2005183851 A JP 2005183851A JP 2005183851 A JP2005183851 A JP 2005183851A JP 4190518 B2 JP4190518 B2 JP 4190518B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Bipolar Transistors (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
本発明は、シリコンから成る実装基板に半導体素子が設けられた半導体装置、およびこれに用いられたシリコンから成る実装基板に関する。 The present invention relates to a semiconductor device in which a semiconductor element is provided on a mounting substrate made of silicon, and a mounting substrate made of silicon used therein.
一般的にシリコン基板上にトランジスタ素子が形成された半導体装置は、図5に示すような構成が主に用いられる。1はシリコン基板、2はシリコン基板1が実装される放熱板等のアイランド、3はリード端子、及び4は封止用の樹脂モールドである。 In general, a semiconductor device in which a transistor element is formed on a silicon substrate mainly has a configuration as shown in FIG. 1 is a silicon substrate, 2 is an island such as a heat sink on which the silicon substrate 1 is mounted, 3 is a lead terminal, and 4 is a resin mold for sealing.
シリコン基板11に形成されるトランジスタ素子は、図6に示すように、例えば、N型シリコン基板11にコレクタ領域となるN型のエピタキシャル層12にボロン等のP型の不純物を拡散してベース領域13が形成され、そのベース領域13内にリン等のN型の不純物を拡散してエミッタ領域14が形成される。シリコン基板11の表面にベース領域13、エミッタ領域14の一部を露出させる開口部を有した絶縁膜15が形成され、その露出されたベース領域13、エミッタ領域14上にアルミニウム等の金属が蒸着されベース電極16、エミッタ電極17が形成される。このような構成のトランジスタではシリコン基板がコレクタ電極18となる。 As shown in FIG. 6, the transistor element formed on the silicon substrate 11 has a base region formed by diffusing a P-type impurity such as boron into an N-type epitaxial layer 12 serving as a collector region in the N-type silicon substrate 11, for example. 13 is formed, and an emitter region 14 is formed by diffusing N-type impurities such as phosphorus in the base region 13. An insulating film 15 having openings for exposing portions of the base region 13 and the emitter region 14 is formed on the surface of the silicon substrate 11, and a metal such as aluminum is deposited on the exposed base region 13 and emitter region 14. Then, the base electrode 16 and the emitter electrode 17 are formed. In the transistor having such a configuration, the silicon substrate serves as the collector electrode 18.
上記のように、トランジスタ素子が形成されたシリコン基板1は、図4に示すように、銅ベースの放熱板等のアイランド2に半田等のろう材5を介して固着実装され、シリコン基板1の周辺に配置されたリード端子3にトランジスタ素子のベース電極、エミッタ電極とがそれぞれワイヤーボンディングによってワイヤーで電気的に接続されている。コレクタ電極に接続されるリード端子はアイランドと一体に形成されており、シリコン基板をアイランド上に実装することで電気的に接続された後、エポキシ樹脂等の熱硬化型樹脂4によりトランスファーモールドによって、シリコン基板とリード端子の一部を完全に被覆保護し、3端子構造の半導体装置が提供される。 As described above, the silicon substrate 1 on which the transistor element is formed is fixedly mounted on an island 2 such as a copper-based heat sink via a brazing material 5 such as solder, as shown in FIG. A base electrode and an emitter electrode of the transistor element are electrically connected to the lead terminals 3 arranged in the periphery by wires by wire bonding. The lead terminal connected to the collector electrode is formed integrally with the island, and after being electrically connected by mounting the silicon substrate on the island, transfer molding with a thermosetting resin 4 such as epoxy resin, A semiconductor device having a three-terminal structure in which a silicon substrate and a part of a lead terminal are completely covered and protected is provided.
樹脂モールドされた半導体装置は、通常、ガラスエポキシ基板等の配線基板に実装され、実装基板上に実装された他の半導体装置、回路素子と電気的に接続され所定の回路動作を行うための一部品として取り扱われる。 A resin-molded semiconductor device is usually mounted on a wiring substrate such as a glass epoxy substrate, and is electrically connected to other semiconductor devices and circuit elements mounted on the mounting substrate to perform a predetermined circuit operation. Treated as a part.
図8は、実装基板上に半導体装置を実装したときの断面図を示し、20は半導体装置、21、23はベース又はエミッタ電極用のリード端子、22はコレクタ用のリード端子、30は実装基板である。 FIG. 8 shows a cross-sectional view when a semiconductor device is mounted on a mounting substrate, 20 is a semiconductor device, 21 and 23 are base or emitter electrode lead terminals, 22 is a collector lead terminal, and 30 is a mounting substrate. It is.
実装基板30上に半導体装置20が実装される実装面積は、リード端子21、22、23とそのリード端子と接続される導電パッドで囲まれた領域によって表される。実装面積は半導体装置20内のシリコン基板(半導体チップ)面積に比べ大きく、実際に機能を持つ半導体チップの面積に比べ実装面積の殆どはモールド樹脂、リード端子によって取られている。 A mounting area where the semiconductor device 20 is mounted on the mounting substrate 30 is represented by a region surrounded by lead terminals 21, 22, and 23 and conductive pads connected to the lead terminals. The mounting area is larger than the area of the silicon substrate (semiconductor chip) in the semiconductor device 20, and most of the mounting area is taken by the mold resin and the lead terminal as compared with the area of the semiconductor chip that actually has a function.
ここで、実際に機能を持つ半導体チップ面積と実装面積との比率を有効面積率として考慮すると、樹脂モールドされた半導体装置では有効面積率が極めて低いことが確認されている。有効面積率が低いことは、半導体装置20を配線基板30上の他の回路素子と接続使用とする場合に、実装面積の殆どが機能を有する半導体チップとは直接関係のないデッドスペースとなる。有効面積率が小さいと上記したように、実装基板30上でデットスペースが大きくなり、実装基板30の高密度小型化の妨げとなる。 Here, it is confirmed that the effective area ratio is extremely low in the resin-molded semiconductor device when the effective area ratio is considered as the ratio between the actually functioning semiconductor chip area and the mounting area. The low effective area ratio means that when the semiconductor device 20 is connected to other circuit elements on the wiring board 30, most of the mounting area becomes a dead space that is not directly related to a functioning semiconductor chip. If the effective area ratio is small, the dead space is increased on the mounting substrate 30 as described above, which hinders high-density downsizing of the mounting substrate 30.
特に、この問題はパッケージサイズが小さい半導体装置に顕著に現れる。例えば、EIAJ規格のSC75A外形に搭載される半導体チップの最大サイズは、図7に示すように、0.40mm×0.40mmが最小である。この半導体チップを金属リード端子とワイヤーで接続し、樹脂モールドすると半導体装置の全体のサイズは、1.6mm×1.6mmとなる。この半導体装置のチップ面積は0.16mmで、半導体装置を実装する実装面積は半導体装置の面積とほぼ同様として考えて、2.56mmであるため、この半導体装置の有効面積率は約6.25%となり、実装面積の殆どが機能を持つ半導体チップ面積と直接関係のないデットスペースとなっている。 This problem is particularly noticeable in a semiconductor device having a small package size. For example, the maximum size of a semiconductor chip mounted on the EIAJ standard SC75A outline is 0.40 mm × 0.40 mm as shown in FIG. When this semiconductor chip is connected to a metal lead terminal with a wire and resin-molded, the overall size of the semiconductor device is 1.6 mm × 1.6 mm. The chip area of this semiconductor device is 0.16 mm, and the mounting area for mounting the semiconductor device is 2.56 mm, assuming that it is almost the same as the area of the semiconductor device. Therefore, the effective area ratio of this semiconductor device is about 6.25. Therefore, most of the mounting area is a dead space not directly related to the area of the functioning semiconductor chip.
この有効面積率に関する問題は、特に、上記したようにパッケージサイズが極めて小さい半導体装置において顕著に現れるが、半導体チップを金属リード端子でワイヤー接続し、樹脂モールドする、樹脂封止型の半導体装置であっても同様に問題となる。 This problem regarding the effective area ratio is particularly noticeable in a semiconductor device having a very small package size as described above. However, in a resin-encapsulated semiconductor device in which a semiconductor chip is wire-connected by a metal lead terminal and resin-molded. Even if it exists, it becomes a problem as well.
近年の電子機器、例えば、パーソナルコンピュータ、電子手帳等の携帯情報処理装置、8mmビデオカメラ、携帯電話、カメラ、液晶テレビ等において用いられる配線基板は、電子機器本体の小型化に伴い、その内部に使用される実装基板も高密度小型化の傾向にある。 Wiring boards used in recent electronic devices, for example, portable information processing devices such as personal computers and electronic notebooks, 8 mm video cameras, mobile phones, cameras, liquid crystal televisions, etc. The mounting substrate used is also in the trend of high density and miniaturization.
しかし、上記の先行技術の樹脂封止型の半導体装置では、上述したように、半導体装置を実装する実装面積にデットスペースが大きいため、実装基板の小型化に限界があり、実装基板の小型化の妨げの一つの要因となっていた。 However, in the above-described prior art resin-encapsulated semiconductor device, as described above, since the mounting area for mounting the semiconductor device has a large dead space, there is a limit to downsizing of the mounting substrate, and downsizing of the mounting substrate. Was one of the obstacles.
ところで、有効面積率を向上させる先行技術として特開平3−248551号公報がある。この先行技術について、図9にもとずいて簡単に説明する。この先行技術は、樹脂モールド型半導体装置を実装基板等に実装したときの実装面積をできるだけ小さくするために、半導体チップ40のベース、エミッタ、及びコレクタ電極と接続するリード端子41、42、43を樹脂モールド44の側面より外側に導出させず、リード端子41、42、43を樹脂モールド44側面と同一面となるように形成することが記載されている。 By the way, there is JP-A-3-248551 as a prior art for improving the effective area ratio. This prior art will be briefly described with reference to FIG. In this prior art, lead terminals 41, 42, and 43 connected to the base, emitter, and collector electrodes of the semiconductor chip 40 are provided in order to minimize the mounting area when the resin mold type semiconductor device is mounted on a mounting substrate or the like. It is described that the lead terminals 41, 42, 43 are formed so as to be flush with the side surface of the resin mold 44 without being led out from the side surface of the resin mold 44.
この構成によれば、リード端子41、42、43の先端部分が導出しない分だけ実装面積を小さくすることができ、有効面積率を若干向上させることはできるが、デッドスペースの大きさはあまり改善されない。 According to this configuration, the mounting area can be reduced by an amount that does not lead out the leading end portions of the lead terminals 41, 42, and 43, and the effective area ratio can be slightly improved, but the size of the dead space is greatly improved. Not.
有効面積率を向上させるためには、半導体装置の半導体チップ面積と実装面積とをほぼ同一にするこが条件であり、樹脂モールド型の半導体装置では、この先行技術の様に、リード端子の先端部を導出させなくても、モールド樹脂の存在によって有効面積率を向上させることは困難である。 In order to improve the effective area ratio, it is necessary to make the semiconductor chip area and mounting area of the semiconductor device substantially the same. In the resin mold type semiconductor device, as in this prior art, the tip of the lead terminal Even if the part is not derived, it is difficult to improve the effective area ratio due to the presence of the mold resin.
また、上記の半導体装置では、半導体チップと接続するリード端子、モールド樹脂を必要不可欠とするために、半導体チップとリード端子とのワイヤ接続工程、モールド樹脂の射出成形工程という工程を必要とし、材料コスト面及び製造工程が煩雑となり、製造コストを低減できない課題がある。 Further, in the above semiconductor device, the lead terminal to be connected to the semiconductor chip and the mold resin are indispensable, and therefore, a process of wire connection process between the semiconductor chip and the lead terminal and an injection molding process of the mold resin are required. There is a problem that the cost and the manufacturing process are complicated, and the manufacturing cost cannot be reduced.
有効面積率を最大限大きくするには、上記したように、半導体チップを直接実装基板上に実装することにより、半導体チップ面積と実装面積とがほぼ同一となり有効面積率が最大となる。
、特開平6−338504号公報に示すように、半導体チップ45上に複数のバンプ電極46を形成したフリップチップを実装基板47フェイスダウンボンディングする技術が知られている(図10参照)。この先行技術は、通常、MOSFET等、シリコン基板の同一主面にゲート(ベース)電極、ソース(エミッタ)電極、ドレイン(コレクタ)電極が形成され、電流或いは電圧のパスが横方向に形成される比較的発熱量の少ない横型の半導体装置に主に用いられる。
In order to maximize the effective area ratio, as described above, by mounting the semiconductor chip directly on the mounting substrate, the area of the semiconductor chip and the mounting area are almost the same, and the effective area ratio is maximized.
As shown in Japanese Patent Laid-Open No. 6-338504, a technique is known in which a flip chip in which a plurality of bump electrodes 46 are formed on a semiconductor chip 45 is face-down bonded to a mounting substrate 47 (see FIG. 10). In this prior art, a gate (base) electrode, a source (emitter) electrode, and a drain (collector) electrode are usually formed on the same main surface of a silicon substrate such as a MOSFET, and a current or voltage path is formed in a horizontal direction. It is mainly used for horizontal semiconductor devices that generate a relatively small amount of heat.
しかし、トランジスタデバイス等のようにシリコン基板が電極の一つとなり、各電極が異なる面に形成され電流のパスが縦方向に流れる縦型の半導体装置では、上記のフリップチップ技術を使用することは困難である。 However, in a vertical semiconductor device such as a transistor device where a silicon substrate is one of the electrodes and each electrode is formed on a different surface and the current path flows in the vertical direction, the above-described flip chip technology is not used. Have difficulty.
半導体チップを実装基板等の基板上に実装する他の先行技術として、例えば、特開平7−38334号公報に示すように、実装基板51上に形成された導電パターン52上に半導体チップ53をダイボンディングし、半導体チップ53周辺に配置された導電パターン52と半導体チップ53との電極をワイヤ54で接続する技術が知られている(図11参照)。この先行技術では、先に述べたシリコン基板が一つの電極を構成した縦型構造のトランジスタ等の半導体チップに用いることはできる。 As another prior art for mounting a semiconductor chip on a substrate such as a mounting substrate, for example, as shown in Japanese Patent Laid-Open No. 7-38334, a semiconductor chip 53 is formed on a conductive pattern 52 formed on a mounting substrate 51. A technique for bonding and connecting electrodes of the conductive pattern 52 and the semiconductor chip 53 arranged around the semiconductor chip 53 with a wire 54 is known (see FIG. 11). This prior art can be used for a semiconductor chip such as a transistor having a vertical structure in which the above-described silicon substrate constitutes one electrode.
半導体チップ53とその周辺に配置された導電パターン52とを接続するワイヤ54は通常、金細線が用いられることから、金細線とボンディング接続されるボンディング接合部のピール強度(引張力)を大きくするために、約200℃〜300℃の加熱雰囲気中でボンディングを行うことが好ましい。しかし、絶縁樹脂系の実装基板上に半導体チップをダイボンディングする場合には、上記した温度まで加熱すると配線基板に歪みが生じること、及び、実装基板上に実装されたチップコンデンサ、チップ抵抗等の他の回路素子を固着する半田が溶融するために、加熱温度を約100℃〜150℃程度にしてワイヤボンディング接続が行われているため、ボンディング接合部のピール強度が低下する問題がある。 Since the wire 54 that connects the semiconductor chip 53 and the conductive pattern 52 disposed around the semiconductor chip 53 is usually a gold fine wire, the peel strength (tensile force) of the bonding joint that is bonded to the gold fine wire is increased. Therefore, it is preferable to perform bonding in a heated atmosphere of about 200 ° C. to 300 ° C. However, when a semiconductor chip is die-bonded on an insulating resin-based mounting substrate, the wiring substrate is distorted when heated to the above temperature, and a chip capacitor mounted on the mounting substrate, a chip resistor, etc. Since the solder for fixing other circuit elements is melted, wire bonding connection is performed at a heating temperature of about 100 ° C. to 150 ° C., so that there is a problem that the peel strength of the bonding junction is lowered.
この先行技術では、通常、ダイボンディングされた半導体チップはエポキシ樹脂等の熱硬化性樹脂で被覆保護されるために、ピール強度の低下はエポキシ樹脂の熱硬化時の収縮等によって接合部が剥離されるという問題がある。 In this prior art, since the die-bonded semiconductor chip is usually covered and protected with a thermosetting resin such as an epoxy resin, the reduction in peel strength is caused by the shrinkage during the thermosetting of the epoxy resin and the joint part is peeled off. There is a problem that.
本発明は、上述した事情に鑑みて成されたものであり、本発明は、半導体チップと接続されるリード端子、及びモールド樹脂を必要とせず、半導体チップ面積と実装基板上に実装する実装面積との比率である有効面積率を最大限向上させ、実装面積のデットスペース最小限小さくした半導体装置を提供する。 The present invention has been made in view of the above-described circumstances, and the present invention does not require a lead terminal connected to a semiconductor chip and a mold resin, and a semiconductor chip area and a mounting area mounted on a mounting substrate. The effective area ratio, which is the ratio of the above, is maximally improved, and a semiconductor device with a reduced mounting space is minimized.
本発明は、上記の課題を解決するために以下の構成を採用した。
第1に、シリコン基板からなり、その表面にある絶縁層上に設けられ、前記シリコン基板と絶縁された配線が設けられた実装基板と、その表面に形成された能動素子と前記配線が電気的に接続され、前記実装基板の上に設けられた半導体チップとを有する半導体装置であり、
前記実装基板を前記半導体チップを構成するシリコンから成すことで解決するものであり、
配線が設けられた実装基板もシリコンにすることにより、半導体チップと実装基板の熱膨張係数をマッチングさせ、その応力を抑制するものである。
第2に、前記シリコン基板は導電性を有し、前記シリコン基板が露出した部分を介して、前記配線と前記シリコン基板を電気的に接続することにより、ノイズによる影響を減少したものである。
第3に、前記配線および前記シリコン基板には、パシベーション膜が形成され、このパシベーション膜の一部が取り除かれることにより前記配線が露出し、この露出部を介して前記配線と前記能動素子を電気的に接続することにより、実装基板上の配線の腐食を防止するものである。
第4に、シリコン基板からなり、その表面にある絶縁層上に設けられ、前記シリコン基板と絶縁された配線が設けられた実装基板と、その表面に形成された能動素子と前記配線が電気的に接続され、前記実装基板の表面に前記能動素子が設けられた面を向けて設けられた半導体チップとを有する半導体装置であり、
前記実装基板と前記半導体チップとの間には、接着性の樹脂を設けられることで解決するものである。
第5に、前記接着性の樹脂は、熱硬化型であり、硬化時の熱収縮により、前記能動素子と前記配線の電気的導通が更に良好に成るものである。
第6に、その表面に半導体素子を実装するためのシリコン基板から成る実装基板であり、前記シリコン基板の表面には絶縁層が設けられ、前記半導体素子と電気的に接続される配線が設けられることで解決するものである。
第7に、前記半導体素子は、シリコンからなり、前記シリコン基板は、前記半導体素子と熱膨張係数が等しいことで解決するものである。
第8に、前記配線および前記シリコン基板を覆うようにパシベーション膜が設けられ、前記パシベーションの一部が取り除かれることにより、前記配線が露出することで解決するものである。
第9に、前記絶縁層は、シリコン酸化膜或いはシリコン窒化膜から成ることで解決するものである。
第10に、前記配線と前記シリコン基板は、電気的に接続されることで解決するものである。
The present invention employs the following configuration in order to solve the above problems.
First, a mounting substrate that is formed of a silicon substrate and is provided on an insulating layer on the surface thereof and provided with wiring insulated from the silicon substrate, an active element formed on the surface, and the wiring are electrically connected. And a semiconductor device having a semiconductor chip provided on the mounting substrate,
The mounting substrate is made of silicon constituting the semiconductor chip, and is solved.
The mounting substrate on which the wiring is provided is also made of silicon, thereby matching the thermal expansion coefficients of the semiconductor chip and the mounting substrate and suppressing the stress.
Second, the silicon substrate has conductivity, and the influence of noise is reduced by electrically connecting the wiring and the silicon substrate through a portion where the silicon substrate is exposed.
Third, a passivation film is formed on the wiring and the silicon substrate, and the wiring is exposed by removing a part of the passivation film, and the wiring and the active element are electrically connected via the exposed portion. By connecting them electrically, corrosion of the wiring on the mounting board is prevented.
Fourth, the mounting substrate is formed of a silicon substrate and provided on an insulating layer on the surface thereof, and provided with wiring insulated from the silicon substrate, and the active element formed on the surface and the wiring are electrically connected. A semiconductor device having a semiconductor chip connected to a surface of the mounting substrate facing the surface on which the active element is provided,
The problem is solved by providing an adhesive resin between the mounting substrate and the semiconductor chip.
Fifth, the adhesive resin is a thermosetting type, and the electrical continuity between the active element and the wiring is further improved by heat shrinkage during curing.
Sixth, there is a mounting substrate made of a silicon substrate for mounting a semiconductor element on its surface, and an insulating layer is provided on the surface of the silicon substrate, and a wiring electrically connected to the semiconductor element is provided. It will be solved.
Seventh, the semiconductor element is made of silicon, and the silicon substrate has a thermal expansion coefficient equal to that of the semiconductor element.
Eighth, the problem is solved by providing a passivation film so as to cover the wiring and the silicon substrate, and exposing the wiring by removing a part of the passivation.
Ninth, the insulating layer is solved by being made of a silicon oxide film or a silicon nitride film.
Tenth, the wiring and the silicon substrate are solved by being electrically connected.
配線基板にシリコン基板を用いる事で、
第1に、既存の半導体製造装置をそのまま使用することができ、新たに設備導入を行う必要がない特徴を有する。
第2に、基板60と固着したときに両基板60、65が共にシリコン基板であると熱膨張係数αが等しいため外部加熱或いは自己発熱による熱発生が生じた場合でも上下で同一応力が加わり相殺するために基板60、65の歪による悪影響を抑制
することができる特徴を有する。
第3に、シリコン基板は導電性を有することで、配線パターン67と配線基板65とを電気的に導通することができる。このことにより、配線基板65がシールド板となりシールド効果を得ることができノイズによる悪影響を抑制することができる特徴を有する。
By using a silicon substrate for the wiring board,
First, there is a feature that an existing semiconductor manufacturing apparatus can be used as it is, and it is not necessary to newly introduce equipment.
Second, if both the substrates 60 and 65 are silicon substrates when they are fixed to the substrate 60, the thermal expansion coefficient α is equal, so even if heat is generated by external heating or self-heating, the same stress is applied vertically to cancel out. Therefore, it has a feature that the adverse effect due to the distortion of the substrates 60 and 65 can be suppressed.
Third, since the silicon substrate has conductivity, the wiring pattern 67 and the wiring substrate 65 can be electrically connected. As a result, the wiring board 65 becomes a shield plate to obtain a shielding effect, and the adverse effect due to noise can be suppressed.
以下に、本発明の半導体装置の実施形態について説明する。 Hereinafter, embodiments of the semiconductor device of the present invention will be described.
本発明の半導体装置は、図1に示すように、半導体基板60と、能動素子が形成される能動素子形成領域61と、能動素子形成領域61に形成された能動素子の一の電極であり、外部接続するための一の外部接続用電極62と、能動素子形成領域61と電気的に分離され基板60の一部分を能動素子の他の電極の外部電極とする他の外部接続用電極63、64と、外部接続用電極63、64の電極領域63A,64Aに形成された高濃度拡散層81と、能動素子の他の電極と他の外部接続用電極63、64とを接続する配線パターンが形成された配線基板65とをから構成されている。 As shown in FIG. 1, the semiconductor device of the present invention includes a semiconductor substrate 60, an active element formation region 61 in which an active element is formed, and one electrode of the active element formed in the active element formation region 61. One external connection electrode 62 for external connection, and other external connection electrodes 63 and 64 that are electrically separated from the active element formation region 61 and use a part of the substrate 60 as an external electrode of another electrode of the active element. And a wiring pattern that connects the high-concentration diffusion layer 81 formed in the electrode regions 63A and 64A of the external connection electrodes 63 and 64 and the other electrodes of the active element and the other external connection electrodes 63 and 64. The wiring board 65 is made up of.
半導体基板60は、N+型の単結晶シリコン基板が用いられ、その基板60上にエピタキシャル成長技術によりN-型のエピタキシャル層66が形成される。半導体基板60の所定領域はパワーMOS、トランジスタ等の能動素子が形成される能動素子形成領域61と能動素子の電極接続され外部接続用電極63、64となる外部接続電極領域63A,64Aとが設けられている。 The semiconductor substrate 60 is an N + type single crystal silicon substrate, and an N − type epitaxial layer 66 is formed on the substrate 60 by an epitaxial growth technique. A predetermined region of the semiconductor substrate 60 is provided with an active element formation region 61 where active elements such as power MOSs and transistors are formed, and external connection electrode regions 63A and 64A which are connected to the active element electrodes and become external connection electrodes 63 and 64. It has been.
この能動素子形成領域61に上記した能動素子が形成される。ここでは、N-型のエピタキシャル層をコレクタ領域66Aとしたトランジスタが形成される。能動素子形成領域61上にホトレジストを形成し、ホトレジストによって露出された領域にボロン(B)等のP型の不純物を選択的に熱拡散して所定の深さを有した島状のベース領域71が形成される。 The active element described above is formed in the active element formation region 61. Here, a transistor having an N− type epitaxial layer as a collector region 66A is formed. A photoresist is formed on the active element formation region 61, and P-type impurities such as boron (B) are selectively thermally diffused into the region exposed by the photoresist to form an island-shaped base region 71 having a predetermined depth. Is formed.
ベース領域71形成後、能動素子形成領域61上に再度ホトレジストを形成し、ホトレジストによって露出されたベース領域71内にリン(P)、アンチモン(Sb)等のN型の不純物を選択的に熱拡散してトランジスタのエミッタ領域72が形成される。このエミッタ領域72を形成する際に、ベース領域71を囲むリング状のガードリング用のN+型の拡散領域73を形成しておく場合もある。
さらに、N+型のエミッタ領域72を形成する際、N+型の拡散は外部接続用電極となる電極領域63A,64A上にも行われ、電極領域63A、64Aに高濃度拡散層81が形成される。
After the base region 71 is formed, a photoresist is formed again on the active element forming region 61, and N-type impurities such as phosphorus (P) and antimony (Sb) are selectively thermally diffused in the base region 71 exposed by the photoresist. Thus, the emitter region 72 of the transistor is formed. When the emitter region 72 is formed, an N + type diffusion region 73 for a ring-shaped guard ring surrounding the base region 71 may be formed.
Further, when the N + -type emitter region 72 is formed, the N + -type diffusion is also performed on the electrode regions 63A and 64A serving as external connection electrodes, and the high concentration diffusion layer 81 is formed in the electrode regions 63A and 64A. Is done.
半導体基板60の表面には、ベース領域71表面を露出するベースコンタクト孔及びエミッタ領域72表面を露出するエミッタコンタクト孔を有するシリコン酸化膜、或いはシリコン窒化膜等の絶縁膜74が形成される。ガードリング用の拡散領域73を形成した場合には、かかる、拡散領域73表面を露出するガードリングコンタクト孔が形成される。この絶縁膜74は、外部接続用電極となる電極領域63A,64A上にも形成され、電極領域63A,64Aの表面を露出する外部接続用コンタクト孔が形成されている。 An insulating film 74 such as a silicon oxide film or a silicon nitride film having a base contact hole exposing the surface of the base region 71 and an emitter contact hole exposing the surface of the emitter region 72 is formed on the surface of the semiconductor substrate 60. When the guard ring diffusion region 73 is formed, the guard ring contact hole exposing the surface of the diffusion region 73 is formed. The insulating film 74 is also formed on the electrode regions 63A and 64A serving as external connection electrodes, and external connection contact holes are formed to expose the surfaces of the electrode regions 63A and 64A.
ベースコンタクト孔、エミッタコンタクト孔、外部接続用コンタクト孔及びガードリングコンタクト孔によって露出されたベース領域71、エミッタ領域72、電極領域63A,64A及びガードリング拡散領域73上には、選択的にアルミニウム等の金属材料で蒸着されたベース電極75、エミッタ電極76、接続用電極77が形成される。 On the base region 71, the emitter region 72, the electrode regions 63A and 64A, and the guard ring diffusion region 73 exposed by the base contact hole, the emitter contact hole, the external connection contact hole and the guard ring contact hole, aluminum or the like is selectively formed. A base electrode 75, an emitter electrode 76, and a connection electrode 77 deposited with the above metal material are formed.
ベース電極75、エミッタ電極76、及び接続用電極77にアルミニウムを用いた場合には、基板60上にPSG膜、SiN、SiNx等の絶縁物からなるパッシベーション膜を形成し、ベース電極75、エミッタ電極76、接続用電極77上のパッシベーション膜を選択的に除去し、各電極75、76、77の表面を露出させる。さらに、露出された領域内にクロム、銅等を選択的にメッキしてメッキ層79を形成し各電極75、76、77の腐食による不具合を防止する必要がある。 When aluminum is used for the base electrode 75, the emitter electrode 76, and the connection electrode 77, a passivation film made of an insulator such as a PSG film, SiN, SiNx, etc. is formed on the substrate 60, and the base electrode 75, the emitter electrode 76, the passivation film on the connection electrode 77 is selectively removed, and the surfaces of the electrodes 75, 76, 77 are exposed. Furthermore, it is necessary to selectively plate chromium, copper, or the like in the exposed region to form a plated layer 79 to prevent problems due to corrosion of the electrodes 75, 76, 77.
能動素子形成領域61及び外部接続電極領域63A,64Aは、半導体基板60の所定の任意の領域に形成することができ、この実施形態では、図2に示すように、基板60の中央部分に能動素子形成領域61が形成され、その領域61の挟んでトライアングル形状に成るように外部接続用電極領域63A,64Aが形成される。 The active element formation region 61 and the external connection electrode regions 63A and 64A can be formed in a predetermined arbitrary region of the semiconductor substrate 60. In this embodiment, as shown in FIG. An element formation region 61 is formed, and external connection electrode regions 63A and 64A are formed so as to have a triangle shape with the region 61 interposed therebetween.
トランジスタが形成された能動素子形成領域61と外部接続電極領域63A,64Aとを有した半導体基板60表面上にはシリコン系、エポキシ系或いはポリイミド系或いは光硬化性の絶縁接着樹脂層78を介して配線基板65が固着される。配線基板65上にはアルミニウム、銅等の配線パターン67が形成されており、この配線パターン67によって、トランジスタのベース電極75、エミッタ電極76と外部接続電極領域63A,64Aとの電気的が接続がそれぞれ行われる。 A silicon-based, epoxy-based, polyimide-based, or photocurable insulating adhesive resin layer 78 is provided on the surface of the semiconductor substrate 60 having the active element forming region 61 in which the transistor is formed and the external connection electrode regions 63A, 64A. The wiring board 65 is fixed. A wiring pattern 67 made of aluminum, copper, or the like is formed on the wiring substrate 65. With this wiring pattern 67, the base electrode 75 and emitter electrode 76 of the transistor are electrically connected to the external connection electrode regions 63A and 64A. Each done.
配線基板65としては、ガラスエポキシ基板、セラミックス基板、絶縁処理された金属基板、フェノール基板、シリコン基板等の基板を用いることができるが、本発明ではシリコン基板を用いることが好ましい。シリコン基板を配線基板65として用いた場合、表面にSiO2或いはSiN×等の絶縁層を形成し、その絶縁層上にアルミニウム等の金属を選択的に蒸着し、所定形状の配線パターン67が形成される。 As the wiring substrate 65, a glass epoxy substrate, a ceramic substrate, an insulated metal substrate, a phenol substrate, a silicon substrate, or the like can be used. In the present invention, it is preferable to use a silicon substrate. When a silicon substrate is used as the wiring substrate 65, an insulating layer such as SiO2 or SiNx is formed on the surface, and a metal such as aluminum is selectively deposited on the insulating layer to form a wiring pattern 67 having a predetermined shape. The
配線基板65にシリコン基板を用いる大きな理由は、第1に、既存の半導体製造装置をそのまま使用することができ、新たに設備導入を行う必要がない。第2に、基板60と固着したときに両基板60、65が共にシリコン基板であると熱膨張係数αが等しいため外部加熱或いは自己発熱による熱発生が生じた場合でも上下で同一応力が加わり相殺するために基板60、65の歪による悪影響を抑制することができる。第3に、シリコン基板は導電性を有するためである。 The main reason for using a silicon substrate for the wiring board 65 is that an existing semiconductor manufacturing apparatus can be used as it is, and it is not necessary to introduce new equipment. Second, if both the substrates 60 and 65 are silicon substrates when they are fixed to the substrate 60, the thermal expansion coefficient α is equal, so even if heat is generated by external heating or self-heating, the same stress is applied vertically to cancel out. Therefore, adverse effects due to distortion of the substrates 60 and 65 can be suppressed. Third, the silicon substrate is conductive.
シリコン基板を用いた配線基板65上には、上記したように、SiO2或いはSiN×等の絶縁層82を介して、トランジスタのベース電極75、エミッタ電極76と接続されるアルミニウム等の金属からなる所定形状の冗長用の配線パターン67が形成されている。この配線パターン67の一方は配線基板65と電気的に導通されている。即ち、配線基板65上に形成される絶縁層82の所定位置にコンタクト孔が形成され、このコンタクト孔内にニッケル等のメッキ層83が形成され、このメッキ層83上に配線パターン67の一部分を重畳形成することにより、配線パターン67と配線基板65とを電気的に導通することができる。 On the wiring substrate 65 using a silicon substrate, as described above, a predetermined metal made of a metal such as aluminum connected to the base electrode 75 and the emitter electrode 76 of the transistor via the insulating layer 82 such as SiO 2 or SiN ×. A redundant wiring pattern 67 having a shape is formed. One of the wiring patterns 67 is electrically connected to the wiring board 65. That is, a contact hole is formed at a predetermined position of the insulating layer 82 formed on the wiring board 65, and a plating layer 83 of nickel or the like is formed in the contact hole, and a part of the wiring pattern 67 is formed on the plating layer 83. By overlapping the wiring pattern 67, the wiring pattern 67 and the wiring board 65 can be electrically connected.
他の配線パターン67は配線基板65と絶縁状態を保持しておく。本実施形態では、エミッタ電極76と接続される配線パターン67のみがシリコン基板からなる配線基板65とが電気的に接続されている。エミッタ電極76と配線基板65とを電気的に導通状態にすることにより、配線基板65がシールド板となりシールド効果を得ることができノイズによる悪影響を抑制することができる。 Other wiring patterns 67 are kept insulated from the wiring board 65. In the present embodiment, only the wiring pattern 67 connected to the emitter electrode 76 is electrically connected to the wiring substrate 65 made of a silicon substrate. By making the emitter electrode 76 and the wiring board 65 electrically conductive, the wiring board 65 becomes a shield plate and a shielding effect can be obtained, and adverse effects due to noise can be suppressed.
配線基板65上に形成される配線パターン67は、ここでは、トランジスタのベース、エミッタ電極を冗長させるパターンのみが形成されるが、必要に応じて冗長パターン以外のパターン形成する場合もある。 Here, as the wiring pattern 67 formed on the wiring substrate 65, only a pattern for making the base and emitter electrodes of the transistor redundant is formed, but a pattern other than the redundant pattern may be formed if necessary.
配線パターン67にアルミニウムを用いた場合には、上記したように、配線基板65上にPSG膜、SiN、SiNx等の絶縁物からなるパッシベーション膜を形成し、配線パターン67上のパッシベーション膜を選択的に除去し、バンプ電極68が形成される配線パターン67の表面を露出させる。さらに、露出された領域内にクロム、銅等を選択的にメッキしてメッキ層69を形成し配線パターン67の腐食による不具合を防止している。メッキ層69上には、高さ約3μ〜25μの金等の金属からなるバンプ電極68が形成され、このバンプ電極68により、外部接続電極領域63A,64Aに形成された接続電極77との接触が行われ電気的導通が成される。 半導体基板60と配線基板65とを接着する樹脂層78は、上記したように、種々の材料が存在するが、例えば、紫外線で硬化するアクリル樹脂等の光硬化性樹脂とエポキシ樹脂等の熱硬化性樹脂とを混合させたハイブリッドタイプの光熱硬化性樹脂を用いるものとする。光熱硬化性樹脂を基板60上に塗布し、能動素子形成領域61上に形成されたトランジスタのベース電極75、エミッタ電極76および外部接続電極領域63A、64A上に形成された接続電極77と配線基板65上に形成したバンプ電極68とが一致するように両基板60、65との位置合わせを行い密着させる。 When aluminum is used for the wiring pattern 67, as described above, a passivation film made of an insulator such as a PSG film, SiN, SiNx or the like is formed on the wiring substrate 65, and the passivation film on the wiring pattern 67 is selectively used. The surface of the wiring pattern 67 on which the bump electrode 68 is formed is exposed. Further, chromium, copper, or the like is selectively plated in the exposed region to form a plated layer 69 to prevent problems due to corrosion of the wiring pattern 67. A bump electrode 68 made of a metal such as gold having a height of about 3 μ to 25 μ is formed on the plating layer 69, and the bump electrode 68 is in contact with the connection electrode 77 formed in the external connection electrode regions 63 A and 64 A. And electrical conduction is established. As described above, the resin layer 78 for bonding the semiconductor substrate 60 and the wiring substrate 65 includes various materials. For example, a thermosetting resin such as an acrylic resin that is cured by ultraviolet rays and a thermosetting resin such as an epoxy resin. It is assumed that a hybrid type photothermosetting resin mixed with a curable resin is used. A photothermosetting resin is applied onto the substrate 60, and the base electrode 75, the emitter electrode 76 and the connection electrodes 77 formed on the external connection electrode regions 63A and 64A formed on the active element formation region 61 and the wiring substrate. The two substrates 60 and 65 are aligned and brought into close contact so that the bump electrodes 68 formed on 65 coincide with each other.
その後、約80℃〜100℃程度の加熱処理を行い樹脂層78を熱硬化させ、両基板60、65を固着一体化する。この時、各電極75、76、77とバンプ電極68とは接触し電気的導通は行われているが、十分な導通状態ではない。その後、紫外線を照射することで樹脂層78中の光硬化性樹脂の硬化が始まり、その光熱硬性樹脂の硬化時の収縮力で両基板60、65が互いに引き合わさられ、基板60上の各電極75、76、77とバンプ電極68との接触が十分に保たれ電気的導通が確実に行われる。樹脂層78は各電極75、76、77とバンプ電極68とを良好に導通させるとともに、両基板60、65の接着をも同時に行うものである。 Thereafter, a heat treatment of about 80 ° C. to 100 ° C. is performed to thermally cure the resin layer 78, and the substrates 60 and 65 are fixed and integrated. At this time, the electrodes 75, 76, 77 and the bump electrode 68 are in contact with each other and are electrically connected, but are not in a sufficiently conductive state. Thereafter, curing of the photocurable resin in the resin layer 78 is started by irradiating with ultraviolet rays, and both the substrates 60 and 65 are attracted to each other by the contraction force at the time of curing of the photothermosetting resin. 75, 76, 77 and the bump electrode 68 are sufficiently kept in contact with each other to ensure electrical conduction. The resin layer 78 provides good conduction between the electrodes 75, 76, 77 and the bump electrode 68, and simultaneously bonds the two substrates 60, 65 together.
ところで、配線パターン67上に形成するバンプ電極68の高さが低い場合には、基板60上の形成した各電極上にもバンプ電極を形成することが好ましい。配線パターン67上に形成したバンプ電極68の高さが低すぎると両基板60、65の離間距離、即ち樹脂層78の膜厚が薄くなり、後述するスリット孔80を形成したときに、スリット孔80の先端部分が配線基板65の表面まで達し配線パターン67が断線する可能性があり、両基板60、65の離間距離を十分に考慮する必要がある。 By the way, when the height of the bump electrode 68 formed on the wiring pattern 67 is low, it is preferable to form the bump electrode also on each electrode formed on the substrate 60. If the bump electrode 68 formed on the wiring pattern 67 is too low, the distance between the substrates 60 and 65, that is, the film thickness of the resin layer 78 becomes thin. There is a possibility that the distal end portion of 80 reaches the surface of the wiring board 65 and the wiring pattern 67 is disconnected, and it is necessary to sufficiently consider the distance between the boards 60 and 65.
同一基板60上に形成された能動素子形成領域61と外部接続電極領域63A,64Aとは、基板60の裏面側から形成されたスリット孔80によって、それぞれ電気的に分離され、個々の領域61、63A,64Aがトランジスタの外部接続用電極62、63、64となる。 The active element formation region 61 and the external connection electrode regions 63A and 64A formed on the same substrate 60 are electrically separated from each other by the slit holes 80 formed from the back surface side of the substrate 60. 63A and 64A become the external connection electrodes 62, 63 and 64 of the transistor.
即ち、能動素子形成領域61の基板60はトランジスタのコレクタ電極用の外部接続用電極62、一の外部接続電極領域64Aの基板60はトランジスタのベース電極用の外部接続用電極64、及び他の外部接続電極領域63Aの基板60はトランジスタのエミッタ電極用の外部接続用電極63となり、同一の半導体基板60を用い、且つ、同一平面上にトランジスタの各電極の外部接続用電極62、63、64が形成されることになる。 That is, the substrate 60 in the active element formation region 61 is the external connection electrode 62 for the collector electrode of the transistor, the substrate 60 in the one external connection electrode region 64A is the external connection electrode 64 for the base electrode of the transistor, and other external connection electrodes. The substrate 60 in the connection electrode region 63A becomes the external connection electrode 63 for the emitter electrode of the transistor. The same semiconductor substrate 60 is used, and the external connection electrodes 62, 63, 64 of each electrode of the transistor are formed on the same plane. Will be formed.
トランジスタのベース電極用の外部接続用電極64、エミッタ電極用外部接続用電極63となる電極領域64A,63Aには、上記したように、高濃度拡散層81を形成していおり、ベース電極75とベース電極用の外部接続用電極64、及びエミッタ電極76とエミッタ電極用の外部接続用電極63間の配線抵抗によるロスを緩和している。この高濃度拡散層81は、電極領域64A,63Aのエピタキシャル層66の膜厚が比較的薄い場合、上記したように、エミッタ領域72を形成する拡散工程で形成される。 As described above, the high concentration diffusion layer 81 is formed in the electrode regions 64A and 63A to be the external connection electrode 64 for the base electrode of the transistor and the external connection electrode 63 for the emitter electrode. The loss due to the wiring resistance between the base electrode external connection electrode 64 and the emitter electrode 76 and the emitter electrode external connection electrode 63 is reduced. The high-concentration diffusion layer 81 is formed in the diffusion step of forming the emitter region 72 as described above when the epitaxial layer 66 in the electrode regions 64A and 63A is relatively thin.
エピタキシャル層60の膜厚が比較的厚い場合には、エピタキシャル層60を形成する前に、電極領域63A,64A上にN+型の不純物をデポジションし、その後、エピタキシャル層60を形成し、さらに熱拡散工程を行い基板60側から高濃度拡散領域81を成長させておいた状態にしておけば、エミッタ領域72を形成するときに高濃度拡散領域81、81が接触し、電極領域63A,64A内に高濃度拡散層81を形成することができる。 When the film thickness of the epitaxial layer 60 is relatively large, N + type impurities are deposited on the electrode regions 63A and 64A before the epitaxial layer 60 is formed, and then the epitaxial layer 60 is formed and further heated. If the high concentration diffusion region 81 is grown from the substrate 60 side by performing the diffusion process, the high concentration diffusion regions 81 and 81 come into contact with each other when the emitter region 72 is formed, and the electrode regions 63A and 64A A high concentration diffusion layer 81 can be formed.
各外部接続用電極62、63、64を電気的に分離するスリット孔80は、上記のように、半導体基板60の裏面側から樹脂層78まで達するように形成され、例えば、イオンビーム、レーザ等を照射する光学的方法、ドライエッチング、ウエットエッチングによる化学的方法、或いはダイシング装置によるダイシングブレードを用いた機械的方法等により形成される。上記のいずれの方法によってもスリット孔80を形成することはできる。 As described above, the slit hole 80 for electrically separating the external connection electrodes 62, 63, 64 is formed so as to reach the resin layer 78 from the back surface side of the semiconductor substrate 60. For example, an ion beam, a laser, etc. Is formed by a chemical method using dry etching, wet etching, or a mechanical method using a dicing blade by a dicing apparatus. The slit hole 80 can be formed by any of the above methods.
ここで重要なことは、スリット孔80の深さが浅くなると各外部接続用電極62、63、64の電気分離が十分に行なわれず短絡不良となる不具合が生じるため、各外部接続用電極62、63、64が完全に電気的に分離するように、スリット孔80の先端部(底部)は樹脂層78内に約2μ〜6μ程度入るように形成される。スリット孔80によって各外部接続用電極62、63、64は完全に分離区画されるが、樹脂層78によって同一平面に支持固定される。また、各外部接続用電極62、63、64となる基板60表面には、半田メッキ等のメッキ層が形成され、配線基板上に形成された導電パターンとの半田接続を良好にする。 What is important here is that if the depth of the slit hole 80 becomes shallow, the electrical connection between the external connection electrodes 62, 63, 64 is not sufficiently performed, and a short circuit failure occurs. The front end portion (bottom portion) of the slit hole 80 is formed so as to be within the resin layer 78 by about 2 μ to 6 μ so that 63 and 64 are completely electrically separated. The external connection electrodes 62, 63, 64 are completely separated and partitioned by the slit hole 80, but are supported and fixed on the same plane by the resin layer 78. In addition, a plating layer such as solder plating is formed on the surface of the substrate 60 to be the external connection electrodes 62, 63, 64, so that the solder connection with the conductive pattern formed on the wiring substrate is improved.
半導体基板60にスリット孔80を設けて、トランジスタの各外部接続用電極62、63、64を電気的に分離した半導体装置は、セラミックス基板、ガラスエポキシ基板、フェノール基板、絶縁処理を施した金属基板等の配線基板上に形成された導電パターンのパッド上に固着実装される。このパッド上には半田クリームが予め印刷形成された半田層が形成されており、半田を溶融させて本発明の半導体装置を搭載すれば配線基板のパッド上に半導体装置を固着実装することができる。この固着実装工程は、図示されないが、実装基板上に実装されるチップコンデンサ、チップ抵抗等の半田実装される他の回路素子の実装工程と同一の工程でできる。 A semiconductor device in which a slit hole 80 is provided in a semiconductor substrate 60 and the external connection electrodes 62, 63, 64 of the transistor are electrically separated includes a ceramic substrate, a glass epoxy substrate, a phenol substrate, and a metal substrate subjected to insulation treatment. It is fixedly mounted on a pad of a conductive pattern formed on a wiring board such as. A solder layer in which solder cream is pre-printed is formed on the pad, and the semiconductor device can be fixedly mounted on the pad of the wiring board by melting the solder and mounting the semiconductor device of the present invention. . Although not shown, this fixed mounting process can be performed in the same process as the mounting process of other circuit elements to be mounted by solder such as chip capacitors and chip resistors mounted on the mounting substrate.
また、本発明の半導体装置を配線基板上に実装した時、各外部接続用電極62、63、64はスリット孔80の間隔分だけ離間されているために実装基板と固着する半田は隣接配置された外部接続用電極62、63、64を短絡させることはない。 When the semiconductor device of the present invention is mounted on the wiring board, the external connection electrodes 62, 63, 64 are separated by the interval of the slit holes 80, so that the solder that is fixed to the mounting board is disposed adjacently. The external connection electrodes 62, 63, 64 are not short-circuited.
ところで、図2に示すように、本実施形態の半導体装置で、例えば、従来例で説明した半導体装置とほぼ同じ機能をもつ能動素子能動素子形成領域61を0.5mm×0.5mmサイズとし、ベース、エミッタ電極となる接続電極領域63A,64Aを0.3mm×0.2mmサイズとし、スリット孔80の幅を0.1mmとする半導体装置では有効面積率は次のようになる。即ち、素子面積が0.25mmであり、実装面積となる半導体装置の面積が1.28mmとなることから、有効面積率は約19.53%となる。 By the way, as shown in FIG. 2, in the semiconductor device of this embodiment, for example, the active element active element forming region 61 having substantially the same function as the semiconductor device described in the conventional example is 0.5 mm × 0.5 mm in size, In the semiconductor device in which the connection electrode regions 63A and 64A serving as the base and emitter electrodes are 0.3 mm × 0.2 mm in size and the width of the slit hole 80 is 0.1 mm, the effective area ratio is as follows. That is, the element area is 0.25 mm, and the area of the semiconductor device as the mounting area is 1.28 mm, so that the effective area ratio is about 19.53%.
従来例で説明した0.40mm×0.40mmのチップサイズを有する半導体装置の有効面積率は上記したように6.25%であることから、本発明の半導体装置では有効面積率で約3.12倍大きくなり、実装基板上に実装する実装面積のデットスペースを小さくすることができ、実装基板の小型化に寄与することができる。 Since the effective area ratio of the semiconductor device having the chip size of 0.40 mm × 0.40 mm described in the conventional example is 6.25% as described above, the effective area ratio of the semiconductor device of the present invention is about 3. It becomes 12 times larger, the dead space of the mounting area to be mounted on the mounting board can be reduced, and it can contribute to the downsizing of the mounting board.
本実施形態では、実装基板との接続容易性を考慮し、外部接続用電極62、63、64がトライアングルとなるように配置したが、外部接続電極62、63、64を直線上に配置すれば、半導体基板60上の不使用領域を無くすことができ、有効面積率をさらに向上させることが可能である。 In the present embodiment, the external connection electrodes 62, 63, and 64 are arranged so as to form a triangle in consideration of the ease of connection with the mounting board. However, if the external connection electrodes 62, 63, and 64 are arranged on a straight line, The unused area on the semiconductor substrate 60 can be eliminated, and the effective area ratio can be further improved.
上述したように、本発明の半導体装置によれば、半導体基板上にベース領域、エミッタ領域に接続される配線パターンが形成された配線基板が固着配置され、半導体基板に形成された複数のスリット孔により素子領域及び外部接続電極領域とを分離し、それぞれコレクタ領域、ベース領域、及びエミッタ領域用の外部接続用極とし、エミッタ電極と接続される配線パターンが配線基板とが導通し、エミッタ電極と配線基板とが同電位にすることにより、従来の半導体装置のように、外部電極と接続する金属製のリード端子、保護用の封止モールドが不必要となり、半導体装置の外観寸法を著しく小型化にすることができると共にシールド効果が向上し、対ノイズ特性の優れた半導体装置を提供することができる。 As described above, according to the semiconductor device of the present invention, the wiring substrate on which the wiring pattern connected to the base region and the emitter region is fixedly disposed on the semiconductor substrate, and a plurality of slit holes formed in the semiconductor substrate. The element region and the external connection electrode region are separated from each other by the external connection poles for the collector region, the base region, and the emitter region, and the wiring pattern connected to the emitter electrode is electrically connected to the wiring substrate. By using the same potential as the wiring board, the metal lead terminals connected to the external electrodes and the protective sealing mold are not required as in conventional semiconductor devices, and the external dimensions of the semiconductor device are significantly reduced. In addition, it is possible to provide a semiconductor device with improved shielding effect and excellent anti-noise characteristics.
また、上記したように、外部接続用の金属リード端子、及び樹脂封止用モールドが不要であるために、半導体装置の製造コストを著しく低減化することができる。 Further, as described above, the metal lead terminal for external connection and the mold for resin sealing are unnecessary, so that the manufacturing cost of the semiconductor device can be significantly reduced.
本実施形態では、能動素子形成領域61にトランジスタを形成したが、縦型或いは比較的発熱量の少ない横型のデバイスであればこれに限らず、例えば、パワーMOSFET、IGBT、HBT等のデバイスに本発明を応用することができることは説明するまでもない。 In the present embodiment, the transistor is formed in the active element formation region 61. However, the transistor is not limited to this as long as it is a vertical type or a horizontal type device with a relatively small amount of heat generation. Needless to say, the invention can be applied.
ところで、上記の実施形態では、樹脂層78に光熱硬化性樹脂を用いて基板60の各電極と配線基板65の配線パターンとの電気的導通を行ったが、本発明では、この両者の電気的導通はいかなる手段にも応用することができ、例えば、図3に示す用に異方導電性樹脂を樹脂層78として用いても基板60の各電極と配線基板65の配線パターンとの接続が容易に行うことができる。 By the way, in the above-described embodiment, the photothermosetting resin is used for the resin layer 78 to electrically connect the electrodes of the substrate 60 and the wiring pattern of the wiring substrate 65. The continuity can be applied to any means. For example, even if an anisotropic conductive resin is used as the resin layer 78 as shown in FIG. 3, the connection of each electrode of the substrate 60 and the wiring pattern of the wiring substrate 65 is easy. Can be done.
異方導電性樹脂は、粒径の導電物81を樹脂ペースト中に混入したものと、粒径の導電物を樹脂シート中に散布したものとがあり、どちらのタイプの樹脂を用いることも可能である。異方導電性樹脂は両基板60、65上に形成された配線パターン等が重畳する領域が粒径の導電物81を介して電気的接続が行われるもである。異方導電性樹脂を用いる場合には、基板60上の各電極75、76、77及び配線基板65上の配線パターン67上のそれぞれにバンプ電極68を形成することが好ましい。 Anisotropic conductive resins include those in which conductive material 81 having a particle size is mixed in a resin paste and those in which conductive material having a particle size is dispersed in a resin sheet. Either type of resin can be used. It is. The anisotropic conductive resin is electrically connected through a conductive material 81 having a grain size in a region where wiring patterns and the like formed on both substrates 60 and 65 overlap. When an anisotropic conductive resin is used, it is preferable to form bump electrodes 68 on the electrodes 75, 76, 77 on the substrate 60 and the wiring pattern 67 on the wiring substrate 65.
例えば、異方導電性シートを基板60上に配置し、基板60上のバンプ電極68と配線基板65上のバンプ電極68とが一致するように位置あわせを行い両基板60、65に所定の圧力を加えながら約120℃程度の加熱処理を行い導電性シートを溶かして樹脂層78とし、粒径の導電物81により各電極75、76、77と配線パターン67との導通が行われる。各電極75、76、77、及び配線パターン67上にバンプ電極68を形成することで、配線パターン67と重畳するガードリング用電極とは異方導電性樹脂の導電物が接触されないため導通せず、確実に各電極75、76、77のバンプ電極68と配線基板65上のバンプ電極68とが接触し電気的導通が行われる。 For example, an anisotropic conductive sheet is disposed on the substrate 60 and aligned so that the bump electrodes 68 on the substrate 60 and the bump electrodes 68 on the wiring substrate 65 coincide with each other. The conductive sheet is melted to form a resin layer 78 by applying a heat treatment at about 120 ° C. while adding the conductive material 81, and the electrodes 75, 76, 77 are electrically connected to the wiring pattern 67 by the conductive material 81 having a particle size. By forming the bump electrode 68 on each of the electrodes 75, 76, 77 and the wiring pattern 67, the conductive material of the anisotropic conductive resin is not brought into contact with the guard ring electrode overlapping the wiring pattern 67. The bump electrode 68 of each electrode 75, 76, 77 and the bump electrode 68 on the wiring board 65 are surely in contact with each other, and electrical conduction is performed.
他の電気的導通の方法として、図4に示すように、両基板60、65上に形成したバンプ電極83、83を一致するように両基板60、65の位置合わせを行い、溶融しバンプ電極83、83の接続を行い、基板60上の各電極75、76、77と配線基板65上の配線パターン67との電気的導通が行われる。その後、両基板60、65に圧力を加えながら、両基板60、65のすき間に液状の熱硬化性樹脂からなる含浸材を流し込み熱処理を行い樹脂層78形成し、スリット孔80が形成される。 As another electrical conduction method, as shown in FIG. 4, the bump electrodes 83 and 83 formed on the both substrates 60 and 65 are aligned so that the both substrates 60 and 65 coincide with each other, and are melted to form bump electrodes. 83 and 83 are connected, and electrical connection between the electrodes 75, 76, 77 on the substrate 60 and the wiring pattern 67 on the wiring substrate 65 is performed. Thereafter, while applying pressure to both the substrates 60 and 65, an impregnating material made of a liquid thermosetting resin is poured between the substrates 60 and 65 to perform heat treatment, thereby forming the resin layer 78, and the slit holes 80 are formed.
本発明では、各電極75、76、77と配線パターン67とが接続されるものであれば、いかなる構造、いかなる材料を用いて行うことができる。 In the present invention, any structure and any material can be used as long as each electrode 75, 76, 77 and the wiring pattern 67 are connected.
以上に詳述したように、本発明の半導体装置によれば、、半導体基板上にベース領域、エミッタ領域に接続される配線パターンが形成された配線基板が固着配置され、半導体基板に形成された複数のスリット孔により素子領域及び外部接続電極領域とを分離し、それぞれコレクタ領域、ベース領域、及びエミッタ領域用の外部接続用極とし、エミッタ電極と接続される配線パターンが配線基板とが導通し、エミッタ電極と配線基板とが同電位にすることにより、従来の半導体装置のように、外部電極と接続する金属製のリード端子、保護用の封止モールドが不必要となり、半導体装置の外観寸法を著しく小型化にすることができると共にシールド効果が向上し、対ノイズ特性の優れた半導体装置を提供することができる。 As described in detail above, according to the semiconductor device of the present invention, the wiring substrate on which the wiring pattern connected to the base region and the emitter region is formed is fixedly disposed on the semiconductor substrate and formed on the semiconductor substrate. The element region and the external connection electrode region are separated from each other by a plurality of slit holes, and are used as external connection electrodes for the collector region, base region, and emitter region, respectively, and the wiring pattern connected to the emitter electrode is electrically connected to the wiring substrate. By setting the emitter electrode and the wiring board to the same potential, the metal lead terminal connected to the external electrode and the protective sealing mold are unnecessary as in the conventional semiconductor device, and the external dimensions of the semiconductor device Can be remarkably reduced in size and the shielding effect can be improved, and a semiconductor device having excellent anti-noise characteristics can be provided.
また、上記したように、外部接続用の金属リード端子、及び樹脂封止用モールドが不要であるために、半導体装置の製造コストを著しく低減化することができる。 Further, as described above, the metal lead terminal for external connection and the mold for resin sealing are unnecessary, so that the manufacturing cost of the semiconductor device can be significantly reduced.
60:半導体基板
61:能動素子形成領域
65:配線基板
67:配線パターン
60: Semiconductor substrate 61: Active element formation region 65: Wiring substrate 67: Wiring pattern
Claims (1)
前記シリコンから成る基板上に実装され、表面には能動素子が形成されたシリコンから成る半導体基板とを有し、Mounted on a substrate made of silicon, and having a semiconductor substrate made of silicon on which active elements are formed on the surface;
前記半導体基板の能動素子と前記開口部から露出する前記配線パターンの他端を電気的に接続し、前記配線パターンの一端を前記シリコン基板と電気的に接続し、Electrically connecting the active element of the semiconductor substrate and the other end of the wiring pattern exposed from the opening; electrically connecting one end of the wiring pattern to the silicon substrate;
前記シリコンから成る基板を前記半導体基板を構成するシリコンから成すことで、熱応力の発生を抑制し、前記シリコンから成る基板にシールド効果を持たせた事を特徴とした半導体装置。A semiconductor device characterized in that the substrate made of silicon is made of silicon constituting the semiconductor substrate, thereby suppressing generation of thermal stress and providing a shielding effect to the substrate made of silicon.
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