[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JP4024531B2 - Thermistor built-in power semiconductor module - Google Patents

Thermistor built-in power semiconductor module Download PDF

Info

Publication number
JP4024531B2
JP4024531B2 JP2001383927A JP2001383927A JP4024531B2 JP 4024531 B2 JP4024531 B2 JP 4024531B2 JP 2001383927 A JP2001383927 A JP 2001383927A JP 2001383927 A JP2001383927 A JP 2001383927A JP 4024531 B2 JP4024531 B2 JP 4024531B2
Authority
JP
Japan
Prior art keywords
power semiconductor
semiconductor chip
thermistor
power
copper circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001383927A
Other languages
Japanese (ja)
Other versions
JP2003188336A (en
Inventor
茂 岡本
秀久 橘
成治 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sansha Electric Manufacturing Co Ltd
Original Assignee
Sansha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sansha Electric Manufacturing Co Ltd filed Critical Sansha Electric Manufacturing Co Ltd
Priority to JP2001383927A priority Critical patent/JP4024531B2/en
Publication of JP2003188336A publication Critical patent/JP2003188336A/en
Application granted granted Critical
Publication of JP4024531B2 publication Critical patent/JP4024531B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Power Conversion In General (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an increase in switching loss even when the temperature of a semiconductor chip rises, though the conventional semiconductor module for electric power comprising an inverter, where a plurality of semiconductor chips for electric power such as IGBTs or FETs are fixed to a copper circuit, has such a demerit that the temperature of the semiconductor chip increases as conductive current increases and switching loss is made large, and furthermore the temperature increases as a result. <P>SOLUTION: A thermistor is arranged near a semiconductor chip for electric power on a copper circuit, and it is electrically connected with a gate, so that the resistance value of the gate is reduced when the temperature increases. In such a circuit, switching loss can be reduced because the resistance value of the gate is made small even when the temperature increases. <P>COPYRIGHT: (C)2003,JPO

Description

【0001】
【発明の属する技術分野】
本発明は,サーミスタを内蔵した電力用半導体モジュールに関するものである。
【0002】
【従来の技術】
IGBTまたはFETの電力用半導体チップを複数個,銅回路に固着して電気回路たとえばインバータを形成し,放熱用金属ベース下面及び端子金具の先端を除く全体を樹脂モールドした電力用半導体モジュールでは,通電する電流が大きくなりIGBT又はFETの温度が高くなるほどスイッチング損失が大きくなって,この損失が熱となって益々高温になり遂に半導体チップを焼損することがあった。このため上記半導体チップに通電する電流が制限値を越えるときはこれを検出するための電流検出手段と電流を停止する為の電流遮断手段を必要とした。使用環境の温度が高い場合には,負荷電流の変化が起こったとき使用中突然に電流が停止する事態も発生した。
【0003】
【発明が解決しようとする課題】
上記のようなIGBT又はFETなど半導体チップの温度が高くなるほどスイッチング損失が大きくなって,遂に半導体チップを焼損する従来の欠点を排除し,温度が高くなっても,これに伴ってスイッチング損失が大きくならない電力用半導体モジュールに改良することが本発明の目的である。
【0004】
【課題を解決するための手段】
上記の目的を達成するため、半導体チップの接合温度とスイッチング損失の関係を究明した。一方でIGBTまたはFETのゲート抵抗値とスイッチング損失の関係を究明し、スイッチング損失はゲート抵抗値の減少と共に小さくなる特性を見出したので、この特性を応用して以下に述べる構成とした。金属ベース上面に絶縁層を介して銅回路を形成し、該銅回路上には直列接続された2つのIGBT又はFETの電力用半導体チップを2組並列接続して、インバータ等の電気回路を形成した電力用半導体モジュールに於いて、電気回路を構成する要素である複数のIGBTまたはFETの各ゲートにそれぞれ直列に温度が高くなるにつれて抵抗値が小さくなるサーミスタを接続し、該サーミスタはIGBTまたはFETの電力用半導体チップに略同等の温度となるように電力用半導体チップに近い位置の銅回路に配置した。該半導体チップのゲートに該サーミスタが直列に接続されて制御端子金具に接続されて外部に導出される。該半導体チップの電力を外部へ接続するための電力端子金具を具備し、銅回路と該半導体チップとサーミスタ及び、電力端子金具と制御端子金具の先端を除く部分とを覆う充填材によって充填され、上記金属ベースの下面を露出して電力用半導体モジュールが形成される。
【0005】
上記半導体チップの近傍にサーミスタを配置し,該半導体チップのゲートに該サーミスタを直列接続して該サーミスタに直列に抵抗器を接続したり,更に該サーミスタと直列抵抗を接続したものに並列に抵抗器を接続して制御用端子に接続し導出されることも有効である。
【0006】
上記IGBT又はFETのゲートに直列にサーミスタが接続されると温度が高くなるにつれて抵抗値が小さくなるサーミスタの特性の影響を受けて,全合成抵抗のゲート抵抗値は高温になればなるほど小さくなる方向に作用する。従って上記のようにゲート抵抗が小であるとき,スイッチング損失が小であるから,高温になるにつれてスイッチング損失が小さくなる。
【0007】
【発明の実施の形態】
本発明による実施の形態を図1と図2によって説明する。図2おいて,5,6,7,8はIGBTまたはFETの電力用半導体素子で,電力用半導体素子5と6は直列に接続され,電力用半導体素子7と8は直列に接続されている。この電力用半導体素子の直列回路は並列に接続されてインバータの機能を持つ電気回路が構成されている。それぞれの電力用半導体素子5,6,7,8のゲートには,直列にサーミスタ9が接続され,このサーミスタ9と直列に抵抗10が接続され,さらにサーミスタ9と抵抗10との直列回路と並列に抵抗11が接続されて,電力用半導体素子のスイッチング損失が大きくならないにしている。
【0008】
図1はインバータの機能を持つ電気回路を構成した場合の電力用半導体モジュールの構造図を示す。金属ベース1の表面に絶縁層2を介して銅回路3が形成されている回路基板に電力用半導体チップ5,6,7,8やサーミスタ9,抵抗器10、11などのチップ部品が固着され,半導体チップ間は金属片12で電気接続されたり銅回路3で電気接続されている。サーミスタ9は該半導体チップに近い位置の銅回路3に配置され,半導体チップ温度に略同等になるように固着されている。該半導体チップのゲートはボンディングワイヤ15で電気接続されて,抵抗器10を介して制御端子金具13に接続されて導出される。抵抗器10を省いて制御端子金具13に直接接続される場合も有効であり,抵抗器11がゲートと制御端子金具13との中間に接続されることも有効である。金属ベース1の部品搭載側全体を図示しない充填材で覆って電力用半導体モジュールが形成される。充填材は例えばエポキシ樹脂などの充填用絶縁物である。
【0009】
電力用半導体チップ5,6,7,8は銅回路3にそれぞれ固着されていて該銅回路に接続された電力端子金具14によって外部に導出されている。制御端子金具13と電力用半導体チップ5,6,7,8のゲートの中間に接続されたサーミスタ9に直列接続の抵抗器10は抵抗値ゼロの場合もある,すなわちサーミスタ単体で要求される抵抗値が得られる場合には抵抗器10も抵抗器11も不要でありサーミスタ9から制御端子金具に直接接続される銅回路を形成することも有効である。以上に述べた実施例は基本回路に対してのみ図示しているが,半導体の保護回路部品を組み込んで一体化してしまう場合や,交流を直流に整流する回路などの周辺回路を構成する回路部品を組み込んで総合的な機能を持つ電力用半導体モジュールとして形成されることも実施例の範囲に含むものとする。
【0010】
【発明の効果】
本発明によれば,IGBTまたはFETなど電力用半導体チップの温度が高くなるほどスイッチング損失が大きくなって,益々高温になり遂に半導体チップを焼損するという従来の欠点を排除することが出来たので,電流検出手段や電流遮断手段を必要とした従来の電力半導体モジュールより小型に形成することが可能となり製作工数が低減出来たほか材料の削減により安価に提供でき,そのうえ省資源,省エネルギーにも寄与できたので工業的価値が大きい。
【図面の簡単な説明】
【図1】 本発明による一実施形態を示すサーミスタ内蔵電力用半導体モジュールの構造斜視図。
【図2】 本発明による一実施形態を示すサーミスタ内蔵電力用半導体モジュールの回路図。
【符号の説明】
1 金属ベース
2 絶縁層
3 銅回路
4 回路基板
5,6,7,8 電力用半導体チップ
9 サーミスタ
10,11 抵抗器
12 金属片
13 制御端子金具
14 電力端子金具
15 ボンディングワイヤ
16 充填材
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power semiconductor module incorporating a thermistor.
[0002]
[Prior art]
In a power semiconductor module in which a plurality of IGBT or FET power semiconductor chips are fixed to a copper circuit to form an electric circuit, for example, an inverter, and the entire surface except the bottom surface of the heat dissipating metal base and the terminal fitting is resin molded. As the current flowing increases and the temperature of the IGBT or FET increases, the switching loss increases. This loss becomes heat, and the semiconductor chip may eventually burn out. For this reason, when the current applied to the semiconductor chip exceeds the limit value, a current detecting means for detecting this and a current interrupting means for stopping the current are required. When the temperature of the usage environment was high, there was a situation where the current suddenly stopped during use when the load current changed.
[0003]
[Problems to be solved by the invention]
As the temperature of the semiconductor chip such as IGBT or FET as described above increases, the switching loss increases. Finally, the conventional defect of burning the semiconductor chip is eliminated, and the switching loss increases as the temperature increases. It is an object of the present invention to improve to a power semiconductor module that does not become.
[0004]
[Means for Solving the Problems]
In order to achieve the above object, the relationship between the semiconductor chip junction temperature and the switching loss was investigated. On the other hand, the relationship between the gate resistance value of the IGBT or FET and the switching loss was investigated, and the characteristic that the switching loss becomes smaller as the gate resistance value decreases was found. A copper circuit is formed on the upper surface of the metal base via an insulating layer, and two sets of power semiconductor chips of two IGBTs or FETs connected in series are connected in parallel on the copper circuit to form an electric circuit such as an inverter. In the power semiconductor module, a thermistor having a resistance value that decreases as the temperature rises in series is connected to each gate of a plurality of IGBTs or FETs that are elements constituting an electric circuit, and the thermistors are IGBTs or FETs. It was arranged on a copper circuit at a position close to the power semiconductor chip so as to have a temperature substantially equal to that of the power semiconductor chip . The thermistor is connected in series to the gate of the semiconductor chip, is connected to the control terminal fitting, and is led out to the outside. A power terminal fitting for connecting the power of the semiconductor chip to the outside is provided, and is filled with a filler that covers the copper circuit, the semiconductor chip and the thermistor, and the power terminal fitting and the portion excluding the tip of the control terminal fitting, A power semiconductor module is formed by exposing the lower surface of the metal base.
[0005]
A thermistor is disposed in the vicinity of the semiconductor chip, the thermistor is connected in series to the gate of the semiconductor chip, and a resistor is connected in series to the thermistor. It is also effective to connect and connect to a control terminal.
[0006]
When a thermistor is connected in series to the gate of the IGBT or FET, the resistance value decreases as the temperature increases, and the gate resistance value of the total combined resistance decreases as the temperature increases. Act on. Therefore, when the gate resistance is small as described above, the switching loss is small, so that the switching loss decreases as the temperature increases.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment according to the present invention will be described with reference to FIGS. In FIG. 2, reference numerals 5, 6, 7 and 8 denote IGBT or FET power semiconductor elements. The power semiconductor elements 5 and 6 are connected in series, and the power semiconductor elements 7 and 8 are connected in series. . The series circuit of the power semiconductor elements is connected in parallel to form an electric circuit having the function of an inverter. A thermistor 9 is connected in series to the gate of each power semiconductor element 5, 6, 7, 8, a resistor 10 is connected in series with the thermistor 9, and in parallel with a series circuit of the thermistor 9 and resistor 10. The resistor 11 is connected to the power semiconductor element so that the switching loss of the power semiconductor element does not increase.
[0008]
FIG. 1 is a structural diagram of a power semiconductor module when an electric circuit having an inverter function is configured. Chip components such as power semiconductor chips 5, 6, 7, 8, thermistor 9, resistors 10, 11 are fixed to a circuit board on which a copper circuit 3 is formed on the surface of the metal base 1 via an insulating layer 2. The semiconductor chips are electrically connected by a metal piece 12 or by a copper circuit 3. The thermistor 9 is disposed on the copper circuit 3 at a position close to the semiconductor chip, and is fixed so as to be substantially equal to the semiconductor chip temperature. The gate of the semiconductor chip is electrically connected by a bonding wire 15 and is connected to a control terminal fitting 13 via a resistor 10 and led out. It is also effective when the resistor 10 is omitted and it is directly connected to the control terminal fitting 13, and it is also effective that the resistor 11 is connected between the gate and the control terminal fitting 13. A power semiconductor module is formed by covering the entire component mounting side of the metal base 1 with a filler (not shown). The filler is a filling insulator such as an epoxy resin.
[0009]
The power semiconductor chips 5, 6, 7, and 8 are fixed to the copper circuit 3 and led out to the outside by power terminal fittings 14 connected to the copper circuit. The resistor 10 connected in series to the thermistor 9 connected between the control terminal fitting 13 and the gate of the power semiconductor chip 5, 6, 7, 8 may have a zero resistance value, that is, the resistance required for the thermistor alone. When the value is obtained, neither the resistor 10 nor the resistor 11 is required, and it is also effective to form a copper circuit that is directly connected from the thermistor 9 to the control terminal fitting. Although the embodiment described above is shown only for the basic circuit, the circuit component constituting the peripheral circuit such as the circuit for rectifying the alternating current into the direct current when the semiconductor protective circuit component is incorporated and integrated. It is also included in the scope of the embodiment to be formed as a power semiconductor module having a comprehensive function.
[0010]
【The invention's effect】
According to the present invention, since the switching loss increases as the temperature of the power semiconductor chip such as IGBT or FET increases, the conventional defect that the semiconductor chip is burned out at higher temperatures can be eliminated. It can be made smaller than conventional power semiconductor modules that require detection means and current interrupting means, and the number of manufacturing steps can be reduced. In addition, it can be provided at low cost by reducing the materials, and also contributes to resource and energy savings. So industrial value is great.
[Brief description of the drawings]
FIG. 1 is a structural perspective view of a power semiconductor module with a built-in thermistor according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of a thermistor built-in power semiconductor module according to an embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Metal base 2 Insulation layer 3 Copper circuit 4 Circuit board 5, 6, 7, 8 Power semiconductor chip 9 Thermistor 10, 11 Resistor 12 Metal piece 13 Control terminal metal fitting 14 Power terminal metal fitting 15 Bonding wire 16 Filler

Claims (1)

金属ベースの上面に絶縁層を介して銅回路を形成し該銅回路上に直列接続された2つのIGBT又はFETの電力用半導体チップを2組並列接続して電気回路を構成し、該電気回路の電力を外部へ接続するための電力端子金具を具備し、銅回路と該電力用半導体チップ及び先端を除く電力端子金具を覆う充填材によって充填され該電力端子金具を導出するとともに上記金属ベースの下面を露出して形成される電力用半導体モジュールにおいて、温度が高くなるにつれて抵抗値が小さくなるサーミスタを備え、該サーミスタを上記電力用半導体チップに略同等の温度となるように該電力用半導体チップに近い位置の銅回路に配置し、該半導体チップのゲートに該サーミスタをそれぞれ直列接続して制御用端子として導出されたことを特徴とするサーミスタ内臓電力用半導体モジュールA copper circuit is formed on an upper surface of a metal base via an insulating layer, and two sets of power semiconductor chips of two IGBTs or FETs connected in series on the copper circuit are connected in parallel to form an electric circuit. A power terminal fitting for connecting the electric power to the outside, filled with a filler covering the copper circuit, the power semiconductor chip and the power terminal fitting excluding the tip, and leading out the power terminal fitting and A power semiconductor module formed by exposing a lower surface includes a thermistor whose resistance value decreases as the temperature increases, and the power semiconductor chip has a temperature substantially equal to that of the power semiconductor chip. placed copper circuit position close to, be characterized by the thermistor to the gate of the semiconductor chip is derived as the respective terminal control connected in series Semiconductor module for thermistor visceral power
JP2001383927A 2001-12-18 2001-12-18 Thermistor built-in power semiconductor module Expired - Fee Related JP4024531B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001383927A JP4024531B2 (en) 2001-12-18 2001-12-18 Thermistor built-in power semiconductor module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001383927A JP4024531B2 (en) 2001-12-18 2001-12-18 Thermistor built-in power semiconductor module

Publications (2)

Publication Number Publication Date
JP2003188336A JP2003188336A (en) 2003-07-04
JP4024531B2 true JP4024531B2 (en) 2007-12-19

Family

ID=27593795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001383927A Expired - Fee Related JP4024531B2 (en) 2001-12-18 2001-12-18 Thermistor built-in power semiconductor module

Country Status (1)

Country Link
JP (1) JP4024531B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9917435B1 (en) 2016-09-13 2018-03-13 Ford Global Technologies, Llc Piecewise temperature compensation for power switching devices
US10122357B2 (en) 2016-11-14 2018-11-06 Ford Global Technologies, Llc Sensorless temperature compensation for power switching devices

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200530566A (en) 2004-03-05 2005-09-16 Hitachi Ind Equipment Sys Method for detecting temperature of semiconductor element and semiconductor power converter
JP4366269B2 (en) * 2004-07-30 2009-11-18 株式会社日立産機システム Semiconductor element temperature detection method and power conversion device
JP4802499B2 (en) * 2005-01-07 2011-10-26 トヨタ自動車株式会社 Power control circuit and vehicle
JP4816182B2 (en) * 2006-03-23 2011-11-16 株式会社日立製作所 Switching element drive circuit
US8420987B2 (en) 2008-11-18 2013-04-16 Electronics And Telecommunications Research Institute Thermistor with 3 terminals, thermistor-transistor, circuit for controlling heat of power transistor using the thermistor-transistor, and power system including the circuit
KR101312267B1 (en) * 2008-11-18 2013-09-25 한국전자통신연구원 Thermistor with 3 terminals, thermistor-transistor, circuit for controlling heat of power transistor using the same thermistor-transistor, and power system comprising the same circuit
DE102011007271B4 (en) 2010-04-19 2022-08-11 Electronics And Telecommunications Research Institute Variable gate field effect transistor
JP6040656B2 (en) * 2012-09-13 2016-12-07 富士電機株式会社 Semiconductor device
JP6044215B2 (en) 2012-09-13 2016-12-14 富士電機株式会社 Semiconductor device
DE102013112261B4 (en) * 2013-11-07 2023-01-26 Semikron Elektronik Gmbh & Co. Kg power semiconductor circuit
DE112019007678T5 (en) 2019-08-27 2022-06-15 Mitsubishi Electric Corporation POWER SEMICONDUCTOR MODULE AND POWER CONVERTER
JP7322654B2 (en) 2019-10-15 2023-08-08 富士電機株式会社 semiconductor module
JP7396118B2 (en) 2020-02-28 2023-12-12 富士電機株式会社 semiconductor module
JP7508946B2 (en) 2020-08-26 2024-07-02 富士電機株式会社 Semiconductor Module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9917435B1 (en) 2016-09-13 2018-03-13 Ford Global Technologies, Llc Piecewise temperature compensation for power switching devices
US10122357B2 (en) 2016-11-14 2018-11-06 Ford Global Technologies, Llc Sensorless temperature compensation for power switching devices

Also Published As

Publication number Publication date
JP2003188336A (en) 2003-07-04

Similar Documents

Publication Publication Date Title
JP4024531B2 (en) Thermistor built-in power semiconductor module
US6563211B2 (en) Semiconductor device for controlling electricity
US7848104B2 (en) Power module
US20080106160A1 (en) Power Module and Motor Integrated Control Unit
US6841866B2 (en) Power semiconductor device
US8423317B2 (en) Temperature detection method of semiconductor device and power conversion apparatus
US20140063747A1 (en) Cooling structure for a shunt resistor and inverter apparatus using the same
JP2001210784A (en) Flexible power device
JP4985810B2 (en) Semiconductor device
US11349470B2 (en) Gate driver and protection system for a solid-state switch
Liang et al. Planar bond all: A new packaging technology for advanced automotive power modules
CN110838712A (en) Intelligent power module and air conditioner
CN107492531B (en) Semiconductor device with a plurality of semiconductor chips
JP3889562B2 (en) Semiconductor device
US20090121777A1 (en) Semiconductor device, semiconductor device manufacturing method, power control device, and electronic equipment and module
JP2002368192A (en) Semiconductor device
JP5370308B2 (en) Semiconductor device, semiconductor device manufacturing method, and semiconductor device mounting method
CN209592033U (en) Power semiconductor modular and vehicle
JP5909396B2 (en) Circuit equipment
JP4631179B2 (en) Semiconductor device and inverter device using the same
JP4366269B2 (en) Semiconductor element temperature detection method and power conversion device
US20240096844A1 (en) Bonded connection means
US12133366B2 (en) Power electronics module with improved cooling
CN114730748A (en) Power module with encapsulated power semiconductor for the controlled supply of electrical power to consumers and method for producing the same
JP4375299B2 (en) Power semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040816

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070508

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070706

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070807

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070829

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20071002

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20071003

R150 Certificate of patent or registration of utility model

Ref document number: 4024531

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101012

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111012

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121012

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131012

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees