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JP4019717B2 - Component built-in multilayer wiring module substrate and manufacturing method thereof - Google Patents

Component built-in multilayer wiring module substrate and manufacturing method thereof Download PDF

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Publication number
JP4019717B2
JP4019717B2 JP2002007131A JP2002007131A JP4019717B2 JP 4019717 B2 JP4019717 B2 JP 4019717B2 JP 2002007131 A JP2002007131 A JP 2002007131A JP 2002007131 A JP2002007131 A JP 2002007131A JP 4019717 B2 JP4019717 B2 JP 4019717B2
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Japan
Prior art keywords
conductor layer
component
layer
multilayer wiring
electrodes
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JP2002007131A
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Japanese (ja)
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JP2003209362A (en
Inventor
達広 岡野
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Toppan Inc
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Toppan Inc
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Description

【0001】
【発明の属する技術分野】
本発明は、半導体パッケージ用多層配線回路基板に関し、特に配線層間に部品を埋め込んで形成した部品内蔵多層配線モジュール基板に関する。
【0002】
【従来の技術】
従来の配線回路基板は、配線基板の表面に部品を実装した表面実装が行われており、抵抗素子やコンデンサは配線基板の配線層の所望の部分にハンダ、導電接着剤などの接合部材を用いて表面実装が行われている。
【0003】
従来の配線基板では、基板表面に抵抗素子やコンデンサなどが隙間なく実装されており、そのため配線基板の配線密度は高密度化されるとともに複雑化が進んでいる。こような状況では、特に高密度多層配線基板では配線基板の表面実装だけでは限界があり、更なる部品実装密度の向上が求められている。
また、多層配線基板の配線密度が向上するにつれて多層配線基板の検査が困難となりさらに収率も低下する傾向にある。
【0004】
【発明が解決しようとする課題】
本発明は、上記要望に鑑み考案されたもので、高密度多層配線基板の部品実装密度を向上させた部品内蔵多層配線モジュール基板及びその製造方法を提供することを目的とする。
【0005】
【課題を解決するための手段】
本発明に於いて上記問題を解決するために、まず請求項1においては、絶縁基材の両面に配線層及び絶縁層が所定層数形成された多層配線基板の基板内部に部品が内蔵された部品内蔵多層配線モジュール基板であって、前記部品は抵抗素子、コンデンサ、インダクタからなり、前記多層配線基板に形成された貫通孔もしくは開口部に埋め込まれ、前記部品の両端の電極はかしめられ、かつ前記部品の両端の電極が前記配線層に電気的に接続されており、前記部品の両端の電極に金皮膜が形成されていることを特徴とする部品内蔵多層配線モジュール基板としたものである。
【0007】
さらにまた、請求項においては、以下の工程を備えていることを特徴とする請求項1に記載の部品内蔵多層配線モジュール基板の製造方法としたものである。
(a)絶縁基材の両面に導体層を形成する工程。
(b)前記絶縁基材及び導体層の所定位置に貫通孔を形成する工程。
(c)前記貫通孔に両端の電極に金皮膜が形成された部品を埋め込み、かしめる工程。
(d)前記導体層をパターニング加工し、配線層を形成する工程。
(e)前記絶縁基材及び前記配線層の両面に絶縁層を形成する工程。
(f)前記絶縁層の所定位置に開口部を形成する工程。
(g)前記絶縁層上前記開口部内壁に薄膜導体層を形成する工程。
(h)両端の電極に金皮膜が形成された前記部品の一方の電極を下にして、前記薄膜導体層が形成された前記開口部に埋め込む工程。
(i)前記薄膜導体層及び前記部品の両端の電極上に電解めっきにて所定厚の第2導体層を形成し、前記部品の他方の電極と前記導体層を電気的に接続する工程。
(j)前記第2導体層をパターニング加工し、第2配線層を形成する工程。
(k)工程(e)〜工程(j)の工程を必要回数繰り返して、所定層数の部品内蔵多層配線モジュール基板を作製する工程。
【0008】
本発明の部品内蔵多層配線モジュール基板は、部品を多層配線基板内部に内蔵することで多層配線基板表面の実装部品点数を減少させ、且つ部品の実装密度を向上させたもので、部品内蔵多層配線モジュール基板の製造方法は、ビルドアップ多層配線基板の製造法がそのまま適用できるのが特徴である。
【0009】
【発明の実施の形態】
本発明の実施の形態につき説明する。
図1に、本発明の部品内蔵多層配線モジュール基板の一実施例を示す模式構成部分断面図を、図2(a)〜(f)及び図3(g)〜(j)に、本発明の部品内蔵多層配線モジュール基板の製造方法の一例を工程順に示す模式構成部分断面図をそれぞれ示す。
本発明の部品内蔵多層配線モジュール基板100は図1に示すように、多層配線基板内の絶縁基材11及び配線層間の絶縁層51に部品40を埋め込んで多層配線モジュール基板を形成したもので、このように部品を立体的に配置することにより、従来の表面実装に比べて部品の実装密度を向上させたものである。
【0010】
内蔵できる部品(受動素子)は、抵抗素子、コンデンサ、インダクタであり、例えばセラミック製の部品の両端に金属製の電極を付設したもので、この両端の電極に工夫がしてある。後記する両面に導体層が形成された絶縁基材の貫通孔に部品を挿入し、かしめで部品を固定する場合には部品が確実に固定され、電気的導通も確実にとれるようになっている。例えば、電極の材質を銅にすることで、部品挿入後かしめて固定する時に潰れやすい構造にするとか、配線層との電気的導通をとるのに電解銅めっき等でで容易にできること等である。また、接続信頼性を確保するため、部品両端の電極表面に金皮膜が形成されており、銅と接触して金が拡散することにより、時間の経過とともに接続信頼性が向上するようになっている。
【0011】
以下、本発明の部品内蔵多層配線モジュール基板の製造方法について説明する。
まず、絶縁基材11の両面に銅箔を積層して導体層21を形成した両面銅貼り積層板を準備する(図2(a)参照)。
次に、両面銅貼り積層板の所定位置に打ち抜きによって貫通孔31を形成する(図2(b)参照)。
【0012】
次に、貫通孔31に貫通孔径と同じ外径である両端の電極41に金皮膜が形成された部品(抵抗素子40R、コンデンサ40C、インダクタ40Lのいずれか)40を挿入する。挿入後に電極41をかしめて、電極41をつぶすことで部品40が貫通孔31から抜けないように加工される。さらに、部品40両端の電極41と導体層21上に電解銅めっきによって数μmの薄膜導体層(特に図示せず)を形成し、部品40両端の電極41と導体層21との電気的接合を確実に行う(図2(c)参照)。
ここで、部品40の抵抗素子40R、コンデンサ40C及びインダクタ40Lの一例を図4(a、b及びc)に示す。抵抗素子40Rはセラミック外装管42の内部に抵抗体43が充填されており、両端に電極41が形成されたものである(図4(a)参照)。コンデンサ40Cはセラミック外装管42の内部に誘電体44が充填されており、両端に電極41が形成されたものである(図4(b)参照)。インダクタ40Lはセラミック外装管42の内部に誘電体45に巻かれたコイル46が設置され、両端に電極41が形成されたものである(図4(c)参照)。さらに、電極41の表面には金皮膜(特に表示せず)が形成されている。
【0013】
次に、導体層21をパターニング処理して、部品40と電気的に接続された第1配線層21a及び第1配線層21bを形成する(図2(d)参照)。
【0014】
次に、絶縁接着フィルを両面に貼り合わせ所定厚の絶縁層51を形成する(図2(e)参照)。ここで、絶縁層51の厚さは絶縁層に取り付ける部品の高さによって決定する。
次に、絶縁層51の所定位置にレーザー加工等により部品40の外径と同じ径の開口部52を形成する(図2(f)参照)。
【0015】
次に、無電解銅めっきにより絶縁層51上及び開口部52の内壁に所定厚の薄膜導体層61を形成する(図3(g)参照)。
ここで、薄膜導体層61は部品を取り付ける際の部品の電極と電気的接続を図るためと、薄膜導体層61をカソード電極にして導体層を形成するための電極として利用するものである。
【0016】
次に、薄膜導体層61が形成された開口部52に両端に電極41が形成された部品(抵抗素子40R、コンデンサ40C、インダクタ40Lのいずれか)40の一方の電極41に導電接着剤等を塗布し、導電接着剤塗布面の電極41を下にして挿入し、加熱して配線層導電接着剤を硬化させる(図3(h)参照)。
ここで、部品40の一方の電極41と第1配線層21a及び第1配線層21bとの電気的接続が確実に行われる。
次に、薄膜導体層61をカソード電極にして電解銅めっきを行い、薄膜導体層61上に導体層62を形成する(図3(i)参照)。
ここで、部品40の他方の電極41と導体層62との電気的接続が確実に行われる。
【0017】
次に、薄膜導体層61及び導体層62をパターニング処理して第2配線層62a及び第2配線層62bを形成し、部品40が内蔵された4層の部品内蔵多層配線モジュール基板100を得る(図3(j)参照)。
さらに必要であれば、上記絶縁層形成、開口部形成、部品取り付け、配線層形成工程を繰り返すことにより、所望の層数の部品内蔵多層配線モジュール基板を得ることができる。
【0018】
【実施例】
以下、実施例により本発明を詳細に説明する。
<実施例1>
まず、50μm厚のポリイミドフィルムからなる絶縁基材11の両面に12μm厚の銅箔を貼り合わせて導体層21を形成した(図2(a)参照)。
次に、100μmφの凸部を有する金型を用いてプレス穴明け加工を行い、絶縁基材11及び導体層21に抵抗素子40Rの外径と同じ径の貫通孔31を形成した(図2(b)参照)。
次に、図4(a)に示す両端の電極41に金皮膜が形成された抵抗素子40Rを貫通孔31に挿入し、両端の電極41をかしめた(図2(c)参照)。
【0019】
次に、抵抗素子40R両端の電極41と導体層21上に電解銅めっきによって2μm厚の薄膜導体層(特に図示せず)を形成し、薄膜導体層及び導体層21をパターニング処理して、抵抗素子40Rの電極41と電気的に接続された第1配線層21a及び第2配線層21bを形成した(図2(d)参照)。
【0020】
次に、50μm厚のポリイミドフィルムを貼り合わせて、絶縁層51を形成した(図2(e)参照)。
次に、絶縁層51の所定位置にレーザー加工によりコンデンサ40Cの外径と同じ径の開口部52を形成した(図2(f)参照)。
【0021】
次に、無電解銅めっきにより絶縁層51上及び開口部52の内壁に2μm厚の薄膜導体層61を形成した(図3(g)参照)。
次に、薄膜導体層61が形成された開口部52に図4(b)に示す両端の電極に金皮膜が形成されたコンデンサ40Cの一方の電極41に導電接着剤等を塗布し、導電接着剤塗布面の電極41を下にして挿入し、加熱して配線層導電接着剤を硬化させた(図3(h)参照)。
【0022】
次に、薄膜導体層61をカソード電極にして電解銅めっきを行い、薄膜導体層61上に導体層62を形成した(図3(i)参照)。
次に、薄膜導体層61及び導体層62をパターニング処理して第2配線層62a及び第2配線層62bを形成し、抵抗素子40R及びコンデンサ40Cが内蔵された4層の部品内蔵多層配線モジュール基板100を得た(図3(j)参照)。
【0023】
<実施例2>
まず、50μm厚のポリイミドフィルムからなる絶縁基材11の両面に12μm厚の銅箔を貼り合わせて導体層21を形成した(図2(a)参照)。
次に、100μmφの凸部を有する金型を用いてプレス穴明け加工を行い、絶縁基材11及び導体層21にコンデンサ40Cの外径と同じ径の貫通孔31を形成した(図2(b)参照)。
次に、図4(b)に示す両端の電極41に金皮膜が形成されたコンデンサ40Cを貫通孔31に挿入し、両端の電極41をかしめた(図2(c)参照)。
【0024】
次に、コンデンサ40C両端の電極41と導体層21上に電解銅めっきによって2μm厚の薄膜導体層(特に図示せず)を形成し、薄膜導体層及び導体層21をパターニング処理して、コンデンサ40Cの電極41と電気的に接続された第1配線層21a及び第1配線層21bを形成した(図2(d)参照)。
【0025】
次に、50μm厚のポリイミドフィルムを貼り合わせて、絶縁層51を形成した(図2(e)参照)。
次に、絶縁層51の所定位置にレーザー加工によりインダクタ40Lの外径と同じ径の開口部52を形成した(図2(f)参照)。
【0026】
次に、無電解銅めっきにより絶縁層51上及び開口部52の内壁に2μm厚の薄膜導体層61を形成した(図3(g)参照)。
次に、薄膜導体層61が形成された開口部52に図4(c)に示す両端の電極に金皮膜が形成されたインダクタ40Lの一方の電極41に導電接着剤等を塗布し、導電接着剤塗布面の電極41を下にして挿入し、加熱して配線層導電接着剤を硬化させた(図3(h)参照)。
【0027】
次に、薄膜導体層61をカソード電極にして電解銅めっきを行い、導体層62を形成した(図3(i)参照)。
次に、薄膜導体層61及び導体層62をパターニング処理して第2配線層62a及び第2配線層62bを形成し、コンデンサ40C及びインダクタ40Lが内蔵された4層の部品内蔵多層配線モジュール基板100を得た(図3(j)参照)。
【0028】
【発明の効果】
本発明の部品内蔵多層配線モジュール基板を用いることで、今まで基板表面にに実装されていた抵抗素子、コンデンサ及びインダクタを立体的に配置することができ、部品実装密度を向上することができる。
また、配線層のレイアウトにも余裕ができ、配線基板の配線幅が広くとれることで信号の減衰が減少し、配線基板の収率を向上できる。
さらに、部品の両端の電極表面に金めっき皮膜を形成することにより、銅からなる配線層との拡散性を利用して、電極と配線層の電気的導通を確かなものとすることができる。
また、絶縁基材と導体層が形成された貫通孔に部品を固定する際かしめを行うので、部品の固定と電気的導通が確実にできるので、製造歩留まりが向上する利点がある。
【図面の簡単な説明】
【図1】本発明の部品内蔵多層配線モジュール基板の一実施例を示す模式構成部分断面図である。
【図2】(a)〜(f)に、本発明の部品内蔵多層配線モジュール基板の製造方法の一例の一部を示す模式構成部分断面図である。
【図3】(g)〜(j)に、本発明の部品内蔵多層配線モジュール基板の製造方法の一例の一部を示す模式構成部分断面図である。
【図4】(a)〜(c)は、本発明の部品内蔵多層配線モジュール基板に使用する部品(抵抗素子、コンデンサ及びインダクタ)の一例を示す模式構成断面図である。
【符号の説明】
11……絶縁基材
21……導体層
21a、21b……第1配線層
31……貫通孔
40……部品
40R……抵抗素子
40C……コンデンサ
40L……インダクタ
41……電極
42……セラミック外装管
43……抵抗体
44、45……誘電体
46……コイル
51……絶縁層
52……開口部
61……薄膜導体層
62……導体層
62a、62b……第2配線層
100……部品内蔵多層配線モジュール基板
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer wiring circuit board for a semiconductor package, and more particularly to a component built-in multilayer wiring module board formed by embedding parts between wiring layers.
[0002]
[Prior art]
Conventional wiring circuit boards are surface-mounted with components mounted on the surface of the wiring board, and resistance elements and capacitors use bonding members such as solder and conductive adhesive at desired parts of the wiring layer of the wiring board. Surface mounting is performed.
[0003]
In a conventional wiring board, a resistance element, a capacitor, and the like are mounted on the surface of the board without any gap, and therefore, the wiring density of the wiring board is increased and complicated. In such a situation, particularly in the case of a high-density multilayer wiring board, there is a limit only by the surface mounting of the wiring board, and further improvement of the component mounting density is required.
Further, as the wiring density of the multilayer wiring board increases, the inspection of the multilayer wiring board becomes difficult, and the yield also tends to decrease.
[0004]
[Problems to be solved by the invention]
The present invention has been devised in view of the above-mentioned demands, and an object thereof is to provide a component built-in multilayer wiring module substrate in which the component mounting density of the high-density multilayer wiring substrate is improved and a manufacturing method thereof.
[0005]
[Means for Solving the Problems]
In order to solve the above-mentioned problems in the present invention, first, in claim 1, components are built in a substrate of a multilayer wiring board in which a predetermined number of wiring layers and insulating layers are formed on both surfaces of an insulating base material. A component built-in multilayer wiring module substrate, wherein the component is composed of a resistance element, a capacitor, and an inductor, embedded in a through-hole or opening formed in the multilayer wiring substrate , and electrodes at both ends of the component are caulked, and An electrode at both ends of the component is electrically connected to the wiring layer, and a gold film is formed on the electrodes at both ends of the component.
[0007]
Furthermore, according to a second aspect of the present invention, there is provided the method for manufacturing a component built-in multilayer wiring module substrate according to the first aspect, comprising the following steps.
(A) The process of forming a conductor layer on both surfaces of an insulating base material.
(B) The process of forming a through-hole in the predetermined position of the said insulation base material and a conductor layer.
(C) A step of embedding and caulking parts in which a gold film is formed on the electrodes at both ends in the through hole.
(D) A step of patterning the conductor layer to form a wiring layer.
(E) The process of forming an insulating layer on both surfaces of the said insulating base material and the said wiring layer.
(F) A step of forming an opening at a predetermined position of the insulating layer.
(G) forming a thin film conductor layer on the inner wall of the opening on the insulating layer;
(H) A step of embedding in the opening in which the thin-film conductor layer is formed, with one electrode of the component having a gold film formed on the electrodes at both ends facing down.
(I) A step of forming a second conductor layer having a predetermined thickness on the thin film conductor layer and the electrodes at both ends of the component by electroplating, and electrically connecting the other electrode of the component and the conductor layer.
(J) A step of patterning the second conductor layer to form a second wiring layer.
(K) A step of producing a multilayer wiring module substrate with a predetermined number of layers by repeating the steps (e) to (j) as many times as necessary.
[0008]
The component built-in multilayer wiring module substrate according to the present invention reduces the number of mounted components on the surface of the multilayer wiring substrate and improves the mounting density of the components by incorporating the components inside the multilayer wiring substrate. A feature of the module substrate manufacturing method is that the build-up multilayer wiring substrate manufacturing method can be applied as it is.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described.
FIG. 1 is a schematic partial sectional view showing an embodiment of a component built-in multilayer wiring module substrate according to the present invention. FIGS. 2 (a) to (f) and FIGS. 3 (g) to (j) The schematic structure partial sectional view which shows an example of the manufacturing method of a component built-in multilayer wiring module board in order of a process is shown, respectively.
As shown in FIG. 1, the component built-in multilayer wiring module substrate 100 of the present invention is formed by embedding components 40 in the insulating base material 11 and the insulating layer 51 between the wiring layers in the multilayer wiring substrate to form a multilayer wiring module substrate. Thus, by arranging the components three-dimensionally, the mounting density of the components is improved as compared with the conventional surface mounting.
[0010]
Components (passive elements) that can be incorporated are resistance elements, capacitors, and inductors. For example, metal electrodes are attached to both ends of a ceramic component, and the electrodes at both ends are devised. When parts are inserted into the through holes of the insulating base material with conductor layers formed on both sides, which will be described later, and the parts are fixed by caulking, the parts are securely fixed, and electrical conduction is ensured. . For example, by using copper as the material of the electrode, it is possible to make the structure easy to be crushed when it is caulked and fixed after component insertion, or it can be easily performed by electrolytic copper plating or the like to obtain electrical continuity with the wiring layer. . In addition, in order to ensure connection reliability, a gold film is formed on the electrode surfaces at both ends of the component, and gold diffuses in contact with copper, so that connection reliability improves over time. Yes.
[0011]
Hereinafter, the manufacturing method of the component built-in multilayer wiring module substrate of the present invention will be described.
First, a double-sided copper-clad laminate in which a copper layer is laminated on both sides of the insulating base material 11 to form a conductor layer 21 is prepared (see FIG. 2A).
Next, a through hole 31 is formed by punching at a predetermined position of the double-sided copper-clad laminate (see FIG. 2B).
[0012]
Next, a component (any one of the resistor element 40R, the capacitor 40C, and the inductor 40L) 40 in which a gold film is formed on the electrodes 41 at both ends having the same outer diameter as the through hole diameter is inserted into the through hole 31. After the insertion, the electrode 41 is caulked, and the electrode 41 is crushed so that the component 40 does not come out of the through hole 31. Further, a thin film conductor layer (not shown) of several μm is formed on the electrode 41 and the conductor layer 21 at both ends of the component 40 by electrolytic copper plating, and the electrode 41 and the conductor layer 21 at both ends of the component 40 are electrically joined. Make sure (see FIG. 2 (c)).
Here, an example of the resistive element 40R, the capacitor 40C, and the inductor 40L of the component 40 is shown in FIGS. 4 (a, b, and c). The resistance element 40R has a ceramic outer tube 42 filled with a resistor 43, and electrodes 41 are formed at both ends (see FIG. 4A). The capacitor 40C has a ceramic outer tube 42 filled with a dielectric 44, and electrodes 41 are formed at both ends (see FIG. 4B). The inductor 40L has a coil 46 wound around a dielectric 45 inside a ceramic outer tube 42, and electrodes 41 are formed on both ends (see FIG. 4C). Further, a gold film (not particularly shown) is formed on the surface of the electrode 41.
[0013]
Next, the conductor layer 21 is patterned to form a first wiring layer 21a and a first wiring layer 21b that are electrically connected to the component 40 (see FIG. 2D).
[0014]
Next, an insulating adhesive film is bonded to both surfaces to form an insulating layer 51 having a predetermined thickness (see FIG. 2E). Here, the thickness of the insulating layer 51 is determined by the height of a component attached to the insulating layer.
Next, an opening 52 having the same diameter as the outer diameter of the component 40 is formed at a predetermined position of the insulating layer 51 by laser processing or the like (see FIG. 2F).
[0015]
Next, a thin film conductor layer 61 having a predetermined thickness is formed on the insulating layer 51 and on the inner wall of the opening 52 by electroless copper plating (see FIG. 3G).
Here, the thin-film conductor layer 61 is used as an electrode for forming a conductor layer by using the thin-film conductor layer 61 as a cathode electrode in order to make an electrical connection with an electrode of the component when the component is attached.
[0016]
Next, a conductive adhesive or the like is applied to one electrode 41 of a component 40 (any one of the resistance element 40R, the capacitor 40C, and the inductor 40L) in which the electrode 41 is formed at both ends in the opening 52 where the thin film conductor layer 61 is formed. Apply, insert with the electrode 41 on the conductive adhesive application surface down, and heat to cure the wiring layer conductive adhesive (see FIG. 3 (h)).
Here, the electrical connection between the one electrode 41 of the component 40 and the first wiring layer 21a and the first wiring layer 21b is reliably performed.
Next, electrolytic copper plating is performed using the thin film conductor layer 61 as a cathode electrode to form a conductor layer 62 on the thin film conductor layer 61 (see FIG. 3I).
Here, the electrical connection between the other electrode 41 of the component 40 and the conductor layer 62 is ensured.
[0017]
Next, the thin film conductor layer 61 and the conductor layer 62 are patterned to form the second wiring layer 62a and the second wiring layer 62b, thereby obtaining the four-layer component built-in multilayer wiring module substrate 100 in which the component 40 is embedded ( (See FIG. 3 (j)).
Further, if necessary, a multilayer wiring module substrate with a desired number of layers can be obtained by repeating the insulating layer formation, opening formation, component attachment, and wiring layer formation steps.
[0018]
【Example】
Hereinafter, the present invention will be described in detail by way of examples.
<Example 1>
First, a conductor layer 21 was formed by laminating a 12 μm thick copper foil on both surfaces of an insulating substrate 11 made of a 50 μm thick polyimide film (see FIG. 2A).
Next, press drilling was performed using a mold having a convex part of 100 μmφ, and a through hole 31 having the same diameter as the outer diameter of the resistance element 40R was formed in the insulating base material 11 and the conductor layer 21 (FIG. 2 ( b)).
Next, a resistance element 40R in which a gold film was formed on the electrodes 41 at both ends shown in FIG. 4A was inserted into the through hole 31, and the electrodes 41 at both ends were caulked (see FIG. 2C).
[0019]
Next, a thin film conductor layer (not shown) having a thickness of 2 μm is formed on the electrode 41 and the conductor layer 21 at both ends of the resistance element 40R by electrolytic copper plating, and the thin film conductor layer and the conductor layer 21 are subjected to patterning treatment, thereby A first wiring layer 21a and a second wiring layer 21b electrically connected to the electrode 41 of the element 40R were formed (see FIG. 2D).
[0020]
Next, a 50 μm-thick polyimide film was bonded to form an insulating layer 51 (see FIG. 2E).
Next, an opening 52 having the same diameter as the outer diameter of the capacitor 40C was formed at a predetermined position of the insulating layer 51 by laser processing (see FIG. 2F).
[0021]
Next, a thin film conductor layer 61 having a thickness of 2 μm was formed on the insulating layer 51 and on the inner wall of the opening 52 by electroless copper plating (see FIG. 3G).
Next, a conductive adhesive or the like is applied to one electrode 41 of the capacitor 40C in which a gold film is formed on the electrode at both ends shown in FIG. 4B in the opening 52 in which the thin film conductor layer 61 is formed. The electrode 41 on the coating surface of the adhesive was inserted with the electrode 41 facing down, and the wiring layer conductive adhesive was cured by heating (see FIG. 3 (h)).
[0022]
Next, electrolytic copper plating was performed using the thin film conductor layer 61 as a cathode electrode to form a conductor layer 62 on the thin film conductor layer 61 (see FIG. 3I).
Next, the thin-film conductor layer 61 and the conductor layer 62 are patterned to form the second wiring layer 62a and the second wiring layer 62b, and the four-layer component built-in multilayer wiring module substrate in which the resistor element 40R and the capacitor 40C are built. 100 was obtained (see FIG. 3 (j)).
[0023]
<Example 2>
First, a conductor layer 21 was formed by laminating a 12 μm thick copper foil on both surfaces of an insulating substrate 11 made of a 50 μm thick polyimide film (see FIG. 2A).
Next, press punching was performed using a mold having a convex portion of 100 μmφ, and a through hole 31 having the same diameter as the outer diameter of the capacitor 40C was formed in the insulating base material 11 and the conductor layer 21 (FIG. 2B). )reference).
Next, a capacitor 40C in which a gold film was formed on the electrodes 41 at both ends shown in FIG. 4B was inserted into the through hole 31, and the electrodes 41 at both ends were caulked (see FIG. 2C).
[0024]
Next, a thin film conductor layer (not specifically shown) having a thickness of 2 μm is formed on the electrode 41 and the conductor layer 21 at both ends of the capacitor 40C by electrolytic copper plating, and the thin film conductor layer and the conductor layer 21 are subjected to patterning processing, thereby forming the capacitor 40C. The first wiring layer 21a and the first wiring layer 21b electrically connected to the electrode 41 were formed (see FIG. 2D).
[0025]
Next, a 50 μm-thick polyimide film was bonded to form an insulating layer 51 (see FIG. 2E).
Next, an opening 52 having the same diameter as the outer diameter of the inductor 40L was formed at a predetermined position of the insulating layer 51 by laser processing (see FIG. 2F).
[0026]
Next, a thin film conductor layer 61 having a thickness of 2 μm was formed on the insulating layer 51 and on the inner wall of the opening 52 by electroless copper plating (see FIG. 3G).
Next, a conductive adhesive or the like is applied to one electrode 41 of the inductor 40L in which a gold film is formed on the electrodes at both ends shown in FIG. 4 (c) in the opening 52 where the thin film conductor layer 61 is formed. The electrode 41 on the coating surface of the adhesive was inserted with the electrode 41 facing down, and the wiring layer conductive adhesive was cured by heating (see FIG. 3 (h)).
[0027]
Next, electrolytic copper plating was performed using the thin film conductor layer 61 as a cathode electrode to form a conductor layer 62 (see FIG. 3I).
Next, the thin film conductor layer 61 and the conductor layer 62 are patterned to form the second wiring layer 62a and the second wiring layer 62b, and the four-layer component built-in multilayer wiring module substrate 100 in which the capacitor 40C and the inductor 40L are built. (See FIG. 3 (j)).
[0028]
【The invention's effect】
By using the component built-in multilayer wiring module substrate of the present invention, it is possible to three-dimensionally arrange resistance elements, capacitors, and inductors that have been mounted on the substrate surface so far, and to improve the component mounting density.
In addition, the layout of the wiring layer can be afforded and the wiring width of the wiring board can be widened, so that the signal attenuation is reduced and the yield of the wiring board can be improved.
Furthermore, by forming a gold plating film on the electrode surfaces at both ends of the component, the electrical continuity between the electrode and the wiring layer can be ensured by utilizing the diffusibility with the wiring layer made of copper.
Further, since the caulking is performed when the component is fixed to the through hole in which the insulating base material and the conductor layer are formed, the component can be securely fixed and electrically connected, so that the manufacturing yield is improved.
[Brief description of the drawings]
FIG. 1 is a schematic partial sectional view showing an embodiment of a component built-in multilayer wiring module substrate according to the present invention.
FIGS. 2A to 2F are schematic structural partial cross-sectional views showing a part of an example of a method for manufacturing a component built-in multilayer wiring module substrate according to the present invention. FIGS.
FIGS. 3G to 3J are schematic structural partial cross-sectional views illustrating a part of an example of a method for manufacturing a component built-in multilayer wiring module substrate according to the present invention. FIGS.
FIGS. 4A to 4C are schematic cross-sectional views showing examples of components (resistive elements, capacitors, and inductors) used in the component built-in multilayer wiring module substrate of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Insulating base material 21 ... Conductor layer 21a, 21b ... 1st wiring layer 31 ... Through-hole 40 ... Component 40R ... Resistance element 40C ... Capacitor 40L ... Inductor 41 ... Electrode 42 ... Ceramic Outer tube 43... Resistors 44 and 45... Dielectric 46... Coil 51... Insulating layer 52... Opening 61 ... Thin-film conductor layer 62 ... Conductor layers 62a and 62b. ... Multi-layer wiring module board with built-in components

Claims (2)

絶縁基材の両面に配線層及び絶縁層が所定層数形成された多層配線基板の基板内部に部品が内蔵された部品内蔵多層配線モジュール基板であって、前記部品は抵抗素子、コンデンサ、インダクタからなり、前記多層配線基板に形成された貫通孔もしくは開口部に埋め込まれ、前記部品の両端の電極はかしめられ、かつ前記部品の両端の電極が前記配線層に電気的に接続されており、前記部品の両端の電極に金皮膜が形成されていることを特徴とする部品内蔵多層配線モジュール基板。A multilayer wiring module board with built-in components in which components are built inside a multilayer wiring board in which a predetermined number of wiring layers and insulating layers are formed on both surfaces of an insulating base material, wherein the components include a resistance element, a capacitor, and an inductor. Embedded in a through hole or opening formed in the multilayer wiring board, electrodes at both ends of the component are caulked, and electrodes at both ends of the component are electrically connected to the wiring layer, A multilayer wiring module substrate with a built-in component, wherein a gold film is formed on electrodes at both ends of the component. 以下の工程を備えていることを特徴とする請求項1に記載の部品内蔵多層配線モジュール基板の製造方法。
(a)絶縁基材の両面に導体層を形成する工程。
(b)前記絶縁基材及び導体層の所定位置に貫通孔を形成する工程。
(c)前記貫通孔に両端の電極に金皮膜が形成された部品を埋め込み、かしめる工程。
(d)前記導体層をパターニング加工し、配線層を形成する工程。
(e)前記絶縁基材及び前記配線層の両面に絶縁層を形成する工程。
(f)前記絶縁層の所定位置に開口部を形成する工程。
(g)前記絶縁層上前記開口部内壁に薄膜導体層を形成する工程。
(h)両端の電極に金皮膜が形成された前記部品の一方の電極を下にして、前記薄膜導体層が形成された前記開口部に埋め込む工程。
(i)前記薄膜導体層及び前記部品の両端の電極上に電解めっきにて所定厚の第2導体層を形成し、前記部品の他方の電極と前記導体層を電気的に接続する工程。
(j)前記第2導体層をパターニング加工し、第2配線層を形成する工程。
(k)工程(e)〜工程(j)の工程を必要回数繰り返して、所定層数の部品内蔵多層配線モジュール基板を作製する工程。
The manufacturing method of the component built-in multilayer wiring module substrate according to claim 1, comprising the following steps.
(A) The process of forming a conductor layer on both surfaces of an insulating base material.
(B) The process of forming a through-hole in the predetermined position of the said insulation base material and a conductor layer.
(C) A step of embedding and caulking parts in which a gold film is formed on the electrodes at both ends in the through hole.
(D) A step of patterning the conductor layer to form a wiring layer.
(E) The process of forming an insulating layer on both surfaces of the said insulating base material and the said wiring layer.
(F) A step of forming an opening at a predetermined position of the insulating layer.
(G) forming a thin film conductor layer on the inner wall of the opening on the insulating layer;
(H) A step of embedding in the opening in which the thin-film conductor layer is formed, with one electrode of the component having a gold film formed on the electrodes at both ends facing down.
(I) A step of forming a second conductor layer having a predetermined thickness on the thin film conductor layer and the electrodes at both ends of the component by electroplating, and electrically connecting the other electrode of the component and the conductor layer.
(J) A step of patterning the second conductor layer to form a second wiring layer.
(K) A step of producing a multilayer wiring module substrate with a predetermined number of layers by repeating the steps (e) to (j) as many times as necessary.
JP2002007131A 2002-01-16 2002-01-16 Component built-in multilayer wiring module substrate and manufacturing method thereof Expired - Fee Related JP4019717B2 (en)

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