JP4068215B2 - Booster circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a booster circuit, for example, a VPP generation circuit that is mounted in a dynamic RAM (random access memory) or the like and generates a word line selection potential, and a technique that is particularly effective for improving its supply efficiency and reliability.
[0002]
[Prior art]
A plurality of word lines and bit lines arranged orthogonally, an information storage capacitor, and an address selection MOSFET (metal oxide semiconductor field effect transistor. In this specification, a MOSFET is a generic term for an insulated gate field effect transistor) There is a memory integrated circuit device such as a dynamic RAM whose basic component is a memory array including a large number of dynamic memory cells arranged at the intersections of word lines and bit lines. In these dynamic RAMs and the like, the internal voltage VPP having a potential at least higher than the threshold voltage of the address selection MOSFET than the high level of the storage data written in the memory cell is often used as the selection potential of the word line. A type RAM or the like is provided with a VPP generation circuit that generates an internal voltage VPP based on an externally supplied power supply voltage.
[0003]
On the other hand, in recent years, the progress of miniaturization and high integration technology of semiconductor integrated circuits has been remarkable, and dynamic RAM and the like have benefited from the increase in scale and capacity, and the operating power supply tends to be lowered in voltage. is there. In addition, in a dynamic RAM or the like whose operating power supply voltage is being lowered, as one means for efficiently generating the internal voltage VPP as the word line selection potential, for example, a plurality of boost capacitors precharged to the power supply voltage are selected. For example, Japanese Patent Application Laid-Open No. 5-189970 discloses a booster circuit that is connected in series and generates an internal voltage having a potential several times the power supply voltage.
[0004]
[Problems to be solved by the invention]
Prior to the present invention, the inventors of the present application tried to develop a dynamic RAM having a plurality of banks and incorporating a VPP generation circuit including the above-described booster circuit as a charge pump circuit. I noticed. That is, the charge pump circuit constituting the VPP generation circuit of the dynamic RAM includes k unit boosting circuits UVB1 to UVBk as illustrated in FIG. 15, and each of these unit boosting circuits has a capacitance. Ca-Cd, precharge N-channel MOSFETs Na-Nd, and inverters Vb-Vd are included. When internal node na is set to a high level higher than internal node nv, that is, voltage B by the threshold voltage of MOSFET Nf, and internal node nb is set to a high level such as power supply voltage VCC, the upper electrodes of capacitors Ca to Cd Is precharged to approximately the power supply voltage VCC. When the internal node na is set to a low level lower than the internal node nv by the threshold voltage of the MOSFET Ne and the internal node nb is set to a low level such as the ground potential VSS, the capacitors Ca to Cd are connected to the inverters Vb to Vd. The internal node n1k is coupled in series via a P-channel MOSFET.
VPP≈ (k + 1) × VCC
A high potential internal voltage VPP is obtained.
[0005]
However, in the above charge pump circuit, when the capacitors Ca to Cd are connected in series, the comparison corresponding to approximately 2 × VCC to k × VCC is performed between the gate and drain of the P-channel and N-channel MOSFETs constituting the inverters Vb to Vd. A relatively large voltage of approximately VCC + Vth to k × VCC + Vth is applied between the drain and source of the precharging MOSFETs Na to Nd. As a result, as the dynamic RAM is miniaturized and highly integrated, these MOSFETs may break down withstand voltage, thereby reducing the reliability of the dynamic RAM. In order to cope with this, when the number of unit booster circuits provided in the charge pump circuit is reduced, the supply efficiency of the internal voltage VPP is lowered, and the word line selection potential becomes insufficient.
[0006]
An object of the present invention is to increase the supply efficiency of a VPP generation circuit that generates a word line selection potential, such as a dynamic RAM, and to improve its reliability.
[0007]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0008]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, a booster circuit such as a VPP generation circuit that is incorporated in a dynamic RAM or the like and generates a word line selection potential is connected to the first potential supply point via a corresponding precharge MOSFET. 1 capacitor, one electrode of which is coupled to the first node and further coupled to the first potential supply point via the corresponding precharge MOSFET, the other electrode of the second capacitor And an N channel type second MOSFET that receives a third potential at its gate and an N channel type second that receives a first internal signal at its gate. And a P-channel third MOSFET provided between the other electrode of the second capacitor and the second node and receiving a third potential at its gate. An internal voltage booster including one or more unit boost circuits coupled in series in a manner such that the second node is sequentially coupled to one electrode of the first capacitor or the first node of the preceding circuit. In addition to the circuit configuration, the gates of the first and third MOSFETs of each unit boost circuit constituting the internal voltage booster circuit are connected to the first power supply voltage potential or the first node of the previous unit boost circuit. A potential is supplied as a third potential.
[0009]
As a result, an internal voltage having a desired high potential can be easily generated, the supply efficiency of a booster circuit such as a VPP generation circuit can be increased, and between the gate and drain of the first and third MOSFETs The voltage applied to the capacitor can be reduced to prevent breakdown of the breakdown voltage and to improve the reliability of the booster circuit.
[0010]
Also, a P-channel or N-channel output transfer MOSFET is provided between the output terminal of the internal voltage booster circuit and the internal voltage supply point, and the same configuration as that of the internal voltage booster circuit is provided at the gate of the output transfer MOSFET. Then, the output voltage of the gate voltage booster circuit including one unit booster circuit is supplied.
[0011]
Thereby, the high potential generated by the internal voltage booster circuit can be prevented from being lowered by the threshold voltage of the output transfer MOSFET, and the supply efficiency of the booster circuit such as the VPP generation circuit can be further increased.
[0012]
Further, the output voltage of the internal voltage booster circuit or the gate voltage booster circuit is connected between the first power supply voltage supply point and the first internal node to which the gate of the precharge MOSFET is commonly coupled and the boost capacitor is coupled. A receiving N-channel sixth MOSFET is provided.
[0013]
As a result, the potential of the first internal node is prevented from becoming unspecified due to power supply bumps, etc., and the operation of the booster circuit is stabilized, thereby further improving the reliability of the booster circuit and thus the dynamic RAM including the same. Can do.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing an embodiment of a dynamic RAM including a VPP generation circuit VPPG (boost circuit) to which the present invention is applied. The outline of the configuration and operation of the dynamic RAM of this embodiment and the VPP generation circuit VPPG included therein will be described first with reference to FIG. 1 are formed on one semiconductor substrate surface such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique.
[0015]
In FIG. 1, the dynamic RAM of this embodiment includes four banks BANK0 to BANK3 and an interface circuit IF provided in common to these banks. Among these, the interface circuit IF exchanges a start control signal, an address signal, input data, output data, and the like (not shown) with an external access device, and controls each part of the dynamic RAM.
[0016]
Banks BANK0 to BANK3 include memory arrays ARY0 to ARY3 and a pair of sense amplifiers SA arranged on both sides of each memory array. The dynamic RAM is a so-called dependent type, and the sense amplifiers SA except for two arranged at both ends are shared by the banks on both sides.
[0017]
A common column address decoder CD is provided at the lower end of the banks BANK0 to BANK3, and row address decoders RD0 to RD3 and bank controllers BC0 to BC3 are provided on the left side of each bank. Among these, the column address decoder CD is supplied with a column address signal CA of a predetermined bit from the interface circuit IF. The row address decoders RD0 to RD3 are supplied with a row address signal RA of a predetermined bit from the interface circuit IF and with an internal voltage VPP from a VPP generation circuit VPPG described later. Further, the bank controllers BC0 to BC3 are supplied with a row bank address signal RBA and a column bank address signal CBA of predetermined bits from the interface circuit IF, and part of the output signals are VPP as row bank selection signals BR0 to BR3. This is supplied to the generation circuit VPPG.
[0018]
The column address decoder CD decodes the column address signal CA supplied from the interface circuit IF when the dynamic RAM is in a column cycle, and corresponding bits of the bit line selection signal for the sense amplifiers SA of the banks BANK0 to BANK3. Is alternatively set to an effective level. The row address decoder RD of the banks BANK0 to BANK3 decodes the row address signal RA supplied from the interface circuit IF when the dynamic RAM is in a row cycle, and the corresponding word lines of the memory arrays ARY0 to ARY3. Is alternatively set to a selection level such as the internal voltage VPP.
[0019]
On the other hand, the bank controllers BC0 to BC3 decode the row bank address signal RBA or the column bank address signal CBA supplied from the interface circuit IF when the dynamic RAM is set to the column cycle or the row cycle, and the row bank selection signal BR0. Control signals such as .about.BR3 are selectively formed to control the operations of the banks BANK0 to BANK3. The bank controllers BC0 to BC3 selectively form a shared control signal for selectively turning on the shared MOSFET of the sense amplifier SA. The effective level of the shared control signal is the same as the selection potential of the word line. The internal voltage is VPP.
[0020]
In this embodiment, the memory arrays ARY0 to ARY3 constituting the banks BANK0 to BANK3 are actually divided into a plurality of submemory arrays including its direct peripheral circuits, and the word lines constituting each memory array are: Actually, it is hierarchized as a main word line and a sub word line, but since these are not linearly related to the present invention, they are shown in a simplified manner and a detailed description is omitted.
[0021]
The dynamic RAM of this embodiment further includes a VPP generation circuit VPPG that generates an internal voltage VPP that is an effective level of the selection potential of the word line and the shared control signal based on a power supply voltage VCC supplied from the outside. Prepare. The VPP generation circuit VPPG is not particularly limited, but includes one level sensor LS and an oscillation circuit OSC provided in common to the banks BANK0 to BANK3, and four one-shots provided corresponding to the banks BANK0 to BANK3. Pulse generation circuits OP0 to OP3, pulse synthesis circuits ADD0 to ADD3 and charge pump circuits PC0 to PC3 are included. Among these, the predetermined reference voltage VR is supplied to the non-inverting input terminal + of the level sensor LS, and the output voltage of the VPP generation circuit VPPG, that is, the internal voltage VPP is supplied to the inverting input terminal −. The output signal ACT of the level sensor LS is supplied to the oscillation circuit OSC.
[0022]
On the other hand, corresponding row bank selection signals BR0 to BR3 are supplied from the bank controllers BC0 to BC3 of the banks BANK0 to BANK3 to the one-shot pulse generation circuits OP0 to OP3, respectively. Further, the output signal, that is, the pulse signal PS is commonly supplied from the oscillation circuit OSC to one input terminal of the pulse synthesis circuits ADD0 to ADD3, and the corresponding one-shot pulse generation circuits OP0 to OP0 are connected to the other input terminal. Output signals OPO0 to OPO3 of OP3 are supplied respectively. Further, a predetermined internal control signal DET is commonly supplied to one input terminal of the charge pump circuits PC0 to PC3, and an output signal of the corresponding pulse synthesis circuit ADD0 to ADD3, that is, a charge pump is supplied to the other input terminal. Control signals PCC0 to PCC3 are supplied. The output terminals of the charge pump circuits PC0 to PC3 are commonly coupled, and the potential thereof is the internal voltage VPP.
[0023]
The level sensor LS of the VPP generation circuit VPPG senses the potential of the internal voltage VPP based on the reference voltage VR, and selectively sets the output signal ACT to the high level when the potential of the internal voltage VPP does not reach a predetermined potential. . In addition, the oscillation circuit OSC is selectively activated in response to the high level of the output signal ACT of the level sensor LS, and selectively generates a pulse signal PS having a predetermined frequency.
[0024]
On the other hand, the one-shot pulse generation circuits OP0 to OP3 start from the rise to the high level and the fall to the low level of the row bank selection signals BR0 to BR3 supplied from the corresponding bank controllers BC0 to BC3 of the banks BANK0 to BANK3. One-shot pulse signals OPO0 to OPO3 each having a predetermined pulse width are generated. The pulse synthesis circuits ADD0 to ADD3 output their output signals based on the pulse signal PS supplied from the oscillation circuit OSC and the one-shot pulse signals OPO0 to OPO3 supplied from the corresponding one-shot pulse generation circuits OP0 to OP3. Charge pump control signals PCC0 to PCC3 are selectively formed and supplied to the corresponding charge pump circuits PC0 to PC3. Further, the charge pump circuits PC0 to PC3 are selectively activated when both the internal control signal DET and the corresponding charge pump control signals PCC0 to PCC3 are set to the low level, and generate a predetermined internal voltage VPP.
[0025]
Specific configurations and operations of VPP generation circuit VPPG, level sensor LS, oscillation circuit OSC, one-shot pulse generation circuits OP0 to OP3, pulse synthesis circuits ADD0 to ADD3, and charge pump circuits PC0 to PC3, and their features Will be described in detail later.
[0026]
FIG. 2 is a circuit diagram showing one embodiment of a one-shot pulse generation circuit OP0 included in the VPP generation circuit VPPG of the dynamic RAM shown in FIG. Based on this figure, the specific configuration and operation of the one-shot pulse generation circuit OP0 included in the VPP generation circuit VPPG of this embodiment will be described. In the following circuit diagram, a MOSFET with an arrow attached to the channel (back gate) portion is a P channel type (second conductivity type), and an N channel type (first conductivity type) without an arrow. It is shown separately from the MOSFET. Further, the one-shot pulse generation circuits OP1 to OP3 have the same configuration as the one-shot pulse generation circuit OP0 in FIG.
[0027]
In FIG. 2, the one-shot pulse generation circuit OP0 is not particularly limited, but constitutes a delay circuit together with an exclusive OR circuit EO1 having an inverting output terminal, a total of five inverters V1 to V5, and inverters V1 to V4. It includes resistors R1 to R4 and capacitors C11 to C14. A row bank selection signal BR0 is supplied to one input terminal of the exclusive OR circuit EO1 from the bank controller BC0 of the corresponding bank BANK0 via an inverter V5, and the other input terminal receives the row bank selection signal BR0. A delay signal from the delay circuit is supplied. The inverted output signal of the exclusive OR circuit EO1 is supplied as a one-shot pulse signal OPO0 to one input terminal of the corresponding pulse synthesizing circuit ADD0.
[0028]
Needless to say, the inverted output signal of the exclusive OR circuit EO1 is selectively set to the low level when the signals supplied to one and the other input terminals thereof have different logic levels. Therefore, the inverted output signal of the exclusive OR circuit EO1, that is, the one-shot pulse signal OPO0, is from the time when the row bank selection signal BR0 is set to the high level to the time when the delay signal by the delay circuit is set to the high level, The signal is selectively set to the high level after the selection signal BR0 is set to the low level until the delay signal is set to the low level.
[0029]
As will be described later, the one-shot pulse signal OPO0 is supplied to the charge pump circuit PC0 via the corresponding pulse synthesizing circuit ADD0, and a single boost operation is performed by the charge pump circuit PC0 in response to the high level. Further, as described above, the one-shot pulse signal OPO0 is set to a high level only for a predetermined period in response to the row bank selection signal BR0 being changed to a high level or being changed to a low level. The change of the high level indicates that immediately after that, the designated word line in the memory array ARY0 of the bank BANK0 is alternatively set to the selection level, and the change of the row bank selection signal BR0 to the low level immediately after that This shows that the shared MOSFET that uses the voltage VPP as a selection level is turned on. As described above, when the load with respect to the internal voltage VPP increases, the single boost operation by the charge pump circuit PC0 is selectively performed, so that the current supply capability as the internal voltage VPP is temporarily increased, and the potential thereof is increased. Variations can be suppressed.
[0030]
FIG. 3 is a circuit diagram showing one embodiment of the level sensor LS included in the VPP generation circuit VPPG of the dynamic RAM shown in FIG. A specific configuration and operation of the level sensor LS included in the dynamic RAM VPP generation circuit VPPG of this embodiment will be described with reference to FIG.
[0031]
In FIG. 3, the level sensor LS is not particularly limited, but P-channel MOSFETs P1 and P2 and an N-channel MOSFET N1 provided in series between the inverting input terminal − and the ground potential VSS (second power supply voltage), And a differential circuit centered on a pair of N-channel MOSFETs N2 and N3. Among these, MOSFET P1 is formed in a diode form so that its inverting input terminal-side is its anode by commonly coupling its gate and drain, and MOSFET N1 is also commonly coupled by its gate and drain, The inverting input terminal minus side is in the form of a diode so as to be its anode. The gate of MOSFET P2 is coupled to the non-inverting input terminal + of level sensor LS.
[0032]
As described above, the internal voltage VPP is supplied to the source of the MOSFET P1, that is, the inverting input terminal − of the level sensor LS, and the predetermined reference voltage VR is supplied to the gate of the MOSFET P2, that is, the non-inverting input terminal + of the level sensor LS. The The reference voltage VR is an internal voltage VDL. This internal voltage VDL is used as a high-potential side operation power supply of the sense amplifier SA, and the potential is, for example, +1.8 V (volt). This is a relatively low potential. Needless to say, the potential of the internal voltage VDL becomes a high level for writing to the memory cell.
[0033]
Next, the drains of the MOSFETs N2 and N3 constituting the differential circuit are coupled to the power supply voltage VCC (first power supply voltage) via the P-channel type load MOSFETs P3 and P4 in the form of a current mirror, and their common coupling The connected source is coupled to the ground potential VSS via an N-channel MOSFET N4 receiving the power supply voltage VCC at its gate. The gate of MOSFET N2 is coupled to the commonly coupled drains of MOSFETs P2 and N1, and the gate of MOSFET N3 is coupled to the non-inverting input terminal + of level sensor LS. The potential at the commonly coupled drains of the MOSFETs P4 and N3 is supplied to the oscillation circuit OSC as the output signal ACT of the level sensor LS after passing through the inverter V6. The power supply voltage VCC is not particularly limited, but is a positive potential of + 2.5V.
[0034]
The internal voltage VPP is higher than a predetermined potential, that is, a potential obtained by adding the threshold voltages of the MOSFETs P1 and P2 to the internal voltage VDL, that is, VDL + 2Vthp (hereinafter, the threshold voltage of one P-channel MOSFET is expressed as Vthp). At the time, in the level sensor LS, the MOSFETs P1 and P2 are turned on, and the gate potential of the MOSFET N2 constituting the differential circuit becomes a high level higher than the internal voltage VDL. Therefore, the MOSFET N2 of the differential circuit is turned on, the MOSFET N3 is turned off, and the output signal ACT of the level sensor LS is set to a low level such as the ground potential VSS.
[0035]
On the other hand, when the potential of the internal voltage VPP decreases and becomes lower than the predetermined potential, that is, VDL + 2Vthp, the MOSFETs P1 and P2 of the level sensor LS are turned off, and the gate potential of the MOSFET N2 becomes a low level lower than the internal voltage VDL. Therefore, the MOSFET N2 of the differential circuit is turned off, and the MOSFET N3 is turned on instead, and the output signal ACT of the level sensor LS is set to a high level such as the power supply voltage VCC.
[0036]
As will be described later, the output signal ACT of the level sensor LS is supplied to the oscillation circuit OSC, and the oscillation circuit OSC selectively performs an oscillation operation in response to the high level. Further, the output signal of the oscillation circuit OSC, that is, the pulse signal PS is supplied to the charge pump circuit PC0 via the corresponding pulse synthesis circuit ADD0, and is continuously boosted by the charge pump circuit PC0 in response to the repeated change to the high level. Operation is performed. As a result, the potential of the internal voltage VPP rises. However, when the potential reaches the predetermined potential, that is, VDL + 2Vthp, the output signal ACT of the level sensor LS is set to the low level, and in response thereto, the oscillation circuit OSC and the charge pump circuit PC0 The operation is stopped. As a result, the internal voltage VPP is controlled so that its center potential becomes the predetermined potential, that is, VDL + 2Vthp.
[0037]
In this embodiment, the threshold voltage Vthp of the P-channel MOSFETs P6 and P7 constituting the level sensor LS is not particularly limited, but is set to 0.8 V, for example, and the center potential of the internal voltage VPP is, for example, +3.4 V It is said. This potential is based on the potential of the internal voltage VDL serving as the high-potential side operation power supply of the sense amplifier SA, for example, +1.8 V plus the threshold voltage of the address selection MOSFETs constituting the memory cells of the memory arrays ARY0 to ARY3 The potential is sufficiently high, and high level writing to the memory cell is surely performed.
[0038]
FIG. 4 is a circuit diagram showing one embodiment of the oscillation circuit OSC included in the VPP generation circuit VPPG of the dynamic RAM shown in FIG. A specific configuration and operation of the oscillation circuit OSC included in the VPP generation circuit VPPG of the dynamic RAM of this embodiment will be described with reference to FIG.
[0039]
In FIG. 4, the oscillation circuit OSC is not particularly limited, but includes a clocked inverter composed of P-channel MOSFETs P6 and P7 and N-channel MOSFETs N5 and N6, and a P-channel MOSFET P5 provided in parallel with the MOSFETs P6 and P7. Of these, the output signal ACT of the level sensor LS is commonly supplied to the gates of the MOSFETs P5 and N5, and the commonly coupled gates of the MOSFETs P6 and N6 are coupled to the output terminal of the inverter VA described later. Further, the commonly coupled drains of the MOSFETs P5 and P7 and N5 are coupled to the gates of the MOSFETs P6 and N6 after passing through a delay circuit composed of four resistors R5 to R8, capacitors C15 to C18 and inverters V7 to VA, respectively. The The output signal of the final stage inverter VA constituting the delay circuit passes through the inverter VB and is then supplied to the subsequent pulse synthesis circuits ADD0 to ADD3 as the output signal of the oscillation circuit OSC, that is, the pulse signal PS.
[0040]
When the potential of the internal voltage VPP reaches the predetermined potential and the output signal ACT of the level sensor LS is set to a low level, the MOSFET P5 is turned on and the MOSFET N5 is turned off in the oscillation circuit OSC. For this reason, the clocked inverter composed of MOSFETs P6 and P7 and N5 and N6 is in a so-called non-transmission state, and its output terminal is fixed to a high level such as the power supply voltage VCC via the MOSFET P5. Therefore, the output signal of the inverter VA becomes a high level, and the output signal of the inverter VB, that is, the pulse signal PS is fixed at a low level such as the ground potential VSS. Further, since the high level of the output signal of the inverter VA is transmitted to the gates of the MOSFETs P6 and N6 constituting the clocked inverter, the clocked inverter is not in the form of turning off the MOSFETs P6 and N5 and turning on the MOSFET N6. It becomes a transmission state.
[0041]
Next, when the potential of the internal voltage VPP becomes lower than the predetermined potential and the output signal ACT of the level sensor LS is set to the high level, in the oscillation circuit OSC, the MOSFET P5 is turned off and the MOSFET N5 is turned on. Therefore, the clocked inverter composed of MOSFETs P6 and P7 and N5 and N6 is in a transmission state, and its output terminal is first set to a low level such as the ground potential VSS. The clocked inverter in the transmission state is coupled with the four inverters V7 to VA in a ring shape to form one ring oscillator, and starts an oscillation operation. As a result, the output signal of the oscillation circuit OSC, that is, the pulse signal PS becomes a continuous pulse signal having a period corresponding to the delay time of the delay circuit, and the charge pump circuit PC0 performs a continuous boosting operation in response to this. Is called.
[0042]
FIG. 5 is a circuit diagram showing one embodiment of the pulse synthesizing circuit ADD0 included in the VPP generation circuit VPPG of the dynamic RAM shown in FIG. A specific configuration and operation of the pulse synthesis circuit ADD0 included in the dynamic RAM VPP generation circuit VPPG of this embodiment will be described with reference to FIG. Since the pulse synthesis circuits ADD1 to ADD3 have the same configuration as the pulse synthesis circuit ADD0, analogy with the following description regarding the pulse synthesis circuit ADD0.
[0043]
In FIG. 5, the pulse synthesizing circuit ADD0 includes a NOR gate NO1 although not particularly limited. The output signal, that is, the one-shot pulse signal OPO0 is supplied from the corresponding one-shot pulse generation circuit OP0 to one input terminal of the NOR gate NO1, and the output signal, that is, the pulse, is supplied from the oscillation circuit OSC to the other input terminal. A signal PS is supplied. The output signal of the NOR gate NO1 is supplied to the corresponding charge pump circuit PC0 as the output signal of the pulse synthesis circuit ADD0, that is, the charge pump control signal PCC0.
[0044]
As described above, the output signal of the one-shot pulse generation circuit OP0, that is, the one-shot pulse signal OPO0 is normally set to the low level, and the row bank selection signal BR0 supplied from the bank controller BC0 of the corresponding bank BANK0 changes to the high level or the low level. When this is done, it is temporarily set to the high level for a predetermined period. Further, the output signal, that is, the pulse signal PS of the oscillation circuit OSC is normally set to low level when the oscillation circuit OSC is in an inoperative state, and is repeatedly set to high level with a predetermined period when the oscillation circuit OSC is in an operation state. The As a result, the output signal of the pulse synthesizing circuit ADD0, that is, the charge pump control signal PCC0 is normally set to a high level such as the power supply voltage VCC when the one-shot pulse signal OPO0 and the pulse signal PS are both set to the low level. Is at a low level such as the ground potential VSS.
[0045]
FIG. 6 shows a circuit diagram of a first embodiment of the charge pump circuit PC0 included in the VPP generation circuit VPPG of the dynamic RAM of FIG. 1, and FIG. 7 shows a signal waveform diagram of the embodiment. It is shown. Based on these drawings, the specific configuration and operation of the charge pump circuit PC0 included in the VPP generation circuit VPPG of the dynamic RAM of this embodiment and its features will be described. Since the charge pump circuits PC1 to PC3 have the same configuration as the charge pump circuit PC0 of FIGS. 6 and 7, it should be analogized from the following description regarding this.
[0046]
In FIG. 6, the charge pump circuit PC0 is not particularly limited, but the NOR gate receives the internal control signal DET at one input terminal and the output signal of the pulse synthesis circuit ADD0, that is, the charge pump control signal PCC0 at the other input terminal. Contains NO2. The output signal of the NOR gate NO2, that is, the internal signal n1 at the internal node n1, is supplied to one input terminal of the NOR gates NO3 and NO4, and to the other input terminal of the NOR gate NO3 via a delay circuit composed of inverters VD and VE. Supplied. Further, an inverted signal of the internal signal n1 by the inverter VC, that is, the internal signal n2 (first internal signal) at the internal node n2 is an N-channel MOSFET NA1 (second MOSFET, which constitutes the unit boost circuit UB1, hereinafter, each unit boost circuit). Are supplied to the gate of the second MOSFET) and to one input terminal of the NOR gate NO5. The other input terminal of the NOR gate NO4 is supplied with an inverted delay signal of the output signal of the NOR gate NO3 by the inverters VF to VH, that is, the internal signal n3 at the internal node n3, and the other input terminal of the NOR gate NO5 has its inverters VF, Delayed signals by VG, VI and VJ, that is, the internal signal n4 at the internal node n4 is supplied.
[0047]
The internal signal n3 is further supplied to the other electrode, that is, the lower electrode of the capacitor C4 (third capacitor) constituting the substantial internal voltage booster circuit. The output signal of the NOR gate NO4, that is, the internal signal n5 at the internal node n5 is supplied to the other electrode of the capacitor C1 (fourth capacitor), that is, the lower electrode, and the output signal of the NOR gate NO5, that is, the internal signal n6 at the internal node n6 is The other electrode of the capacitor C2 (first capacitor), that is, the lower electrode is supplied.
[0048]
The drain of the MOSFET NA1 of the unit boost circuit UB1 is connected to a capacitor C31 (second capacitor; hereinafter referred to as “first MOSFET. The MOSFETs N91 to N9j of each unit boost circuit are hereinafter referred to as first MOSFETs”). Capacitors C31 to C3j of each unit boost circuit are coupled to the other electrode, that is, the lower electrode of the second capacitor, and the source thereof is a second potential supply point, that is, a ground potential VSS (second power supply voltage supply point). ). The lower electrode of the capacitor C31 is further coupled to the second node via a P-channel type transfer MOSFET P81 (third MOSFET; hereinafter, the MOSFETs P81 to P8j of each unit boost circuit become the third MOSFET), and the capacitor It is coupled to one electrode or upper electrode of C2, and is coupled to the gate of an N-channel MOSFET N8 (sixth MOSFET). The first potential, that is, the power supply voltage VCC is commonly supplied to the gates of the MOSFETs P81 and N91. The substrate portion of MOSFET P81 is coupled to its source, that is, the upper electrode of capacitor C2.
[0049]
One electrode, that is, the upper electrode of the capacitor C1 is coupled to the internal node b1 (first internal node). The upper electrode of the capacitor C2 is coupled to the first potential supply point, that is, the power supply voltage VCC (first power supply voltage supply point) through an N-channel precharge MOSFET NB whose gate is coupled to the internal node b1. Is done. Further, one electrode, that is, the upper electrode of the capacitor C31 of the unit boost circuit UB1 is coupled to the first node of the unit boost circuit UB1, and then its gate is coupled to the internal node b1. To the power supply voltage VCC and to the internal node b3, that is, the gate of the N-channel type output transfer MOSFET NL. The upper electrode of the capacitor C4, that is, the internal node b2, is coupled to the power supply voltage VCC via an N-channel type precharge MOSFET NG whose gate is coupled to the internal node b1, and the charge pump circuit PC0 via the output transfer MOSFET NL. Are coupled to the output terminal, that is, the internal voltage supply point VPP.
[0050]
The internal node b1 further includes an N-channel MOSFET N7 (fifth MOSFET) in the form of a diode with the power supply voltage VCC side as an anode, the MOSFET N8 whose gate is coupled to the upper electrode of the capacitor C2, The node b1 is connected to the power supply voltage VCC through three N-channel MOSFETs ND to NF (fourth MOSFETs) each having a diode form with the anode on the b1 side. The internal node b2 further includes an N-channel MOSFET NH having a diode form with the power supply voltage VCC side as an anode, and three N-channels each having a diode form with the internal node b2 side as an anode. Coupled to power supply voltage VCC through MOSFETs NI-NK. The internal voltage supply point VPP is coupled to the power supply voltage VCC via an N-channel MOSFET NM in the form of a diode with the power supply voltage VCC side as its anode, and is connected to the ground potential VSS via a predetermined smoothing capacitor C5. Combined.
[0051]
Here, as shown in FIG. 7, the internal control signal DET is normally fixed at a low level such as the ground potential VSS, for example, when it is desired to stop the operation of the VPP generation circuit VPPG including the charge pump circuit PC0 on a trial basis. Is selectively set to a high level such as the power supply voltage VCC. Further, as described above, the charge pump control signal PCC0 is set to a high level such as the normal power supply voltage VCC, and is selectively set to a low level such as the ground potential VSS under a predetermined condition.
[0052]
When either the internal control signal DET or the charge pump control signal PCC0 is set to the high level, the output signal of the NOR gate NO2, that is, the internal signal n1, is set to the low level such as the ground potential VSS in the charge pump circuit PC0, and the inverter VC The inversion signal, that is, the internal signal n2, is set to a high level such as the power supply voltage VCC. Further, since the output signal of the NOR gate NO3 is set to a high level such as the power supply voltage VCC in response to the low level of the internal signal n1 and the delay signal by the inverters VD and VE, the internal signal n3 is set to the second potential, that is, the ground potential VSS. The internal signal n4 is set to a high level such as the power supply voltage VCC. The output signal of the NOR gate NO4, that is, the internal signal n5 is set to a high level such as the power supply voltage VCC by setting both the internal signals n1 and n3 to the low level, and the output signal of the NOR gate NO5, that is, the internal signal n6, is the internal signal n2. In response to the high level of n4 and n4, the low level such as the ground potential VSS is obtained.
[0053]
The internal node b1 is boosted to a potential V11 close to 2 × VCC (herein, the absolute value of the power supply voltage VCC is represented as VCC, and so on) by the boosting action of the capacitor C1 when the internal signal n5 is set to the high level. However, when the potential becomes abnormally high for some reason, it is clamped to VCC + 3Vthn (herein, the threshold voltage of one N-channel MOSFET is expressed as Vthn, and so on) by the MOSFETs ND to NF. Further, in response to the high level of the internal node b1, the precharge MOSFETs NB, NC and NG are turned on, and the power supply voltage VCC is transmitted to the upper electrodes of the capacitors C2, C31 and C4. At this time, the low level of the internal signals n6 and n3, that is, the ground potential VSS is transmitted to the lower electrodes of the capacitors C2 and C4, respectively. The lower electrode of the capacitor C31 constituting the unit boost circuit UB1 is connected to the MOSFET NA1 that is turned on by receiving the high level of the internal signal n2 and the MOSFET N9 that is turned on by receiving the power supply voltage VCC at its gate. Ground potential VSS is transmitted.
[0054]
From these facts, the capacitors C2, C31 and C4 are both precharged so that the upper electrode is set to the power supply voltage VCC and the lower electrode is set to the ground potential VSS. At this time, the transfer MOSFET NL is turned off because the internal nodes b2 and b3 are both set to the power supply voltage VCC, and the potential of the internal voltage VPP at the internal voltage supply point VPP is maintained at a high potential.
[0055]
Next, when the charge pump control signal PCC0 is changed to the low level while the internal control signal DET remains at the low level, in the charge pump circuit PC0, the output signal of the NOR gate NO2, that is, the internal signal n1, is first set to the high level such as the power supply voltage VCC. In response to this, the internal signal n2 is changed to a low level such as the ground potential VSS. Further, when the delay time t1 of the delay circuit composed of the inverters VD and VE elapses, the internal signal n3 is set to a high level such as the power supply voltage VCC, and the internal signal n4 is set to a low level such as the ground potential VSS with a slight delay. Is done. The output signal of the NOR gate NO4, that is, the internal signal n5 is changed to the low level like the ground potential VSS in response to the high level change of the internal signal n1, and the output signal of the NOR gate NO5, that is, the internal signal n6, is the low level of the internal signals n2 and n4. At this point, the power supply voltage VCC is set to a high level.
[0056]
The potential of the internal node b1 is lowered via the capacitor C1 when the internal signal n5 is set to the low level. However, since the diode-type MOSFET N7 is provided between the internal node b1 and the power supply voltage VCC, the low level V12 is set to VCC. Clamped at -Vthn. Therefore, the boosted potential V11 of the internal node b1 is 2 × VCC−Vthn. In response to the low level of the internal node b1, the precharge MOSFETs NB, NC and NG are turned off, and the precharge operations of the capacitors C2, C31 and C4 are stopped. At this time, the lower electrode of the capacitor C2 is boosted by the high level of the internal signal n6, and in response to this, the potential of the upper electrode is pushed up to 2 × VCC. Also, the MOSFET P81 receiving the power supply voltage VCC at its gate is turned on upon receiving the boost potential of the upper electrode of the capacitor C2, but the MOSFET N91 receiving the power supply voltage VCC at its gate potential applies the boost potential of the lower electrode of the capacitor C31. In response to this, the MOSFET NA1 is turned off in response to the low level of the internal signal n2. As a result, the boost potential of the upper electrode of the capacitor C2 is transmitted to the lower electrode of the capacitor C31, and the potential of the internal node b3 is pushed up to 3 × VCC.
[0057]
On the other hand, the potential at the upper electrode of the capacitor C4, that is, the internal node b2, is boosted to a high potential of 2 × VCC by boosting the lower electrode by the high level of the internal signal n3. The high potential of the internal node b2 is not affected by the threshold voltage via the transfer MOSFET NL which is turned on when the gate potential, that is, the internal node b3 is set to a high potential of 3 × VCC. It is transmitted to the internal voltage supply point VPP. However, since the potential of the internal voltage VPP is monitored by the level sensor LS as described above, the center potential is actually controlled to be the predetermined potential, that is, VDL + 2Vthp.
[0058]
When the upper electrodes of the capacitors C2, C31 and C4 are set to a high potential, in the charge pump circuit PC0, the MOSFET N8 provided between the power supply voltage VCC and the internal node b1 receives the boosted potential of the upper electrode of the capacitor C2. Turns on. As described above, the diode-shaped MOSFET N7 and ND to NF are provided between the power supply voltage VCC and the internal node b1, and the potential thereof is held within the range of VCC−Vthn to VCC + 3Vthn. During this period, the potential of the internal node b1 is in a substantially floating state. Therefore, when the potential of the power supply voltage VCC varies due to, for example, a power supply bump, the potential between the potential of the internal node b1 and the latest potential of the power supply voltage VCC. The relationship becomes unspecified. As described above, the MOSFET N8 is provided between the power supply voltage VCC and the internal node b1, and this is turned on each time the boosting operation of the charge pump circuit PC0 is performed, so that the internal node b1 has the latest potential of the power supply voltage VCC. As a result, the operation of the charge pump circuit PC0 and hence the dynamic RAM is stabilized.
[0059]
Further, in this embodiment, as described above, the gate of the transfer MOSFET P81 that selectively couples the capacitors C2 and C31 in series is coupled to the power supply voltage VCC and is connected to the MOSFET NA1 that is in a complementary relationship with the transfer MOSFET P81. In the meantime, a MOSFET N91 whose gate is coupled to the power supply voltage VCC is provided, and this MOSFET N91 is automatically turned off during the boost operation by the unit boost circuit UB1. As a result, the gate-drain voltage of the transfer MOSFET P81 is compressed to 2 × VCC-VCC, that is, VCC, and the connection between the lower electrode of the capacitor C31 at the boosted potential and the MOSFET NA1 is broken, and the gate is connected to the ground potential. The drain of MOSFET NA1 receiving VSS is in a floating state. As a result, the breakdown breakdown of the transfer MOSFET P81 and the MOSFETs N91 and NA1 constituting the unit boost circuit UB1 can be prevented, thereby improving the reliability of the charge pump circuit PC0 and hence the dynamic RAM.
[0060]
When the charge pump control signal PCC0 is returned to a high level such as the power supply voltage VCC, the internal signal n1 is first set to a low level such as the ground potential VSS in the charge pump circuit PC0. The signal n2 is set to a high level like the power supply voltage VCC. In response to the high level of the internal signal n2, the internal signal n6 is set to a low level such as the ground potential VSS. In response to the low level of the internal signal n6, the internal node b3 is set to the low level. Further, when the delay time t2 of the inverters VD and VE, the NOR gate NO3, and the delay time t1 of the inverters VF to VH have elapsed after the internal signal n1 is set to the low level, the internal signal n3 is set to the low level. In response to the low level, the internal signal n5 is set to a high level such as the power supply voltage VCC, and the internal node b2 is set to a low level such as the power supply voltage VCC. The internal node b1 is set to the potential V11 in response to the high level of the internal signal n5.
[0061]
As apparent from the above description, the delay time Δt1 from when the internal node b1 is set to the low level such as the potential V12 until the internal node b2 is changed to the high level such as 2 × VCC is equal to the internal node b1. It acts to prevent the boost potential of b2 from coming off to the power supply voltage VCC side via the MOSFET NG. The delay time Δt2 from when the internal node b2 is set to the high level to when the internal node b3 is set to a high level such as 3 × VCC is the transfer time before the boost potential of the internal node b2 reaches a sufficient potential. The delay time Δt3 from the time when the internal node b3 is set to the low level such as the power supply voltage VCC until the internal node b1 is set to the voltage V11 after the internal node b3 is set to the low level is the off state of the transfer MOSFET NL. This acts to prevent the precharge operation of the capacitors C2, C3 and C4 from being started.
[0062]
FIG. 8 shows a circuit diagram of a second embodiment of the charge pump circuit PC0 included in the VPP generation circuit VPPG of the dynamic RAM of FIG. Since the charge pump circuit PC0 of this embodiment basically follows the embodiment of FIG. 6, only the parts different from this will be described.
[0063]
In FIG. 8, the charge pump circuit PC0 of this embodiment includes an internal capacitor C4 (third capacitor) that receives an internal signal n3 on the other electrode, that is, the lower electrode, and i, that is, one unit boost circuit UB3. The voltage booster circuit includes a capacitor C2 and a gate voltage booster circuit including i + 1, that is, two unit boost circuits UB1 and UB2. Among these, the unit boost circuit UB3 constituting the internal voltage booster circuit is substantially serially coupled to the capacitor C4 in such a manner that the second node, that is, the source of the MOSFET P83 is coupled to the upper electrode of the capacitor C4. That is, the upper electrode of the capacitor C33 is coupled to the internal node b2 as the output terminal of the internal voltage booster circuit. The upper electrode of the capacitor C4 is further coupled to the power supply voltage VCC via the N-channel type precharge MOSFET NG, and the upper electrode of the capacitor C33 constituting the unit boost circuit UB3 is supplied via the N-channel type precharge MOSFET NO. Coupled to voltage VCC. The internal node b2 is coupled to the internal voltage supply point VPP via an N channel type output transfer MOSFET NL.
[0064]
On the other hand, the unit boost circuits UB1 and UB2 constituting the gate voltage booster circuit are serially coupled such that the second node is coupled to the upper electrode of the capacitor C2 or the first node of the unit boost circuit UB1 in the previous stage, The first node of unit boost circuit UB2 is coupled to internal node b3 as the output terminal of the gate voltage booster circuit. The upper electrode of the capacitor C2 is coupled to the power supply voltage VCC via an N-channel precharge MOSFET NB, and the upper electrodes of the capacitors C31 and C32 constituting the unit boost circuits UB1 and UB2 are respectively N-channel precharge MOSFETNC. And NN to the power supply voltage VCC. Internal node b3 is coupled to the gate of output transfer MOSFET NL.
[0065]
When either the internal control signal DET or the charge pump control signal PCC0 is at a high level, the lower electrode of the capacitor C33 constituting the unit boost circuit UB3 of the internal voltage booster circuit is connected to the ground potential VSS via the MOSFETs N93 and NA3. And the low level of the internal signal n3 is supplied to the lower electrode of the capacitor C4. In addition, the upper electrode of the capacitor C33 is precharged to the power supply voltage VCC via the precharge MOSFET NO that is in the on state in response to the high level of the internal node b1, and the upper electrode of the capacitor C4 is also high level of the internal node b1. In response, the power supply voltage VCC is precharged via the precharge MOSFET NG in the on state. As a result, the upper electrodes of the capacitors C33 and C4 are both set to the power supply voltage VCC, and the internal node b3 is also set to the power supply voltage VCC.
[0066]
At this time, the lower electrodes of the capacitors C31 and C32 constituting the unit boost circuits UB1 and UB2 of the gate voltage booster circuit correspond when either the internal control signal DET or the charge pump control signal PCC0 is set to the high level. The ground potential VSS is supplied through the MOSFETs N91 and NA1 or N92 and NA2, and the low level of the internal signal n6 is supplied to the lower electrode of the capacitor C2. Further, the upper electrodes of the capacitors C31 and C32 are precharged to the power supply voltage VCC through the precharge MOSFETs NC and NN which are in the ON state in response to the high level of the internal node b1, and the upper electrode of the capacitor C2 is also internal. In response to the high level of the node b1, it is precharged to the power supply voltage VCC via the precharge MOSFET NB in the on state. As a result, the capacitors C2 and the upper electrodes of C31 and C32 are both set to the power supply voltage VCC, the internal node b3 is also set to the power supply voltage VCC, and the transfer MOSFET NL is turned off.
[0067]
Next, when the internal control signal DET and the charge pump control signal PCC0 are both set to the low level, the lower electrode of the capacitor C4 constituting the internal voltage booster circuit is boosted in response to the high level of the internal signal n3, and the upper electrode Is pushed up to 2 × VCC. In response to this high potential, the transfer MOSFET P83 of the unit boost circuit UB3 is turned on, the potential of the lower electrode of the capacitor C33 is pushed up to 2 × VCC, and the MOSFET N93 receives the high potential of the lower electrode of the capacitor C33. Turns off. As a result, the potential of the upper electrode of the capacitor C33, that is, the internal node b2, is pushed up to 3 × VCC.
[0068]
At this time, the lower electrode of the capacitor C2 constituting the gate voltage booster circuit is boosted in response to the high level of the internal signal n6, and the potential of the upper electrode is pushed up to 2 × VCC. In response to this high potential, the transfer MOSFET P81 of the unit boost circuit UB1 is turned on, the potential of the lower electrode of the capacitor C31 is pushed up to 2 × VCC, and the MOSFET N91 receives the high potential of the lower electrode of the capacitor C31. Turns off. As a result, the potential of the upper electrode of the capacitor C31, that is, the internal node b2, is pushed up to 3 × VCC. Further, in the unit boost circuit UB2, the transfer MOSFET P82 is turned on in response to the high potential of the upper electrode of the capacitor C31 constituting the unit boost circuit UB1, and the potential of the lower electrode of the capacitor C32 is pushed up to 3 × VCC. In response to the high potential of the lower electrode of the capacitor C32, the MOSFET N92 is turned off.
[0069]
Therefore, since the potential of the upper electrode of the capacitor C32, that is, the internal node b3 is pushed up to 4 × VCC which is higher than VCC by the internal node b2, the high potential of the internal node b2 is affected by the threshold voltage of the transfer MOSFET NL. Without being transmitted to the internal voltage supply point VPP. As a result, while obtaining the same effect as the embodiment of FIG. 6, it is possible to further increase the potential of the internal node n2, which is the source of the internal voltage VPP, and to increase the supply efficiency of the charge pump circuit PC0, that is, the VPP generation circuit VPPG. It will be possible. The supply current and supply efficiency of the charge pump circuit PC0, that is, the VPP generation circuit VPPG will be compared and examined in detail after the third to fifth embodiments are described.
[0070]
FIG. 9 shows a circuit diagram of a third embodiment of the charge pump circuit PC0 included in the dynamic RAM VPP generation circuit VPPG of FIG. Note that the charge pump circuit PC0 of this embodiment basically follows the embodiment of FIGS. 6 and 8, and therefore, only the portions different from this will be described.
[0071]
In FIG. 9, the charge pump circuit PC0 of this embodiment does not include a gate voltage booster circuit, and a capacitor C4 ( Third capacity ) And a unit boost circuit UB3 including a capacitor C33 (second capacitor). The upper electrode of the capacitor C33 constituting the unit boost circuit UB3 of the internal voltage booster circuit is coupled to the internal node b2 and further coupled to the internal voltage supply point VPP via the P-channel type output transfer MOSFET PB. The gate of the output transfer MOSFET PB is coupled to the output terminal of the level shift circuit LSF that uses the internal voltage VPP as its high-potential side operating power supply and the ground potential VSS as the low-potential side operating power supply, that is, the internal node b4. Coupled to feed point VPP.
[0072]
Here, the level shift circuit LSF is not particularly limited, but includes a pair of P-channel MOSFETs P9 and PA whose source is coupled to the internal voltage supply point VPP and whose gate and drain are cross-coupled to each other. Among these, the drain of the MOSFET P9 is coupled to the output terminal of the NOR gate NO6, that is, the internal node n8 via the N channel MOSFET NP receiving the power supply voltage VCC at its gate, and the drain of the MOSFET PA is connected to the ground potential via the N channel MOSFETs NQ and NR. Coupled to VSS. The gate of MOSFETQ is coupled to power supply voltage VCC, and the gate of MOSFETNR is coupled to internal node n8.
[0073]
A delay signal of the internal signal n7 by the inverters VH and VL is supplied to one input terminal of the NOR gate NO6, and an inverted signal of the internal signal n1 by the inverter VM is supplied to the other input terminal. As a result, the output signal of the NOR gate NO6, that is, the internal signal n8 (second internal signal) at the internal node n8 is set to the low level like the normal ground potential VSS, and the power supply voltage VCC is received in response to the high level of the charge pump control signal PCC0. It is considered as a high level.
[0074]
When the internal signal n8 is set to a low level such as the ground potential VSS, in the level shift circuit LSF, the MOSFETNR is turned off and the MOSFETNP is turned on. For this reason, the MOSFET PA is turned on, the MOSFET P9 is turned off, and the output signal of the level shift circuit LSF, that is, the internal signal b4 at the internal node b4 is set to an invalid level, that is, a high level such as the internal voltage VPP. The Therefore, the output transfer MOSFET PB is turned off, and the potential of the internal voltage supply point VPP is maintained at a high potential.
[0075]
Next, when the charge pump control signal PCC0 is set to a low level and the internal signal n8 is set to a high level such as the power supply voltage VCC, the MOSFET NP is turned off and the MOSFET NR is turned on in the level shift circuit LSF. Therefore, the MOSFET P9 is turned on, the MOSFET PA is turned off, and the output signal of the level shift circuit LSF, that is, the internal signal b4 is set to the effective level, that is, the low level such as the ground potential VSS. As a result, the output transfer MOSFET PB is turned on, and a high potential of 3 × VCC generated by the internal voltage booster circuit is transmitted to the internal voltage supply point VPP via this.
[0076]
That is, in the charge pump circuit PC0 of this embodiment, the output transfer MOSFET is replaced with the P-channel MOSFET PB, so that it is not necessary to provide a gate voltage booster circuit. As a result, the charge pump circuit PC0 and thus the VPP generation circuit VPPG are eliminated. This simplifies the circuit configuration and can achieve the same effects as the embodiment of FIG.
[0077]
FIG. 10 shows a circuit diagram of a fourth embodiment of the charge pump circuit PC0 included in the dynamic RAM VPP generation circuit VPPG of FIG. 1, and FIG. 11 shows a circuit diagram of the fifth embodiment. It is shown. The charge pump circuit PC0 of this embodiment basically follows the embodiments of FIGS. 6, 8 and 9, and therefore only the parts different from this will be described.
[0078]
In FIG. 10, the charge pump circuit PC0 of this embodiment does not include a gate voltage booster circuit, and includes an internal voltage including a unit boost circuit UB3 including a capacitor C4 (first capacitor) and a capacitor C33 (second capacitor). Includes a booster circuit. The upper electrode of the capacitor C33 serving as the output terminal of the internal voltage booster circuit is coupled to the internal voltage supply point VPP via the N-channel output transfer MOSFET NS. This transfer MOSFET NS is formed in a diode form with its gate and drain coupled together in common, with the internal node b2 side as the anode.
[0079]
Thus, in this embodiment, although the high potential of 3 × VCC generated by the internal voltage booster circuit is lowered by the threshold voltage Vthn of the output transfer MOSFET NS and transmitted to the internal voltage supply point VPP, the output transfer The gate voltage boosting circuit for boosting the gate potential of the MOSFET NS is not required, and the circuit configuration of the charge pump circuit PC0 is further simplified as compared with the embodiment of FIG. 9, and the output transfer MOSFET is a P-channel type. A similar effect can be obtained while preventing latch-up due to this.
[0080]
Next, in the embodiment of FIG. 11, the output transfer MOSFET NS of FIG. 10 is replaced with a P-channel type output transfer MOSFET PC. This transfer MOSFET PC is also in the form of a diode with the internal node b2 side as an anode, and its substrate is coupled to the internal voltage supply point VPP. Thus, the output transfer MOSFET PC operates in the same manner as the output transfer MOSFET NS of FIG. Therefore, even in this embodiment, the high potential of 3 × VCC generated by the internal voltage booster circuit is lowered by the threshold voltage Vthp of the output transfer MOSFET PC and transmitted to the internal voltage supply point VPP. Similar to the embodiment of FIG. 10, the same effect can be obtained while simplifying the circuit configuration of the charge pump circuit PC0.
[0081]
FIG. 12 shows a characteristic diagram of one embodiment for explaining the supply efficiency of the VPP generation circuit VPPG including the charge pump circuit PC0 of FIG. 6 and FIGS. 8 to 11, and FIG. The characteristic view of one Example for demonstrating this is shown. Based on these drawings, the supply efficiency and supply current of the charge pump circuit PC0 of FIG. 6 and FIGS. 8 to 11 will be described and compared. In FIG. 12, the horizontal axis indicates the potential ratio of the internal voltage VPP and the power supply voltage VCC, and the vertical axis indicates the supply efficiency of each embodiment. In FIG. 13, the horizontal axis indicates the potential ratio between the internal voltage VPP and the power supply voltage VCC, and the vertical axis indicates the supply current of each embodiment.
[0082]
First, in the first embodiment shown in FIG. 6, as described above, the internal voltage VPP is boosted only by the one-stage capacitor C4, and the boosted potential of the internal node b2 is 2 × VCC. For this reason, the supply current IPP of the charge pump circuit PC0 is set such that the capacitance value of the capacitor C4 is C, and the charge utilization efficiency of the charge pump circuit PC0 is η. _c When the period of the charge pump control signal PCC0 is T,
IPP = C × (2 × VCC−VPP) × η _c / T ……………………… (1)
It becomes. Further, an equivalent pump capacity C of the charge pump circuit PC0 obtained from this equation _i The
C _i = C × (2 × VCC−VPP) × η _c / VCC …………………… (2)
And other capacity that does not contribute to boosting is C _L Suppose that the supply efficiency η of the charge pump circuit PC0 takes into account the current required for charging and discharging each capacitor,
η = C _i / (2 × C _L +2 x C _i ) ……………………………………… (3)
It becomes.
[0083]
For this reason, the supply efficiency η of the charge pump circuit PC0 obtained by the above equation (3) does not contribute to boosting in the region where the potential of the internal voltage VPP is close to the power supply voltage VCC as shown by a thin solid line in FIG. Capacity C _L Is comparatively small and becomes larger than the embodiment of FIGS. 8 to 11, but becomes smaller as the potential of the internal voltage VPP becomes higher, and when the potential of the internal voltage VPP becomes twice the power supply voltage VCC, Real capacity C of equation (2) _i Becomes zero, and the supply efficiency η also becomes zero. Further, the supply current IPP of the charge pump circuit PC0 obtained by the above equation (1) is similar to the supply efficiency η in the region where the potential of the internal voltage VPP is close to the power supply voltage VCC as shown by the thin solid line in FIG. Although it becomes larger than the embodiments of FIGS. 8 to 11, it becomes smaller than these embodiments as the potential of the internal voltage VPP becomes higher, and becomes zero when the potential of the internal voltage VPP becomes twice the power supply voltage VCC. .
[0084]
Next, in the second embodiment shown in FIGS. 8 and 9, boosting of the internal voltage VPP is performed by double boost, that is, two-stage capacitors C4 and C33, and the boosted potential of the internal node b2 is 3 × VCC. It becomes. The high potential of the internal node b2 is transmitted to the internal voltage supply point VPP without being affected by the threshold voltage of the output transfer MOSFET NL or PB. For this reason, the supply current IPP of the charge pump circuit PC0 is C when the capacitance values of the capacitors C4 and C33 are C.
IPP = (C / 2) × (3 × VCC−VPP) × η _c / T …………… (4)
It becomes. Further, an equivalent pump capacity C of the charge pump circuit PC0 obtained from this equation _i The
C _i = (C / 2) x (3 x VCC-VPP) x η _c / VCC ………… (5)
And other capacity that does not contribute to boosting is C _L Then, the supply efficiency η of the charge pump circuit PC0 is
η = C _i / (2 × C _L +3 x C _i ) ……………………………………… (6)
It becomes.
[0085]
For this reason, the supply efficiency η of the charge pump circuit PC0 obtained by the above equation (6) does not contribute to boosting in the region where the potential of the internal voltage VPP is close to the power supply voltage VCC, as shown by the thick dotted line in FIG. Capacity C _L 6 is relatively smaller than that of the embodiment of FIG. 6, but becomes larger than that of the embodiment of FIG. 6 as the potential of the internal voltage VPP increases. Eventually, the potential of the internal voltage VPP becomes three times the power supply voltage VCC. Then, the equivalent capacitance C of the above equation (5) _i Becomes zero, and the supply efficiency η also becomes zero. Further, the supply current IPP of the charge pump circuit PC0 obtained by the above equation (4) is similar to the supply efficiency η in the region where the potential of the internal voltage VPP is close to the power supply voltage VCC as shown by the thick dotted line in FIG. Although it becomes smaller than the embodiment of FIG. 6, it becomes larger than the embodiment of FIG. 6 as the potential of the internal voltage VPP becomes higher, and eventually becomes zero when the potential of the internal voltage VPP becomes three times the power supply voltage VCC.
[0086]
In other words, this embodiment has an effective circuit configuration in the present situation where the potential ratio between the internal voltage VPP and the power supply voltage VCC is increasing, especially in the dynamic RAM, and the large supply efficiency and supply current are obtained. be able to.
[0087]
Next, in the fourth embodiment shown in FIG. 10, the internal voltage VPP is boosted by double boost, that is, by two-stage capacitors C4 and C33, and the boosted potential of the internal node b2 is 3 × VCC. The high potential of the internal node b2 is lowered by the threshold voltage Vthn of the transfer MOSFET NS and transmitted to the internal voltage supply point VPP. Therefore, the supply current IPP of the charge pump circuit PC0 is
IPP = (C / 2) × (3 × VCC−Vthn−VPP) × η _c / T …………………………… (7)
It becomes. Further, the substantial pump capacity C of the charge pump circuit PC0 obtained from this equation _i The
C _i = (C / 2) × (3 × VCC−Vthn−VPP) × η _c / VCC
And other capacity that does not contribute to boosting is C _L Then, the supply efficiency η of the charge pump circuit PC0 is
η = C _i / (2 × C _L +3 x C _i ) ……………………………………… (8)
It becomes.
[0088]
For this reason, the supply efficiency η of the charge pump circuit PC0 obtained by the above equation (8) is, as shown by the thick solid line in FIG. 12, generally the transfer MOSFET NS as compared with the embodiment of FIGS. Similarly to the supply efficiency η, the supply current IPP obtained by the threshold voltage Vthn is reduced by the threshold voltage Vthn and is obtained by the above equation (7), as shown by the thick solid line in FIG. As a result, the threshold voltage Vthn of the transfer MOSFET NS is reduced as a whole.
[0089]
That is, in this embodiment, the supply efficiency and the supply current are slightly reduced as compared with the embodiments of FIGS. 8 and 9, but the gate voltage booster circuit and the level shift circuit LSF for controlling the gate potential of the transfer MOSFET NS It becomes unnecessary and the circuit configuration of the charge pump circuit PC0 can be further simplified. In addition, since the transfer MOSFET is an N-channel type, latch-up can be prevented even if the potential of the internal voltage VPP increases to some extent, but the substrate voltage of the transfer MOSFET is set to the ground potential VSS or a predetermined negative potential. As a result, the threshold voltage Vthn becomes relatively large, and the supply efficiency and supply current are correspondingly reduced.
[0090]
On the other hand, in the fifth embodiment shown in FIG. 11, as in the embodiments of FIGS. 8 and 9, the internal voltage VPP is boosted by the double boost, that is, the two-stage capacitors C4 and C33, and the internal node b2 is boosted. The subsequent potential is 3 × VCC, but the high potential of the internal node b2 is lowered by the threshold voltage Vthp of the transfer MOSFET PC. Therefore, the supply current IPP of the charge pump circuit PC0 is
IPP = (C / 2) × (3 × VCC−Vthp−VPP) × η _c / T ……………………… (9)
It becomes. Further, an equivalent pump capacity C of the charge pump circuit PC0 obtained from this equation _i The
C _i = (C / 2) × (3 × VCC−Vthp−VPP) × η _c / VCC
And other capacity that does not contribute to boosting is C _L Then, the supply efficiency η of the charge pump circuit PC0 is still
η = C _i / (2 × C _L +3 x C _i ) …………………………………… (10)
It becomes.
[0091]
For this reason, the supply efficiency η of the charge pump circuit PC0 obtained by the above equation (10) is generally that of the transfer MOSFET PC as compared with the embodiment of FIGS. 8 and 9, as shown by the thick solid line in FIG. Similarly to the supply efficiency η, the supply current IPP obtained by the threshold voltage Vthp is smaller than the supply current IPP obtained by the above equation (9), as shown by the thick solid line in FIG. As a result, the threshold voltage Vthp of the transfer MOSFET PC is reduced as a whole.
[0092]
That is, in this embodiment, the supply efficiency and the supply current are slightly reduced as compared with the embodiments of FIGS. 8 and 9, but the gate voltage booster circuit and the level shift circuit LSF for controlling the gate potential of the transfer MOSFET PC are not provided. It becomes unnecessary, and the circuit configuration of the charge pump circuit PC0 can be further simplified. However, if the potential of the internal voltage VPP is increased to some extent, the transfer MOSFET is a P-channel type, which may cause latch-up.
[0093]
FIG. 14 is a partial circuit diagram showing a sixth embodiment of the charge pump circuit PC0 included in the VPP generation circuit VPPG of the dynamic RAM shown in FIG. The charge pump circuit PC0 of this embodiment basically follows the embodiment of FIG. 6 and FIGS. 8 to 11, and therefore, only the portions different from this will be described. FIG. 14 partially shows a portion related to the gate voltage booster circuit of the charge pump circuit PC0. As is apparent from the above embodiment, the charge pump circuit PC0 includes j−1 unit boost circuits. It goes without saying that an N-channel type output transfer MOSFET that receives the output voltage of the internal voltage booster circuit including the gate voltage booster circuit or the gate voltage booster circuit is provided.
[0094]
14, in the charge pump circuit PC0 of this embodiment, the source of the second node, that is, the transfer MOSFETs P81 to P8j is one electrode of the capacitor C2 (first capacitor), that is, the upper electrode, or the first circuit of the preceding circuit. It includes j-stage unit boost circuits UB1 to UBj that are substantially serially coupled in such a manner that they are sequentially coupled to the nodes, that is, the upper electrodes of capacitors C31 to C3j-1. Upper electrodes of capacitors C31 to C3j (first capacitors) constituting these unit boost circuits UB1 to UBj are coupled to a power supply voltage VCC via corresponding N-channel precharge MOSFETs NC1 to NCj. The unit boost circuits UB1 to UBj perform the precharge operation for the capacitors C31 to C3j when the internal node n2 is set to the low level and the internal node n5 is set to the high level, and the internal node n2 is set to the high level. When n6 is set to the high level, the boost operation as described above is performed. At this time, the capacitors C31 to C3j constituting the unit boost circuits UB1 to UBj are coupled in series, and a high potential VB of (j + 1) × VCC is obtained at the upper electrode of the capacitor C3j of the unit boost circuit UBj in the final stage. It becomes.
[0095]
In this embodiment, the power supply voltage VCC is supplied as the third potential to the gates of the transfer MOSFETs P81 and MOSFETN91 constituting the unit boost circuit UB1, and the transfer MOSFETs P82 to P8j and MOSFETN92 constituting the other unit boost circuits UB2 to UBj. The gates of .about.N9j are supplied with the potential at the first node of the preceding circuit, that is, the unit boost circuits UB1 to UBj-1, that is, the upper electrodes of the capacitors C31 to C3j-1, as the third potential. Therefore, when the boost operation of the unit boost circuits UB1 to UBj is performed, the voltage applied between the gates and drains of these transfer MOSFETs P81 to P8j and MOSFETs N91 to N9j is independent of the potential of the generated internal voltage VPP. All are VCC. As a result, breakdown breakdown of these MOSFETs can be further prevented, and the reliability of the charge pump circuit PC0 and thus the dynamic RAM can be further enhanced.
[0096]
The effects obtained from the above embodiments are as follows. That is,
(1) A booster circuit, such as a VPP generation circuit, which is built in a dynamic RAM or the like and generates a selection potential of a word line, has one electrode coupled to a first potential supply point via a corresponding precharge MOSFET. A first capacitor, a second capacitor having one electrode coupled to the first node and further coupled to a first potential supply point via a corresponding precharge MOSFET, the other of the second capacitors An N-channel first MOSFET which is provided in series between the electrode and the second potential supply point and receives a third potential at its gate and an N-channel first which receives a first internal signal at its gate. 2 MOSFETs, and a P-channel type third MOSFET provided between the other electrode of the second capacitor and the second node and receiving a third potential at the gate thereof, respectively. An internal voltage booster circuit including one or more unit boost circuits substantially serially coupled in such a manner that the second node of the first capacitor is sequentially coupled to one electrode of the first capacitor or the first node of the preceding circuit. By configuring it as it is, an effect that an internal voltage having a desired high potential can be easily generated is obtained.
(2) According to the above item (1), it is possible to increase the supply efficiency of the VPP generation circuit and the like included in the dynamic RAM and the like where the operating power supply voltage is lowered and to increase the supply current.
[0097]
(3) In the above items (1) and (2), the first power supply voltage potential or the previous unit boost circuit is connected to the gates of the first and third MOSFETs of each unit boost circuit constituting the internal voltage booster circuit. By supplying the potential at the first node as the third potential, the voltage applied between the gate and drain of the first and third MOSFETs can be reduced to prevent breakdown of the breakdown voltage. It is done.
(4) According to the above (3), it is possible to improve the reliability of the VPP generation circuit and the dynamic RAM including the VPP generation circuit.
[0098]
(5) In the above items (1) to (4), an N-channel type output transfer MOSFET is provided between the output terminal of the internal voltage booster circuit and the internal voltage supply point. By supplying the output voltage of the gate voltage booster circuit having the same structure as the voltage booster circuit and including one unit booster circuit, the high potential generated by the internal voltage booster circuit is output regardless of the potential of the internal voltage. An effect is obtained that it can be prevented from being lowered by the threshold voltage of the transfer MOSFET.
(6) According to the above item (5), it is possible to further increase the supply efficiency of the VPP generation circuit included in the dynamic RAM or the like where the operating power supply voltage is lowered, and to increase the supply current. .
[0099]
(7) In the above items (5) and (6), the output transfer MOSFET is replaced with a P-channel MOSFET, and the gate of the output transfer MOSFET is applied to the gate by applying a control voltage converted in potential by the level shift circuit. An effect is obtained in that the gate voltage booster circuit for boosting the potential is eliminated, and the circuit configuration of the VPP generation circuit can be simplified.
(8) In the above items (5) and (6), the output transfer MOSFET is replaced with a diode-shaped N-channel or P-channel MOSFET, thereby eliminating the gate voltage booster circuit and the level shift circuit, and the VPP generation circuit. The circuit configuration can be further simplified.
[0100]
(9) In the above items (1) to (8), between the first power supply voltage supply point and the first internal node to which the gate of the precharge MOSFET and one electrode of the fourth capacitor are coupled. By providing the sixth N-channel MOSFET that receives the output voltage of the internal voltage booster circuit or the gate voltage booster circuit, it is possible to prevent the potential of the first internal node from becoming unspecified due to a power bump or the like. As a result, the operation of the circuit and the dynamic RAM can be further stabilized.
[0101]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the dynamic RAM can include an arbitrary number of banks, and the VPP generation circuit VPPG also includes an arbitrary number of one-shot pulse generation circuits, pulse synthesis circuits, and charge pump circuits. It will be prepared. Various block configurations of the dynamic RAM and its VPP generation circuit VPPG are conceivable. The polarity and absolute value of the power supply voltage and each internal voltage, the effective level of each signal, and the like are not limited by this embodiment. Embodiments can be taken.
[0102]
2, 3, 4, and 5, the specific configurations of the one-shot pulse generation circuits OP <b> 0 to OP <b> 3, the level sensor LS, the oscillation circuit OSC, and the pulse synthesis circuits ADD <b> 0 to ADD <b> 3 can take various embodiments. 6 and 8 to 11, the charge pump circuits PC0 to PC3 can include an arbitrary number of unit booster circuits. Further, in FIG. 14, the MOSFETs N91 to N9j constituting the unit boost circuits UB1 to UBj are replaced with a plurality of N-channel MOSFETs coupled in series, thereby further preventing breakdown of the MOSFETs NA1 to NAj that are turned off during boosting. can do. The specific circuit configuration of the charge pump circuit PC0 shown as each example, the conductivity type of the MOSFET, and the like can take various embodiments as long as the basic logic conditions are not changed.
[0103]
In FIG. 7, the absolute level and time relationship of each internal signal of the charge pump circuit PC0 does not affect the gist of the present invention.
[0104]
In the above description, the case where the invention made mainly by the present inventor is applied to the VPP generation circuit of the dynamic RAM, which is a field of use as the background, has been described. However, the present invention is not limited thereto. The present invention can also be applied to various types of memory integrated circuit devices and logic integrated circuit devices including other types of booster circuits of type RAM and similar booster circuits. The present invention can be widely applied to a booster circuit including at least a boost capacitor and an apparatus or system including the booster circuit.
[0105]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, a booster circuit such as a VPP generation circuit that is incorporated in a dynamic RAM or the like and generates a word line selection potential is connected to the first potential supply point via a corresponding precharge MOSFET. 1 capacitor, one electrode of which is coupled to the first node and further coupled to the first potential supply point via the corresponding precharge MOSFET, the other electrode of the second capacitor And an N channel type second MOSFET that receives a third potential at its gate and an N channel type second that receives a first internal signal at its gate. And a P-channel third MOSFET provided between the other electrode of the second capacitor and the second node and receiving a third potential at its gate. An internal voltage booster including one or more unit boost circuits coupled in series in a manner such that the second node is sequentially coupled to one electrode of the first capacitor or the first node of the preceding circuit. By constructing based on the circuit, it is possible to easily generate an internal voltage that is set to a desired high potential, and to improve the supply efficiency of the VPP generation circuit and the like included in a dynamic RAM or the like where the operating power supply voltage is lowered. The supply current can be increased.
[0106]
The first power supply voltage potential or the potential at the first node of the preceding unit boost circuit is supplied as the third potential to the gates of the first and third MOSFETs of each unit boost circuit constituting the internal voltage booster circuit. As a result, the voltage applied between the gate and drain of the first and third MOSFETs can be reduced to prevent breakdown of the breakdown voltage. As a result, the VPP generation circuit and the dynamic RAM including the same can be prevented. Reliability can be increased.
[0107]
A P-channel or N-channel output transfer MOSFET is provided between the output terminal of the internal voltage booster circuit and the internal voltage supply point, and the output transfer MOSFET has the same configuration as that of the internal voltage booster circuit at the gate. By supplying the output voltage of the gate voltage booster circuit including the unit boost circuit having many stages or the control voltage converted by the level shift circuit, the high potential generated by the internal voltage booster circuit is independent of the internal voltage potential. It is possible to prevent the output transfer MOSFET from being lowered by the threshold voltage, thereby further improving the supply efficiency of the VPP generation circuit and the dynamic RAM including this, and further increasing the supply current. .
[0108]
A predetermined voltage constituting an internal voltage booster circuit or a gate voltage booster circuit is formed between the first power supply voltage supply point and the first internal node to which the gate of the precharge MOSFET and one electrode of the fourth capacitor are coupled. By providing an N-channel type sixth MOSFET that receives the boosted voltage of the unit boost circuit, it is possible to prevent the potential of the first internal node from becoming unspecified due to a power supply bump or the like. Such operations can be further stabilized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a dynamic RAM to which the present invention is applied.
FIG. 2 is a circuit diagram showing an embodiment of a one-shot pulse generation circuit included in the VPP generation circuit of the dynamic RAM in FIG. 1;
FIG. 3 is a circuit diagram showing an embodiment of a level sensor included in the VPP generation circuit of the dynamic RAM shown in FIG.
4 is a circuit diagram showing an embodiment of an oscillation circuit included in the VPP generation circuit of the dynamic RAM shown in FIG. 1; FIG.
5 is a circuit diagram showing an embodiment of a pulse synthesis circuit included in the VPP generation circuit of the dynamic RAM of FIG. 1;
6 is a circuit diagram showing a first embodiment of a charge pump circuit included in the VPP generation circuit of the dynamic RAM of FIG. 1; FIG.
7 is a signal waveform diagram showing an embodiment of the charge pump circuit of FIG. 6. FIG.
8 is a circuit diagram showing a second embodiment of a charge pump circuit included in the VPP generation circuit of the dynamic RAM of FIG. 1; FIG.
9 is a circuit diagram showing a third embodiment of the charge pump circuit included in the VPP generation circuit of the dynamic RAM of FIG. 1; FIG.
10 is a circuit diagram showing a fourth embodiment of a charge pump circuit included in the VPP generation circuit of the dynamic RAM of FIG. 1; FIG.
11 is a circuit diagram showing a fifth embodiment of the charge pump circuit included in the VPP generation circuit of the dynamic RAM of FIG. 1; FIG.
12 is a characteristic diagram showing an embodiment for explaining the supply efficiency of the charge pump circuit of FIG. 6 and FIGS. 8 to 11. FIG.
13 is a characteristic diagram showing an embodiment for explaining a supply current of the charge pump circuit of FIG. 6 and FIGS. 8 to 11. FIG.
14 is a partial circuit diagram showing a sixth embodiment of the charge pump circuit included in the VPP generation circuit of the dynamic RAM shown in FIG. 1; FIG.
FIG. 15 is a circuit diagram showing an example of a conventional charge pump circuit.
[Explanation of symbols]
IF ... Interface circuit, BANK0 to BANK3 ... Bank, ARY0 to ARY3 ... Memory array, BC0 to BC3 ... Bank controller, RBA ... Row bank address signal, CBA ... Column bank address signal, BR0 to BR3 ... Row bank selection signal, RD0 to RD3 ... Row address decoder, RA ... Row address signal, SA ... Sense amplifier, CD ... Column address decoder, CA ... Column address signal, VPPG ... VPP generation circuit, OP0-OP3 ...... One-shot pulse generation circuit, LS ... Level sensor, VPP ... Word line selection voltage, VR ... Reference voltage, OSC ... Oscillation circuit, ADD0 to ADD3 ... Pulse synthesis circuit, PC0 to PC3 ... Charge pump circuit.
UB1 to UBj: unit boost circuit, LSF: level shift circuit.
UVB1 to UVBk... Unit booster circuit, S1 to S2.
DET: Internal control signal, PCC0: Charge pump control signal.
P1 to PC, P81 to P8j... P channel MOSFET, N1 to NU, N91 to N9j, NA1 to NAj, NC1 to NCj, Na to Nf... N channel MOSFET, R1 to R8. ˜C18, C31 to C3j, Ca to Ce, Co... Capacity, V1 to VM, Va to Vd... Inverter, EO1... Exclusive OR circuit, NO1 to NO6. , B1 to b4, na to nb, nv, n11 to n1k... Internal node, VCC... Power supply voltage, VSS... Ground potential, VPP, VDL.

Claims (6)

A first capacitor having an upper electrode coupled to a first potential supply point via a corresponding precharge MOSFET;
A second capacitor coupled to the output node and coupled to the first potential supply point via a corresponding precharge MOSFET; a lower electrode of the second capacitor; and a second potential. A first conductivity type first MOSFET that receives the potential of the first potential supply point at a gate provided in series with the supply point, and a first conductivity type first MOSFET that receives a first internal signal at its gate. Unit boost circuit including two MOSFETs and a second MOSFET of the second conductivity type that receives the potential of the first potential supply point at the gate provided between the lower electrode of the second capacitor and the input node Including
The second MOSFET is provided on the second potential supply point side,
The input node of the unit boost circuit is coupled to the upper electrode of the first capacitor;
A gate of the precharge MOSFET is coupled to a first internal node;
A fourth capacitor having an upper electrode coupled to the first internal node;
A predetermined number of fourth MOSFETs of a first conductivity type provided between a first potential supply point and the first internal node and having a diode form with the first internal node side as an anode; ,
A predetermined number of fifth conductivity type fifth MOSFETs that are provided between a first potential supply point and the first internal node and are in the form of a diode with the first potential supply point side as an anode. When,
A sixth conductivity type sixth MOSFET is provided between the first potential supply point and the first internal node, and a gate is coupled to the upper electrode of the first capacitor. A booster circuit. The booster circuit according to claim 1,
The first capacitor and the unit boost circuit constitute a gate voltage booster circuit,
The booster circuit further includes an internal voltage including the plurality of unit boost circuits and a third capacitor (C4) whose upper electrode is coupled to the first potential supply point via a corresponding precharge MOSFET. A booster circuit;
An output transfer MOSFET of a first conductivity type provided between the upper electrode of the third capacitor and an internal voltage supply point and receiving the output voltage of the gate voltage booster circuit at its gate;
The booster circuit according to claim 1, wherein the gate of the first MOSFET and the gate of the third MOSFET receive a potential at a first potential supply point . The booster circuit according to claim 2, wherein
The internal voltage booster circuit further includes:
Including i unit boost circuits coupled substantially in series such that the input node is sequentially coupled to the upper electrode of the third capacitor or the output node of the preceding circuit;
The gate voltage booster circuit
A booster circuit comprising: (i + 1) unit boost circuits that are substantially serially coupled such that the input node is sequentially coupled to the upper electrode of the first capacitor or the output node of the preceding circuit. The booster circuit according to claim 1,
The first capacitor and the unit boost circuit constitute an internal voltage booster circuit,
The booster circuit further includes:
The internal voltage at the internal voltage supply point is a high-potential side operating voltage source, the second potential is a low-potential side operating voltage source, and the output signal is selectively effective level according to the second internal signal. A level shift circuit and
A booster provided between an upper electrode of the second capacitor and an internal voltage supply point, and including a second conductivity type output transfer MOSFET for receiving an output signal of the level shift circuit at a gate. circuit. The booster circuit according to claim 1,
The first capacitor and the unit boost circuit constitute an internal voltage booster circuit,
The booster circuit further includes:
A first conductivity type or a second conductivity type provided between the upper electrode of the second capacitor and the internal voltage supply point, and having a diode shape with the upper electrode side of the first capacitor as an anode. A booster circuit including an output transfer MOSFET. The booster circuit according to any one of claims 1 to 5,
The booster circuit is included in a dynamic RAM having a plurality of banks, and is provided corresponding to each of the banks,
The booster circuit according to claim 1, wherein the internal voltage at the internal voltage supply point is used as a selection potential of a word line constituting the bank.

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