JP4047075B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a gate insulating film made of a high dielectric material.
[0002]
[Prior art]
With the recent progress in technology for higher integration and higher speed in semiconductor devices, MOSFETs have been miniaturized. As the gate insulating film is made thinner with miniaturization, problems such as an increase in gate leakage current due to tunneling current become obvious. In order to suppress this problem, HfO ₂ , ZrO ₂ , La ₂ O _Three TiO ₂ Or Ta ₂ O _Five By using a gate insulating film (hereinafter referred to as a high-k gate insulating film) using a high dielectric constant material such as ₂ A method of increasing the physical film thickness while realizing the equivalent film thickness (hereinafter referred to as EOT (Equivalent Oxide Thickness)) has been studied.
[0003]
In recent system LSIs, it is common to integrate an internal circuit that performs arithmetic processing, a peripheral circuit that handles input and output, and a circuit having a plurality of functions such as a DRAM on a single chip. For a MOSFET constituting such a system LSI, high driving force and low leakage current are required.
[0004]
As a conventional method for forming a high-k gate insulating film, a method described in JP 2000-058832 A (United States Patent 6,013,553) is known.
[0005]
FIG. 5 shows a cross-sectional structure of a conventional semiconductor device disclosed in the above publication, specifically, a MOSFET having a high-k gate insulating film made of zirconium oxynitride or hafnium oxynitride.
[0006]
As shown in FIG. 5, an epitaxial Si layer 2 is formed on the Si substrate 1. The upper portion of the epitaxial Si layer 2 is doped with impurities, and the upper portion becomes the channel region 3 when a voltage is applied. A conductive gate electrode 5 is formed on the channel region 3 via a high-k gate insulating film 4.
[0007]
The formation method of the high-k gate insulating film 4 is as follows. That is, after forming the epitaxial Si layer 2 including the portion to become the channel region 3 on the Si substrate 1, the pressure is 1.33 × 10 × 10. ^-1 An oxide layer having a thickness of less than 1 nm is formed by performing a heat treatment at about 600 to 700 ° C. for about 30 seconds on the Si substrate 1 in an oxygen atmosphere of about Pa. Thereafter, the oxide layer is left as it is, or is removed by dilute HF, and the Si surface is terminated with hydrogen, or an ultrahigh vacuum state (1.33 × 10 6 using a cluster tool) is used. ^-6 Either a sublimation by a heat treatment at about 780 ° C. at about Pa) to form an atomically smooth Si surface is performed. Instead of leaving the oxide layer, that is, the silicon oxide film, a protective barrier layer made of an ultrathin silicon oxynitride film may be formed.
[0008]
After preparing the Si substrate 1 having either a clean Si surface, an oxide layer, or a protective barrier layer as described above, a sputtering method, vapor deposition method, chemical vapor deposition (CVD) is performed on the Si substrate 1. A metal layer made of zirconium or hafnium is deposited by a method or a plasma CVD method. Then, NO or N against the metal layer ₂ Oxynitriding treatment using a gas containing oxygen and nitrogen such as O, N ₂ And O ₂ Remote plasma processing at low temperature using a substrate (the substrate processing chamber and the plasma generation chamber are different), or NH _Three A high-k gate insulating film 4 made of zirconium oxynitride or hafnium oxynitride is formed by performing a remote plasma nitridation process using silicon and a subsequent oxidation process.
[0009]
Thereafter, the high-k gate insulating film 4 is densified by annealing the high-k gate insulating film 4 at about 750 ° C. for 20 seconds in an inert gas atmosphere such as Ar or a reducing gas atmosphere. To do. The high-k gate insulating film 4 thus formed is amorphous or polycrystalline, and SiO ₂ The dielectric constant is significantly higher than the relative dielectric constant.
[0010]
[Problems to be solved by the invention]
However, the above-described conventional MOSFET has a problem that the reliability life of the high-k gate insulating film is shortened.
[0011]
In view of the above, an object of the present invention is to realize a high-k gate insulating film having a long reliability life.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, the present inventor has studied the cause of shortening of the reliability life of the conventional high-k gate insulating film, and as a result, has obtained the following knowledge. That is, when a high-k gate insulating film is formed on a silicon substrate by using the above-described conventional method, SiO interface is formed on the silicon substrate interface. ₂ A silicate (a ternary compound of high-k material (metal oxide such as zirconium oxide) and silicon) is formed. In general, silicates have a lower dielectric constant than the original high-k material that does not contain silicon. Further, as a result of the crystallization of the high-k material constituting the gate insulating film being advanced by annealing (PDA (Post Deposition Anneal) for densifying the gate insulating film) after the deposition of the high-k gate insulating film, oxygen diffuses from the -k material through the grain boundaries to the silicon substrate, which causes SiO at the silicon substrate interface ₂ Will be formed. That is, the high-k gate insulating film is made of SiO having a low relative dielectric constant. ₂ Or SiO ₂ And a high-k layer having a high relative dielectric constant or a high-k layer having a silicate close to the composition of the high-k material. However, in such a laminated structure, when a voltage is applied through the gate electrode, electric field concentration occurs in the interface layer having a low dielectric constant, and as a result, dielectric breakdown is likely to occur, resulting in a high-k gate insulating film. It is considered that the reliability, which is an important characteristic of, deteriorates.
[0013]
Accordingly, the inventor of the present application has determined that the reliability lifetime of the high-k gate insulating film and the ratio of the interface layer thickness to the total thickness of the high-k gate insulating film are T1 / (T1 + T2) (where T1 is the interface layer thickness). The correlation with the physical thickness (T2 is the physical thickness of the high-k layer) was examined using simulation. The result is shown in FIG. The simulation was performed by applying a trap generation model (JHStathis, Technical Digest of International Electron Device and Material (1998), p167.) To a high-k gate insulating film. Specifically, for the high-k gate insulating film, the leakage current J _g Leakage current J immediately after stress application ₀ , Defect generation rate per injected charge P _g (= Current increase ratio ΔJ at dielectric breakdown) _g / J ₀ ), And critical defect density N when it leads to dielectric breakdown _bd , And based on these values, the dielectric breakdown lifetime T in the high-k gate insulating film is obtained. _bd (= N _bd / P _g ) In the simulation, the ratio T1 / (T1 + T2) is changed while adjusting the physical thicknesses T1 and T2 so that the EOT of the high-k gate insulating film is always kept at 1.5 nm. The reliability lifetime of the high-k gate insulating film under a stress of 1 V applied voltage (temperature is room temperature) was calculated. However, in the simulation, the relative dielectric constant ε1 of the interface layer is fixed to a constant value of 3.9, whereas the relative dielectric constant ε2 of the high-k layer is 8.0, 12.0, 18.0. And multiple values of 24.0. Here, the relationship EOT = T1 + (ε1 / ε2) × T2 holds.
[0014]
As shown in FIG. 1, when the ratio T1 / (T1 + T2), that is, the ratio of the interface layer thickness to the total thickness of the high-k gate insulating film is 0.2 or less, the reliability of the high-k gate insulating film Can be kept high. Further, as the ratio T1 / (T1 + T2) increases, the reliability of the high-k gate insulating film tends to deteriorate. Furthermore, considering that the logarithmic scale is used for the vertical axis in FIG. 1, setting the ratio T1 / (T1 + T2) to 0.2 or less dramatically improves the reliability of the high-k gate insulating film. It turns out that it has the effect to make it. Specifically, by setting the ratio T1 / (T1 + T2) to 0.2 or less, for example, the reliability life is increased by three orders of magnitude or more compared to the case where the ratio T1 / (T1 + T2) is about 0.5. can do.
[0015]
Further, as shown in FIG. 1, in a gate insulating film having a structure where the ratio T1 / (T1 + T2) is 0.0 to 0.2, the high-k layer has a relative dielectric constant ε2 of 8.0 to 12.2. As the value increases to 0, the length of the reliability life increases, and in the range of ε2 from 12.0 to 18.0, the length of the reliability life is almost saturated and shows the maximum value. On the other hand, when ε2 increases from 18.0 to 24.0, the length of the reliability life decreases. Incidentally, in general, the value of the relative dielectric constant ε2 in the high-k layer changes in the thickness direction. Therefore, the average value of the relative dielectric constant ε2 in the high-k layer is ε2 _av Ε2 _av Is preferably 12.0 or more and 18.0 or less. When a silicate film containing one metal, silicon and oxygen is used as the high-k layer, the composition of the high-k layer is M _X Si _Y Assuming O (where M represents one metal and X> 0 and Y> 0), 12.0 ≦ ε2 described above _av The condition of ≦ 18.0 is equivalent to the condition of 0.20 ≦ Y / (X + Y) ≦ 0.30. That is, from the viewpoint of the reliability of the high-k gate insulating film, 0.20 ≦ Y / (X + Y) ≦ 0.30 rather than using a complete metal oxide containing no silicon as the material of the high-k layer. Silicon-containing silicate M satisfying the relationship _X Si _Y It is preferable to use O. The reason is considered to be that the electric field concentration on the interface layer is reduced by reducing the difference in relative dielectric constant between the high-k layer and the interface layer. The interface layer is also M _X Si _Y In some cases, silicate represented by O may be included, but Y / (X + Y) in this silicate is 0.90 or more, and compositionally SiO 2 ₂ Is almost equivalent.
[0016]
Further, the inventor of the present application has determined the reliability lifetime of the high-k gate insulating film and the total thickness (T1 + T2) of the high-k gate insulating film having the interface layer thickness T1 (where T2 is the physicality of the high-k layer). The correlation with the ratio to the thickness was determined experimentally. The result is shown in FIG. The interface layer used in the experiment has a composition of SiO. ₂ SiON film (relative permittivity ε1 = 3.9) close to, and the high-k layer used in the experiment is Si formed by CVD (chemical vapor deposition) method. _Three N _Four It is a film (relative dielectric constant ε2 = 7.5). In the experiment, the ratio T1 / (T1 + T2) was changed while adjusting the physical thicknesses T1 and T2 so that the EOT of the high-k gate insulating film always kept 3.0 nm. The total amount of charge injected into the insulating film before breakdown occurs under a stress of applied voltage 3.5 V (temperature is 100 ° C.) (total breakdown charge Q _bd ) Was measured. Here, the total dielectric breakdown Q _bd Corresponds to the reliability lifetime of the high-k gate insulating film.
[0017]
As shown in FIG. 2, when the ratio T1 / (T1 + T2) is 0.2 or less, the reliability of the high-k gate insulating film can be maintained high. On the other hand, when the ratio exceeds 0.3, the reliability increases rapidly. It was experimentally proved to deteriorate. In addition, considering that the logarithmic scale is used on the vertical axis in FIG. 2, setting the ratio T1 / (T1 + T2) to 0.2 or less dramatically improves the reliability of the high-k gate insulating film. It turns out that it has the effect to make it.
[0018]
As described above, from the results shown in FIGS. 1 and 2, from the viewpoint of the reliability of the high-k gate insulating film, the ratio of the interface layer thickness T1 to the total thickness (T1 + T2) is set to 0.3 or less. It is essential that the ratio T1 / (T1 + T2) is 0.2 or less.
[0019]
The present invention has been made based on the above knowledge. Specifically, the semiconductor device according to the present invention is premised on a semiconductor device having a high dielectric constant insulating film formed on a semiconductor substrate. The dielectric constant insulating film has an interface layer formed at the interface with the semiconductor substrate, and a high dielectric constant layer formed on the interface layer and having a higher relative dielectric constant than the interface layer, and the thickness of the interface layer T1 and the thickness T2 of the high dielectric constant layer satisfy the relationship of T1 / (T1 + T2) ≦ 0.3.
[0020]
According to the semiconductor device of the present invention, when the ratio of the interface layer thickness T1 to the total thickness (T1 + T2) in the high dielectric constant insulating film is set to 0.3 or less, the voltage is applied to the high dielectric constant insulating film. Also, the electric field concentration on the interface layer can be suppressed. Therefore, a high-k gate insulating film having a long reliability life can be realized by using such a high dielectric constant insulating film. At this time, since the interface layer having a low relative dielectric constant is thin and the high dielectric constant layer having a high relative dielectric constant is thick, the EOT of the high-k gate insulating film can be reduced.
[0021]
In the semiconductor device of the present invention, T1 and T2 preferably satisfy the relationship of T1 / (T1 + T2) ≦ 0.2.
[0022]
In this way, the reliability of the high dielectric constant insulating film can be further improved.
[0023]
In the semiconductor device of the present invention, the relative dielectric constant ε1 of the interface layer is 3.9 or more and 7.0 or less, and the relative dielectric constant ε2 of the high dielectric layer is larger than 7.0. Average value ε2 of relative permittivity ε2 _av Is preferably 12.0 or more and 18.0 or less.
[0024]
In this way, since the difference in relative dielectric constant between the high dielectric constant layer and the interface layer is limited within a predetermined range, the electric field concentration on the interface layer during voltage application is further relaxed, and the high dielectric constant The reliability of the insulating film can be further improved.
[0025]
In the semiconductor device of the present invention, the relative dielectric constant ε1 of the interface layer is 3.9 or more and 7.0 or less, and the relative dielectric constant ε2 of the high dielectric layer is larger than 7.0. , Which consists of a silicate containing one metal, silicon and oxygen, and the composition of the high dielectric constant layer is M _X Si _Y When O (where M represents one metal and X> 0 and Y> 0), X and Y satisfy the relationship of 0.20 ≦ Y / (X + Y) ≦ 0.30. Is preferred.
[0026]
In this way, the relative dielectric constant difference between the high dielectric constant layer and the interface layer is reduced compared to the case where a complete metal oxide not containing silicon is used as the material of the high dielectric constant layer. Electric field concentration on the interface layer during voltage application is further relaxed, and as a result, the reliability of the high dielectric constant insulating film can be further improved.
[0027]
In the semiconductor device of the present invention, the high dielectric constant layer is preferably made of silicate containing hafnium or zirconium, silicon, and oxygen.
[0028]
In this way, a high-k gate insulating film having a long reliability life can be reliably realized.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.
[0030]
3A to 3E are cross-sectional views showing respective steps of the semiconductor device manufacturing method according to the present embodiment.
[0031]
As shown in FIG. 3A, for example, an element isolation insulating film 12 is formed on a Si (100) substrate 11, thereby forming a device region R. _D Is specified.
[0032]
Next, after sequentially performing standard RCA cleaning and diluted HF cleaning on the Si substrate 11, for example, NH _Three A heat treatment at about 600 to 700 ° C. is performed on the Si substrate 11 in a gas. As a result, as shown in FIG. _D A silicon nitride film (Si _Three N _Four Film) 13 is formed.
[0033]
Next, as shown in FIG. 3C, for example, the CVD method is used to form Si. _Three N _Four HfO on the film 13 ₂ A film 14 is formed. Specifically, Hf t-butoxide (C ₁₆ H ₃₆ HfO _Four ) N inside ₂ Bubbling is performed by blowing a carrier gas such as. As a result, the liquid Hf source is made into a gaseous state, the source gas is introduced into the reaction furnace together with the carrier gas, and HfO is used by using RT-CVD (Rapid Thermal CVD) treatment at a temperature of about 500 ° C. ₂ A film 14 is formed. At this time, HfO ₂ In order to improve the growth rate or film quality of the film 14, the dry O ₂ Gas is introduced into the reactor. HfO formed in this way ₂ When the composition analysis was performed on the film 14, Hf, O, C, and H were contained in the Hf source. ₂ The film 14 contained trace amounts of C and H of about 1 to 2 atomic% or less. In the reactor, N ₂ Gas is also introduced, but at temperatures around 500 ° C, N ₂ Since the gas is very inert, N ₂ The contribution of gas is very small.
[0034]
Next, for example, N ₂ In gas, HfO ₂ The film 14 is subjected to PDA treatment at about 600 to 800 ° C. for about 30 seconds. As a result, oxidation of the Si substrate 11 and HfO ₂ Desorption of hydrogen from the film 14, HfO ₂ Densification and microcrystallization of the film 14, and Si substrate 11 or Si _Three N _Four Film 13 and HfO ₂ Reaction such as interdiffusion of Si and Hf with the film 14 occurs. As a result, HfO ₂ Si is deposited on the Si substrate 11 at the beginning of deposition of the film 14 (see FIG. 3C). _Three N _Four A film 13 is formed and Si _Three N _Four HfO on the film 13 ₂ The structure in which the film 14 is formed finally has an interface layer 15 having a low relative dielectric constant formed on the Si substrate 11 and a high relative dielectric constant on the interface layer 15 as shown in FIG. The structure changes to the structure in which the high-k layer 16 is formed. Here, the interface layer 15 is made of SiO. ₂ Or SiO ₂ The high-k layer 16 is made of silicate close to the composition of HfO. ₂ Or HfO ₂ It consists of a silicate close to the composition. Further, the interface layer 15 and the high-k layer 16 each contain a small amount of N.
[0035]
Next, as shown in FIG. 3E, a gate electrode 17 made of, for example, polysilicon is formed on the high-k gate insulating film having a laminated structure of the interface layer 15 and the high-k layer 16. Specifically, SiH _Four After forming a polysilicon film at a deposition temperature of about 540 ° C. using, for example, 5 × 10 5 with respect to the polysilicon film ¹⁵ The gate electrode 17 is formed by implanting P ions at a dose of cm −2 and then patterning the ion-implanted polysilicon film. Thereby, the nMOSFET structure is completed. The activation annealing for the impurities implanted into the gate electrode 17 is performed by dry N ₂ This was performed by RTP (Rapid Thermal Process) in gas at 900 ° C. for 30 seconds.
[0036]
The feature of this embodiment is, for example, HfO ₂ Before the film 14 is formed, Si is deposited on the Si substrate 11. _Three N _Four By forming the film 13, or for example HfO ₂ The ratio of the thickness of the interface layer 15 to the total thickness of the high-k gate insulating film is set to a predetermined value by setting the PDA processing temperature for the film 14 lower or by setting the PDA processing time shorter. It is to set within the range. Specifically, the thickness T1 of the interface layer 15 with respect to the total thickness of the high-k gate insulating film, that is, the total thickness (T1 + T2) of the thickness T1 of the interface layer 15 and the thickness T2 of the high-k layer 16 Is set to 0.3 or less, more preferably 0.2 or less. Thereby, in this embodiment, since electric field concentration on the interface layer 15 can be suppressed even when a gate voltage is applied, a high-k gate insulating film having a long reliability life can be realized. Further, CV (capacitance-voltage) measurement is performed using a LCR (inductance-capacitance-resistance) meter for a MOS capacitor having a gate insulating film in which the interface layer 15 and the high-k layer 16 are laminated, When the EOT of the gate insulating film was calculated by a simulation program in consideration of the depletion of the gate electrode or the quantization effect of the substrate based on the measurement result, a sufficiently small EOT was obtained. That is, in the present embodiment, since the interface layer 15 having a low relative dielectric constant is thin and the high-k layer 16 having a high relative dielectric constant is thick, the EOT of the high-k gate insulating film can be reduced.
[0037]
FIG. 4A shows the semiconductor device of this embodiment, that is, HfO formed using an Hf precursor. ₂ 3 shows a high-resolution cross-sectional TEM (transmission electron microscope) image of a MOSFET provided with a gate insulating film whose dielectric is a high-k material. As shown in FIG. 4A, the total thickness of the high-k gate insulating film in the semiconductor device of this embodiment (the sum of the thickness T1 of the interface layer 15 and the thickness T2 of the high-k layer 16 (T1 + T2 )) Is about 3.0 to 3.3 nm. Further, the thickness T1 of the interface layer 15 is about 0.4 to 0.5 nm. That is, the ratio T1 / (T1 + T2) of the thickness of the interface layer 15 to the total thickness of the high-k gate insulating film is about 0.12 to 0.17, and the relationship recommended in the present invention: T1 / (T1 + T2) ≦ 0.3 (more preferably T1 / (T1 + T2) ≦ 0.2) is sufficiently satisfied.
[0038]
FIG. 4B shows a semiconductor device as a comparative example, that is, HfO formed by the same method as in this embodiment. ₂ The high-resolution cross-sectional TEM image of the other MOSFET provided with the gate insulating film which uses a dielectric as a high-k material is shown. As shown in FIG. 4B, in the semiconductor device of the comparative example, the interface layer 25 and the high-layer are formed on the Si substrate 21 so as to correspond to the MOS capacitor structure of this embodiment shown in FIG. A gate electrode 27 made of Poly-Si is formed through a gate insulating film having a laminated structure with the k layer 26. In the semiconductor device of the comparative example, the total thickness of the high-k gate insulating film (the total of the thickness T1 ′ of the interface layer 25 and the thickness T2 ′ of the high-k layer 26 (T1 ′ + T2 ′)) Is about 3.0 to 3.3 nm. Further, the thickness T1 ′ of the interface layer 25 is about 1.0 nm. That is, the ratio T1 ′ / (T1 ′ + T2 ′) of the thickness of the interface layer 25 to the total thickness of the high-k gate insulating film is about 0.30 to 0.33, and is the relationship recommended in the present invention. Does not meet.
[0039]
The gate area is 5000 μm for each of the MOS capacitor structure of the present embodiment shown in FIG. 4A and the MOS capacitor structure of the comparative example shown in FIG. ² As a result, the reliability life of the gate insulating film under a stress (temperature is room temperature) under an applied voltage of 3.0 V (the gate electrode side is low potential) was calculated. As a result, the reliability lifetime of the gate insulating film of this embodiment in which the relative thickness of the interface layer is small is 1 × 10. ^Four The reliability life of the gate insulating film of the comparative example in which the relative thickness of the interface layer is large is about 1 × 10 seconds. ² It was about a second. That is, when the ratio T1 / (T1 + T2) of the interface layer thickness to the total thickness of the high-k gate insulating film is 0.2 or less, the reliability life of the high-k gate insulating film is dramatically improved. . This is presumably because if the low dielectric constant interface layer formed on the surface of the Si substrate can be made thin, it is possible to avoid the occurrence of reliability degradation due to the strong electric field strength concentrated on the interface layer.
[0040]
Incidentally, as shown in FIGS. 4A and 4B, in the high-resolution cross-sectional TEM image of the high-k gate insulating film, the image of the interface layer is clearly white compared to the image of the high-k layer. Here, the composition of the high-k gate insulating film is Hf _X Si _Y If O (where X> 0, Y> 0), Y / (X + Y) = 0.90 corresponds to the boundary between the interface layer and the high-k layer. Note that the composition of the high-k gate insulating film changes so that the Si composition gradually decreases from the Si substrate side, in other words, the value of Y / (X + Y) gradually decreases from 1.0. That is, the range satisfying the relationship of 0.90 ≦ Y / (X + Y) ≦ 1.0 is the interface layer, and the range satisfying the relationship of Y / (X + Y) <0.90 is the high-k layer. At this time, the relative dielectric constant ε1 of the interface layer is not less than 3.9 and not more than 7.0, and the relative dielectric constant ε2 of the high-k layer is larger than 7.0.
[0041]
In the present embodiment, Si on the Si substrate 11 _Three N _Four HfO through membrane 13 ₂ After forming the film 14, HfO ₂ PDA treatment was performed on the film 14, thereby forming a high-k gate insulating film having a stacked structure of the interface layer 15 and the high-k layer 16. Such a portion (near the substrate, near the electrode, the center of the film, etc.) may be included. PDA processing conditions are not particularly limited, but the PDA processing temperature is preferably about 800 ° C. or lower, and the PDA processing temperature is preferably about 30 seconds or lower.
[0042]
In the present embodiment, HfO is used by using Hf t-butoxide which is a liquid Hf source. ₂ A film 14 was formed, but HfO ₂ The formation method of the film | membrane 14 is not specifically limited. Specifically, for example, Hf nitrato (Hf (NO _Three ) _Four ) Is heated to a liquid state and a carrier gas such as Ar is blown into the liquid raw material to perform bubbling, and then the reaction of a CVD apparatus having a substrate heater and a cold wall with the vaporized raw material together with the carrier gas. Introduced into the furnace and then HfO using RT-CVD process at a temperature of about 200 ° C ₂ The film 14 may be formed. At this time, HfO ₂ In order to improve the growth rate or film quality of the film 14, the dry O ₂ Gas is introduced into the reactor. HfO formed in this way ₂ When composition analysis is performed on the film 14, Hf, O, and N are contained in the Hf source. ₂ The film 14 contains a trace amount of N of about 1 to 2 atomic% or less. Ar gas is also introduced into the reactor, but Ar gas is very inactive at a temperature of about 200 ° C., so the contribution of Ar gas is very small.
[0043]
In this embodiment, HfO is used as a material for the high-k gate insulating film (that is, the high-k layer 16 therein). ₂ Was used. However, instead of this, other metal oxides, specifically, Zr oxide having the same properties as Hf (ZrO ₂ ), TiO ₂ , Ta ₂ O _Five , La ₂ O _Three Or Al ₂ O _Three Also, when the thickness T1 of the interface layer 15 and the thickness T2 of the high-k layer 16 are T1 / (T1 + T2) ≦ 0.3 (more preferably T1 / (T1 + T2) ≦ 0.2). As long as the relationship (1) is satisfied, the dramatic improvement effect similar to that of the present embodiment occurs in the reliability lifetime of the high-k gate insulating film. In particular, the relative dielectric constant ε1 of the interface layer is 3.9 or more and 7.0 or less, and the relative dielectric constant ε2 of the high-k layer 16 is larger than 7.0. Average value of dielectric constant ε2 ε2 _av Is 12.0 or more and 18.0 or less, the following special effects can be obtained. That is, since the relative dielectric constant difference between the high-k layer 16 and the interface layer 15 is limited within a predetermined range, the electric field concentration on the interface layer 15 during voltage application is further relaxed, and the high-k layer The reliability of the gate insulating film can be further improved.
[0044]
In the present embodiment, the composition of the high-k gate insulating film (that is, the high-k layer 16 therein) is M. _X Si _Y A metal silicate represented by O (where M represents one metal and X> 0 and Y> 0) (may contain elements other than metal, silicon and oxygen), for example, Hf silicate (Hf _X Si _Y O ₂ ) Or Zr silicate (Zr _X Si _Y O ₂ ), Etc., as long as the relationship of ratio T1 / (T1 + T2) ≦ 0.3 (preferably the relationship of T1 / (T1 + T2) ≦ 0.2) is satisfied, the reliability lifetime of the high-k gate insulating film The same dramatic improvement effect as in the present embodiment occurs. In particular, the relative dielectric constant ε1 of the interface layer is 3.9 or more and 7.0 or less, the relative dielectric constant ε2 of the high-k layer 16 is larger than 7.0, and the high-k layer 16 is 0. Metal silicate M satisfying the relationship of 20 ≦ Y / (X + Y) ≦ 0.30 _X Si _Y When it is O, the following special effects are obtained. That is, the relative dielectric constant difference between the high-k layer 16 and the interface layer 15 is smaller than when a complete metal oxide not containing silicon is used. As a result, the reliability of the high-k gate insulating film can be further improved.
[0045]
By the way, HfO of this embodiment ₂ When, for example, an Hf silicate film is formed instead of the film 14, the following method can be used. That is, Hf t-butoxide (C ₁₆ H ₃₆ HfO _Four ) And Si source TDEAS (Tetrakis Diethyl Amino Silicon: Si [N (C ₂ H _Five ) ₂ ] _Four ) And N as the carrier gas ₂ After being introduced into the reaction furnace together with the gas, a Hf silicate film can be formed by performing a CVD process at a temperature of about 300 to 500 ° C. At this time, the composition of the Hf silicate film can be changed by adjusting the mixing ratio of the Hf source and the Si source or the temperature of the CVD process. Further, in order to improve the growth rate or film quality of the Hf silicate film, dry O ₂ Gas may be introduced into the reactor.
[0046]
In the present embodiment, the Si substrate 11 is used as the substrate, but instead of this, another semiconductor substrate such as a SiGe substrate or a SiC substrate may be used.
[0047]
In the present embodiment, a Poly-Si gate electrode is used as the gate electrode 17, but a metal gate electrode may be used instead. Specifically, a metal gate electrode having a laminated structure of a TiN film and an Al film or a single layer structure of a TaN film may be formed by using, for example, PVD (physical vapor deposition) by Ar sputtering.
[0048]
【The invention's effect】
According to the present invention, the ratio of the interface layer thickness T1 to the total thickness (T1 + T2) in the high-k gate insulating film is 0.3 or less, more preferably 0.2 or less. Therefore, the reliability life of the high-k gate insulating film can be improved.
[Brief description of the drawings]
FIG. 1 shows the reliability lifetime of a high-k gate insulating film and the total thickness of the high-k gate insulating film having an interface layer thickness T1 (T1 + T2) (where T2 is the physical thickness of the high-k layer) It is a figure which shows the result of having investigated the correlation with the ratio with respect to) using simulation.
FIG. 2 shows the reliability lifetime of the high-k gate insulating film and the total thickness of the high-k gate insulating film having the interface layer thickness T1 (T1 + T2) (where T2 is the physical thickness of the high-k layer) It is a figure which shows the result of having investigated the correlation with ratio to) by experiment.
FIGS. 3A to 3E are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIGS.
4A is a diagram showing a high-resolution cross-sectional TEM image of a semiconductor device according to an embodiment of the present invention, and FIG. 4B is a diagram showing a high-resolution cross-sectional TEM image of a semiconductor device according to a comparative example. is there.
FIG. 5 is a cross-sectional view of a conventional semiconductor device.
[Explanation of symbols]
11 Si substrate
12 Insulating film for element isolation
13 Si _Three N _Four film
14 HfO ₂ film
15 Interface layer
16 high-k layers
17 Gate electrode
21 Si substrate
25 Interface layer
26 high-k layer
27 Gate electrode
R _D Device area

Claims (28)

A semiconductor device having a high dielectric constant insulating film formed on a semiconductor substrate,
The high dielectric constant insulating film is
An interface layer formed at the interface with the semiconductor substrate;
A high dielectric constant layer formed on the interface layer and having a relative dielectric constant higher than that of the interface layer;
The interface layer thickness T1 and the high dielectric constant layer thickness T2 are:
Meet the relationship of T1 / (T1 + T2) ≦ 0.3,
The relative dielectric constant ε1 of the interface layer is 3.9 or more and 7.0 or less, and the relative dielectric constant ε2 of the high dielectric layer is larger than 7.0.
The high dielectric constant layer is made of a silicate containing a first metal, silicon, and oxygen,
When the composition of the high dielectric constant layer is M _X Si _Y O (where M represents the first metal and X> 0, Y> 0),
X and Y are
A semiconductor device characterized by satisfying a relationship of 0.20 ≦ Y / (X + Y) ≦ 0.30 . 2. The semiconductor device according to claim 1, wherein a relative dielectric constant ε <b> 2 of the high dielectric constant layer is greater than 7.0 and 18.0 or less. The semiconductor device according to claim 2, wherein a relative dielectric constant ε2 of the high dielectric constant layer is 12.0 or more and 18.0 or less. The semiconductor device according to claim 1, wherein the first metal is Hf or Zr. The semiconductor device according to claim 1, wherein the first metal is Ti, Ta, La, or Al. T1 and T2 are
T1 / (T1 + T2) The semiconductor device according to any one of claims 1-5 characterized by satisfying the relation of ≦ 0.2. The semiconductor device according to claim 1, wherein the interface layer contains nitrogen. The semiconductor device according to claim 7, wherein the nitrogen concentration in the interface layer is 4/7 or less in terms of atomic ratio. The semiconductor device according to claim 1, wherein the high dielectric constant layer contains carbon and hydrogen. The semiconductor device according to claim 9, wherein the carbon and hydrogen concentrations in the high dielectric constant layer are 2 atomic% or less. SiO of the high dielectric constant layer ₂ 11. The semiconductor device according to claim 1, wherein the converted film thickness is about 3.0 nm. SiO of the high dielectric constant layer ₂ 11. The semiconductor device according to claim 1, wherein the converted film thickness is 3.0 nm or less. SiO of the high dielectric constant layer ₂ The semiconductor device according to claim 12, wherein the converted film thickness is 1.5 nm or more and 3.0 nm or less. SiO of the high dielectric constant layer ₂ 13. The semiconductor device according to claim 12, wherein the converted film thickness is about 1.5 nm. SiO of the high dielectric constant layer ₂ 13. The semiconductor device according to claim 12, wherein the converted film thickness is less than 1.5 nm. The semiconductor device according to claim 1, wherein the high dielectric constant insulating film has a thickness of 3.3 nm or less. The semiconductor device according to claim 16, wherein a thickness of the high dielectric constant insulating film is not less than 3.0 nm and not more than 3.3 nm. The semiconductor device according to claim 16, wherein a thickness of the high dielectric constant insulating film is 3.0 nm or less. The semiconductor device according to claim 1, further comprising a gate electrode containing polysilicon on the high dielectric constant insulating film. The semiconductor device according to claim 1, further comprising a metal gate electrode on the high dielectric constant insulating film. 21. The semiconductor device according to claim 20, wherein the metal gate electrode includes at least one of Ti, Al, or Ta. 21. The semiconductor device according to claim 20, wherein the metal gate electrode includes TiN. 21. The semiconductor device according to claim 20, wherein the metal gate electrode contains TaN. The semiconductor device according to claim 1, wherein the semiconductor substrate is a Si substrate. The semiconductor device according to claim 1, wherein the semiconductor substrate is a SiC substrate. The semiconductor device according to claim 1, wherein the semiconductor substrate contains Ge. 27. The semiconductor device according to claim 26, wherein the semiconductor substrate is a SiGe substrate. 27. The semiconductor device according to claim 1, wherein the high dielectric constant layer has a crystallized portion and a crystal grain boundary.

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