JP2015069989A - Method of manufacturing silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress reduction in channel mobility caused by heat treatment after deposition of a gate insulating film.SOLUTION: A gate insulating film 10 is formed on a silicon carbide substrate 50. When the gate insulating film 10 is formed, firstly, a first layer 6a is deposited on the silicon carbide substrate 50 at a first temperature by a chemical vapor growth method. Then, the first layer 6a is annealed at a second temperature higher than the first temperature. Then, a second layer 6b is deposited on the first layer 6a after the first layer 6a is annealed. After the gate insulating film 10 is formed in this way, the silicon carbide substrate 50 is heated to a temperature higher than the second temperature.

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device, and more particularly to a method for manufacturing a silicon carbide semiconductor device having a gate insulating film.

Silicon carbide semiconductor devices, that is, semiconductor devices having a silicon carbide (SiC) substrate include those having a gate insulating film such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or IGBT (Insulated Gate Bipolar Transistor). . As the gate insulating film, a silicon dioxide (SiO ₂ ) film formed by a thermal oxidation method is often used. Many interface states exist at the interface between the SiO ₂ film formed by thermal oxidation and the SiC substrate. As a result, the channel mobility is extremely small compared to the electron mobility in the bulk. For this reason, the on-resistance value of the semiconductor device becomes higher than an ideal value. Therefore, it has been studied to use a deposition method, or to use a thermal oxidation method and a deposition method together, instead of forming the gate insulating film depending only on the thermal oxidation method.

Non-Patent Document 1 discloses a form in which an Al ₂ O ₃ film is formed on a SiC substrate at 190 ° C. or 230 ° C. by chemical vapor deposition. Furthermore, a mode in which a very thin thermal oxide film is inserted between the SiC substrate and the Al ₂ O ₃ film is disclosed.

  The gate insulating film formed by the deposition method as described above may require post-deposition annealing (PDA: Post Deposition Anneal) in order to reduce leakage current and improve relative dielectric constant. Even when the PDA process is not performed, the gate insulating film is often heated at a high temperature after the gate insulating film is formed. For example, a heating process performed to obtain an ohmic junction of a source electrode provided on a SiC substrate is typical. This step is performed at a high temperature of about 1000 ° C., for example.

  According to Patent Document 1, PDA treatment is performed at a high temperature of 400 ° C. or higher on an oxide film deposited at a low temperature of less than 400 ° C. At this time, the pressure in the oxygen atmosphere is set to 0.05 Pa or more and 5 Pa or less in order to prevent the MOS interface from deteriorating.

JP 2009-49099 A

S. Hino, et al., "High channel mobility 4H-SiC metal-oxide-semiconductor field-effect transistor with low temperature metal-organic chemical-vapor deposition grown Al2O3 gate insulator", Applied Physics Letters, Vol. 92, (2008 ), 183503

  Although it can be reduced to some extent by the technique of Patent Document 1, when the gate insulating film is heated at a high temperature after the deposition, the channel state density is increased due to an increase in interface state density. Therefore, a method for further suppressing this phenomenon is desired.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a silicon carbide semiconductor device capable of suppressing a decrease in channel mobility caused by a heat treatment after deposition of a gate insulating film. It is to provide a manufacturing method.

  The method for manufacturing a silicon carbide semiconductor device of the present invention includes the following steps. A gate insulating film is formed on the silicon carbide substrate. The step of forming the gate insulating film includes a step of depositing a first layer on the silicon carbide substrate at a first temperature by a chemical vapor deposition (CVD) method, and a second temperature higher than the first temperature. Annealing the first layer and depositing a second layer on the first layer after the step of annealing the first layer. After the gate insulating film is formed, the silicon carbide substrate is heated to a temperature higher than the second temperature.

  According to the present invention, it is possible to suppress a decrease in channel mobility due to the heat treatment after the gate insulating film is deposited.

1 is a cross sectional view schematically showing a configuration of a silicon carbide semiconductor device in one embodiment of the present invention. It is sectional drawing which shows schematically the 1st process of the manufacturing method of the silicon carbide semiconductor device in one embodiment of this invention. It is sectional drawing which shows schematically the 2nd process of the manufacturing method of the silicon carbide semiconductor device in one embodiment of this invention. FIG. 7 is a cross sectional view schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device in one embodiment of the present invention. FIG. 10 is a cross sectional view schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device in one embodiment of the present invention. FIG. 10 is a cross sectional view schematically showing a fifth step of the method for manufacturing the silicon carbide semiconductor device in one embodiment of the present invention. FIG. 11 is a cross sectional view schematically showing a sixth step of the method for manufacturing the silicon carbide semiconductor device in one embodiment of the present invention. It is sectional drawing which shows schematically the 7th process of the manufacturing method of the silicon carbide semiconductor device in one embodiment of this invention. It is sectional drawing which shows schematically the 8th process of the manufacturing method of the silicon carbide semiconductor device in one embodiment of this invention. It is sectional drawing which shows schematically the 9th process of the manufacturing method of the silicon carbide semiconductor device in one embodiment of this invention. It is a graph which shows the result of the experiment which investigated the relationship between the annealing temperature of a gate insulating film, and the channel mobility of a lateral MOSFET, (a) when a dimethylamide hydride is used for the precursor raw material of CVD method, and a precursor It is a figure of (b) when using triethylaluminum as a raw material. It is a graph which shows the result of the experiment which investigated the relationship between annealing temperature and the detection intensity | strength by the spectroscopy of OH ^- gas desorption from the layer formed by CVD method, and dimethylamide hydride was used for the precursor raw material. It is a figure of the case where it uses (a) and the case where triethylaluminum is used for a precursor raw material (b).

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. In crystallographic Miller index notation, a minus before the number is used instead of the bar on the number.

(Device structure)
Referring to FIG. 1, MOSFET 90 (silicon carbide semiconductor device) of the present embodiment is an n-channel and vertical power device. The breakdown voltage can be secured, for example, about several hundred V to 3 kV. MOSFET 90 has an epitaxial substrate 50 (silicon carbide substrate), a gate electrode 7, a source electrode 8 (main electrode), a drain electrode 9, and a gate insulating film 10. Epitaxial substrate 50 includes single crystal substrate 1, drift layer 2, base region 3, and source region 4.

  Single crystal substrate 1 is made of n-type (first conductivity type) silicon carbide. The plane orientation of the single crystal substrate 1 (upper plane orientation in the figure) is, for example, a (0001) plane, a (000-1) plane, or a (11-20) plane. The polytype of the crystal structure of silicon carbide is, for example, 4H, 6H, or 3C. A silicon carbide layer is formed epitaxially on one main surface (upper surface in the drawing) of single crystal substrate 1. The crystal structure of this silicon carbide layer is the same as that of single crystal substrate 1. This silicon carbide layer has a drift layer 2, a base region 3 and a source region 4.

Drift layer 2 is arranged on single crystal substrate 1. Drift layer 2 has n-type. The impurity concentration of drift layer 2 is preferably higher than the impurity concentration of single crystal substrate 1, and is, for example, about 1 × 10 ¹⁴ to 1 × 10 ¹⁸ cm ⁻³ . The thickness of the drift layer 2 is, for example, 5 to 200 μm.

The base region 3 is formed in a well shape on the drift layer 2. The depth of the base region 3 is required not to exceed the thickness of the drift layer 2 and is, for example, 0.5 to 3 μm. Base region 3 has p-type (second conductivity type). The p-type impurity concentration in the base region 3 is higher than the n-type impurity concentration in the drift layer 2 and is, for example, about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ .

Source region 4 is provided on base region 3 so as to be separated from drift layer 2. For this reason, the depth of the source region 4 is smaller than the depth of the base region 3. Source region 4 has n-type. The impurity concentration of the source region 4 is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ .

  Gate insulating film 10 includes a portion disposed on the base region so as to connect drift layer 2 and source region 4. The gate insulating film 10 has a silicon nitride layer 5 and first and second layers 6a and 6b. The silicon nitride layer 5, the first layer 6 a and the second layer 6 b are sequentially stacked on the epitaxial substrate 50. Silicon nitride layer 5 and gate insulating film 10 may be formed longer than gate electrode 7 in the gate length direction (lateral direction in FIG. 1). The silicon nitride layer 5 may be omitted. In this case, the first layer 6a and the second layer 6b are sequentially stacked on the epitaxial substrate 50 without the silicon nitride layer 5 interposed therebetween.

In the present embodiment, the first and second layers 6a and 6b are made of an oxide containing an aluminum element, and specifically made of alumina (Al ₂ O ₃ ). Therefore, each of the first and second layers 6a and 6b has the same main constituent elements, that is, Al and O. Thereby, compared with the case where both main elements differ, a manufacturing method can be simplified. The materials of the first and second layers 6a and 6b are not necessarily the same. Further, instead of Al ₂ O ₃ , SiO ₂ , SiON, HfO ₂ or AlON may be used.

  The gate electrode 7 is provided on the gate insulating film 10. The material of the gate electrode 7 is, for example, doped polycrystalline silicon (polysilicon), doped polycrystalline silicon carbide, a low-resistance refractory metal, or a nitride of a low-resistance refractory metal. The low resistance refractory metal is, for example, aluminum (Al), titanium (Ti), molybdenum (Mo), tantalum (Ta), niobium (Nb), or tungsten (W).

  The source electrode 8 is an ohmic electrode provided on one main surface (upper surface in the drawing) of the epitaxial substrate 50. The source electrode 8 is separated from the drift layer 2 and is in contact with the source region 4, preferably in contact with the base region 3. Drain electrode 9 is an ohmic electrode provided on the other main surface (lower surface in the drawing) of epitaxial substrate 50, in other words, the other main surface (lower surface in the drawing) of single crystal substrate 1. As a material of the source electrode 8 and the drain electrode 9, aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), or a composite thereof can be used.

(Device operation)
Next, the operation of the MOSFET 90 will be described. When a voltage exceeding the threshold value is applied to the gate electrode 7, an inversion channel layer is formed on the surface of the base region 3 immediately below the gate electrode 7. Thereby, a path through which charges flow is formed between the source region 4 and the drift layer 2. When the MOSFET is an n-channel type as in the present embodiment, majority carriers are electrons, and electrons flowing from the source region 4 to the drift layer 2 are generated by a voltage applied between the source electrode 8 and the drain electrode 9. According to the formed electric field, it reaches the drain electrode 9 through the drift layer 2 and the single crystal substrate 1. In other words, a current flows from the drain electrode 9 to the source electrode 8. The first and second conductivity types may be interchanged. In this case, the MOSFET is a p-channel type. In the case of the p-channel type, the majority carriers are holes, and the holes injected from the drain electrode 9 reach the surface of the drift layer 2 and then pass through the inversion channel layer formed on the surface of the base region 3. It flows into the source region 4.

(Device manufacturing method)
Next, a method for manufacturing MOSFET 90 will be described below.

  Referring to FIG. 2, drift layer 2 is formed on single crystal substrate 1 using an epitaxial crystal growth method. Thereby, the epitaxial substrate 50 is obtained.

  Referring to FIG. 3, a mask (not shown) is formed using a photoengraving technique so that a region where base region 3 is to be formed is exposed in the surface of drift layer 2. The mask material is, for example, a resist, silicon dioxide, or silicon nitride. Impurities are added on the drift layer 2 by ion implantation using this mask as an impurity implantation blocking film. Thereby, the base region 3 is formed. When MOSFET 90 (FIG. 1) is an n-channel, boron (B) or aluminum (Al) can be used as an impurity. In the case of a p-channel, phosphorus (P) or nitrogen (N) can be used. After the impurity implantation is completed, the mask is removed.

  Referring to FIG. 4, a mask (not shown) is formed using a photoengraving technique so that a region where source region 4 is to be formed is exposed in the surface of base region 3. The mask material is, for example, a resist, silicon dioxide, or silicon nitride. Impurities are added to the base region 3 by ion implantation using this mask as an impurity implantation blocking film. Thereby, the source region 4 is formed. When MOSFET 90 (FIG. 1) is an n-channel, phosphorus (P) or nitrogen (N) can be used as an impurity. In the case of a p-channel, boron (B) or aluminum (Al) can be used. After the impurity implantation is completed, the mask is removed. Note that the order of ion implantation in the base region 3 (FIG. 3) and ion implantation in the source region 4 (FIG. 4) may be interchanged.

  Next, heat treatment for activating the implanted impurities is performed. Specifically, the epitaxial substrate 50 is heated by a heat treatment apparatus at, for example, about 1300 to 1900 ° C. for about 30 seconds to 1 hour.

  Next, gate insulating film 10 (FIG. 7) is formed on epitaxial substrate 50 by the steps of FIGS. This method will be described in detail below.

  Referring to FIG. 5, silicon nitride layer 5 is formed on epitaxial substrate 50 by irradiating epitaxial substrate 50 with radical nitrogen under a reduced pressure atmosphere. By increasing the temperature to 500 ° C. during this treatment, the nitridation is promoted, so that the silicon nitride layer 5 having a sufficient thickness can be obtained.

  Referring to FIG. 6, first layer 6 a is deposited on epitaxial substrate 50 through silicon nitride layer 5. This deposition is performed by a CVD method. The CVD method has a good film thickness uniformity as compared with a physical growth method such as a sputtering method, and can process a large number of substrates at the same time.

  The temperature at which the first layer 6a is deposited (deposition temperature) T1 (first temperature) is, for example, about 200 ° C. The pressure of the atmosphere is reduced to about 0.1 to 1000 Pa, for example. When the first layer 6a is made of alumina as in the present embodiment, the raw material is supplied to the epitaxial substrate 50 by, for example, vapor phase supply of triethylaluminum and water. Thereby, a source gas containing a hydrogen element and an oxygen element is supplied onto the epitaxial substrate 50. The thickness at which the first layer 6a is formed is preferably about 15 nm or more, and is about 15 nm in the present embodiment.

Next, the first layer 6a is annealed at a temperature T2 (second temperature) higher than the temperature T1. The temperature T2 is about 600 ° C., for example. By this annealing, residual impurities are desorbed as a gas from the first layer 6a. In the present embodiment, OH ^- gas is desorbed. This annealing is preferably performed in an inert atmosphere such as nitrogen or argon, or in a high vacuum. The annealing time is preferably 1 minute or longer in order to sufficiently desorb the residual gas.

  Referring to FIG. 7, a second layer 6b is then deposited on the first layer 6a. The second layer 6b can be deposited by a CVD method similar to the deposition of the first layer 6a. The deposition temperature of the second layer 6b may be increased with respect to the deposition temperature of the first layer 6a. This is because, since the first layer 6a suppresses the oxidation of the epitaxial substrate 50 during the deposition of the second layer 6b, even if the deposition temperature of the second layer 6b is further increased, the epitaxial substrate 50 is adversely affected. This is because is small. By increasing the deposition temperature, the quality of the second layer 6b can be improved by reducing the residual impurities in the second layer 6b.

  The thickness of the second layer 6b is about 45 nm in the present embodiment. As a result, the sum of the thicknesses of the first and second layers 6a and 6b is 15 + 45 = 60 nm. Therefore, the thickness of the first layer 6a is set to a quarter or less of the sum of the thicknesses of the first and second layers 6a and 6b.

The main constituent elements of the second layer 6b are preferably the same as the main constituent elements (Al and O in the present embodiment) of the first layer 6a. When the main constituent elements of the first and second layers 6a and 6b are the same, the composition between the main constituent elements may be different or the same. In the present embodiment, the main constituent elements and the composition of the second layer 6b are the same as the main constituent elements and the composition of the first layer 6a. In other words, the material of the second layer 6b is Al ₂ O ₃ like the material of the first layer 6a.

  As described above, the gate insulating film 10 is formed by the steps of FIGS.

  Referring to FIG. 8, gate electrode 7 is deposited on gate insulating film 10. Referring to FIG. 9, gate electrode 7 is patterned using photolithography. This patterning is preferably performed so that the gate electrode 7 overlaps the source region 4 when viewed in plan in a range of 10 nm to 5 μm, for example. Thereby, the influence of the fringe effect at the end of the gate electrode 7 is suppressed. Therefore, since the voltage is uniformly applied to the surface of the base region 3, the inversion channel layer can be reliably formed on the surface of the base region 3. Next, unnecessary portions of the silicon nitride layer 5 and the gate insulating film 10 are removed by patterning using a photoengraving technique. Wet or dry etching can be used in this patterning. By this patterning, the surface of the source region 4 is exposed.

  Referring to FIG. 10, deposition and patterning of source electrode 8 are performed on source region 4 exposed as described above. Referring again to FIG. 1, drain electrode 9 is deposited on the other main surface (lower surface in FIG. 1) of epitaxial substrate 50.

  Next, the epitaxial substrate 50 is heated to a temperature T3 higher than the temperature T2 of the annealing (FIG. 6) of the first layer 6a described above. Thereby, ohmic contact between each of the source electrode 8 and the drain electrode 9 and the epitaxial substrate 50 is obtained. The annealing temperature for the purpose of obtaining ohmic contact is preferably 900 ° C. or higher, for example, about 1000 ° C.

  In the present embodiment, the step of heating the epitaxial substrate 50 to the temperature T3 higher than the temperature T2 is performed for the purpose of obtaining ohmic contact, but the heating at the temperature T3 is performed with the gate insulating film 10 formed. As long as it is performed later, it may be performed for other purposes. For example, it may be performed for the purpose of modifying the second layer 6b.

(Comparative example)
As described above, after the first layer 6a is deposited and before the second layer 6b is deposited (FIG. 6), the first layer 6a is annealed at the temperature T2. In the comparative example in which this annealing is not performed, after the deposition of the first and second layers 6a and 6b by the CVD method at the temperature T1, annealing at the temperature T3 for ohmic contact between the source electrode 8 and the drain electrode 9 is performed. Is done. Since the deposition of the first and second layers 6a and 6b by the CVD method is performed at a relatively low temperature T1, during the deposition, residual impurities in the film generated from the source gas, specifically, OH-gas is removed. Separation is inadequate. Therefore, a large amount of OH ^- gas is desorbed from the entire first and second layers 6a and 6b during the subsequent annealing at the high temperature T3. As a result, the surface of the epitaxial substrate 50 is greatly oxidized. Therefore, the channel mobility of MOSFET 90 is lowered.

(Function and effect)
In contrast, according to the present embodiment, after the first layer 6a is deposited and before the second layer 6b is deposited (FIG. 6), annealing is performed at a temperature T2 that satisfies T3>T2> T1. it is, impurities remaining from the first layer 6a, in particular OH ^- gas, desorption of promoted. At this time, the second layer 6b has not yet been deposited, and the temperature T2 is lower than the temperature T3. For these reasons, OH desorbs ^- amount of gas generated is reduced. Therefore, the oxidation of the epitaxial substrate 50 by the desorbed OH ^- gas can be suppressed. Then, in the annealing at the temperature T3 after the deposition of the second layer 6b, the diffusion of OH ^- gas from the second layer 6b onto the epitaxial substrate 50 is the first in which the gas is desorbed as described above. This is prevented by the layer 6a. For this reason, the oxidation of the epitaxial substrate 50 by the OH ^- gas from the second layer 6b is also suppressed. As described above, the oxidation of the epitaxial substrate 50 by the OH ^- gas from the first and second layers 6a and 6b is suppressed. Thereby, unlike the comparative example described above, it is possible to suppress a decrease in channel mobility due to the heat treatment at the temperature T3 after the gate insulating film 10 is deposited.

When the thickness of the first layer 6a is a more 15 nm, OH from annealing (Fig. 1) at the second layer 6b of the temperature T3 by the first layer 6a ^- acts to prevent diffusion of the gas is further enhanced Therefore, the oxidation of the epitaxial substrate 50 is further suppressed. Further, when the thickness of the first layer 6a is equal to or less than a quarter of the sum of the thicknesses of the first and second layers 6a and 6b, the thickness of the first layer 6a is not excessively large. It is possible to avoid excessive generation of OH ^- gas during annealing at the temperature T2 (FIG. 6). Thereby, the oxidation of the epitaxial substrate 50 is further suppressed.

  The first layer 6a is formed on the epitaxial substrate 50 via the silicon nitride layer 5. Since the epitaxial substrate 50 is protected by the silicon nitride layer 5 having a high barrier property against oxygen and water, oxidation of the epitaxial substrate 50 is further suppressed. As a result, a decrease in channel mobility can be further suppressed.

(Content of related experiments)
As described above, according to the present embodiment, in order to prevent deterioration of channel mobility due to high-temperature annealing, the method for desorbing residual impurities in the film generated from the source gas used in the CVD method is optimal. It becomes. Experiments conducted by the present inventors before reaching such an idea will be described below.

First, a p-type epitaxial growth layer having an aluminum concentration of about 1 × 10 ¹⁶ cm ⁻³ is formed on the (0001) plane of a silicon carbide substrate having a polytype 4H crystal structure, and a silicon nitride layer is formed on the surface by radical nitridation. did. The silicon nitride layer is known to be effective in suppressing unintended oxidation of silicon carbide and obtaining high channel mobility. An n-type source region and an n-type drain region were formed on the surface by ion implantation. Thereafter, an Al ₂ O ₃ gate insulating film of 60 nm was deposited at a deposition temperature of 190 ° C. by a CVD method using triethylaluminum (Al (C ₂ H ₅ ) ₃ ) and water (H ₂ O) as precursor materials.

  Thereafter, some samples (sample A) were annealed at a temperature of 900 ° C. in a nitrogen gas atmosphere. This annealing process simulates the heat treatment necessary to obtain an ohmic electrode. The remaining sample (Sample B) was not annealed. Thereafter, an aluminum film was deposited on the gate insulating film, and a portion other than the channel region was removed from the film to form a gate electrode. Thereafter, a part of the gate insulating film on the n-type source region and the n-type drain region was removed, and after depositing aluminum, unnecessary portions of aluminum were removed to form a source electrode and a drain electrode. A lateral MOSFET was manufactured as described above.

The channel mobility was measured from the electrical characteristics of the MOSFET. As a result, the channel mobility was as high as about 200 cm ² / Vs in sample B, but as low as 30 cm ² / Vs in sample A. That is, it was confirmed that the channel mobility deteriorates in the heat treatment at 900 ° C.

In order to investigate the cause, the following experiment was further conducted. A p-type epitaxial growth layer having an aluminum concentration of about 1 × 10 ¹⁶ cm ⁻³ is formed on the (0001) plane of a silicon carbide substrate having a polytype 4H crystal structure, and then dimethylamide hydride (H (CH ₃ ) ₂ Al ) Or a CVD method using triethylaluminum and water as precursor materials, an Al ₂ O ₃ gate insulating film was deposited to 60 nm at a deposition temperature of 190 ° C. In this experiment, a silicon nitride layer was not formed. Thereafter, some samples were annealed in a nitrogen gas atmosphere at a temperature of 400 ° C. or 600 ° C. Thereafter, a lateral MOSFET was formed by forming a gate electrode, a source electrode, and a drain electrode according to the method described above, and the channel mobility was measured.

  Each of the graphs of FIG. 11A and FIG. 11B shows the channel mobility when dimethylamide hydride and triethylaluminum are used as precursor raw materials. Note that the channel mobility when annealing is not performed after deposition is shown as an annealing temperature of 0 ° C. for the convenience of graph representation.

Regardless of which precursor material is used, the channel mobility is as high as about 300 cm ² / Vs unless annealing is performed after the gate insulating film is deposited. When annealing was performed, a decrease in channel mobility was observed. Specifically, when dimethylamide hydride and water were used as precursors, the channel mobility decreased to less than 1 cm ² / Vs in both cases where the annealing temperature was 400 ° C. and 600 ° C. On the other hand, the channel mobility when triethylaluminum and water are used as precursors is reduced to less than 1 cm ² / Vs when the annealing temperature is 600 ° C., but is approximately 80 cm ² / V when the annealing temperature is 400 ° C. Vs, and the amount of decrease was suppressed. Thus, it was shown that the ease of channel mobility degradation due to the heat treatment after the gate insulating film deposition depends on the type of precursor material.

In order to investigate this cause, the composition and amount of gas desorbed while being heated in a vacuum atmosphere after depositing Al ₂ O ₃ on a silicon carbide substrate under the same deposition conditions, temperature-programmed desorption gas spectroscopy It was investigated by. Each of the graphs of FIG. 12A and FIG. 12B shows the annealing temperature dependence of the detected signal intensity of OH ^- gas when dimethylamide hydride and triethylaluminum are used as precursor raw materials.

From both graphs, OH due to differences in the precursor source ^- state of desorption of gas was found to differ. Specifically, when dimethylamide hydride is used as a precursor raw material, OH ⁻ gas is desorbed at about 200 to 300 ° C., whereas when triethylaluminum is used, OH ⁻ gas is about 400 to 600 ° C. Was shown to be detached. Notably, OH ^- annealing temperature which the gas desorption corresponds with state of degradation of the channel mobility described above, OH ^- channel mobility degradation by annealing at a temperature such that the gas is desorbed It is that.

The present inventors have this result, OH in the deposited Al ₂ O ₃ anneal desorbed from this ^- the gas oxidizes the silicon carbide substrate was thought to be responsible for degrading the channel characteristics. This is described in the above-mentioned document: S. Hino, et al., "High channel mobility 4H-SiC metal-oxide-semiconductor field-effect transistor with low temperature metal-organic chemical-vapor deposition grown Al ₂ O ₃ gate insulator" , Applied Physics Letters, Vol. 92, (2008), 183503, it is consistent with the channel mobility becoming higher when the gate insulating film is deposited at a low temperature of 190 ° C where silicon carbide hardly oxidizes. . This also matches that the deterioration of channel mobility due to annealing is more gentle when a silicon nitride layer, which is considered to have a high barrier property against oxygen and water, is formed under the Al ₂ O ₃ layer.

Therefore, the present inventors cannot suppress the oxidation of the silicon carbide substrate by dividing the deposition of the Al ₂ O ₃ gate insulating film by the CVD method into two stages and adding a desorption annealing process therebetween. I thought. Specifically, after depositing the first layer by the CVD method, higher than its deposition temperature, and at a temperature lower than the high-temperature annealing temperature needed after the gate insulating film formation, OH from the first layer ^- gas It was considered preferable to obtain a gate insulating film having the first and second layers by performing desorption annealing treatment for desorption and then depositing the second layer. And this hypothesized that the following effects can be obtained.

By setting the desorption annealing temperature higher than the deposition temperature of the first layer, the vapor pressure of the OH ⁻ gas is increased, and the OH ⁻ gas that could not be desorbed during the deposition of the first layer is in the gas phase. To desorb. Since the second layer has not yet been formed at the time of desorption annealing, the amount of desorbed OH ⁻ gas is small, and its temperature is lower than that of high temperature annealing. For this reason, the oxidation of the silicon carbide substrate during desorption annealing is sufficiently small. A second layer is then deposited, followed by a high temperature anneal. At this time, the first layer that has been baked in advance by desorption annealing prevents the OH ^- gas generated from the second layer from diffusing into the silicon carbide substrate. For this reason, the quantity by which a silicon carbide substrate is finally oxidized can be reduced significantly.

In order to verify the above hypothesis, a lateral MOSFET was fabricated by the following method. A p-type epitaxial growth layer having an aluminum concentration of about 1 × 10 ¹⁶ cm ⁻³ was formed on the (0001) plane of a silicon carbide substrate having a polytype 4H crystal structure, and a silicon nitride layer was formed on the surface by radical nitridation. In the preparation of Sample C as a comparative example, a gate insulating film of 60 nm was deposited at a deposition temperature of 190 ° C. using triethylaluminum and water as precursor materials. On the other hand, in Sample D, a 15 nm gate insulating film is first deposited by the same deposition method, followed by desorption annealing at 600 ° C. for 3 minutes in a nitrogen atmosphere, and then 45 nm Al ₂ O ₃ is deposited by the same deposition method. Deposited. Thereby, the total film thickness of Al ₂ O ₃ was set to 60 nm. Each of Samples C and D was annealed at 900 ° C. for 3 minutes simulating high temperature annealing. Thereafter, a gate electrode, a source electrode, and a drain electrode were formed by the above-described method, thereby manufacturing a lateral MOSFET.

As a result of evaluating the channel characteristics of these MOSFETs, the channel mobility of Sample C was 30 cm ² / Vs, whereas the channel mobility of Sample D was 90 cm ² / Vs. That is, it was confirmed that the channel mobility of the sample D was remarkably higher than the channel mobility of the sample C of the comparative example.

(Appendix)
In the present invention, the embodiments can be appropriately modified and omitted within the scope of the invention. For example, the silicon carbide semiconductor device may be a MISFET (Metal Insulator Semiconductor Field Effect Transistor) other than the MOSFET. The silicon carbide semiconductor device is not limited to the MISFET, and may be another insulated gate transistor element such as an IGBT. The insulated gate transistor is not limited to a vertical type, and may be a horizontal semiconductor element in which a source, a gate, and a drain electrode are formed on the same main surface.

  1 single crystal substrate, 2 drift layer, 3 base region, 4 source region, 5 silicon nitride layer, 6a first layer, 6b second layer, 7 gate electrode, 8 source electrode, 9 drain electrode, 10 gate insulating film 90 MOSFET (silicon carbide semiconductor device).

Claims (9)

Forming a gate insulating film on the silicon carbide substrate, the step of forming the gate insulating film comprising depositing a first layer on the silicon carbide substrate at a first temperature by a chemical vapor deposition method; And depositing a second layer on the first layer after the step of annealing the first layer at a second temperature higher than the first temperature and the step of annealing the first layer And a step of heating the silicon carbide substrate to a temperature higher than the second temperature after the step of forming the gate insulating film.   2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein each of said first and second layers has the same main constituent element.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step of depositing the first layer includes a step of supplying a source gas containing a hydrogen element onto the silicon carbide substrate.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the first layer is made of an oxide containing an aluminum element.   The thickness of the said 1st layer is a manufacturing method of the silicon carbide semiconductor device of any one of Claims 1-4 which is 15 nm or more.   The thickness of the said 1st layer is manufacture of the silicon carbide semiconductor device of any one of Claims 1-5 which is 1/4 or less of the sum of the thickness of the said 1st and 2nd layer. Method.   The step of forming the gate insulating film includes the step of forming a silicon nitride layer on the silicon carbide substrate before the step of depositing the first layer, and the step of depositing the first layer includes the step of depositing the first layer, The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the method is performed by depositing the first layer on the silicon carbide substrate via a silicon nitride layer.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step of annealing the first layer includes a step of desorbing a gas from the first layer. Further comprising forming a main electrode on the silicon carbide substrate;
The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step of heating the silicon carbide substrate includes a step of obtaining ohmic contact between the silicon carbide substrate and the main electrode. .

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