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JP3929302B2 - Large circuit board - Google Patents

Large circuit board Download PDF

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Publication number
JP3929302B2
JP3929302B2 JP2001387365A JP2001387365A JP3929302B2 JP 3929302 B2 JP3929302 B2 JP 3929302B2 JP 2001387365 A JP2001387365 A JP 2001387365A JP 2001387365 A JP2001387365 A JP 2001387365A JP 3929302 B2 JP3929302 B2 JP 3929302B2
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JP
Japan
Prior art keywords
plating
common electrode
electrode line
circuit board
conductor pattern
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JP2001387365A
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Japanese (ja)
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JP2003188500A (en
Inventor
正浩 大田原
正義 菊地
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Citizen Watch Co Ltd
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Citizen Watch Co Ltd
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Description

【0001】
【発明の属する技術分野】
本発明は、複数の個別回路基板に対応する導体パターン領域を、一括して配列した大型回路基板に関するものである
【0002】
【従来の技術】
半導体パッケージ等の回路基板は、大型回路基板に複数の個別回路基板に対応する導体パターン領域を一括して配列形成し、最終的に個別回路基板の境界線に沿って切断して得られている。
個別の回路基板に切断分離する前に、導体パターンの外部接続用端子(パッド)等の所要部位にニッケルめっきおよび金めっき等の電気めっき被膜を形成することが多い。
【0003】
図7は従来の大型回路基板に、複数の個別回路基板に対応する導体パターン領域を、一括して配列形成した構造例を示す要部平面図であり、分離する前の4つの回路基板の一部分を示している。図7において、50は個別回路基板であり、該回路基板上に配設された導体パターン56は必要に応じてパッド電極51、スルーホール52に接続され、該スルーホール52は裏側の導体パターン(図示せず)と導通している。また、個別回路基板50の境界線沿って形成したメッキ用共通電極線53は、メッキ処理を必要とする導体パターンに接続しており、このメッキ用共通電極線53を用いて該導体パターンに電気メッキを行なうようにしている。電気メッキ終了後は、前記導体パターン56と前記メッキ用共通電極線53の接続をカットライン54、55に沿って切断し、大型回路基板から個別回路基板50を分離することにより、単個の回路基板を得ていた。
【0004】
しかしながら、上記の方法では、1本のメッキ用共通電極線53を切断分離するために、2回の切断工程が必要となるうえ、メッキ用共通電極線53が形成された部分は最後には除去するので、材料に無駄な部分が生じるという問題もあった。
【0005】
そこでこの問題を解決した回路基板構造が特開平11−340609号公報に記載されている。同公報の図1によれば、単位配線板32が複数個作り込まれ、配線パターン34の端子部等の所要露出部に電気めっきを施すため、配線パターン34を繋ぐめっき用リード36が形成されたプリント配線板30において、めっき用リード36は、隣接する単位配線板32間に、隣接する両単位配線板32の対応する所要配線パターン34間をつなげると共に、両単位配線板32を分離する切断線33に対して交叉するよう曲折して設けられている。
【0006】
上記構造によれば、切断線33に沿って1回切断すればすべての配線パターン34を分離できるので、従来の構造より切断工数が半分になり、また材料に無駄も生じないという効果が有る、しかしながら、次のような問題がある。同公報図1の1つの単位配線板32内において、配線パターン34同士の配線間隔が狭いと、切断線33で切断した後の単位配線板32に残存する、隣接する前記めっき用リード36の間隔が、前記切断線33の近傍でより小となり、両者がショートし易くなる。従ってこのような構造では、配線パターン34同士の配線間隔を広げる必要があり、配線密度を高くできないという課題があった。
【0007】
そこでさらにこの問題を解決した回路基板構造がWO01/78139号公報に記載されている。同公報の第4図には、2つの回路基板20Aが隣接して形成された大型回路基板の要部平面図が記載されている。2つの回路基板20Aには、それぞれ、導体パターンとしてのスルーホール11が形成されている。回路基板20Aの表面側では、回路基板20Aを個別に分割するためのカットラインXを跨いで対向するスルーホール11同士が1対1でメッキ用共通電極線22Aで接続されており、さらに回路基板20Aの裏面側では、対角関係にあるスルーホール11同士を、カットラインXを斜めに跨ぐようにメッキ用共通電極線22Bで接続している。つまりメッキ用共通電極線22A、22Bは平面的にカットラインXを蛇行しているが、回路基板20Aの表と裏に別々に形成しているので、両者が接触してショートするという問題は解消され、スルーホール11の間隔(配線パターン間の間隔と同じ)を狭くして配線密度を高めることができる。
【0008】
【発明が解決しようとする課題】
しかしながら、上記WO01/78139号公報に記載された回路基板構造でも次のような問題点があった。一般にスルーホール内への金属膜形成は、回路基板素地に対する無電解メッキを用いている。無電解メッキによる金属膜厚は、その処理時間によって異なるものの、非常に薄い膜なので、回路基板表面に予め銅箔を張り合せて形成した配線パターンよりはその抵抗値が高い。そのため、上記WO01/78139号公報に記載されたメッキ用共通電極線22A、22Bによって電気メッキを行なうと、電気メッキ用の電極端子に近い側の膜厚に対し、複数のスルーホール11を介して電気メッキされた部分の膜厚が非常に薄くなり、メッキ膜の厚みに大きなバラツキが生じていた。メッキ膜の厚みが違うと、配線抵抗が異なるので、電気回路としても大きな問題となっていた。
本発明は上記のような問題を解決し、大型回路基板から個別の回路基板を切断するときの工数が少なく、且つ電気メッキしたメッキ膜の厚みバラツキが少ない大型回路基板及び回路基板を提供することである。
【0009】
【課題を解決するための手段】
上記目的を達成するための本発明における大型回路基板は、複数の個別回路基板に対応する導体パターン領域を配列するとともに、該導体パターンに接続したメッキ用共通電極線を配設し、該導体パターンにメッキを施した後に切断して前記個別回路基板を得るための大型回路基板に於いて、該大型回路基板の面方向に離間した位置に第1及び第2の前記メッキ用共通電極線を設け、該第1のメッキ用共通電極線に対し該第2のメッキ用共通電極線と反対側にある前記導体パターンの少なくとも一部を、該第1のメッキ用共通電極線を経由することなく該第2のメッキ用共通電極線に接続し、該第2のメッキ用共通電極線に対し該第1のメッキ用共通電極線と反対側にある前記導体パターンの少なくとも一部を、該第2のメッキ用共通電極線を経由することなく該第1のメッキ用共通電極線に接続すると共に、前記第1及び第2のメッキ用共通電極線は互いに異なる基板面に設けたことを特徴とする
【0012】
請求項2に記載の大型回路基板は、請求項1に於いて、前記第1及び第2の前記メッキ用共通電極線の間に、該第1又は第2の前記メッキ用共通電極線に接続される導体パターンを有することを特徴とする。
【0013】
請求項3に記載の大型回路基板は、請求項1または請求項2に於いて、前記第1のメッキ用共通電極線に対し前記第2のメッキ用共通電極線と反対側にある前記導体パターンの少なくとも一部が該第1のメッキ用共通電極線に接続され、又は前記第2のメッキ用共通電極線に対し前記第1のメッキ用共通電極線と反対側にある前記導体パターンの少なくとも一部が該第2のメッキ用共通電極線に接続されることを特徴とする
【0014】
請求項4に記載の大型回路基板は、請求項1から請求項3において、前記第1のメッキ用共通電極線と前記第2のメッキ用共通電極線との間に切断線が設けられていることを特徴としている。
【0016】
【発明の実施の形態】
図1は本発明の一実施例を示す大型回路基板の表面側平面図、図2は大型回路基板の裏面側平面図、図3は個別回路基板の境界線部分裏面側を示す要部平面図であり、表面側のメッキ用共通電極線を破線で示している。図4は図3の一部を示す要部拡大平面図である。
図1、図2において、1は4つの個別回路基板2〜5に対応する導体パターン領域を配列した大型回路基板であり、個別回路基板2〜5はボールグリッドアレイ(以下BGAと略記する)の回路基板である。大型回路基板1の四辺に付した記号A、B、C、Dは、大型回路基板1及び個別回路基板2〜5の方向や部位の説明に使用するために付した、四辺を示す記号であり、図2、図3にも同様に付している。
【0017】
図1に示す如く、個別回路基板2〜5の中央部にはICチップ搭載エリア6が配設され、ICチップ搭載エリア6の周囲を取巻くように、リードパターン7が配設されている。8はリードパターン7と接続したスルーホールであり、図2に示した個別回路基板2〜5の裏面側に配設した配線パターン9と接続している。図2に於いて10は略格子状に配設した外部接続用のパッド電極であり、配線パターン9とそれぞれ接続されている。本実施例ではリードパターン7、スルーホール8、配線パターン9、パッド電極10が導体パターンを示している。
【0018】
図1に於いて11、12は電気メッキの時、各導体パターンへ電流を導くためのメッキ用共通電極線であり、一部は個別回路基板2〜5の完成領域内に配設されている。図1に示した表面側においてメッキ用共通電極線11は、個別回路基板2〜5のB辺に沿って配設され、各個別回路基板2〜5のB辺側に隣接する各個別回路基板のD辺側に配設したスルーホール8に接続している。
【0019】
また同様にメッキ用共通電極線12は、個別回路基板2〜5のA辺に沿って配設され、各個別回路基板2〜5のA辺側に隣接する各個別回路基板のC辺側に配設したスルーホール8に接続している。つまりメッキ用共通電極線11、12は、個別回路基板2〜5の表面側のC辺とD辺に沿って配設したスルーホール8とリードパターン7へメッキ電流を供給するとともに、裏面側のC辺とD辺に沿って配設したスルーホール8と接続した配線パターン9、パッド電極10へメッキ電流を供給するための電極線である。
【0020】
同様に図2において、13、14は電気メッキの時、各導体パターンへ電流を導くためのメッキ用共通電極線であり、一部は個別回路基板2〜5の完成領域内に配設されている。図2に示した裏面側においてメッキ用共通電極線13は、個別回路基板2〜5のD辺に沿って配設され、各個別回路基板2〜5のD辺側に隣接する各個別回路基板のB辺側に配設したスルーホール8に接続している。
【0021】
また同様にメッキ用共通電極線14は、個別回路基板2〜5のC辺に沿って配設され、各個別回路基板2〜5のC辺側に隣接する各個別回路基板のA辺側に配設したスルーホール8に接続している。つまりメッキ用共通電極線13、14は、個別回路基板2〜5の裏面側のA辺とB辺に沿って配設したスルーホール8と配線パターン9及びパッド電極10へメッキ電流を供給するとともに、表面側のA辺とB辺に沿って配設したスルーホール8と接続したリードパターン7へメッキ電流を供給するための電極線である。
【0022】
次に図3、図4に基づいて、メッキ用共通電極線11〜14の配置関係を説明する。各図において、メッキ用共通電極線11、12は破線で示してあり、メッキ用共通電極線13、14と裏面側の導体パターンは実線で示してある。この時、メッキ用共通電極線13、14を第1のメッキ用共通電極線とし、メッキ用共通電極線11、12を第2のメッキ用共通電極線と定義する。
【0023】
第1のメッキ用共通電極線13と第2のメッキ用共通電極線11の関係について説明すると、大型回路基板1の面方向に離間した位置に第1のメッキ用共通電極線13及び第2のメッキ用共通電極線11を設け、該第1メッキ用共通電極線13の、該第2のメッキ用共通電極線11と反対側にある前記導体パターン8bの少なくとも一部を、該第1のメッキ用共通電極線13を経由することなく該第2のメッキ用共通電極線11に接続し、該第2のメッキ用共通電極線11の、前記第1のメッキ用共通電極線13と反対側にある前記導体パターン8aの少なくとも一部を、該第2のメッキ用共通電極線11を経由することなく該第1のメッキ用共通電極線13に接続している。
【0024】
第1のメッキ用共通電極線14と第2のメッキ用共通電極線12の関係についても同様であり、上記の説明に於いて符号11を12に、符号13を14に、符号8aを8cに、符号8bを8dにそれぞれ読み替えれば良い。
【0025】
図3ではメッキ用共通電極線11〜14と各スルーホール8との接続がわかるように破線の配線と実線の配線をずらして記載したが、実際には図4の如く表面側と裏面側の配線を重ねることができるので、図4における縦方向の配線間隔を狭くした高密度配線が可能である。
【0026】
上記の如きメッキ用共通電極線11〜14を備えた大型回路基板1に電気メッキを施した後は、図に示した如くメッキ用共通電極線11と13の間、及びメッキ用共通電極線12と14の間をそれぞれ1回切断する(各図中では仮想切断線と記載した)だけで、導体パターンとメッキ用共通電極線11〜14との不要な接続は切断され、各導体パターンが所定の接続関係を保った状態で個別回路基板2〜5を得ることができる。
【0027】
上記実施例によれば、メッキ用共通電極線11〜14から各導体パターンまでの経路には高々1個のスルーホールしか挿入されないため、配線抵抗のバラツキを小さくでき、メッキ電流の差が小さくできるためメッキ厚にも差がなく、且つ個別回路基板2〜5を切断分離するときは、1回の切断で良いので、工数を削減することができる。
【0028】
図3に於いて、前記第1メッキ用共通電極線14の、前記第2のメッキ用共通電極線12と反対側にある複数の前記導体パターン8eは該第1メッキ用共通電極線14に接続されている。従って個別回路基板2〜5に切断した状態で該メッキ用共通電極線14には該個別回路基板2〜5上の複数の導体パターンが接続された状態で残存することになるが、このような構成は例えば電源配線等、2以上の導体パターンを結ぶ配線として利用する事が出来る。
【0029】
すなわち、第1のメッキ用共通電極線14に対し第2のメッキ用共通電極線12と反対側にある導体パターン8eの少なくとも一部を第2のメッキ用共通電極線12を経由することなく第1のメッキ用共通電極線14に接続し、又は第2のメッキ用共通電極線12に対し第1のメッキ用共通電極線14と反対側にある導体パターン8cの少なくとも一部を第1のメッキ用共通電極線14を経由することなく第2のメッキ用共通電極線12に接続する事が出来る。
【0030】
上記の実施例ではメッキ用共通電極線11〜14を導体パターンの一部として利用しているが、勿論本発明はそれに限定されるものではなく、有効な導体パターンとは非導通状態のまま孤立した状態でメッキ用共通電極線11〜14を個別回路基板2〜5に残存させても良い。
【0031】
この場合、無意味なメッキ用共通電極線11〜14が個別回路基板2〜5に残存することになるが、基板スペースとしては、例えば大型部品の搭載スペースや基板保持スペースとして有効利用する事が可能であり、結果的に大型回路基板1から取り得る個別回路基板2〜5の取り個数を増やす事が出来る。無論前記した配線密度の向上、切断工数の減少、均一なメッキ厚等の効果は変わらない。
【0032】
次に本発明の他の実施例を図5に基づいて説明する。図5は個別回路基板2〜5の境界線部分裏面側を示す要部平面図であり、表面側のメッキ用共通電極線11、12を破線で示している。前述の実施例と異なる部分は、導体パターンを構成する一部のスルーホール8fが、メッキ用共通電極線12、14の間に配設したことである。
【0033】
本実施例はパッド電極10の一つ10aを、スルーホール8fを介して個別回路基板2〜5の表面側に配設した導体パターンに導通させることにより、この個別回路基板2〜5を使ったBGAをマザーボード(図示せず)へ実装したとき、個別回路基板2〜5の表面側に配設した導体パターンによってマザーボード側の導体パターンとの電気接続を確認できるようにしている。つまり本実施例は、第1及び第2のメッキ用共通電極線の間に、第1又は第2のメッキ用共通電極線に接続される導体パターンを有しても良いことを示している。
【0034】
なお、上記実施例では個別回路基板2〜5の同一辺に沿って形成したメッキ用共通電極線を、個別回路基板の裏と表、即ち互いに異なる回路基板面に形成したが、本発明はこれに限定されるものではなく、両者を同一面側に配設しても良い。但しその場合はメッキ用共通電極線の両方を、メッキ用共通電極線を形成していない面側へスルーホールによって引回してから隣接した回路基板側へ導く必要がある。
【0035】
この構成は、前記のようにメッキ用共通電極線が占めるスペースを部品搭載スペースとして利用する場合に、該部品とメッキ用共通電極線との干渉をさける等の目的で好適に実施する事が出来る。前記した配線密度の向上効果は薄れるが、切断工数の減少、均一なメッキ厚等の効果は変わらない。
【0036】
図6は本発明の他の実施例であり、メッキを必要とする導体パターンが各個別回路基板2〜5の対向する辺の一方に偏って延設できる場合は、該導体パターンを該一方の辺に隣接する個別回路基板2〜5の領域に設けられたメッキ用共通電極線11、12に接続するだけで良く、従ってメッキ用共通電極線11、12は一辺あたり1本で良い事になる。
【0037】
また上記実施例では、回路基板の両面に導体パターンを形成したが、本発明はこれに限定されるものではなく、片面にのみ導体パターンを形成した場合も同様の構造を実施できるものであり、効果も同様に発揮するものである。
【0038】
なお、全ての図に於いて、前記メッキ用共通電極線は直線であって、かつ該直線と直交する切断線で切断されるように描いたが、本発明に於いて前記メッキ用共通電極線は曲線であっても良く、また切断箇所を限定するものでもない。
【0039】
【発明の効果】
以上のように本発明によれば、複数の個別基板に対応する導体パターン領域を配列し、メッキ用共通電極線を介して導体パターンにメッキを施した後に切断して個別回路基板を得るための大型回路基板に於いて、メッキ用共通電極線から各導体パターンまでの配線抵抗のバラツキを小さくでき、電気メッキによるメッキ厚のバラツキが小さくできる上、個別回路基板に分離する切断工数を削減することができる。またメッキ用共通電極線に接続する導体パターンの間隔を小さくする事が出来るので、高密度の基板実装が実現できる。
【0040】
また、残存したメッキ用共通電極線を導体パターンの一部として利用したり、残存したメッキ用共通電極線のスペースを有効に利用出来るので、結果として、大型回路基板から取り得る個別回路基板の取り個数も増やすことができる。
【図面の簡単な説明】
【図1】本発明の一実施例を示す大型回路基板の表面側平面図である。
【図2】図1に示した大型回路基板の裏面側平面図である。
【図3】個別回路基板の境界線部分裏面側を示す要部平面図である。
【図4】図3の一部を示す要部拡大平面図である。
【図5】本発明の他の実施例であり、個別回路基板の境界線部分裏面側を示す要部平面図である。
【図6】本発明の他の実施例を示す大型回路基板の表面側平面図である。
【図7】従来の大型回路基板構造を示す要部平面図である。
【符号の説明】
1 大型回路基板
2、3、4 5 個別回路基板
7 リードパターン
8 スルーホール
9 配線パターン
10 パッド電極
11、12、13、14 メッキ用共通電極線
[0001]
BACKGROUND OF THE INVENTION
The present invention, a conductor pattern areas corresponding to the plurality of individual circuit board, to a large circuit board arranged collectively.
[0002]
[Prior art]
Circuit boards such as semiconductor packages are obtained by collectively forming conductor pattern regions corresponding to a plurality of individual circuit boards on a large circuit board and finally cutting along the boundary lines of the individual circuit boards. .
Before cutting and separating into individual circuit boards, electroplating films such as nickel plating and gold plating are often formed on required portions such as external connection terminals (pads) of the conductor pattern.
[0003]
FIG. 7 is a plan view of an essential part showing a structural example in which conductor pattern regions corresponding to a plurality of individual circuit boards are collectively formed on a conventional large circuit board, and a part of four circuit boards before separation. Is shown. In FIG. 7, reference numeral 50 denotes an individual circuit board, and a conductor pattern 56 disposed on the circuit board is connected to a pad electrode 51 and a through hole 52 as necessary. (Not shown). In addition, the common electrode line 53 for plating formed along the boundary line of the individual circuit board 50 is connected to a conductor pattern that requires plating, and the common electrode line 53 for plating is used to electrically connect the conductor pattern. I am trying to do plating. After the electroplating is completed, the connection between the conductor pattern 56 and the common electrode line 53 for plating is cut along the cut lines 54 and 55, and the individual circuit board 50 is separated from the large circuit board. I got a substrate.
[0004]
However, in the above method, in order to cut and separate one plating common electrode line 53, two cutting steps are required, and the portion where the plating common electrode line 53 is formed is finally removed. As a result, there is a problem that a wasteful portion is generated in the material.
[0005]
Therefore, a circuit board structure that solves this problem is described in Japanese Patent Application Laid-Open No. 11-340609. According to FIG. 1 of the publication, a plurality of unit wiring boards 32 are formed, and plating leads 36 for connecting the wiring patterns 34 are formed in order to perform electroplating on required exposed portions such as terminal portions of the wiring patterns 34. In the printed wiring board 30, the plating lead 36 connects between the corresponding required wiring patterns 34 of the adjacent unit wiring boards 32 between the adjacent unit wiring boards 32 and cuts the unit wiring boards 32. It is bent and provided so as to cross the line 33.
[0006]
According to the above structure, since all the wiring patterns 34 can be separated by cutting once along the cutting line 33, the cutting man-hour is halved compared to the conventional structure, and there is an effect that the material is not wasted. However, there are the following problems. In the unit wiring board 32 of FIG. 1, if the wiring interval between the wiring patterns 34 is narrow, the interval between the adjacent plating leads 36 remaining on the unit wiring board 32 after being cut by the cutting line 33. However, it becomes smaller in the vicinity of the cutting line 33, and both are likely to be short-circuited. Therefore, in such a structure, it is necessary to widen the wiring interval between the wiring patterns 34, and there is a problem that the wiring density cannot be increased.
[0007]
Therefore, a circuit board structure which further solves this problem is described in WO01 / 78139. FIG. 4 of the same publication shows a plan view of the main part of a large circuit board in which two circuit boards 20A are formed adjacent to each other. The two circuit boards 20A are each formed with a through hole 11 as a conductor pattern. On the surface side of the circuit board 20A, the through holes 11 facing each other across the cut line X for individually dividing the circuit board 20A are connected one by one with the common electrode line 22A for plating, and further, the circuit board On the back side of 20A, the through holes 11 having a diagonal relationship are connected to each other by a common electrode line 22B for plating so as to cross the cut line X diagonally. In other words, the common electrode lines 22A and 22B for plating meander the cut line X in a plane, but they are separately formed on the front and back of the circuit board 20A, so that the problem of short-circuiting due to the contact between them is solved. In addition, it is possible to increase the wiring density by narrowing the interval between the through holes 11 (the same as the interval between the wiring patterns).
[0008]
[Problems to be solved by the invention]
However, the circuit board structure described in the above-mentioned WO01 / 78139 has the following problems. In general, the formation of a metal film in a through hole uses electroless plating on a circuit board substrate. Although the metal film thickness by electroless plating varies depending on the processing time, it is a very thin film and therefore has a higher resistance value than a wiring pattern formed by pasting a copper foil on the surface of a circuit board in advance. Therefore, when electroplating is performed using the common electrode wires for plating 22A and 22B described in the above-mentioned WO01 / 78139, the film thickness on the side near the electrode terminals for electroplating is passed through the plurality of through holes 11. The thickness of the electroplated portion was very thin, and the plating film had a large variation in thickness. When the thickness of the plating film is different, the wiring resistance is different, which is a big problem for an electric circuit.
The present invention solves the above-described problems, and provides a large circuit board and a circuit board with a small number of man-hours when cutting individual circuit boards from a large circuit board and with less variation in the thickness of electroplated plating films. It is.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a large circuit board according to the present invention includes a conductor pattern region corresponding to a plurality of individual circuit boards, and a common electrode line for plating connected to the conductor pattern. In the large circuit board for obtaining the individual circuit board by cutting after plating, the first and second common electrode lines for plating are provided at positions separated in the surface direction of the large circuit board. , wherein without respect first plating common electrode line at least a portion of the conductor pattern on the opposite side of the common electrode line for plating the second, through the common electrode line for plating the first connected to the second plating common electrode line, to the second plating common electrode line at least a portion of the conductor pattern on the opposite side of the common electrode line for plating the first, the second Common electrode wire for plating While connected to the first plating common electrode line without passing through the first and second plating common electrode line is characterized in that provided on the different substrates face each other.
[0012]
The large circuit board according to claim 2 is connected to the first or second plating common electrode line between the first and second plating common electrode lines according to claim 1. It is characterized by having a conductor pattern.
[0013]
The large circuit board according to claim 3 is the conductor pattern according to claim 1 or 2 , wherein the conductor pattern is on the opposite side to the second common electrode line for plating with respect to the first common electrode line for plating. Is connected to the first plating common electrode line, or at least one of the conductor patterns on the opposite side of the first plating common electrode line with respect to the second plating common electrode line. part is characterized in that it is connected to the common electrode line for plating the second.
[0014]
According to a fourth aspect of the present invention, in the large-sized circuit board according to the first to third aspects, a cutting line is provided between the first common electrode line for plating and the second common electrode line for plating . It is characterized by that.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
1 is a plan view of the front surface side of a large circuit board showing an embodiment of the present invention, FIG. 2 is a plan view of the back side of the large circuit board, and FIG. The common electrode line for plating on the surface side is indicated by a broken line. FIG. 4 is an enlarged plan view of a main part showing a part of FIG.
1 and 2, reference numeral 1 denotes a large circuit board in which conductor pattern regions corresponding to four individual circuit boards 2 to 5 are arranged, and each of the individual circuit boards 2 to 5 is a ball grid array (hereinafter abbreviated as BGA). It is a circuit board. Symbols A, B, C, and D attached to the four sides of the large circuit board 1 are symbols indicating the four sides that are attached to be used for explanation of directions and parts of the large circuit board 1 and the individual circuit boards 2 to 5. 2 and FIG. 3 are similarly applied.
[0017]
As shown in FIG. 1, an IC chip mounting area 6 is disposed at the center of the individual circuit boards 2 to 5, and a lead pattern 7 is disposed so as to surround the periphery of the IC chip mounting area 6. Reference numeral 8 denotes a through hole connected to the lead pattern 7, and is connected to the wiring pattern 9 disposed on the back side of the individual circuit boards 2 to 5 shown in FIG. In FIG. 2, reference numeral 10 denotes an external connection pad electrode arranged in a substantially lattice pattern, and is connected to the wiring pattern 9. In this embodiment, the lead pattern 7, the through hole 8, the wiring pattern 9, and the pad electrode 10 are conductor patterns.
[0018]
In FIG. 1, reference numerals 11 and 12 denote plating common electrode lines for guiding current to each conductor pattern during electroplating, and a part thereof is disposed in a completed region of the individual circuit boards 2 to 5. . In the surface side shown in FIG. 1, the common electrode line 11 for plating is disposed along the B side of the individual circuit boards 2 to 5 and is adjacent to the B side of the individual circuit boards 2 to 5. Are connected to a through hole 8 disposed on the D side.
[0019]
Similarly, the common electrode line 12 for plating is disposed along the A side of the individual circuit boards 2 to 5, and on the C side of each individual circuit board adjacent to the A side of each individual circuit board 2 to 5. It is connected to the disposed through hole 8. That is, the common electrode lines 11 and 12 for plating supply plating current to the through holes 8 and the lead patterns 7 arranged along the C side and D side on the front surface side of the individual circuit boards 2 to 5 and These are electrode lines for supplying a plating current to the wiring pattern 9 and the pad electrode 10 connected to the through holes 8 arranged along the C side and the D side.
[0020]
Similarly, in FIG. 2, reference numerals 13 and 14 denote common electrode lines for plating for guiding current to each conductor pattern at the time of electroplating, and a part thereof is disposed in a completed region of the individual circuit boards 2 to 5. Yes. 2, the common electrode line 13 for plating is disposed along the D side of the individual circuit boards 2 to 5 and is adjacent to the D side of the individual circuit boards 2 to 5. To the through hole 8 disposed on the B side.
[0021]
Similarly, the common electrode line 14 for plating is disposed along the C side of the individual circuit boards 2 to 5, and on the A side of each individual circuit board adjacent to the C side of each individual circuit board 2 to 5. It is connected to the disposed through hole 8. In other words, the plating common electrode lines 13 and 14 supply a plating current to the through hole 8, the wiring pattern 9, and the pad electrode 10 disposed along the A side and the B side on the back side of the individual circuit boards 2 to 5. These are electrode wires for supplying a plating current to the lead pattern 7 connected to the through holes 8 arranged along the A side and the B side on the surface side.
[0022]
Next, with reference to FIGS. 3 and 4, the arrangement relationship of the common electrode lines 11 to 14 for plating will be described. In each drawing, the common electrode lines 11 and 12 for plating are indicated by broken lines, and the common electrode lines 13 and 14 for plating and the conductor pattern on the back surface side are indicated by solid lines. At this time, the plating common electrode lines 13 and 14 are defined as the first plating common electrode lines, and the plating common electrode lines 11 and 12 are defined as the second plating common electrode lines.
[0023]
The relationship between the first plating common electrode line 13 and the second plating common electrode line 11 will be described. The first plating common electrode line 13 and the second plating common electrode line 13 are spaced apart from each other in the surface direction of the large circuit board 1. A common electrode line for plating 11 is provided, and at least a part of the conductor pattern 8b on the opposite side of the first common electrode line 11 for plating to the second common electrode line 11 for plating is used for the first plating. The second common electrode line 11 is connected to the second common electrode line 11 without going through the common electrode line 13, and the second common electrode line 11 is opposite to the first common electrode line 13 for plating. At least a part of the conductor pattern 8 a is connected to the first plating common electrode line 13 without passing through the second plating common electrode line 11.
[0024]
The same applies to the relationship between the first common electrode line 14 for plating and the second common electrode line 12 for plating. In the above explanation, reference numeral 11 is 12, reference numeral 13 is 14, reference numeral 8a is 8c. , 8b may be read as 8d.
[0025]
In FIG. 3, the broken line wiring and the solid line wiring are shifted so that the connection between the plating common electrode lines 11 to 14 and each through-hole 8 can be seen. However, in actuality, as shown in FIG. Since wirings can be overlapped, high-density wiring with a narrow vertical wiring interval in FIG. 4 is possible.
[0026]
After electroplating the large circuit board 1 having the plating common electrode lines 11 to 14 as described above, as shown in the figure, between the plating common electrode lines 11 and 13 and the plating common electrode line 12. And 14 are each cut once (denoted as virtual cutting lines in each figure), unnecessary connection between the conductor pattern and the common electrode lines 11 to 14 for plating is cut, and each conductor pattern is predetermined. The individual circuit boards 2 to 5 can be obtained in a state where the above connection relationship is maintained.
[0027]
According to the above embodiment, since only one through hole is inserted in the path from the common electrode lines for plating 11 to 14 to each conductor pattern, the variation in wiring resistance can be reduced and the difference in plating current can be reduced. For this reason, there is no difference in plating thickness, and when the individual circuit boards 2 to 5 are cut and separated, the number of steps can be reduced because one cutting is sufficient.
[0028]
In FIG. 3, the plurality of conductor patterns 8 e on the opposite side of the first plating common electrode line 14 from the second plating common electrode line 12 are connected to the first plating common electrode line 14. Has been. Therefore, a plurality of conductor patterns on the individual circuit boards 2 to 5 remain in the plating common electrode line 14 in a state of being cut into the individual circuit boards 2 to 5. The configuration can be used as a wiring connecting two or more conductor patterns, such as a power supply wiring.
[0029]
That is, the without passing through the first common electrode line 12 for the second plating at least a portion of the conductor pattern 8e with respect to plating the common electrode line 14 on the opposite side of the second plating common electrode line 12 connect to plating the common electrode line 14 of 1 or the first plating at least a portion of the second to plating the common electrode line 12 on the opposite side of the first plating the common electrode line 14 conductor pattern 8c It is possible to connect to the second plating common electrode line 12 without going through the common electrode line 14 .
[0030]
In the above embodiment, the common electrode lines 11 to 14 for plating are used as a part of the conductor pattern. However, the present invention is of course not limited thereto and is isolated from the effective conductor pattern while being in a non-conductive state. In this state, the common electrode lines 11 to 14 for plating may be left on the individual circuit boards 2 to 5.
[0031]
In this case, meaningless common electrode lines 11 to 14 for plating remain on the individual circuit boards 2 to 5, but the board space can be effectively used as a space for mounting large parts or a board holding space, for example. As a result, the number of individual circuit boards 2 to 5 that can be obtained from the large circuit board 1 can be increased. Of course, the effects of improving the wiring density, reducing the number of cutting steps, and uniform plating thickness are not changed.
[0032]
Next, another embodiment of the present invention will be described with reference to FIG. FIG. 5 is a main part plan view showing the boundary line partial back side of the individual circuit boards 2 to 5, and the common electrode lines 11 and 12 for plating on the front side are indicated by broken lines. A difference from the above-described embodiment is that a part of the through holes 8f constituting the conductor pattern are disposed between the common electrode lines 12 and 14 for plating.
[0033]
In this embodiment, one of the pad electrodes 10a is electrically connected to the conductor pattern disposed on the surface side of the individual circuit boards 2 to 5 through the through holes 8f, thereby using the individual circuit boards 2 to 5. When the BGA is mounted on a motherboard (not shown), the electrical connection with the motherboard-side conductor pattern can be confirmed by the conductor pattern disposed on the surface side of the individual circuit boards 2 to 5. That is, the present embodiment shows that a conductor pattern connected to the first or second plating common electrode line may be provided between the first and second plating common electrode lines.
[0034]
In the above embodiment, the common electrode wire for plating formed along the same side of the individual circuit boards 2 to 5 is formed on the back and front of the individual circuit board, that is, on different circuit board surfaces. It is not limited to this, and both may be disposed on the same surface side. In this case, however, both of the common electrode lines for plating need to be led by the through holes to the side where the common electrode line for plating is not formed, and then guided to the adjacent circuit board side.
[0035]
This configuration can be suitably implemented for the purpose of avoiding interference between the component and the common electrode line for plating when the space occupied by the common electrode line for plating is used as a component mounting space as described above. . Although the above-described effect of improving the wiring density is reduced, the effects of reducing the number of cutting steps and uniform plating thickness are not changed.
[0036]
FIG. 6 shows another embodiment of the present invention. When a conductor pattern that requires plating can be extended to one of the opposing sides of each individual circuit board 2 to 5, the conductor pattern is It is only necessary to connect to the common electrode lines 11 and 12 for plating provided in the areas of the individual circuit boards 2 to 5 adjacent to the side, and therefore, only one common electrode line 11 and 12 for plating is required per side. .
[0037]
In the above embodiment, the conductor pattern is formed on both sides of the circuit board, but the present invention is not limited to this, and the same structure can be implemented when the conductor pattern is formed only on one side, The effect is exhibited as well.
[0038]
In all the drawings, the common electrode line for plating is a straight line and is cut by a cutting line orthogonal to the straight line. However, in the present invention, the common electrode line for plating is drawn. May be a curved line, and does not limit the cutting location.
[0039]
【The invention's effect】
As described above, according to the present invention, conductor pattern regions corresponding to a plurality of individual substrates are arranged, and after plating the conductor pattern via the common electrode line for plating, the individual circuit substrate is obtained by cutting. In large circuit boards, variation in wiring resistance from the common electrode line for plating to each conductor pattern can be reduced, variation in plating thickness due to electroplating can be reduced, and the number of cutting steps to be separated into individual circuit boards can be reduced. Can do. In addition, since the interval between the conductor patterns connected to the common electrode line for plating can be reduced, high-density board mounting can be realized.
[0040]
Further, since the remaining common electrode wire for plating can be used as a part of the conductor pattern, or the space of the remaining common electrode wire for plating can be effectively used, as a result, it is possible to remove individual circuit boards that can be obtained from a large circuit board. The number can also be increased.
[Brief description of the drawings]
FIG. 1 is a plan view of a surface side of a large circuit board showing an embodiment of the present invention.
2 is a plan view of the rear surface side of the large circuit board shown in FIG. 1. FIG.
FIG. 3 is a plan view of a principal part showing a boundary line partial back side of an individual circuit board;
4 is an enlarged plan view of a main part showing a part of FIG. 3. FIG.
FIG. 5 is a plan view of the main part showing the back side of the boundary line portion of the individual circuit board according to another embodiment of the present invention.
FIG. 6 is a plan view of the surface side of a large circuit board showing another embodiment of the present invention.
FIG. 7 is a plan view of an essential part showing a conventional large circuit board structure.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Large circuit board 2, 3, 4 5 Individual circuit board 7 Lead pattern 8 Through hole 9 Wiring pattern 10 Pad electrode 11, 12, 13, 14 Common electrode line for plating

Claims (4)

複数の個別回路基板に対応する導体パターン領域を配列すると共に、該導体パターンに接続したメッキ用共通電極線を配設し、該導体パターンにメッキを施した後に切断して前記個別回路基板を得るための大型回路基板に於いて、該大型回路基板の面方向に離間した位置に第1及び第2の前記メッキ用共通電極線を設け、該第1のメッキ用共通電極線に対し該第2のメッキ用共通電極線と反対側にある前記導体パターンの少なくとも一部を、該第1のメッキ用共通電極線を経由することなく該第2のメッキ用共通電極線に接続し、該第2のメッキ用共通電極線に対し該第1のメッキ用共通電極線と反対側にある前記導体パターンの少なくとも一部を、該第2のメッキ用共通電極線を経由することなく該第1のメッキ用共通電極線に接続すると共に、前記第1及び第2のメッキ用共通電極線は互いに異なる基板面に設けたことを特徴とする大型回路基板。A conductor pattern region corresponding to a plurality of individual circuit boards is arranged, a common electrode line for plating connected to the conductor pattern is arranged, and the conductor pattern is plated and then cut to obtain the individual circuit board. large circuit in the substrate for the first and second of said plating common electrode line formed at a position spaced in the surface direction of the large-sized circuit board, the second to the first plating common electrode line Connecting at least a part of the conductive pattern on the opposite side of the common electrode line for plating to the second common electrode line for plating without passing through the first common electrode line for plating; plating to plating the common electrode line and the common electrode line for plating the first at least part of the conductor pattern on the opposite side, the first without passing through the common electrode line for plating the second connection to use the common electrode line Then The said first and second plating common electrode line is large circuit board, characterized in that provided on the different substrates face each other. 前記第1及び第2の前記メッキ用共通電極線の間に、該第1又は第2の前記メッキ用共通電極線に接続される導体パターンを有することを特徴とする請求項1に記載の大型回路基板。2. The large size according to claim 1 , wherein a conductor pattern connected to the first or second plating common electrode line is provided between the first and second plating common electrode lines. Circuit board. 前記第1のメッキ用共通電極線に対し前記第2のメッキ用共通電極線と反対側にある前記導体パターンの少なくとも一部が該第1のメッキ用共通電極線に接続され、又は前記第2のメッキ用共通電極線に対し前記第1のメッキ用共通電極線と反対側にある前記導体パターンの少なくとも一部が該第2のメッキ用共通電極線に接続されていることを特徴とする請求項1または請求項2に記載の大型回路基板。Wherein at least a portion of the conductor pattern on the opposite side to the first common electrode line for the second plating to the plating for the common electrode line is connected to the common electrode line for plating the first or the second billing at least part of the conductor pattern with respect to plating the common electrode line on the opposite side of the first plating for the common electrode line is characterized in that it is connected to the common electrode line for plating the second The large circuit board according to claim 1 or claim 2 . 前記第1のメッキ用共通電極線と前記第2のメッキ用共通電極線との間に切断線が設けられていることを特徴とする請求項1乃至請求項3のいずれか1項に記載の大型回路基板。According to any one of claims 1 to 3, characterized in that cutting lines are provided between the first said common electrode wire for plating in the second plating for the common electrode line Large circuit board.
JP2001387365A 2001-12-20 2001-12-20 Large circuit board Expired - Lifetime JP3929302B2 (en)

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