JP3948923B2 - DA conversion unit test apparatus, test method, and semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a test apparatus for a DA conversion unit, a test method, and a semiconductor integrated circuit device that can suitably perform this test. In particular, the operation is lower than the input / output response speed of the DA conversion unit. The present invention relates to a DA conversion unit test apparatus, a test method, and a semiconductor integrated circuit device that can be measured using a frequency measurement apparatus.
[0002]
[Prior art]
The DA converter is generally constituted by a semiconductor integrated circuit device (hereinafter referred to as LSI), and in recent years, the operating frequency has been increased. This is accompanied by the development of an application field for processing video such as a digital still camera or a digital VTR, or an application field for processing audio such as a digital audio or digital VTR. A high-speed DA converter is required to smoothly output digitally processed moving image data or audio data. In addition, the DA converter used for these applications DA-converts an input digital signal that has been subjected to digital signal processing, and thus has a close relationship with a so-called system LSI. It is often built in as.
[0003]
A test of the above-described DA conversion unit LSI or a system LSI incorporating the DA conversion unit is performed using a dedicated test apparatus called a so-called LSI tester. In particular, the system LSI includes a wide variety of digital signal processing functions in addition to the DA conversion function. The LSI tester for the system LSI converts an analog output signal into a digital signal by an AD converter unit and inputs digital signals. In addition to a test function for comparing with a signal, a function for testing a digital signal processing function is required. Of these, in the DA conversion function test, as with the LSI tester for the DA converter LSI, data is generated by switching the signal pattern of the input digital signal at high speed, and analog output is performed according to the frequency of the input digital signal. A high-speed and high-precision AD converter unit that detects a signal and reconverts it into a digital signal is required.
[0004]
Therefore, an LSI tester for a system LSI with a built-in DA conversion unit is a data that can generate an input digital signal with high-speed and high-precision operation timing in order to test a wide variety of digital signal processing functions. The LSI tester has an analog LSI tester function including an analog detection unit including a high-speed and high-precision AD converter unit simultaneously with a digital LSI tester function including a generation unit.
[0005]
In some cases, an analog detection unit including a high-speed and high-precision AD converter unit is provided separately from a high-speed and high-precision input digital signal data generation unit. In this case, a digital LSI tester specializing in a data generator that generates a digital signal pattern required for testing various digital signal processing functions, and a high-speed, high-precision AD required for testing the DA conversion function An analog LSI tester specialized for an analog detection unit having a converter unit is provided as a separate device.
[0006]
The LSI tester for testing the DA converter LSI is an analog tester specializing in an analog detector having a high-speed, high-precision AD converter required for testing the DA conversion function among the above-mentioned LSI testers for the system LSI. LSI tester.
[0007]
FIG. 6 shows a prior art test configuration 1000. The LSI tester 201 used for the test of the DA conversion unit 101 includes a digital LSI tester function unit 201D including a data generation unit 212 and a determination unit 216, and an analog LSI tester function including a high-speed and high-precision AD converter unit 211. Part 201A. The input digital signal IN output from the data generation unit 212 is input to the DA conversion unit 101 to be tested, and the analog output signal OUT subjected to DA conversion is input to the AD converter unit 211. Since the input analog output signal OUT is switched at high speed, the AD converter unit 214 provided in the digital LSI tester function unit 201D cannot follow. Therefore, the LSI tester 201 needs to include an analog LSI tester function unit 201A including a dedicated AD converter unit 211.
[0008]
The LSI tester 201 has a configuration in which a digital LSI tester function unit 201D and an analog LSI tester function unit 201A are integrated. That is, the analog output signal OUT obtained by DA conversion with respect to the output of the input digital signal IN from the digital LSI tester function unit 201D is input to the analog LSI tester function unit 201A and then provided to the digital LSI tester function unit 201D. It is compared with the expected value in the determination unit 216. On the other hand, if the analog LSI tester function unit 201A is configured to incorporate the data generation unit 212 and the determination unit 216, only the analog LSI tester function unit 201A tests the input / output response characteristics of the DA conversion unit 101. You can also In this case, the digital LSI tester function unit 201D tests various functions of digital signal processing in the system LSI.
[0009]
[Problems to be solved by the invention]
The LSI tester 201 having both functions of a digital LSI tester function and an analog LSI tester function, in addition to the conventional digital LSI tester function unit 201D that generates the input digital signal IN with high-speed and high-precision operation timing, It is necessary to integrate an analog LSI tester function unit 201A including a high-speed and high-precision AD converter unit 211 into one test system. However, in the advanced system LSI, both the digital signal processing function and the DA conversion function are advanced functions. Therefore, in testing, advanced test capabilities are required for the individual test functions of the digital LSI tester function and the analog LSI tester function. Furthermore, when both functions are integrated into one test system, it is also necessary to overcome performance degradation due to mutual interference such as a digital signal becoming a noise source for an analog signal. Therefore, an LSI tester integrated with digital and analog tester functions having sufficient performance is generally expensive, which may increase the test cost.
[0010]
Further, in order to solve the above problems, a configuration in which the digital LSI tester function and the analog LSI tester function are provided as separate devices has been shown. In this case, the digital signal processing function and the DA conversion function are performed twice. In this case, the test time must be divided and the test time is increased. As a result, the test cost may be increased, which is a problem.
[0011]
Also, analog LSI testers may require high-speed and high-precision AD converter units as the DA conversion function speeds up. To realize such AD converter units, analog LSI testers themselves This is a problem because it becomes expensive and may increase the test cost.
[0012]
The present invention has been made to solve the above-mentioned problems of the prior art, and in a test configuration based on a digital LSI tester, the digital signal processing function is tested. An object of the present invention is to provide a test apparatus, a test method, and a semiconductor integrated circuit device for a DA conversion section that can be tested without requiring an analog operation.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, a test apparatus for a DA converter according to claim 1 includes a digit signal generator that alternately and repeatedly switches two different digit signals to output to the DA converter, and two different digits. signal For each of Output from the DA converter Two different An averaging unit that averages analog output signals to obtain an analog average signal and a comparison unit that compares the analog average signal with an expected value are provided.
[0014]
According to a third aspect of the present invention, there is provided a method for testing a DA conversion unit comprising: a digit signal generating step of alternately switching two different digit signals to output to the DA conversion unit; and two different digit signals. For each of Output from the DA converter Two different The method includes an averaging step of averaging analog output signals to obtain an analog average signal, and a comparison step of comparing the analog average signal with an expected value.
[0015]
In the test apparatus for the DA converter of claim 1 or the test method for the DA converter of claim 3, two different digit signals are alternately switched and output to the DA converter. Two different digit signals For each of Output from the DA converter Two different The analog output signal is averaged and compared with the expected value.
[0016]
Thus, the input / output response characteristics of the DA converter with respect to high-speed digit signal switching can be tested without detecting the analog output signal of the DA converter at high speed and with high accuracy.
[0017]
When testing the built-in DA converter as a function of the system LSI, the simple analog test function of the digital LSI tester can be used as it is, and the test integrates the high-speed, high-precision analog LSI tester function. There is no need to have a system. Further, it is not necessary to separately provide an analog LSI tester. There is no need for an expensive LSI tester with highly integrated digital and analog functions, and there is no need to test the digital and analog functions with separate LSI testers, reducing test time and reducing test costs. Reduction can be achieved.
[0018]
Further, when testing an LSI as a DA converter, it is not necessary to provide a high-speed and high-precision analog output signal detection function, and thus the test cost can be similarly reduced.
[0019]
Further, the DA conversion unit test apparatus according to claim 2 is the DA conversion unit test apparatus according to claim 1, wherein two different digit signals are supplied to each of the output driver groups provided in the DA conversion unit. The combination is appropriately selected so that the output drivers are sequentially turned on and off.
[0020]
In the test apparatus for the DA conversion unit according to the second aspect, each output driver of the DA conversion unit is appropriately selected, and two digit signals that are alternately switched so as to sequentially perform the on / off operation are appropriately selected.
[0021]
As a result, a pair of two digit signals that are alternately and repeatedly switched is selected so that each output driver sequentially performs an on / off operation. Therefore, whether or not the on / off operation is normally performed at each digit signal switching cycle is determined for each driver. I can confirm.
[0022]
The averaging unit preferably includes a low-pass filter. As a result, the analog output signal from the DA converter to which two different digit signals are alternately input can be easily averaged. Therefore, if a low pass filter is added to an existing LSI tester, a test apparatus can be configured easily. Furthermore, the expected value is an expected digit signal, and the comparison unit may include an AD conversion unit that AD converts the analog average signal. As a result, since the analog average signal is AD-converted, the AD converter does not need to operate at high speed, and an AD converter provided in advance in an existing LSI tester or an AD converter having a general operation speed can be added. The test apparatus can be configured easily. Further, the comparison can be made with the digit signal, and the analog average signal and the expected value can be compared easily and reliably.
[0023]
The semiconductor integrated circuit device according to claim 4 includes a DA converter and a PLL unit, When testing the DA converter A low-pass filter used in the PLL section to average the analog output signal of the DA converter section use It is characterized by doing.
A semiconductor integrated circuit device according to a fifth aspect is the semiconductor integrated circuit device according to the fourth aspect, further comprising a connection changeover switch for switching the connection of the low-pass filter.
[0024]
According to another aspect of the semiconductor integrated circuit device of the present invention, the low-pass filter used in the PLL unit is used for averaging the analog output signal of the DA conversion unit when testing the input / output response characteristics of the DA conversion unit.
According to another aspect of the semiconductor integrated circuit device of the present invention, the connection destination of the low-pass filter is switched by the connection switch.
[0025]
As a result, the low-pass filter that is used for oscillation of the PLL unit in normal use can be connected to the analog output signal of the DA conversion unit when testing the input / output response characteristics of the DA conversion unit. can do. The LSI tester does not require a low-pass filter, so that it is possible to reduce the number of LSI tester components and the associated cost reduction.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, first and second embodiments embodying a test apparatus, a test method, and a semiconductor integrated circuit device according to the present invention will be described in detail with reference to the drawings based on FIGS.
FIG. 1 is a circuit block diagram showing a test configuration of the first embodiment. FIG. 2 is a signal waveform diagram showing normal input / output response characteristics of the DA converter. FIG. 3 is a signal waveform diagram showing input / output response characteristics when there is a failure in the output driver of the DA converter (in the case of an on-delay failure of the “64” driver). FIG. 4 is an explanatory diagram for explaining the fluctuation of the analog output signal due to the driver operation delay. FIG. 5 is a circuit block diagram showing a test configuration of the second embodiment.
[0027]
In the test configuration 10 of the first embodiment shown in FIG. 1, the LSI tester 2 includes a low-pass filter 4A instead of the analog LSI tester function unit 201A in the conventional LSI tester 201. Further, the analog output signal OUT DA-converted by the DA conversion unit 101 to be tested is provided in the digital LSI tester function unit 201D via the low-pass filter 4A instead of the AD converter unit 211 in the conventional LSI tester 201. Is input to the AD converter 214. Here, the AD converter unit 214 is an AD converter unit provided in advance in the digital LSI tester function unit 201D, and is not particularly provided for high-speed operation.
[0028]
The DA conversion unit 101 includes an input data latch unit 111 that receives an input digital signal IN as an input signal. The input digital signal IN received by the input data latch unit 111 is sent to each of the drivers 113 to 119 via the decoding unit 112. Is controlled to output an analog output signal OUT.
[0029]
The drivers 113 to 119 are configured with binary weighting. That is, “1” driver 113 that outputs “1” digital value, “2” driver 114 that outputs “2” digital value, “4” driver that outputs “4” digital value, and “8” digital value output The “8” driver 116, the “16” driver 117 for outputting the “16” digital value, and the “32” driver 118 for outputting the “32” digital value are provided for each of the lower input digital signals. A driver group is configured. Furthermore, for the upper input digital signal, the analog output signal OUT is controlled for each “64” digital value by providing a predetermined number of “64” drivers 119 that output “64” digital values. The bit width of the digital signal IN is determined. For example, if 15 sets of “64” drivers 119 are provided, 1023 bits can be DA-converted as the bit width.
[0030]
In the DA converter 101, an example is shown in which the output terminals of the drivers 113 to 119 are wired to output an analog output signal OUT. For example, a binary weighted current is obtained by wired connection. The case where it adds and outputs is considered.
[0031]
FIG. 2 shows signal waveforms of input / output response characteristics when the driver of the DA converter 101 operates normally in the first embodiment. FIG. 2 shows operation waveforms when the “63” digital signal and the “64” digital signal are alternately switched in synchronization with the clock signal CLK as the input digital signal IN and input to the DA converter 101. . The analog output signal OUT from the DA converter 101 is synchronized with the clock signal CLK and outputs a “63” digital value when a “63” digital signal is input, and a “64” digital value when a “64” digital signal is input. Is output.
[0032]
The output analog output signal OUT is input to the LSI tester 2, and the high frequency component is blocked by the low pass filter 4A. If the pass frequency band is set to be equal to or lower than the frequency band of the clock signal CLK, the analog output signal OUT is gradually leveled and output as a predetermined value to the analog average signal VOLP from the low-pass filter 4A. Since the digital value (“63” digital value and “64” digital value) that are alternately switched every cycle of the clock signal CLK is output to the analog output signal OUT, the analog average signal VOLP is “63”. An average value (63.5 digital value) of the digital value and the “64” digital value is output. If the AD converter 214 having a resolution twice that of the DA converter 101 is provided, 63.5 digital values are AD converted as expected values for the input of “63” / “64” digital signals. The value can be detected.
[0033]
For the “63” digital signal, the first “64” driver 119 is turned off, and the “1” to “32” drivers 113 to 118 are turned on. For the “64” digital signal, “1” to “32” “Drivers 113 to 118 are turned off, and first“ 64 ”driver 119 is turned on. For each period of the clock signal CLK, the “1” to “32” drivers 113 to 118 and the first “64” driver 119 all operate normally, so that the analog output signal OUT has a correct digital value (“63”). Digital value and “64” digital value) are alternately output, and a 63.5 digital value is output to the analog average signal VOLP as the average value. Therefore, from this test result, it can be confirmed that the high-speed switching operation by the clock signal CLK of the “1” to “32” drivers 113 to 118 and the first “64” driver 119 is normally performed.
[0034]
Next, FIG. 3 illustrates a case where the driver is not operating normally. FIG. 3 exemplifies a case where an operation delay occurs in the ON operation of the first “64” driver 119 and the normal activation does not occur at the frequency of the clock signal CLK. Note that the “1” to “32” drivers 113 to 118 and the first “64” driver 119, which are other drivers involved in the switching operation, are normally switched off. . When a “63” digital signal is input as the input digital signal IN, the “1” to “32” drivers 113 to 118 are turned on, the first “64” driver 119 is turned off, and the analog output signal OUT The “63” digital value is output at. When the input digital signal IN switches from the “63” digital signal to the “64” digital signal, the “1” to “32” drivers 113 to 118 quickly turn off, but the first “64” driver 119 turns on. Since there is an operation delay, the ON operation is not started, and the analog output signal OUT outputs a “0” digital value. In other words, all drivers do not drive the analog output signal OUT.
[0035]
The analog output signal OUT outputs “63” digital values and “0” digital values alternately, and the analog average signal VOLP averaged by the low-pass filter 4A is the 31.5 digital value that is the average value thereof. Is output. Since this is different from the expected 63.5 digital value, the determination unit 216 detects a mismatch and detects a failure in switching the driver operation of the DA conversion unit 101.
[0036]
It is to be noted that, together with the input digital signal IN, the faulty driver can be identified by the output value of the analog average signal VOLP at this time, and further, the contents of the fault can be grasped. The driver that performs the switching operation can be specified by the input digital signal IN. Further, when there is a failure in the on / off operation delay, the output of the faulty driver is fixed to off / on in the switching operation by the clock signal CLK, and the output value of the analog output signal OUT is changed according to the failure mode. This is because it is determined.
[0037]
The reason why the fault driver and the fault mode can be identified is shown in more detail in FIG. In FIG. 4, as described above, it is assumed that the failure of the on / off operation delay indicates the fixed / off state of the driver output (see the failure mode in FIG. 4A). This is a reasonable assumption when the on / off operation delay time is longer than the operation cycle of the high-speed clock signal CLK. FIG. 4B shows the analog average signal VOLP from the low-pass filter depending on the presence / absence / type of the failure mode when the “m” driver and the “n” driver are alternately turned on / off based on the above assumption. The output value is shown.
[0038]
In FIG. 4A, “off-fixed in on-delay” means that the driver output is fixed off, and a “0” digital value is output as the analog output signal OUT. On the other hand, “on-fixed in off-delay” means that the driver output is fixed on, and “m” / “n” digital values are output as analog output signals OUT in the “m” / “n” driver, respectively. To do. Further, when the driver is operating normally without any trouble, each digital value (“m” / “n” digital value) is output at a duty of 50%. When the output value of the analog average signal VOLP from the low-pass filter is calculated based on the above conditions, FIG. 4B is obtained.
[0039]
In FIG. 4B, when the “m” / “n” input digital signal is alternately switched and each driver is operating normally, the analog average signal VOLP is “(m + n) / 2” digital value. This indicates that an output value different from the normal value is output when a failure occurs in at least one of the drivers. The output value of the analog average signal VOLP is the average value of the analog output signals of the “m” / “n” drivers. Therefore, if both drivers are on-delay faults and both drivers are fixed off, the analog average signal outputs a “0” digital value. If both drivers are off-delay faults and both drivers are fixed on, an “m + n” digital value is output. If the “m” driver is an on-delay fault and the “n” driver is an off-delay fault, the “n” driver continues to be turned on and outputs an “n” digital value. ”Output digital values. If either driver is normal and the other has an on / off delay fault, in addition to the “m / 2” or “n / 2” digital value from the normal driver (“m” or “n”) Thus, the “0” / “n” or “m” digital value from the driver (“n” or “m”) of the on / off delay fault is added and output. That is, in the combination of a normal “m” driver and an “n” driver with an on / off delay fault, an “m / 2” / “m / 2 + n” digital value is output as an output value. In addition, in the combination of an “m” driver with an on / off delay fault and a normal “n” driver, a digital value “n / 2” / “m + n / 2” is output.
[0040]
According to the test configuration 10 of the first embodiment, the input / output response of the DA converter 101 to the high-speed switching of the input digital signal IN without detecting the analog output signal OUT of the DA converter 101 at high speed and with high accuracy. Properties can be tested.
[0041]
When the DA converter 101 is built in as a function of the system LSI, the AD converter 214, which is a simple analog test function of the digital LSI tester 201D, can be used as it is. There is no need to integrate high-precision analog LSI tester functions. Further, it is not necessary to separately provide an analog LSI tester. An expensive LSI tester in which digital functions and analog functions are highly integrated is not required, and it is not necessary to test the digital functions and analog functions with separate testers, so that the test time can be shortened. Therefore, the test cost can be reduced.
[0042]
Further, when the DA conversion unit 101 configures an LSI as a DA conversion device, the low-pass filter 4A provided as an analog output signal detection function and the AD converter unit 214 do not need to have high speed and high accuracy. Similarly, the test cost can be reduced.
[0043]
Further, the pair of two input digital signals IN that are alternately and repeatedly switched is selected so that the output drivers 113 to 119 in the DA converter 101 sequentially turn on and off, so that the input digital signal IN of each driver 113 to 119 is selected. It can be confirmed whether or not the on / off operation is normally performed in the switching cycle (clock signal CLK).
[0044]
In addition, the averaging unit includes a low-pass filter 4A, and the analog output signal OUT from the DA conversion unit 101 to which two different input digital signals IN are alternately input can be easily averaged. Therefore, if the low pass filter 4A is added to the existing digital LSI tester function unit 201D, the LSI tester 2 can be configured easily. Furthermore, the expected value determined by the determination unit 216 as a comparison unit is an expected digital value, and an AD conversion unit that AD converts the analog average signal VOLP may be provided. Since the analog average signal VOLP is AD-converted, the AD converter 214, which is an AD converter, does not require a high-speed operation, and the AD converter 214 provided in the existing digital LSI tester function unit 201D or a general operation If the speed AD converter unit 214 is added, the LSI tester 2 can be configured easily. Further, the analog average signal VOLP can be compared with a digital value, and the average value and the expected value can be compared easily and reliably.
[0045]
In the test configuration 20 of the second embodiment shown in FIG. 5, the system LSI (1) in which the DA conversion unit 101 is incorporated as a function includes the PLL unit 3, and the LSI tester of the first embodiment. 2, the low-pass filter 4B used in the PLL unit 3 is also shared for averaging the analog output signal OUT from the DA conversion unit 101. The system LSI (1) is provided with a connection changeover switch 5 for switching the connection of the low-pass filter 4B. Further, since the low-pass filter 4B is originally used for the PLL unit 3, it is not necessary to be provided in the LSI tester. Therefore, the digital LSI tester function unit 201D is used as it is as the LSI tester. Can do.
[0046]
The connection changeover switch 5 is connected to a low-pass filter 4B that is normally connected to the PLL unit 3 by a control unit (not shown) when the input / output response characteristic of the DA conversion unit 101 is tested. Connect to.
[0047]
Since other configurations and operations are the same as those of the test configuration 10 of the first embodiment, a description thereof is omitted here.
[0048]
According to the test configuration 20 of the second embodiment, in addition to the same effects as the test configuration 10 of the first embodiment, the low-pass filter 4B used for oscillation of the PLL unit 3 in a normal use state. Can be connected to the analog output signal OUT of the DA converter 101 when the input / output response characteristic of the DA converter 101 is tested, and the low-pass filter 4B can be shared. A low-pass filter is not required for the LSI tester 201D, and it is possible to reduce the number of components for the LSI tester 201D and to reduce the costs associated therewith.
[0049]
The present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention.
For example, in the present embodiment, the DA conversion unit 101 has been described with respect to the case where the analog output signal OUT is output by adding the output currents from the respective drivers 113 to 119 that are binary-weighted by wired connection. The present invention is not limited to this, and it goes without saying that the present invention can be applied to a general DA conversion unit such as a resistance voltage division by a ladder resistor, a DA conversion unit using an output voltage based on an accumulated charge of a capacitive element, or the like.
In addition, the analog average signal VOLP obtained by averaging the analog output signal OUT has been converted into an expected value by the determination unit 216 after AD conversion by the AD converter unit 214, but is not limited thereto. It is also possible to compare the analog average signal VOLP in an analog value state.
[0050]
(Supplementary Note 1) A digit signal generation unit that alternately and repeatedly switches two different digit signals to output to the DA conversion unit;
An averaging unit that averages each analog output signal output from the DA conversion unit according to the two different digit signals to obtain an analog average signal;
A DA conversion unit testing apparatus, comprising: a comparison unit that compares the analog average signal with an expected value.
(Appendix 2) The two different digit signals are:
The test apparatus for a DA converter according to appendix 1, wherein the combination is appropriately selected so that the output drivers of the output driver group provided in the DA converter are sequentially turned on and off.
(Supplementary Note 3) The averaging unit is
The DA converter test apparatus according to appendix 1, further comprising a low-pass filter.
(Supplementary Note 4) The expected value is an expected digit signal,
The comparison unit includes:
The test apparatus for a DA converter according to appendix 1, further comprising an AD converter that performs AD conversion on the analog average signal.
(Supplementary Note 5) Digit signal generation step of alternately switching two different digit signals and outputting them to the DA converter;
An averaging step of averaging each analog output signal output from the DA converter in accordance with the two different digit signals to obtain an analog average signal;
And a comparison step of comparing the analog average signal with an expected value.
(Appendix 6) The two different digit signals are:
6. The test method for a DA converter according to appendix 5, wherein the combination is appropriately selected so that the output drivers of the output driver group provided in the DA converter are sequentially turned on and off.
(Supplementary note 7) DA conversion unit,
A PLL section,
2. A semiconductor integrated circuit device according to claim 1, wherein a low-pass filter used in the PLL unit is shared to average the analog output signal of the DA conversion unit.
(Appendix 8) Provided with a connection switch
The semiconductor integrated circuit device according to appendix 7, wherein connection switching of the low-pass filter is performed.
[0051]
【The invention's effect】
According to the present invention, a digital signal processing function test is performed with a test configuration based on a digital LSI tester, and a high-speed DA conversion function can be tested without requiring a high-speed analog operation. It is possible to provide a test apparatus, a test method, and a semiconductor integrated circuit device for the DA converter.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram showing a test configuration of a first embodiment.
FIG. 2 is a signal waveform diagram showing normal input / output response characteristics of the DA converter.
FIG. 3 is a signal waveform diagram showing input / output response characteristics when there is a fault in the output driver of the DA converter (in the case of an “64” driver on-delay fault).
FIG. 4 is an explanatory diagram for explaining a change in an analog output signal caused by a driver operation delay.
FIG. 5 is a circuit block diagram showing a test configuration of a second embodiment.
FIG. 6 is a circuit block diagram showing a test configuration of a conventional technique.
[Explanation of symbols]
1 System LSI
10, 20, 1000 test configuration
101 DA converter
111 Input data latch
112 Decoding unit
113 to 119 drivers
2, 201 LSI tester
201A Analog LSI tester function
201D digital LSI tester function
211, 214 AD converter section
212 Data generator
216 judgment part
4A, 4B low-pass filter
IN input digital signal
OUT Analog output signal
VOLP analog average signal

Claims (5)

A digit signal generator that alternately and repeatedly switches two different digit signals to output to the DA converter;
An averaging unit that averages two different analog output signals output from the DA converter for each of the two different digit signals to obtain an analog average signal;
A DA conversion unit testing apparatus, comprising: a comparison unit that compares the analog average signal with an expected value. The two different digit signals are:
The DA converter testing apparatus according to claim 1, wherein the combination is appropriately selected so that the output drivers of the output driver group provided in the DA converter are sequentially turned on and off. A digit signal generating step of alternately switching between two different digit signals and outputting them to the DA converter;
An averaging step of averaging two different analog output signals output from the DA converter for each of the two different digit signals to obtain an analog average signal;
And a comparison step of comparing the analog average signal with an expected value. A DA converter,
A PLL section,
During the test of the DA conversion unit, a semiconductor integrated circuit device characterized by a low-pass filter used for the PLL unit, used to average the analog output signal of the DA converter portion. It has a connection switch,
5. The semiconductor integrated circuit device according to claim 4, wherein connection switching of the low-pass filter is performed.

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