JP2004289286A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which a test for the conversion operations of an analog / digital converter is easily performed with a small number of output pins while suppressing increase in noise. <P>SOLUTION: The semiconductor integrated circuit is composed of: the analog / digital converter 11 for converting an analog signal into a conversion value of a digital signal synchronously with a clock; an expected value generating circuit 12 that is operated by a signal synchronous with the clock and generates an expected value of the digital signal in accordance with the analog signal; an error detection circuit 13 that compares the conversion value converted by the analog / digital converter 11 with the expected value generated from the expected value generating circuit 12 to detect a conversion error in the conversion operation of the analog / digital converter 11; and error storage circuits 14, 15 for storing a result of detection of the conversion error detected by the error detection circuit 13. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit incorporating an analog / digital converter, and more particularly to a test circuit for evaluating an analog / digital converter in a system LSI incorporating an analog / digital converter.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a semiconductor integrated circuit (hereinafter, referred to as an LSI) incorporating an analog / digital converter (hereinafter, referred to as an AD converter), conversion of an analog signal into a digital signal by the AD converter is performed as expected. A characteristic evaluation test has been performed to determine whether or not there is.
[0003]
FIG. 5A is a diagram showing a configuration when a characteristic evaluation test is performed on an LSI equipped with a conventional AD converter.
[0004]
An evaluation test of an AD converter in an LSI equipped with a conventional AD converter is performed as follows. First, the analog signal AN is input from the tester 101 to the AD converter 103 in the LSI 102. FIG. 5B shows the analog signal AN and the clock CLK input to the AD converter 103.
[0005]
The analog signal AN is converted into a digital signal by the AD converter 103, output from the output unit 104 in the AD converter 103 to the signal processing block 105, and output to the tester 101 via the input / output pad 106. Here, the case where 6-bit data is output from the output unit 104 of the AD converter has been described.
[0006]
The tester 101 fetches a digital signal as a result of conversion by the AD converter 103 from the input / output pad 106 as needed for each conversion operation, compares the digital signal with an expected value corresponding to an analog signal output by the tester 101, and compares the digital signal with an expected value. The determination of OK / NG of the conversion result is performed, or the determination of the conversion accuracy and the determination of OK / NG are performed using the signal processing and arithmetic functions of the tester 101.
[0007]
[Problems to be solved by the invention]
However, in the characteristic evaluation test of the AD converter using the above-described configuration, when an AD converter with high resolution is mounted, the number of output pins required to output the conversion result to the tester increases, and these output pins The noise resulting from the switching of the power supply increases. As a result, there is a possibility that correct evaluation of the AD converter cannot be performed.
[0008]
Furthermore, the specification of the A / D converter that has been required in recent years is a high resolution and high speed conversion. This leads to an increase in the number of digital output pins and an increase in noise due to high speed switching. The environment has become more severe for measuring the characteristics of vessels. Further, the demand for an LSI on which a plurality of such AD converters are mounted is increasing, and in this case, the increase in the number of pins and noise is a more serious problem.
[0009]
Also, for example, even for an LSI with a system configuration that originally uses the digital output of the AD converter without extracting it to the outside, it is necessary to extract the digital output to the outside during the characteristic evaluation test. There is a possibility that the LSI cannot be correctly evaluated.
[0010]
Therefore, the present invention has been made in view of the above problems, and has a test circuit capable of easily performing a test of a conversion operation of an analog / digital converter with a small number of output pins and suppressing an increase in noise. To provide a semiconductor integrated circuit.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor integrated circuit according to one embodiment of the present invention includes an analog / digital converter that converts an analog signal into a converted value of a digital signal in synchronization with a clock signal, and a signal synchronized with the clock. An expected value generating circuit that generates an expected value of a digital signal corresponding to the analog signal, the converted value converted by the analog / digital converter, and the expected value generated by the expected value generating circuit And an error detection circuit for detecting a conversion error in the conversion operation of the analog / digital converter, and an error holding circuit for holding a detection result of the conversion error detected by the error detection circuit. It is characterized by.
[0012]
A semiconductor integrated circuit according to another embodiment of the present invention includes an analog / digital converter that converts an analog signal into a converted value of a digital signal in synchronization with a clock signal, and operates with a signal synchronized with the clock. An expected value generation circuit that generates an expected value of a digital signal corresponding to an analog signal, the converted value converted by the analog / digital converter, and the expected value generated by the expected value generation circuit, An error detection circuit that detects the presence or absence of a mismatch between the converted value and the expected value; an error information holding circuit that holds information indicating the presence or absence of the mismatch detected by the error detection circuit; and the error detection circuit. And an error amount holding circuit that counts information indicating that there is a mismatch detected by the method.
[0013]
A semiconductor integrated circuit according to another embodiment of the present invention includes a digital / analog converter for converting a first digital signal into an analog signal, and a conversion of the second digital signal in synchronization with the clock signal. An analog / digital converter for converting the value into a value, a digital code generation circuit controlled by a first signal synchronized with the clock signal, and outputting the first digital signal to the digital / analog converter, and the clock signal An expected value generation circuit that operates with a second signal synchronized with the analog signal and generates an expected value of a third digital signal corresponding to the analog signal input to the analog / digital converter; Comparing the converted value and the expected value generated by the expected value generation circuit, and comparing the converted value with the expected value. An error detection circuit that detects the presence / absence of a mismatch; an error information holding circuit that holds information indicating the presence / absence of the mismatch detected by the error detection circuit; and an indication that the mismatch detected by the error detection circuit exists An error amount holding circuit for counting information.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.
[0015]
[First Embodiment]
First, a semiconductor integrated circuit according to a first embodiment of the present invention will be described.
[0016]
FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit on which the AD converter according to the first embodiment and its test circuit are mounted.
[0017]
As shown in FIG. 1, the semiconductor integrated circuit includes an AD converter 11, an expected value generation circuit 12, an error detection circuit 13, an error information holding circuit 14, and an error amount holding circuit 15.
[0018]
FIG. 2 shows the analog signal AN, the sampling clock CLK, and the frequency-divided clock CLKA generated from the sampling clock CLK input to the AD converter 11. The analog signal AN is generated so as to change in synchronization with the sampling clock CLK, and is input from the tester to the AD converter 11. The AD converter 11 converts the input analog signal AN into a digital signal in synchronization with a sampling clock. Here, the analog signal AN is converted into a 6-bit digital signal (converted value) and output to the error detection circuit 13 from the output terminals DO0, DO1, DO2,..., DO5.
[0019]
The expected value generation circuit 12 outputs an expected value of a digital signal to be output from the AD converter 11 according to the analog signal AN input to the AD converter 11. The expected value generation circuit 12 has a frequency dividing circuit 12A and a counter 12B. The clock CLK supplied to the AD converter 11 is input to the frequency dividing circuit 12A. An output section of the frequency dividing circuit 12A is connected to the counter 12B. The frequency dividing circuit 12A frequency-divides the clock CLK input to the AD converter 11, generates a frequency-divided clock CLKA, and outputs it to the counter 12B. . The counter 12B counts using the divided clock CLKA, and generates a 6-bit expected value RD.
[0020]
The error detection circuit 13 compares the converted value of the AD converter 11 with the expected value of the expected value generation circuit 12 to detect the presence or absence of a mismatch. The error detection circuit 13 has exclusive OR circuits ER0, ER1, ER2,..., ER5, and an OR circuit OR0. Output terminals DO0 to DO5 of the AD converter 11 are connected to first input terminals of the exclusive OR circuits ER0 to ER5, respectively. The output terminals of the counter 12B are connected to the second input terminals of the exclusive OR circuits ER0 to ER5. Further, the output terminals of the exclusive OR circuits ER0 to ER5 are connected to the input terminals of the OR circuit OR0, respectively.
[0021]
The error information holding circuit 14 has a latch circuit, and stores a detection result output from the error detection circuit 13, that is, information indicating the presence or absence of a mismatch. Further, the error amount holding circuit 15 has a counting circuit, and counts and holds the number of consecutive times when the information indicating the presence / absence of mismatch indicates that there is a continuous mismatch. The output terminal of the OR circuit OR0 in the error detection circuit 13 is connected to a latch circuit in the error information holding circuit 14 and a count circuit in the error amount holding circuit 15, respectively.
[0022]
In the test circuit mounted on the above-described semiconductor integrated circuit, the analog signal is swept from 0 V to the maximum voltage, and then the data of the error information holding circuit 14 and the error amount holding circuit 15 are read, thereby obtaining an error in a series of conversion operations. And the amount of error can be evaluated.
[0023]
Next, the operation of the semiconductor integrated circuit shown in FIG. 1 will be described with reference to a timing chart shown in FIG.
[0024]
The analog signal shown in FIG. 2 is output from the tester and input to the AD converter 11. This analog signal sequentially changes from zero in steps of “[1 / power of 2]” of the voltage corresponding to 1 LSB (least significant bit) of the AD converter 11 in synchronization with the sampling clock CLK. The AD converter 11 converts the analog signal into a 6-bit data digital signal (converted value) and outputs the digital signal.
[0025]
At this time, in the expected value generation circuit 12, the frequency of the sampling clock CLK supplied to the AD converter 11 by the frequency dividing circuit 12A is divided by the above [power of 2], and the frequency divided clock CLKA is generated. Then, the counter 12B is operated in synchronization with the divided clock CLKA. Thus, when the voltage of the analog signal input from the tester changes by 1 LSB, the output of the counter 12B is also counted up by one. As a result, the output of the expected value generation circuit 12 becomes a digital signal (expected value) obtained by ideally converting the analog signal.
[0026]
The error detection circuit 13 compares the converted value output from the AD converter 11 with the expected value output from the expected value generation circuit 12 bit by bit, and evaluates whether there is a mismatch between the two values. Thereby, a test of the conversion operation in the AD converter 11 becomes possible.
[0027]
The operations of the above-described AD converter, expected value generation circuit, and error detection circuit will be described below in more detail.
[0028]
For example, 6-bit data as a conversion value output from the AD converter 11 is output to each first input terminal of the exclusive OR circuits ER0 to ER5. On the other hand, 6-bit data output from the expected value generation circuit 12 is input to the second input terminals of the exclusive OR circuits ER0 to ER5. The exclusive OR circuits ER0 to ER5 perform logical operations on the input data, and output “0” when the two data match, and output “1” when they do not match.
[0029]
Outputs from the six exclusive OR circuits ER0 to ER5 are input to an OR circuit OR0. The OR circuit OR0 outputs “0” as the error signal ERR when the input data is all “0”, that is, when the converted value matches the expected value. On the other hand, when there is at least one "1" in the input data, that is, when the conversion value does not match the expected value and there is a conversion error, "1" is output as the error signal ERR.
[0030]
FIG. 3 shows specific examples of the expected value output from the expected value generation circuit 12, the converted value output from the AD converter 11, and the error signal ERR output from the error detection circuit 13.
[0031]
As in the case of the conversion value (1) shown in FIG. 3, when the expected value is “2” and the conversion value output from the AD converter 11 becomes “1”, the error detection circuit 13 outputs the conversion value bit by bit. Are not detected in the comparison result of. As a result, the error signal ERR output from the error detection circuit 13 becomes “1”.
[0032]
Further, as in the case of the conversion value (2) shown in FIG. 3, when the expected value is “2”, the state in which the conversion value output from the AD converter 11 is “1” continues, that is, a conversion error occurs. In such a case, the error signal ERR output from the error detection circuit 13 becomes "1" continuously. The data portion corresponding to the conversion error is indicated by ED in FIG.
[0033]
The signal ERR output from the error detection circuit 13 is latched and held by the error information holding circuit 14. Then, based on the signal held in the error information holding circuit 14, it is determined whether or not a conversion error has occurred during the conversion operation by the AD converter 11. Further, the signal ERR output from the error detection circuit 13 is input to an error amount holding circuit 15 including a count circuit. The error amount holding circuit 15 holds the maximum value of the number of consecutive “1” s of the signal ERR by the count circuit. Thus, by reading the count value held in the count circuit after the end of the conversion test, the maximum error amount during a series of conversion operations can be evaluated.
[0034]
The data held in the error information holding circuit 14 and the error amount holding circuit 15 does not need to be read for each sampling clock CLK of the AD converter 11, and a test of a series of conversion operations from the lowest voltage to the highest voltage of an analog signal is performed. What is necessary is just to read after completion | finish. Therefore, it is possible to test the conversion operation of the AD converter 11 without requiring a digital output from the LSI to the tester during the conversion operation. Thereby, the influence of the switching noise of the digital output on the evaluation can be suppressed. Furthermore, if the error information held in the error information holding circuit 14 and the error amount holding circuit 15 is configured to be read out serially, only one output terminal is required, so that the number of output pins can be reduced. .
[0035]
In the first embodiment, a digital output expected value generation circuit 12, an error detection circuit 13, an error information holding circuit 14, and an error amount holding circuit 15 are constituted by the simple logic circuits shown in FIG. By providing a test circuit on an LSI, even in an LSI equipped with a high-resolution and high-speed analog / digital converter, the number of output test pins can be reduced without requiring digital output to the outside of the LSI. .
[0036]
Further, during a series of conversion operations from 0 V to a full-scale voltage, error results and error amount information are stored, and after the conversion operation, these error results and error amount information are read out to convert analog signals to digital signals. The quality of the conversion operation can be determined. This eliminates the need for a digital signal output during evaluation, and enables testing of the analog / digital converter without being affected by noise.
[0037]
In addition, a tester that can output a step pulse voltage from the outside can easily perform a test without requiring a special tester, program, digital signal processing, or the like. This facilitates a test for confirming the conversion characteristics of an LSI equipped with an analog / digital converter.
[0038]
[Second embodiment]
Next, a semiconductor integrated circuit according to a second embodiment of the present invention will be described. In the second embodiment, when evaluating an AD converter in a semiconductor integrated circuit in which an analog / digital converter (AD converter) and a digital / analog converter (hereinafter, referred to as a DA converter) are simultaneously mounted. The test is performed using the analog output of the DA converter that is not used for the analog input as the analog input of the AD converter. For this reason, a switch circuit is provided for connecting or disconnecting the output section of the DA converter from which the analog signal is output during the test and the input section of the AD converter to which the analog signal is input.
[0039]
FIG. 4 is a circuit diagram illustrating a configuration of a semiconductor integrated circuit equipped with an AD converter, a test circuit thereof, and a DA converter according to the second embodiment.
[0040]
As shown in FIG. 4, the semiconductor integrated circuit has a configuration of the first embodiment including an AD converter 11, an expected value generation circuit 12, an error detection circuit 13, an error information holding circuit 14, and an error amount holding circuit 15. In addition, a DA converter 16, a switch circuit 17, a frequency divider circuit 18, a digital code generation circuit 19, and a switch circuit 20 are provided.
[0041]
The DA converter 16 is connected to the AD converter 11 via the switch circuit 17. The sampling clock CLK is input to the frequency dividing circuit 18, and the frequency dividing circuit 18 is connected to the digital code generating circuit 19. Further, the digital code generation circuit 19 is connected to the DA converter 16 via the switch circuit 20.
[0042]
The switch circuit 17 connects or disconnects the DA converter 16 and the AD converter 11 in accordance with a signal EAT for permitting the test at the time of testing the conversion operation of the AD converter 11. The frequency divider 18 generates a code control clock CLKC by dividing the frequency of the clock CLK, and outputs the code control clock CLKC to the digital code generator 19. The digital code generation circuit 19 switches the digital signal DI input to the DA converter 16 in synchronization with the code control clock CLKC. The switch circuit 20 connects or disconnects the digital code generation circuit 19 and the DA converter 16 according to the signal EAT that permits the test.
[0043]
In the above configuration, in order to change the potential of the analog signal AN of the DA converter 16, it is necessary to switch the digital signal DI input to the DA converter 16. For this reason, in order to control the potential change of the analog signal AN output from the DA converter 16 at a predetermined timing, the sampling clock CLK of the AD converter 11 is synchronized with the frequency-divided code control clock CLKC, and the digital code is controlled. The digital signal DI input to the DA converter 16 is switched by the generation circuit 19. Thus, the digital signal DI input to the DA converter 16 changes in synchronization with the code control clock CLKC obtained by dividing the sampling clock CLK, similarly to the output of the expected value generation circuit 12 shown in FIG. Further, the digital signal DI is received, and the analog signal AN output from the DA converter 16 changes in synchronization with the signal obtained by dividing the sampling clock CLK.
[0044]
As described above, when viewed from the input of the analog signal AN to the AD converter 11, in the first embodiment, the same state as when the step-like pulse (analog signal AN) is applied from the tester is set. Will be. Other configurations and operations are the same as those of the first embodiment.
[0045]
Here, in order to be able to adjust the output change of the digital code generation circuit 19 for the DA converter 16 and the output change of the expected value generation circuit 12 for the AD converter 11, the digital code generation circuit 19 or A signal for operating the expected value generation circuit 12 is obtained as a signal set at a different frequency division ratio with respect to the sampling clock CLK of the AD converter 11. By doing so, even if the resolution of the A / D converter and the resolution of the D / A converter that are simultaneously mounted on the LSI are different, it is possible to test the conversion operation of the A / D converter using the analog output of the D / A converter.
[0046]
In the second embodiment having the above-described configuration, a test of a conversion operation in an AD converter similar to that of the first embodiment can be performed in an LSI equipped with an AD converter and a DA converter. Further, since the analog signal output from the DA converter is used as an analog signal to be input to the AD converter, the input operation of the analog signal from a measuring device such as a tester is not required, and the conversion operation in the AD converter is performed. Can be tested on an LSI.
[0047]
In addition, each of the above-described embodiments can be implemented not only independently, but also in appropriate combinations. Furthermore, each of the embodiments described above includes various stages of the invention, and various stages of the invention can be extracted by appropriately combining a plurality of constituent elements disclosed in each embodiment. is there.
[0048]
【The invention's effect】
As described above, according to the present invention, a semiconductor integrated circuit including a test circuit capable of easily performing a conversion operation test of an analog / digital converter with a small number of output pins and suppressing an increase in noise. It is possible to provide.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit on which an AD converter according to a first embodiment of the present invention and a test circuit thereof are mounted.
FIG. 2 is a diagram showing an analog signal AN, a sampling clock CLK, and a divided clock CLKA used in the first embodiment.
FIG. 3 is a diagram illustrating an operation of the semiconductor integrated circuit according to the first embodiment.
FIG. 4 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.
FIG. 5A is a diagram illustrating a configuration when a characteristic evaluation test is performed on a semiconductor integrated circuit on which a conventional AD converter is mounted, and FIG. 5B is a diagram illustrating an analog signal input to the AD converter; FIG. 3 is a diagram illustrating an AN and a clock CLK.
[Explanation of symbols]
11 AD converter, 12 expected value generation circuit, 13 error detection circuit, 14 error information holding circuit, 15 error amount holding circuit, 16 DA converter, 17 switch circuit, 18 frequency divider circuit, 19: Digital code generation circuit, 20: Switch circuit.

Claims (11)

An analog / digital converter for converting an analog signal into a converted value of a digital signal in synchronization with a clock signal;
An expected value generation circuit that operates on a signal synchronized with the clock and generates an expected value of a digital signal according to the analog signal;
An error detection circuit that compares the conversion value converted by the analog / digital converter with the expected value generated by the expected value generation circuit and detects a conversion error in a conversion operation of the analog / digital converter; ,
An error holding circuit for holding a detection result of the conversion error detected by the error detection circuit;
A semiconductor integrated circuit comprising: The conversion value and the expected value are each composed of a plurality of bits, and the error detection circuit detects the conversion error by comparing the conversion value and the expected value for each of the bits of the plurality of bits. Comprises an error information holding circuit for holding information indicating the presence or absence of the conversion error, and an error amount holding circuit for counting information indicating the presence of the conversion error over the plurality of bits. Item 2. The semiconductor integrated circuit according to item 1. The error amount holding circuit counts information indicating that there is the conversion error, and thereby calculates the conversion value converted by the analog / digital converter and the expected value generated by the expected value generation circuit. 3. The semiconductor integrated circuit according to claim 2, wherein a maximum error amount occurring therebetween is held. 4. The semiconductor integrated circuit according to claim 1, wherein the expected value generation circuit includes a frequency divider that divides the clock signal to generate the signal synchronized with the clock. 5. circuit. An analog / digital converter for converting an analog signal into a converted value of a digital signal in synchronization with a clock signal;
An expected value generation circuit that operates on a signal synchronized with the clock and generates an expected value of a digital signal according to the analog signal;
Error detection that compares the converted value converted by the analog / digital converter with the expected value generated by the expected value generation circuit and detects whether there is a mismatch between the converted value and the expected value. Circuit and
An error information holding circuit that holds information indicating the presence or absence of the mismatch detected by the error detection circuit;
An error amount holding circuit that counts information indicating that there is the mismatch detected by the error detection circuit;
A semiconductor integrated circuit comprising: A digital / analog converter for converting the first digital signal into an analog signal;
An analog / digital converter that converts the analog signal into a converted value of a second digital signal in synchronization with a clock signal;
A digital code generation circuit that is controlled by a first signal synchronized with the clock signal and outputs the first digital signal to the digital / analog converter;
An expectation value generation circuit that operates with a second signal synchronized with the clock signal and generates an expectation value of a third digital signal according to the analog signal input to the analog / digital converter;
Error detection that compares the converted value converted by the analog / digital converter with the expected value generated by the expected value generation circuit and detects whether there is a mismatch between the converted value and the expected value. Circuit and
An error information holding circuit that holds information indicating the presence or absence of the mismatch detected by the error detection circuit;
An error amount holding circuit that counts information indicating that there is the mismatch detected by the error detection circuit;
A semiconductor integrated circuit comprising: The conversion value and the expected value are both composed of a plurality of bits, and the error detection circuit compares the converted value and the expected value for each of the plurality of bits to detect a mismatch. 7. The semiconductor integrated circuit according to claim 5, wherein The error amount holding circuit counts information indicating that there is a mismatch, thereby obtaining a difference between the converted value converted by the analog / digital converter and the expected value generated by the expected value generating circuit. 8. The semiconductor integrated circuit according to claim 7, wherein a maximum error amount generated in said circuit is held. 9. The semiconductor integrated circuit according to claim 1, wherein the expected value generation circuit includes a frequency divider that divides the clock signal to generate the signal synchronized with the clock. circuit. 7. The semiconductor integrated circuit according to claim 6, further comprising a frequency divider that divides the clock signal to generate the first signal. The digital / analog converter is provided between the digital / analog converter and the analog / digital converter, and performs a test between the digital / analog converter and the analog / digital converter when testing the conversion operation of the analog / digital converter. A first switch circuit for setting a connection state;
A connection state provided between the digital code generation circuit and the digital / analog converter when the conversion operation of the analog / digital converter is tested; A second switch circuit;
The semiconductor integrated circuit according to claim 6, further comprising:

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