JP3943165B2 - Placement of chip stack and capacitor mounting - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize effective fixing and connection of a decoupling capacitor while suppressing the effect of propagation delay and a transmission line by providing a planar spacer bonded through a bonding pad on a first die and secured through an adhesive layer, and a second die to be secured to the planar spacer. SOLUTION: A part of a semiconductor package 14 includes a die fixing face 16 and a bonding pad 18. A chip 20 includes a wire bonding pad 26. Electrical connection is made between the chip 20 and the package 14 through the wire bonding pad 26 and a thin wire 28 having a wire bond connection at the package bonding pad 18. A spacer 30 is then bonded to a surface 24 through a nonconductive adhesive layer 36 and a chip 40 is bonded to the surface 34 of the spacer 30 through an adhesive layer 38. Electrical connection between the chip 40 and the package 14 is made through the thin wire 28 wire bonded to a die bond pad 46 through the package bonding pad 18.

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to integrated circuit (IC) assemblies, and more particularly to stacking arrangements for semiconductor dies or chips.
[0002]
[Prior art]
Semiconductor technology has shown a dramatic trend toward higher speeds and higher density of integrated circuits with overall reduction in device size. Generally, an integrated circuit chip is assembled in an integrated circuit package that provides an electrical connection from an external system to the integrated circuit. Without the concomitant improvement in IC packaging, many of the advantages of high device speed would be lost due to wiring propagation delays and transmission line effects on integrated circuit packages and circuit board assemblies.
[0003]
Many IC applications require decoupling capacitors. An example of such an application is that some IC devices need to be insensitive to impacts by ionizing radiation. The fundamental effect of ionizing radiation is the generation of electron-hole pairs in the semiconductor material. In the case of an IC having a supply voltage and a ground voltage, the effect of irradiation is that a large current occurs between the supply voltage and the ground voltage in the chip. Another effect is that the current from the power supply encounters inductance in the connecting leads from the power supply. As a result, the on-chip voltage is essentially reduced. The solution is to place a capacitor across the IC power supply as close as possible to the IC so that it is charged to the chip power supply voltage.
[0004]
[Problems to be solved by the invention]
Therefore, the propagation delay is small, the influence of the transmission line is small, decoupling capacitors can be mounted and connected effectively, and more ICs per unit volume of space by increasing the chip packaging density There is a need to provide a packaging arrangement that can implement the functionality.
[0005]
[Means for Solving the Problems]
According to a first aspect of the present invention, a first die fixed to a die attachment surface, a wire bond extending from a bonding pad on the first die to an external bonding pad, at least a portion of the first die A planar spacer in a space bonded by a bonding pad on the die and fixed by an adhesive layer; a second die fixed to the spacer having a thickness away from the wire bond connected to the first die; These and other needs are addressed by providing a chip stack arrangement that includes wire bonds extending from the pads on the second die to the external bonding pads.
[0006]
In the second aspect, the spacer is integral with the second die.
[0007]
In a third aspect, the spacer has an outer layer and a central layer, both of which have electrically connected surfaces. The second die is fixed by a conductive bonding material. A wire bond connects the conductive surface of the outer layer to a reference voltage.
[0008]
In the fourth aspect, the conductive spacer is used for mounting and connecting the capacitor. Capacitors having opposing conductive surfaces for electrical connection have one surface attached directly to the conductive surface of the spacer and a wire bond connection to the other surface. When using elongated capacitors with opposing conductive edges, an additional dielectric layer is provided on the conductive surface of the spacer, a metal layer is provided on the surface of the dielectric layer, the capacitor is attached and connected by a conductive material. An opening extending in the metal / dielectric layer is provided.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
The chip stack arrangement is indicated generally by 10 in the drawing. As shown in FIG. 1, a portion of a semiconductor package 14 includes a die attach surface 16 for receiving a semiconductor die or chip and a bonding pad 18 on the package or substrate 14. The first chip 20 is mounted on the surface 16 by conventional means. The chip 20 includes a surface 22, a surface 24, and wire bonding pads 26 for making electrical connections to the periphery of the surface 24. Package 14 may be a ceramic package with a recess for chip 20, or package 14 may be part of a multichip module. Package or substrate 14 includes bonding pads 18 for making electrical connections to package conductive paths (not shown). Electrical connection between the chip 20 and the package 14 is made by thin wires 28 having wire bond connections at the wire bond pads 26 and package bond pads 18. For example, aluminum or gold wire can be used, and wedge bonding or ball bonding can be used. Tape automatic bonding (TAB) can also be used.
[0010]
In addition, the arrangement 10 includes a planar spacer 30 having a lower surface 32 bonded to the surface 24 of the chip 20. The spacer 30 includes an upper surface 34, and various materials and configurations are possible depending on the application. A material such as silicon has a good thermal conductivity for heat dissipation and conforms to the thermal expansion coefficient of the chip 20 and the chip 40. Furthermore, silicon can be easily machined, so that the thickness can be properly controlled to provide accurate spacing. In FIG. 1, the spacer 30 is made of silicon and has a planar size or a planar size such that it at least partially rests on the surface 24 of the chip 20 within the area defined by the bonding pads 26. It has become. A spacer size about 40 mils smaller than the chip placed above has been found to be sufficient for the prototype. In FIG. 1, generally, after making a wire bond connection to the chip 20, a spacer 30 is bonded to the surface 24 using a non-conductive adhesive layer 36. It is desirable to use epoxy as an adhesive. Next, the chip 40 is bonded onto the surface 34 of the spacer 30 by an adhesive layer 38 such as epoxy. The chip 40 includes a surface 42 and a surface 44 having wire bond pads 46. The electrical connection between the chip 40 and the package 14 is made by a thin wire 28 with a wire bond connection at the die bond pad 46 and the package bond pad 18. The thickness 48 of the spacer 30 is selected so that the face 42 of the chip 40 is farther from the face 24 of the chip 20 than the highest point of the wire bond connection 28 so that sufficient spacing for wire bonding is obtained. In the case of memory chips, it is common for several pads on each chip to be bonded in parallel to the pads on the package, i.e., the same pad function of both chips can be bonded to the package bond pads. This statement usually applies to all chip pads of a memory chip, except for a chip select pad or chip enable pad that is isolated or bonded to its own unique package or substrate pad. Although only two chips are shown in FIG. 1, additional chip levels can be added by gluing an additional spacer 30 onto the face 44 of the chip 40.
[0011]
FIG. 1 shows a separation spacer. Another arrangement is to incorporate the function of the spacer 30 on the back of an active chip, such as the chip 40 of FIG. The isolation or spacer function can be achieved by chemical etching or mechanical sawing the backside of the wafer 39 as shown in FIG. In either case, the backside of the wafer 39 must be provided with approximately 0.040 inch channels removed on both sides of the wafer street 41. The channel depth is determined by the spacing required for wire bonding. A depth of 0.008 inches has been found to be sufficient for the prototype. A cross-sectional view of the active die 43 (the ratio of dimensions is not constant) including the active die surface 47, the area of silicon removal by chemical etching or mechanical sawing 45, the back or mounting surface 49 is shown in FIG.
[0012]
Some types of integrated circuits (ICs) require that the backside of the chip be connected to ground or Vss. A first alternative embodiment of arrangement 10 is shown in FIG. 4 including a package or substrate 14a having a die attach surface 16a and a package bonding pad 18a.
[0013]
The spacer 50 shown in FIG. 4b has an extended bottom layer or outer layer or shelf 52 having a surface 53 for attaching wire bonds, and contacts the bottom of the top chip and is spaced from the wire bond loop height. It includes two layers or a horizontal surface of the upper inner layer 54 having a feeding surface 55. In one indicated design, the bottom layer 52 generally has a thickness 56 of at least 0.002 inches, the top layer 54 is recessed from the bottom layer 52 by about 0.020 inches, and the surface of the top layer 54 is 55 has a height from surface 53 of about 0.006 inches. The spacer 50 can be a variety of materials. The spacer 50 may be a conductive material such as aluminum. Alternatively, the spacer 50 is made of a non-conductive material, at least a portion of the surfaces 53 and 55 are metallized, and the metallized portions are electrically interconnected by, for example, a metallized surface 59 that joins them. You can also The spacer 50 can be made of a silicon material, and the surfaces 53, 55 and 59 can be covered with a wire-bondable metal such as aluminum or gold.
[0014]
As shown in FIG. 4c, the spacer 50 can be composed of two separate pieces of aluminum joined by, for example, a conductive epoxy. For example, the lower piece 66 is about 0.002 inches thick and the upper piece 68 is about 0.006 inches thick.
[0015]
The advantages of silicon spacers are that they are good thermal conductors, are compatible with die thermal expansion, and are easy to machine by chemical or mechanical means. Other materials such as SiC, AlN, CuW are examples of other materials that have high thermal conductivity and a reasonable thermal fit to silicon.
[0016]
The use of the spacer 50 will be described below. Die 20a is attached to surface 16a by conventional means. Electrical connection between chip 20a and package 14a is made by a thin wire 28a having a Vdd or signal wire bond connection at die bond pad 26a and package bond pad 18a. Next, the conductive spacer 50 is bonded onto the upper surface 24a of the die 20a with a conductive adhesive or a non-conductive adhesive. Examples of non-conductive materials are non-conductive epoxies or polyimides. These bonding chemicals often include electrically insulating and thermally conductive materials such as alumina, diamond or aluminum nitride. Examples of conductive adhesives include epoxies or polyimides with added metals. Next, an electrical connection is made by means of a thin wire 28a having a wire bond connection at the surface 53 of the spacer 50 and the package bond pad 19. Alternatively, a wire bond can be created between the surface 53 and the ground pad on the die 20a. The power supply (Vdd) or signal connection can be made by a pad such as 18a. Next, the top die or the second die 40 a is bonded to the surface 55 of the spacer 50. A conductive adhesive or bonding material is required for electrical connection between the back surface of the chip 40a, that is, the surface 42a and the surface 55 of the spacer 50. Additional chip levels can be added to the stack by gluing additional spacers and active chips on top of the previous chips that have already made wirebond connections.
[0017]
It is often necessary to connect a capacitor to the IC chip. With conductive spacer 50, the capacitor can be mounted on a single chip or on a stack of chips. For example, in FIG. 5, the capacitor 60 is a large area capacitor in which power connection and ground connection are made to two large surfaces 61 and 62. As shown in FIG. 5, the connection of the chip 20b to the package 14b, the attachment and connection of the spacer 50a to the chip 20b, and the attachment and connection of the chip 40b are the same as those described for the same components in FIG. . The conductive spacer 50b is bonded to the chip 40b with a conductive adhesive or a non-conductive adhesive. A wire bond connection is made from the surface 53 of the spacer 50b to the ground pad on the chip 40b. Alternatively, surface 53 can be directly connected to ground (Vss) pad 19b on package 14b. Next, the capacitor 60 is bonded to the spacer 50b with a conductive adhesive so that the bottom surface 61 is in electrical contact with the top surface of the spacer 50b and is effectively grounded. The power supply (Vdd) connection from the power supply pad on the chip 40b or the power supply pad 18b on the package 14b to the surface 62 of the capacitor 60 is made by wire bonding.
[0018]
6 and 7 show another embodiment having a capacitor mounting configuration in which the isolated capacitor 70 has a conductive end 72 for connection to ground and a conductive end 74 for connection to a power source. For example, a type 1206 capacitor can be used. In this embodiment, the assembly process is the same as in FIG. 5 until the attachment and connection of the second chip 40c. The conductive spacer 80 is a modification of the conductive spacer 50 described. The conductive surface 82 corresponds to the conductive surface 53 of the spacer 50. A dielectric material layer 84, such as a polymer film or a thick dielectric paste, needs to be adhered or deposited on the surface 82. A thin metal layer or film 86 is then adhered to the top surface of the dielectric layer 84. An opening 88 is then created in the metal layer 86 and the dielectric layer 84 to expose the conductive surface 82 of the spacer 80. Capacitor 70 is bonded to spacer 80 with conductive material 90 such as a conductive adhesive or solder, or other conductive material. Next, the end portion 74 of the capacitor 70 is connected to the conductive surface 82, and the end portion 72 is connected to the metal layer 86. A wire bond 90 is made between the conductive surface 82 and the ground pad on the chip 40c or to the ground pad on the package 14c. Additional wire bonds 94 are created from the metal layer 86 to the power pads on the chip 4c or to the power pads on the package 14c.
[0019]
Those skilled in the art will appreciate that the materials and processes just described can be varied. For example, a metal layer or film 86 can be pre-bonded to the dielectric layer 84, such as in a clad flexible polymer film. As another example, the openings in the dielectric layer 84 can be patterned before the metal film 86 is deposited and patterned.
[0020]
The scope of the invention is indicated by the appended claims rather than by the foregoing description.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a chip stack arrangement according to the present invention.
FIG. 2 is a cross-sectional view of a chip having an integral spacer.
3 is a plan view of a part of the back surface or bottom of a semiconductor wafer used to obtain the chip of FIG. 2; FIG.
FIG. 4 is a cross-sectional view of another embodiment of the present invention.
FIG. 5 is a cross-sectional view of another embodiment of the present invention.
FIG. 6 is a cross-sectional view of another embodiment of the present invention.
7 is a plan view of the same embodiment as FIG. 6. FIG.
[Explanation of symbols]
16 Die attachment surface 18 Bonding pad 19 Package bond pad 20 First chip 22, 24, 42, 44, 61, 62 Surface 30 Flat spacer 36 Non-conductive adhesive layer 38 Adhesive layer 90 Conductive material 94 Wire bond

Claims (9)

A die mounting surface;
A first die fixed to the die attachment surface;
A first plurality of thin wires extending from a first plurality of bonding pads on the first die to a second plurality of bonding pads external to the first die;
A first outer layer and a first central layer, wherein the first outer layer and the first central layer have conductive surfaces and are electrically interconnected; and at least a part has a planar dimensions as fall within the space bounded, first spacer means secured to a surface of the first die by contacting adhesive layer by the bonding pads,
The first spacer means having a thickness such that the surface of the second die facing the first spacer means is away from the highest point of the first plurality of thin wires from the first die. A second die fixed by a conductive adhesive material;
A second plurality of thin wires extending from a third plurality of bonding pads on the second die to a fourth plurality of bonding pads external to the second die;
Means for electrically connecting the conductive surface of the outer layer of the first spacer means to a first voltage. 2. The chip stack of claim 1 wherein said first spacer means is silicon and said second die is secured to said first spacer means by said conductive adhesive. Placement. One member from the first spacer means and the second die semiconductor wafer, are integrally formed, and the first spacer means, by removing a portion of the back surface of the semiconductor wafer The chip stack arrangement of claim 1, wherein the chip stack arrangement is formed. 2. The first spacer means is silicon and the conductive surfaces of the first outer layer and the first central layer comprise a metal suitable for wire bond connection. Chip stack placement. 2. A chip stack arrangement as claimed in claim 1, wherein said first spacer means is aluminum. 2. A chip stack arrangement according to claim 1, wherein said means for electrically connecting is wire bond means. And second spacer means having a second outer layer and a second central layer secured to the surface of the second die and having a conductive surface and electrically interconnected;
Capacitor means having a first conductive surface fixed to the conductive surface of the second central layer of the second spacer means by a conductive material; and a second conductive surface;
Means for electrically connecting the conductive surface of the second outer layer to a first voltage reference;
The chip stack arrangement of claim 1 including means for electrically connecting said second conductive surface to a second voltage. And second spacer means having a second outer layer and a second central layer secured to the surface of the second die and having a conductive surface and electrically interconnected;
A dielectric layer fixed to the conductive surface of the second central layer;
A conductive layer fixed to the dielectric layer;
An opening extending into the conductive layer and into the dielectric layer to expose the conductive surface of the second central layer;
A capacitor having a first conductive end fixed to the conductive surface of the second central layer by a conductive material, and a second conductive end fixed to the conductive layer by a conductive material Means,
Means for electrically connecting the conductive surface of the second outer layer to a first voltage reference;
The chip stack arrangement of claim 1 including means for electrically connecting said conductive layer to a second voltage. 9. The chip stack arrangement of claim 8, wherein the dielectric layer and the conductive layer are joined before being attached to the conductive surface of the second central layer.

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