JP3898363B2 - Multilayer wiring board for wafer batch contact board, connector connected to the multilayer wiring board, connection structure thereof, and inspection apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer wiring board for a wafer collective contact board that constitutes a part of a wafer collective contact board that is used to collectively test (inspect) semiconductor devices formed on a wafer in a wafer state. The present invention relates to a connector connected to an outer peripheral pad of the multilayer wiring board, and a connection structure thereof.
[0002]
[Prior art]
Inspection of many semiconductor devices formed on a wafer is roughly classified into product inspection (electrical characteristic test) using a probe card and burn-in test which is a reliability test performed thereafter.
The burn-in test is one of screening tests performed to remove a semiconductor device having an inherent defect or a device causing a failure depending on time and stress from manufacturing variations. While the probe card inspection is an electrical characteristic test of the manufactured device, the burn-in test is a thermal acceleration test.
[0003]
The burn-in test is a normal method (one-chip burn-in system) in which a wafer is cut into chips by dicing and packaged one by one after an electrical characteristic test performed for each chip by a probe card. Then, cost is not feasible. Therefore, development and practical use of a wafer batch contact board (burn-in board) for performing a burn-in test on a plurality of semiconductor devices formed on the wafer all at once are being promoted (Japanese Patent Laid-Open No. 7-231019). . Wafer batch burn-in system using wafer batch contact board is not only highly feasible in terms of cost, but also an important technology to enable the latest technological flow such as bare chip shipment and bare chip mounting. .
The wafer batch contact board is different from the conventional probe card in that the wafer batch contact board is used for the batch wafer inspection and the heating test, and the required level is high. When the wafer batch contact board is put into practical use, it becomes possible to perform product inspection (electrical characteristic test), which has been conventionally performed by a probe card, in a wafer batch.
[0004]
FIG. 13 shows a specific example of the wafer batch contact board.
As shown in FIG. 13, the wafer batch contact board has a bumped membrane ring 30 on a multilayer wiring board for wafer batch contact board (hereinafter referred to as a multilayer wiring board) 10 via an anisotropic conductive rubber sheet 20. It has a fixed structure.
The membrane ring 30 with bumps is in charge of a contact portion that is in direct contact with a wafer as an element to be inspected. In the membrane ring 30 with bumps, bumps 33 are formed on one surface of the membrane 32 stretched over the ring 31, and pads 34 are formed on the other surface. The bumps 33 are pads formed on the periphery or center line of each semiconductor chip on the wafer 40 (about 600 to 1000 pins per chip, and the number of pads multiplied by the number of chips is on the wafer). Are formed at positions corresponding to the same number as the pads.
The multilayer wiring board 10 has wiring on the insulating substrate for applying a predetermined burn-in test signal or the like to each bump 33 isolated on the membrane 32 via the pad 34. The multilayer wiring board 10 has a multilayer wiring structure because wiring is complicated.
The anisotropic conductive rubber sheet 20 is an elastic body (made of silicon resin, in which metal particles are embedded in a pad electrode portion) having conductivity only in a direction perpendicular to the main surface. These terminals (not shown) and the pads 34 on the membrane 32 are electrically connected. The anisotropic conductive rubber sheet 20 abuts against the pad 34 on the membrane 32 with a convex portion (not shown) formed on the surface thereof, thereby causing unevenness on the surface of the semiconductor wafer 40 and variations in the height of the bumps 33. Absorbing, the pads on the semiconductor wafer and the bumps 33 on the membrane 32 are securely connected.
[0005]
[Problems to be solved by the invention]
Since the wafer batch contact board performs inspection of semiconductor devices on the wafer all at once, the wafer batch contact board should not have defects such as disconnection and short circuit (open / short). For this reason, inspection at the time of shipment of the wafer batch contact board and inspection at the time of delivery are required.
Such a wafer batch contact board inspection apparatus can be realized in the same manner as the probe card inspection apparatus used for the open / short check of the probe card. In the probe card inspection apparatus, the probe card is inspected using a mother board (DUT board) having pogo pins (extractable pins with springs) corresponding one-to-one with the outer peripheral pads of the probe card.
[0006]
However, since the wafer batch contact board is large and requires a large number of pins, it is very expensive (about 10 million yen) to produce a mother board for wafer batch contact board inspection. , Not profitable and not practical. Furthermore, in this method, since the arrangement of the outer peripheral pads of the wafer batch contact board (multilayer wiring board) differs depending on the semiconductor device to be inspected, a dedicated motherboard is required for each semiconductor device, and the cost is enormous. End up.
[0007]
For this reason, at present, a connector such as an FPC (flexible printed circuit) in which a wiring is formed on a transparent flexible sheet is used, and the position is visually aligned with the outer peripheral pad for connection.
However, even if the power supply lines, ground lines, and signal lines of the multilayer wiring board are reduced in common, the number of outer peripheral pads is still large, and the number of FPCs to be connected must be 10 or more. It is cumbersome and time consuming to accurately align and connect to the outer peripheral pads of the substrate one by one. In addition, inspection at the time of shipment and delivery at the time of wafer batch contact board is 100% inspection, and since the number of wafer batch contact boards is large, connectors can be connected easily and quickly without displacement. Requested.
These problems also apply to a wafer collective inspection apparatus (burn-in inspection apparatus or the like) that performs an actual inspection using a wafer collective contact board.
[0008]
The present invention has been made under the above-described background, and a multilayer wiring board structure and a connector structure for easily connecting a connector to an outer peripheral pad of a multilayer wiring board in a wafer collective contact board easily and without displacement. The first object is to realize the connection structure.
Also, there is no need for an expensive pogo-pin integrated motherboard, and it is possible to easily connect the connector to the outer peripheral pad of the multilayer wiring board in the wafer batch contact board quickly and without misalignment. The second object is to provide an inspection apparatus and a wafer batch inspection apparatus.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is configured as follows.
[0010]
(Configuration 1) A multilayer wiring board constituting a part of a wafer batch contact board used for collectively testing a plurality of semiconductor devices formed on a wafer, wherein the multilayer wiring board is formed in a peripheral region of the multilayer wiring board. A multilayer wiring board for a wafer collective contact board, characterized in that a guide portion that plays a role of guiding and aligning when connecting a connector is provided adjacent to an outer peripheral pad to be formed.
[0011]
(Configuration 2) A multilayer wiring board constituting a part of a wafer batch contact board used for collectively testing a plurality of semiconductor devices formed on a wafer, wherein the multilayer wiring board is formed in a peripheral region of the multilayer wiring board. A multilayer wiring board for a wafer batch contact board, wherein outer peripheral pads to be formed are blocked.
[0012]
(Configuration 3) A multilayer wiring board constituting a part of a wafer batch contact board used for collectively testing a plurality of semiconductor devices formed on a wafer, wherein the multilayer wiring board is formed in a peripheral region of the multilayer wiring board. A multilayer wiring board for a wafer batch contact board, characterized in that the line width and line spacing of the outer peripheral pads formed are standardized.
[0013]
(Configuration 4) A connector connected to an outer peripheral pad in a multilayer wiring board constituting a part of a wafer batch contact board used for collectively testing a plurality of semiconductor devices formed on a wafer, A connector having an engaging portion that engages or fits with a guide portion formed on the multilayer wiring board.
[0014]
(Configuration 5) The connector according to Configuration 4, which has a clip structure that can be attached by narrowing the substrate.
[0015]
(Configuration 6) Peripheral pads formed in a peripheral region of a substrate in a multilayer wiring board constituting a part of a wafer batch contact board used for collectively testing a plurality of semiconductor devices formed on a wafer A structure in which a guide portion that guides and aligns when connecting a connector to the blocked outer peripheral pad is provided adjacent to the blocked outer peripheral pad, and is standardized. And
The structure of the connector for connection connected to the blocked outer peripheral pad has an engaging portion that engages or fits with a guide portion formed on the multilayer wiring board, and narrows the multilayer wiring board. It has a structure with a clip structure that can be attached by
A connection structure characterized in that when the connector is connected to the multilayer wiring board, the guide portion and the engagement portion are engaged and connected.
[0016]
(Configuration 7) A wafer batch contact board inspection apparatus using at least the multilayer wiring board for wafer batch contact boards according to configurations 1 to 3 and the connector according to configurations 4 to 5.
[0017]
(Structure 8) A wafer collective inspection apparatus comprising at least a wafer collective contact board having a multilayer wiring board for wafer collective contact boards according to Structures 1 to 3, and a connector according to Structures 4 to 5.
[0018]
[Action]
According to Configuration 1, by providing a guide portion that plays a role of guiding (positioning) when connecting the connector adjacent to the outer peripheral pad of the multilayer wiring board, the connector may be connected in accordance with the guide portion. Therefore, it is possible to easily connect the connector to the outer peripheral pad and quickly connect the connector without displacement.
[0019]
According to the configuration 2, it is only necessary to connect the connector for each block by making the outer peripheral pad into blocks, and therefore, the connector can be easily and quickly connected to the outer peripheral pad at low cost.
[0020]
According to the configuration 3, the connector can be standardized by standardizing the line width and the line interval of the outer peripheral pad, and the connector can be manufactured easily and inexpensively. In addition, the connector can be manufactured more easily and inexpensively by blocking and standardizing the outer peripheral pad.
[0021]
According to the configuration 4, by providing the connector with the engagement portion, the connector can be easily and reliably connected to the outer peripheral pad simply by engaging or fitting the engagement portion with the guide portion formed on the multilayer wiring board. It can be connected quickly and easily without misalignment.
[0022]
According to the structure 5, it can connect simply and reliably only by narrowing a board | substrate by setting it as a clip-type connector. Moreover, the connector can be easily attached and detached.
[0023]
According to the configuration 6, by combining the above configurations 1 to 5, there is no need for strict alignment by visual inspection at the time of connection, and therefore a connection structure that can easily and quickly connect the connector to the outer peripheral pad without displacement. realizable.
[0024]
According to the configuration 7, by adopting the above configurations 1 to 5, in the wafer batch contact board inspection device, the connector can be easily and quickly connected to the outer peripheral pad without being displaced. Can be shortened.
[0025]
According to the configuration 8, by adopting the above configurations 1 to 5, in the wafer collective inspection apparatus (burn-in inspection apparatus or the like), the connector can be easily and quickly connected to the outer peripheral pad without being misaligned. This makes it possible to shorten the work time.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below.
[0027]
(Production of multilayer wiring board)
9 and 10 are cross-sectional views of relevant parts showing an example of a manufacturing process of a multilayer wiring board.
As shown in step (1) of FIG. 9, a Cr film is approximately sputtered on one side of a glass substrate 1 (made by HOYA: NA40, size 320 mm square, thickness 3 mm) whose surface has been polished flat. A Ni / Cu / Cr multilayer wiring layer 2 is formed by sequentially forming a film with a thickness of 300 Å, a Cu film of about 2.0 μm, and a Ni film of about 0.3 μm.
Here, Cr is provided for the purpose of strengthening the adhesion between glass and Cu. Ni is provided for the purpose of preventing the oxidation of Cu, the purpose of strengthening the adhesion between Cu and resist, and the purpose of preventing the polyimide from remaining at the bottom of the contact hole (via) due to the reaction between Cu and polyimide. ing.
In addition, the formation method of Ni is not limited to a sputtering method, You may form by the electroplating method. It is also possible to reduce contact resistance by forming an Au film on the Ni film by sputtering, electrolytic plating, or electroless plating.
[0028]
Next, as shown in step (2) of FIG. 9, a predetermined photolithography step (resist coating, exposure, development, etching) is performed, and the Ni / Cu / Cr multilayer wiring layer 2 is patterned to form the first layer. The wiring pattern 2a is formed.
Specifically, first, a resist (manufactured by Shipley Co., Ltd .: Microposit S1400) is coated to a thickness of 3 μm, baked at 90 ° C. for 30 minutes, the resist is exposed and developed using a predetermined mask, and a desired resist pattern ( (Not shown). Using this resist pattern as a mask, the Ni / Cu / Cr multilayer wiring layer 2 is etched using an etching solution such as a ferric chloride aqueous solution, then the resist is stripped using the resist stripping solution, washed with water and dried. Thus, the first-layer wiring pattern 2a is formed.
[0029]
Next, as shown in step (3) of FIG. 9, a polyimide polyimide insulating layer 3 is formed by applying a photosensitive polyimide precursor to the thickness of 10 μm on the first wiring pattern using a spinner or the like. Contact holes 4 are formed in the polyimide insulating layer 3.
Specifically, the applied photosensitive polyimide precursor is baked at 80 ° C. for 30 minutes, exposed and developed using a predetermined mask, and the contact hole 4 is formed. The second wiring layer formed in the next process after curing the polyimide at 350 ° C. for 4 hours in a nitrogen atmosphere to completely polyimide the photosensitive polyimide precursor and then roughening the polyimide surface by oxygen plasma treatment In addition, the organic matter such as polyimide and developer residue in the contact hole 4 is oxidized and removed.
[0030]
Next, as shown in step (4) in FIG. 9, the Ni / Cu / Cr multilayer wiring layer 5 is formed in the same manner as in step (1).
[0031]
Next, as shown in step (5) of FIG. 9, the Ni / Cu / Cr multilayer wiring layer 5 is patterned in the same manner as in the above step (2) to form a second wiring pattern 5a.
[0032]
Next, as shown in step (6) of FIG. 10, the above steps (3) to (5) are repeated in the same manner to repeat the second polyimide insulating layer 6 and the contact hole 7, and the third wiring pattern 8a. Were sequentially formed to obtain a glass multilayer wiring board having a three-layer structure.
However, the wiring pattern 8a of the third layer is a multilayer wiring of Au / Ni / Cu / Cr structure for the purpose of improving the electrical contact property with the anisotropic conductive film. Specifically, the first layer wiring except that an Au film is formed on the Ni film to a thickness of 0.5 μm by electrolytic plating and the Au film is etched using an aqueous solution of iodine and potassium iodide. A third-layer wiring pattern 8a was formed in the same manner as the pattern. The Ni film plays a role of enhancing the adhesion between the Au film and Cu. Although an Au film can be formed on the Ni film by electroless plating, the thickness of the Au film cannot be increased.
[0033]
In the present embodiment, in step (6) of FIG. 10, as shown in FIG. 1, outer peripheral pads (external lead terminals) 51 formed in the peripheral region of the uppermost layer of the multilayer wiring board are made into a plurality of outer peripheral pad groups. In addition to making blocks, the line widths and line intervals of the peripheral pads in the vertical, horizontal, and diagonal directions on the paper surface of FIG. Note that FIG. 1 is illustrated in a simplified manner for ease of explanation, and the form of blocking and standardization is not limited to the form shown in FIG. The number of blocks can be designed freely, for example, about 10 to 20. Blocking and standardization can be freely designed according to the type of semiconductor device (for memory, ASIC, MPC, microcomputer, CLD, etc.).
[0034]
Next, as shown in step (10) of FIG. 10, after removing the resist, polyimide as an insulating film is applied on the substrate, and this is patterned to form a protective insulating film 11 to perform wafer batch contact. A multilayer wiring board 10 for boards was obtained.
[0035]
(Formation of guide part)
Next, as shown in FIG. 1, guide holes 53 were provided as guide portions on both sides of each block of the outer peripheral pad 52 that was made into a block.
[0036]
(Production of connector)
Next, as shown in FIG. 2, a connector 60 to be connected to the blocked outer peripheral pad was produced. The connector 60 has guide pins 61 as engaging portions that engage with or fit into the guide holes 53 formed in the multilayer wiring board 10. Further, as shown in FIGS. 2 and 3, the connector 60 has a clip structure having a spring 62 so that it can be attached by narrowing the multilayer wiring board 10. The connector 60 has wiring 63 connected one-to-one to the outer peripheral pad 51 on the multilayer wiring board 10, and a socket 64 is provided at the other end of the wiring 63, and a tester (not shown) is provided via the socket 64. ).
[0037]
In the formation of the guide portion, the guide portion includes a guide hole 54 shown in FIG. 4, a groove-like guide hole 55 shown in FIG. 5, an embedded guide pin 56 shown in FIG. 6, and a convex shape shown in FIG. Or it can be set as aspects, such as a concave guide pattern 57. FIG. In these cases, the engagement portion in the connector may be shaped to fit the guide portion. Note that the guide portion and the engaging portion may be interchanged, the guide portion may be formed on the connector side, and the engaging portion may be formed on the multilayer wiring board side.
[0038]
Formation of guide holes and guide grooves in the glass substrate can be performed using, for example, a drill or an ultrasonic drill. In this case, it is preferable to perform processing while supplying abrasive and water. In the case of a ceramic substrate, a guide hole can be formed by making a hole in the state of a green sheet and then performing sintering. If the depth of the groove-shaped guide hole is about 100 to 500 μm, it can sufficiently function as a guide portion.
[0039]
The convex or concave guide pattern 57 shown in FIG. 7 can be formed simultaneously when patterning the wiring layer or protective insulating film formed on the uppermost layer of the multilayer wiring board. When the guide pattern is formed using the wiring layer, the protective insulating film around the guide pattern is removed. When the guide pattern is formed using the protective insulating film, the protective insulating film around the guide pattern is removed in the case of a convex shape, and the protective insulating film in the guide pattern portion is removed in the case of a concave shape. The height difference of the convex or concave guide pattern is preferably larger, but if it is a height difference of several μm, it can sufficiently function as a guide portion. Therefore, if the height difference is about the same as the thickness of the wiring layer (usually 2 to 20 μm) and the thickness of the protective insulating film (usually 5 to 20 μm), it can sufficiently function as a guide.
It is preferable that the position accuracy and the shape accuracy of the guide portion and the engagement portion are high. However, even if the accuracy is shifted by several μm, if the guide portion and the engagement portion can be engaged (fitted), the outer peripheral pad 51 and There is no problem in connection with the wiring 63. It is easy to form the guide portion and the engagement portion with such an accuracy.
[0040]
(Lamination of anisotropic conductive rubber sheet)
Next, an anisotropic conductive rubber sheet made of silicon resin and having metal particles embedded in the pad electrode portion was bonded to a predetermined position of the multilayer wiring board 10 for wafer batch contact board.
[0041]
(Membrane ring creation)
Next, a membrane ring with bumps, which handles a contact portion that is in direct contact with the wafer, was produced.
[0042]
A method for creating a membrane ring will be described with reference to FIG.
First, as shown in FIG. 11A, a silicon rubber sheet 36 having a uniform thickness of 5 mm is placed on an aluminum plate 35 with high flatness.
On the other hand, for example, a film 37 is prepared by forming a copper film with a thickness of 18 μm on a polyimide film with a thickness of 25 μm by sputtering or plating.
In addition, the material of the film 37, a formation method, thickness, etc. can be selected suitably. For example, a polyimide film having a thickness of about 25 μm (12 to 50 μm) or a silicon rubber sheet having a thickness of about 0.3 mm (0.1 to 0.5 mm) can be used. The film can be formed by a coating method, or a commercially available film or sheet can be used. Furthermore, after casting a polyimide precursor on a copper foil, the polyimide precursor is heated and dried and cured to form a film having a structure in which the copper foil and the polyimide film are bonded together. Alternatively, a structure in which a plurality of conductive metals are sequentially formed on one surface of a film and a conductive metal layer having a laminated structure is formed on one surface of the film can be used.
Further, a thin Ni film may be formed between polyimide and Cu for the purpose of improving the adhesion between them and preventing film contamination, although not particularly shown.
[0043]
Next, a film 37 having a structure in which copper and a polyimide film are bonded to each other is adsorbed on the silicon rubber sheet 36 in a state where the film is uniformly developed with the copper side facing down. At this time, by utilizing the property that the film 37 is adsorbed to the silicon rubber sheet 36, the air layer is expelled and adsorbed so as not to cause wrinkles or deflection, and adsorbed in a uniformly developed state.
[0044]
Next, a thermosetting adhesive 38 is thinly and evenly applied to the adhesive surface of the circular SiC ring 31 having an outer diameter of 260 mmφ, an inner diameter of 240 mmφ, and a thickness of about 2 mm, and is applied on the film 37 to a thickness of about 50 to 100 μm. Put. Here, as the thermosetting adhesive 38, an adhesive that cures at a temperature 0 to 50 ° C. higher than the set temperature 80 to 150 ° C. of the burn-in test is used. In the present embodiment, Bond High Chip HT-100L (main agent: curing agent = 4: 1) (manufactured by Konishi Co., Ltd.) was used.
Further, a highly flat aluminum plate (weight approximately 2.5 kg) is placed on the ring 31 as a weight (not shown).
[0045]
After finishing the above preparation step, the film 37 and the ring 31 are bonded by heating at a temperature (for example, 200 ° C., 2.5 hours) equal to or higher than the set temperature (80 to 150 ° C.) of the burn-in test (FIG. 11 ( b)).
At this time, since the thermal expansion coefficient of the silicon rubber sheet 36 is larger than the thermal expansion coefficient of the film 37, the film 37 adsorbed on the silicon rubber sheet 36 thermally expands by the same amount as the silicon rubber sheet 36. That is, since the thermal expansion of the silicon rubber sheet is larger than when the film 37 is simply heated at a temperature equal to or higher than the set temperature (80 to 150 ° C.) of the burn-in test, the polyimide film is further expanded by this stress. In a state where the tension is large, the thermosetting adhesive 38 is cured, and the film 37 and the ring 31 are bonded. Further, since the film 37 on the silicon rubber sheet 36 is adsorbed in a state of being uniformly spread without wrinkles, deflection, or loosening, the film 37 can be adhered to the ring 31 without wrinkling, bending, or loosening. it can. Furthermore, since the silicon rubber sheet 36 has high flatness and elasticity, the film 37 can be uniformly adhered to the adhesion surface of the ring 31 without unevenness. The tension of the polyimide film is 0.5kg / cm ² That is all.
In addition, when a thermosetting adhesive is not used, the film shrinks and the tension is weakened. In addition, since the curing time of the adhesive varies depending on the location, the ring cannot be evenly and evenly bonded.
[0046]
After finishing the heating and bonding step, the product is cooled to room temperature and contracted to a state before heating. Thereafter, the film 37 outside the ring 31 is cut and removed along the outer periphery of the ring 31 with a cutter to produce a membrane ring (FIG. 11C).
[0047]
Next, a process of processing the membrane ring to form bumps and pads will be described.
[0048]
First, on the copper foil (Cu) of the film 37 having a structure in which the copper foil and the polyimide film in the membrane ring produced above shown in FIG. 12A are bonded together, as shown in FIG. After plating with Ni of 0.2 to 0.5 μm (preferable range is 0.1 to 3 μm), Au is formed thereon with 0.1 to 0.5 μm (preferable range is 0.5 to 2 μm). Then, an Au / Ni / Cu / polyimide film laminated film structure is formed.
[0049]
Next, as shown in FIG. 12C, a bump hole having a diameter of about 30 μm is formed at a predetermined position of the polyimide film using an excimer laser.
[0050]
Next, as shown in FIG. 12 (d), in order to prevent the surface of the uppermost Au film from being plated, a protective film such as a resist is applied to the entire surface excluding a part of the Au film used as an electrode. The Au film is protected by coating with a thickness of about 2 to 3 μm.
[0051]
Next, one of the electrodes is connected to the uppermost Au film, and Ni or Ni alloy is electroplated on the polyimide film side. By this electroplating, the plating grows so as to fill the bump holes shown in FIG. 12 (d), and when it reaches the surface of the polyimide film, it expands isotropically and grows into a substantially hemispherical shape. A bump made of is formed.
Subsequently, an electroplating layer made of Au having a thickness of 1 to 2 μm is formed on the surface of the bump. Thereafter, although not particularly shown, the protective film is peeled off.
[0052]
Then, a resist is newly applied on the uppermost Au, and the resist other than the portion for forming the pad is removed by exposure and development, and a resist pattern is formed on the pad forming portion as shown in FIG. Form.
[0053]
Next, as shown in FIG. 12 (f), the Au film is etched with an iodine / potassium iodide aqueous solution, and the thin Ni film and Cu film existing between Au and Cu are etched with a ferric chloride aqueous solution or the like. After rinsing and rinsing well, the resist is peeled off to form a pad made of Au / Ni / Cu as shown in FIG. At this time, it is desirable to use a spray method for etching because there is little side etching.
[0054]
Through the above steps, bumps and pads are formed on the membrane ring, and the membrane ring with bumps is completed.
[0055]
(Assembly process)
As shown in FIG. 8, the multi-layer wiring board 10 with anisotropic conductive rubber sheet 20 and the membrane ring 30 with bumps manufactured above are aligned so that the pad electrode 34 does not come off, and then bonded together, and the wafer collective contact Completed the board.
[0056]
(Board inspection)
As shown in FIG. 8, a metal plate 72 is placed on an XYZ table 71 of a vacuum chuck 70, a wafer batch contact board is aligned and placed thereon, and the inside is evacuated by a vacuum pump 73. These were adsorbed. A clip-type connector 60 was connected to one block of the blocked pads, and a tester 80 was connected between the connector 60 and the metal plate 72. In this state, the tester was operated to perform open / short check and capacity measurement. Other blocks were similarly tested.
In this case, the connector can be easily and quickly connected to the outer peripheral pad of the multilayer wiring board by the guide portion and the engaging portion without misalignment.
[0057]
(Burn-in test)
Place the wafer on the X, Y, Z table of the vacuum chuck, align the pads on the wafer and the bumps of the membrane ring with bumps, place the wafer batch contact board on the wafer, and vacuum the inside with a vacuum pump These were adsorbed. A clip-type connector was connected to one block of the blocked pads, and a tester was connected between the connector and the metal plate. In that state, it was put in a burn-in apparatus and tested in an operating environment of 125 ° C. Other blocks were similarly tested.
In this case, the connector can be easily and quickly connected to the outer peripheral pad of the multilayer wiring board by the guide portion and the engaging portion without misalignment.
[0058]
In addition, this invention is not limited to the said embodiment, It can deform | transform suitably and implement within the scope of the present invention.
[0059]
For example, the number of wiring layers in the multilayer wiring board for wafer batch contact board is not limited to three layers, but can be a desired number of layers (for example, usually 2 to 5 layers).
[0060]
Further, the glass substrate is not limited to NA40 manufactured by HOYA, but is made of a material that has the same thermal expansion coefficient as Si or has a similar expansion coefficient to Si, and does not warp due to stress and is easy to mold. Things can be used. Examples of such materials include ceramic substrates such as SiC, SiN, and alumina, and other glass substrates (for example, NA35, NA45, SD1, SD2 (from HOYA), Pyrex, 7059 (from Corning)). Such as Si having a thermal expansion coefficient substantially the same as that of Si (coefficient of thermal expansion of 0.6 to 5 PPM, nickel ore, etc.), glass ceramic substrate, resin substrate (especially for small substrates), etc. be able to.
The glass substrate is cheaper and easier to process than the ceramic substrate, the flatness etc. is good by high-precision polishing, and it is transparent, so it is easy to align, and the thermal expansion can be controlled by the material. Excellent in properties. Moreover, if it is an alkali free glass, there will be no bad influence by the surface elution of an alkali.
[0061]
Furthermore, materials such as pads, bumps, and membranes, formation methods, and the like are not limited to the above embodiments.
[0062]
Specifically, the material for forming the bump is preferably nickel (Ni) or a nickel alloy from the viewpoint of good conductivity, low cost, easy formation, and good durability, but is not limited thereto. Also, the method for forming the bump hole is not particularly limited, but it is preferably formed using a laser or a photolithography method in consideration of accuracy and economy.
[0063]
The formation material, formation method, thickness, etc. of the pad (conductive layer) can be selected as appropriate. Copper (Cu) is preferable from the viewpoint of good conductivity, low cost, and easy formation. Further, the pad can have a laminated structure or a single layer structure of a plurality of metal layers such as Cu, Ni, Cr, Al, Au, and Ag. As a method for forming the pad (conductive layer), a film forming method such as sputtering or vapor deposition, a plating method such as electroless plating or electroplating, or a method of bonding a copper foil can be used. The thickness of the pad (conductive layer) is preferably about 5 to 35 μm because durability is required.
[0064]
In addition, instead of Au plating, electroplating with an Au—Co alloy can be performed on the pad surface and the bump surface. In this case, since the Au—Co alloy has higher hardness than Au (pure gold), the bump and the pad surface wear less. Further, the same effect can be obtained by forming palladium, rhodium or an alloy containing these metals instead of Au or Au—Co alloy. Electroplating can be performed in a shorter time than electroless plating, and has high mechanical strength and adhesion and is difficult to peel off. Moreover, since the film thickness of plating can be formed thickly, adhesion (contact property) with a contacted part is good.
[0065]
【The invention's effect】
According to the present invention, the connector can be easily and quickly connected to the outer peripheral pad without being displaced. Therefore, in the inspection of the wafer batch contact board and the wafer batch inspection (burn-in inspection apparatus or the like), the connection work can be made efficient, and these apparatuses can be realized at low cost.
[Brief description of the drawings]
FIG. 1 is a plan view showing a multilayer wiring board according to an embodiment of the present invention.
FIG. 2 is a perspective view showing a connector according to an embodiment of the present invention.
FIG. 3 is a perspective view showing a connection according to an embodiment of the present invention.
FIG. 4 is a partially enlarged perspective view showing a guide portion in the multilayer wiring board according to the embodiment of the present invention.
FIG. 5 is a partially enlarged perspective view showing a guide portion in a multilayer wiring board according to another embodiment of the present invention.
FIG. 6 is a partially enlarged perspective view showing a guide portion in a multilayer wiring board according to another embodiment of the present invention.
FIG. 7 is a partially enlarged perspective view showing a guide portion in a multilayer wiring board according to another embodiment of the present invention.
FIG. 8 is a cross-sectional view schematically showing the wafer batch contact board inspection apparatus according to one embodiment of the present invention.
FIG. 9 is a fragmentary cross-sectional view for explaining a manufacturing step of the multilayer wiring board for wafer batch contact board according to the embodiment of the present invention;
FIG. 10 is a fragmentary cross-sectional view for explaining a manufacturing step of the multilayer wiring board for wafer collective contact board according to the embodiment of the present invention.
FIG. 11 is a cross-sectional view for explaining a membrane ring forming step according to an embodiment of the present invention.
FIG. 12 is a fragmentary cross-sectional view for explaining a membrane ring processing step according to an embodiment of the present invention.
FIG. 13 is a diagram schematically showing a wafer batch contact board.
[Explanation of symbols]
1 Glass substrate
2 Ni / Cu / Cr multilayer wiring layer
2a 1st layer wiring pattern
3 Insulation layer
4 Contact hole
5 Ni / Cu / Cr multilayer wiring layer
5a Second layer wiring pattern
6 Insulation layer
7 Contact hole
8a 3rd layer wiring pattern
10 Multilayer wiring board
11 Insulating film for protection
20 Anisotropic conductive rubber sheet
30 Membrane ring with bump
31 rings
32 Membrane
33 Bump
34 pads
35 Aluminum plate
36 Silicone rubber sheet
37 films
38 Thermosetting adhesive
40 Silicon wafer
51 Perimeter pad
52 Blocked outer pad
53 Guide hole
54 Guide holes penetrated
55 Groove-shaped guide hole
56 Buried guide pins
57 Convex or concave guide pattern
60 connectors
61 Guide pin
62 Spring
63 Wiring
64 socket
70 Vacuum chuck
71 X, Y, Z table
72 metal plate
73 Vacuum pump
80 tester

Claims (5)

A multilayer wiring board constituting a part of a wafer batch contact board used for collectively testing a plurality of semiconductor devices formed on a wafer,
Adjacent to the outer peripheral pad formed in the peripheral area of the multilayer wiring board, provided with a guide portion that plays a role of guiding and aligning when connecting the connector ,
Block outer peripheral pads formed in the peripheral area of the multilayer wiring board ,
Standardize the line width and line spacing of the outer peripheral pads formed in the peripheral area of the multilayer wiring board ,
A multilayer wiring board for a wafer batch contact board. A connector connected to the outer peripheral pad in the multilayer wiring board according to claim 1 ,
Having an engaging part that engages or fits with a guide part formed on the multilayer wiring board ;
A connector having a clip structure that can be attached by narrowing a substrate. In a multilayer wiring board constituting a part of a wafer batch contact board used for collectively testing a plurality of semiconductor devices formed on a wafer, an outer peripheral pad formed in a peripheral area of the multilayer wiring board is provided. A guide that blocks and standardizes line width and line spacing , and plays a role of guiding and positioning when connecting a connector to the blocked outer peripheral pad adjacent to the blocked outer peripheral pad. A structure with a portion, and
The structure of the connector for connection connected to the blocked outer peripheral pad has an engaging portion that engages or fits with a guide portion formed on the multilayer wiring board, and narrows the multilayer wiring board. It has a structure with a clip structure that can be attached by
A connection structure characterized in that when the connector is connected to the multilayer wiring board, the guide portion and the engagement portion are engaged and connected. At least, and the multilayer wiring substrate wafer batch contact board according to claim 1, the inspection apparatus of a wafer batch contact board which comprises using a connector according to claim 2, wherein. At least, the wafer and batch contact board, wafer batch inspection apparatus characterized by comprising a connector according to claim 2, further comprising a wafer batch contact board multilayer wiring board according to claim 1, wherein.

Images