JP3867330B2 - Solid-state imaging device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device having a circuit that outputs three voltage levels (ternary values ) .
[0002]
[Prior art]
As a solid-state imaging device, for example, a pixel having a function of performing photoelectric conversion by incident light, accumulating signal charges obtained by photoelectric conversion, and modulating a channel current according to the accumulated charge amount, for example, a pixel MOS transistor An amplification type solid-state imaging device has been proposed.
[0003]
[Problems to be solved by the invention]
In this amplification type solid-state imaging device, it is desired to reduce the dark current as much as possible. There are two causes of dark current, one is the generation of hot carriers in the pixel MOS transistor, and the other is the electron / hole at the gate portion interface of the pixel MOS transistor, that is, the interface between the gate insulating film and the semiconductor surface. It is generation of a pair.
[0004]
In the amplification type solid-state imaging device, when the pixel MOS transistor is off, a minute current does not flow through the pixel MOS transistor, and hot carriers are not generated. Therefore, no dark current is generated due to the generation of hot carriers. However, during the charge accumulation period (so-called light receiving period), the pixel MOS transistor is in an off state, and in this off state, charges (electrons) cannot be injected into the surface of the gate portion of the pixel MOS transistor. A dark current is increased by generating pairs and accumulating holes in the sensor area.
[0005]
In order to reduce the dark current due to the generation of electron-hole pairs, during the charge accumulation period, a high voltage level is applied to the gate part with the source and drain at the same potential, and charges are injected into the gate part interface, in this example, electrons. However, it is considered to suppress the generation of electron / hole pairs at the interface of the gate portion.
However, when the source and drain are set to the same low voltage and a high voltage level is applied to the gate portion to inject electrons into the gate portion interface, the electrons are injected at the portion where the electric field is high at the source-gate boundary and the drain-gate boundary. Electrons are accelerated and hot carriers are generated, which causes dark current. That is, when an attempt is made to inject electrons in order to suppress the dark current generated from the gate portion interface, a dark current due to hot carriers is generated.
In order to avoid the causes of these two dark currents simultaneously, when electrons are injected into the gate interface, the voltage applied to the control electrode of the pixel is set so as to minimize the electric field at the source-gate boundary and the drain-gate boundary. It needs to be ternary.
[0006]
Incidentally, in order to output a ternary voltage level from the vertical scanning circuit, normally, four switch elements (that is, MOS transistors) at each output stage are required as shown in FIG.
[0007]
FIG. 8 shows an output stage of the vertical scanning circuit, and each output stage has four MOS transistors, ie, two p-channel MOS transistors (PMOS1 and PMOS2) and two n-channel MOS transistors (NMOS1 and NMOS2) as switching elements. Consists of.
The source electrodes of the p-channel MOS transistors PMOS1 and PMOS2 and the n-channel MOS transistors NMOS1 and NMOS2 are connected to power supplies V _H , V _M , and V _L that supply ternary voltages, the drain electrodes are connected to the outputs, and the gate electrodes Each pulse voltage is applied to.
[0008]
That is, a low-voltage level power supply V _L is connected to the source electrode of the first n-channel MOS transistor NMOS 1, and pulse voltages φL ^N [φL ^N _m−1 , φL ^N _m , φL ^N _{m + 1} ,. ‥] is applied, the power source V _M of the intermediate voltage level, both the source electrode and the first source electrode of the p-channel MOS transistor PMOS1 the second n-channel MOS transistor NMOS2 are connected, a pulse voltage φM to the gate electrode of the respective ^N [φM ^N _m−1 , φM ^N _m , φM ^N _{m + 1} ,...] And φM ^P [φM ^P _m−1 , φM ^P _m , φM ^P _{m + 1} ,. power V _H of high voltage level is connected to the source electrode of the p-channel MOS transistor PMOS 2, a pulse voltage .phi.H the gate electrode ^{P _{[φH P m-1, φH P}} m, φH P m + 1, ‥‥ ] is applied Each n-channel and p-channel MOS transistor Star NMOS 1, NMOS 2, PMOS1 and drain electrodes of PMOS2 the output terminal t _{[t m-1, t m,} t m + 1, ‥‥ ] is connected to. Vertical scanning pulses φV [φV _m−1 , φV _m , φV _{m + 1} ,...] Are output from the output terminals t ₁ [t _m−1 , t _m , t _{m + 1} ,.
[0009]
As an example of outputting ternary values by the operation of this vertical scanning circuit, the m-th output stage will be described.
When the pulse voltages φH ^P _m , φM ^P _m , φM ^N _m , and φL ^N _m are supplied to the gate electrodes of the MOS transistors PMOS1, PMOS2, NMOS1 and NMOS2 of the switch element at the timing shown in FIG. A ternary vertical scanning pulse φV _m is obtained from the end t _m .
[0010]
When the low voltage level value V _L is output to the vertical scanning pulse φV _m , only the MOS transistor NMOS1 connected to the pulse voltage φL ^N _m becomes conductive.
If the value V _M of the intermediate voltage level is outputted, a pulse voltage .phi.M ^P _m and .phi.M ^N MOS transistors PMOS1 and NMOS2 which are respectively connected to the _m becomes conductive.
When the high voltage level value V _H is output, the MOS transistor PMOS 2 connected to the pulse voltage φH ^P _m becomes conductive.
[0011]
Thus, in the case of a vertical scanning circuit that outputs ternary values, it has a configuration in which four MOS transistors as switch elements are used for each output stage, and there is a disadvantage that the number of elements is large. In order to control the stage, four pulses of φH ^P , φM ^P , φM ^N , and φL ^N are required for one output stage, and the circuit scale for controlling the output stage is increased.
[0012]
The ternary drive pulse is also required when driving the vertical transfer register of the CCD solid-state image sensor. That is, when charge is transferred through the vertical transfer register, a repetitive pulse of a low voltage level and an intermediate voltage level is applied to the transfer electrode, and when the signal charge is read from the light receiving unit to the vertical transfer register, the transfer electrode has a high voltage level. Applied.
Accordingly, in this case, the circuit configuration for outputting ternary values uses four switch elements as described above.
[0013]
The present invention has been made in view of the point of the above, for example, in the scanning circuit or a read-transfer driving circuit of a solid-state imaging device, the solid-state imaging equipment that is to be reduced the number of switching elements constituting the output stage for outputting the three-value It is to provide.
[0014]
[Means for Solving the Problems]
The solid-state image pickup device according to the present invention is a solid-state image pickup device including a plurality of pixels arranged and an output stage circuit for outputting three voltage levels in a vertical scanning circuit or horizontal scanning circuit, or a readout / transfer driving circuit. In the output stage circuit, the first pulse voltage is supplied to the control electrode, the first main electrode is connected to a low-level power supply, and the second pulse voltage is applied to the control electrode. An n-channel MOS transistor having a first main electrode connected to an intermediate level power supply, a third pulse voltage supplied to the control electrode, and a first main electrode connected to a high level power supply Each of the three MOS transistors is connected to a common output terminal, and each pixel level is output by a ternary voltage level output. Characterized in that it comprises as being controlled in at least three operating states.
The solid-state imaging device according to the present invention includes a plurality of pixels arranged and an output stage circuit that outputs a ternary voltage level in a vertical scanning circuit, a horizontal scanning circuit, or a readout / transfer driving circuit. An output stage circuit comprising: an n-channel MOS transistor having a first pulse voltage supplied to a control electrode and a first main electrode connected to a low level power supply; and a second pulse applied to a control electrode. A p-channel MOS transistor is supplied with a voltage, and the first main electrode is connected to an intermediate level power supply, a third pulse voltage is supplied to the control electrode, and the first main electrode is connected to a high level power supply. P-channel MOS transistors, and the second main electrodes of the three MOS transistors are connected to a common output terminal. Pixel is characterized by comprising as is controlled to at least three operating states.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
In the solid-state imaging device according to the present invention, a circuit that outputs three or more signals having mutually different voltage levels is configured by the same number of switch elements as the number of voltage levels.
[0016]
In the solid-state imaging device according to the present invention, the above circuit outputs three signals having different voltage levels, and is configured by three switch elements .
[0017]
The solid-state imaging device according to the present invention is connected to switching element into three or more power which the first main electrode gives a different signal voltage levels to each other, in so that the second main electrode connected to the output node Constitute.
[0018]
In the solid-state imaging device according to the present invention , the switch element is configured by two n-channel MOS transistors and one p-channel MOS transistor, or is configured by one n-channel MOS transistor and two p-channel MOS transistors.
[0019]
A method for manufacturing a solid-state imaging device according to the present invention includes a circuit configured to output three or more signals having mutually different voltage levels, and includes a circuit composed of the same number of switch elements as the number of voltage levels. In this case, a potential lower than the boundary potential is output at the boundary potential calculated by the ratio between the mutual conductance of the n-channel MOS transistor constituting the switch element and the mutual conductance of the p-channel MOS transistor constituting the switch element . time constitutes a switching element in the n-channel MOS transistor, when causing the output higher than the boundary potential potential is characterized by forming the switch element in the p-channel MOS transistor.
[0020]
Embodiments of the present invention will be described below with reference to the drawings.
[0021]
FIG. 1 shows an embodiment applied to an amplification type solid-state imaging device which is one of XY address type solid-state imaging devices.
In this amplification type solid-state imaging device 1, a plurality of pixel transistors, for example, pixel MOS transistors 2 constituting a unit pixel (cell) are arranged in a matrix, and a first main electrode, that is, a drain electrode of each pixel MOS transistor 2 is provided. are connected in common to a power source V _D, the pixel MOS transistor 2 of the control electrodes of each row, i.e. the scan pulse .phi.V gate electrode from the vertical scanning circuit 3 _{[‥‥, φV m + 1, φV} m, ‥‥ ] is output The second main electrode, ie, the source electrode of the pixel MOS transistor 2 for each column is connected to the vertical signal line 5 that outputs the pixel signal to the horizontal scanning circuit 6.
[0022]
The horizontal scanning circuit 6 includes an operation switch (for example, a MOS switch) 7, a load capacitance element 8, a horizontal switch (for example, a MOS switch) 9, a horizontal signal line 10, and a horizontal shift register 11. That is, a load capacitor element 8 that holds a pixel signal is connected to the vertical signal line 5 via an operation switch 7 controlled by an operation pulse φ _OP , and the horizontal line between the load capacitor element 8 and the horizontal signal line 10 is connected. A horizontal switch 9 controlled by horizontal scanning pulses φH [..., ΦH _n , φH _{n + 1} ,.
[0023]
The pixel signal is held in the load capacitor element 8 via the operation switch 7 during the horizontal blanking period, and the pixel signal held in the load capacitor element 8 is the horizontal scanning pulse φH from the horizontal shift register during the horizontal video period. The horizontal switches 9 controlled by [..., ΦH _n , φH _{n + 1} ,...] Are sequentially turned on and output to the horizontal signal line 10.
[0024]
An end of the horizontal signal line 10 is connected to a horizontal output circuit 15 including an operational amplifier, for example, a differential amplifier 12, a detection capacitor element 13 and a reset switch (for example, reset MOS switch) 14. The sequentially output pixel signals are converted into voltages and output from the output terminal t _out of the imaging device 1.
[0025]
In the horizontal output circuit 15, the horizontal signal line 10 is connected to the inverting input terminal of the differential amplifier 12, a predetermined bias voltage V _B is applied to the non-inverting input terminal, and in parallel to the differential amplifier 12, that is, differential. A detection capacitor 13 and a reset switch 14 to which a reset pulse φ _R is applied are connected between the inverting input terminal and the output terminal of the amplifier 12.
[0026]
FIG. 3A is a plan view of pixel MOS transistors arranged in a matrix, and FIG. 3B shows an example of a semiconductor structure of a unit pixel (that is, pixel MOS transistor 2).
In the pixel MOS transistor 2, a second conductivity type, for example, an n-type semiconductor region 22 and a p-type semiconductor region 23, which serve as an overflow barrier region, are sequentially formed on a first conductivity type, for example, a p-type silicon semiconductor substrate 21. A so-called sensor region 24 made of a p-type semiconductor region having a higher concentration is formed on the surface of the type semiconductor region 23. Further, a ring-shaped gate electrode 26 capable of transmitting light is formed on the sensor region 24 through a gate insulating film 25 made of, for example, SiO _2, and the regions corresponding to the inside and the outside of the ring-shaped gate electrode 26 are formed. An n-type source region 27 and a drain region 28 are formed, respectively, and a signal charge accumulated under the gate in the p-type semiconductor region 23 immediately below the drain region 28 is prevented from leaking to adjacent pixels. An n-type channel stop region 29 is formed.
[0027]
In this pixel MOS transistor 2, as shown in FIG. 3B, the light L transmitted through the ring-shaped gate electrode 26 undergoes photoelectric conversion in the silicon semiconductor to generate an electron / hole pair, and one of these charges In this example, the holes h are accumulated as signal charges in the potential well formed in the p-type sensor region 24 under the gate electrode 26. This charge (hole) h controls the channel current (that is, the channel current flowing through the channel on the surface of the sensor region 24 [so-called source-drain current)) during the read operation, and the amount of change in the channel current is the signal output. Become.
[0028]
As an example, the above-described amplification type solid-state imaging device 1 applies a high level voltage to the control electrode of the pixel MOS transistor 2 in the selected state, and applies an intermediate level voltage in the readout period in the non-selected state, thereby resetting the pixel. It is required to apply a low level voltage during the period. In order to reduce the dark current, it is required to apply a high level voltage to the control electrode while keeping the source and drain of the pixel MOS transistor 2 at the same potential during the charge accumulation period.
[0029]
As shown in the driving timing chart of FIG. 2, in the figure, for example, looking at the horizontal blanking period H _BLK left pixel from m-1 th row of the pixel MOS transistor 2 in the first half of the horizontal blanking period H _BLK In order to output a signal and hold the pixel signal in the load capacitor element 8, that is, to perform a reading operation, the vertical scanning pulse φV _m-1 in the (m-1) th row is set to a high level and applied to the control electrode of the operation switch 7 When the operation pulse φ _OP is raised, the pixel signal is read out to the load capacitor 8 (selective reading). Then, while in the second half of the horizontal blanking period H _BLK, and a vertical scanning pulse .phi.V _m-1 of the m-1 th row in order to reset the signal charges read pixel MOS transistor 2 to a high level, the substrate pulse φ _SUB is raised, and signal charges accumulated in the pixel MOS transistor 2 are discharged to the substrate (so-called selective reset).
[0030]
On the other hand, in the first half of the same horizontal blanking period H _BLK , the control electrodes of the pixel MOS transistors (so-called non-selected pixels) 2 that do not perform reading other than the (m−1) th row are the vertical scanning pulses φV _m and φV in FIG. _As indicated by _{m + 1} , an intermediate level is set so that no signal is read out (non-selective reading).
Further, in the latter half of the same horizontal blanking period, the control electrodes of the pixel MOS transistors 2 other than the (m−1) th row that are not reset are as indicated by the vertical scanning pulses φV _m and φV _{m + 1} in FIG. The signal charge accumulated in the pixel MOS transistor 2 is prevented from being reset by making it low (non-selective reset).
During the horizontal video period, the pixel signal held in the load capacitor element 8 is output to the horizontal signal line 10 by the horizontal switch 9 controlled by the horizontal scanning pulse φH [..., ΦH _n , φH _{n + 1} ,. The signal OUT is output from the horizontal output circuit 15.
[0031]
Next, an embodiment of the circuit configuration of the output stage of the scanning circuit when the output of the vertical scanning circuit or the horizontal scanning circuit is ternary in the above-described XY address type solid-state imaging device will be described. .
[0032]
FIG. 4 shows a first embodiment of the circuit configuration of each output stage of the vertical scanning circuit 3, for example.
Each output stage of the vertical scanning circuit 3 is supplied with a pulse voltage φL ^N [φL ^N _m−1 , φL ^N _m , φL ^N _{m + 1} ] to the control electrode (that is, the gate electrode), and the first main electrode ( That is, the first n-channel MOS transistor NMOS1 whose source electrode is connected to the low-level power supply V _L , and the pulse voltage φM ^N [φM ^N _m−1 , φM ^N _m , φM ^N to the control electrode (that is, the gate electrode)]. _{m + 1]} is supplied, a second n-channel MOS transistor NMOS2 the first main electrode (i.e., source electrode) is connected to the intermediate-level power supply V _M, the pulse voltage φH to the control electrode (or gate electrode) ^P [φH ^P _m−1 , φH ^P _m , φH ^P _{m + 1} ] is supplied, and the first main electrode (that is, the source electrode) is connected to the p-channel MOS transistor PMOS 1 connected to the high-level power supply V _H. It consists of three switch elements. Each MOS transistor NMOS 1, NMOS 2 and PMOS1 of each of the second main electrode (i.e., drain electrode) is connected common output terminal t _{[t m-1, t m,} t m + 1 ] to.
[0033]
Next, the operation of the embodiment of FIG. 4 will be described with reference to the timing chart of FIG.
Take the vertical scanning pulse φV _m as an example. When a low-level value V _L is output to the vertical scanning pulse φV _m , the first n-channel MOS transistor NMOS1 connected to the power source V _L when the pulse voltage φL ^N is at a high level is turned on. a second n-channel MOS transistor NMOS2 pulse voltage .phi.M ^H p-channel MOS transistor connected to a power supply V _H in a high-level PMOS1 and a non-conductive state connected to the power source V _M at a pulse voltage .phi.M ⁿ is low Become.
[0034]
If the value V _M of the intermediate level to a vertical scanning pulse .phi.V _m is output, the first n-channel MOS transistor NMOS1 pulse voltage .phi.L ^N is connected to the power source V _L at the low level becomes nonconductive, the pulse voltage .phi.M ⁿ becomes the second n-channel MOS transistor NMOS2 conduction state of being connected to a power source V _M at a high level, PMOS1 pulse voltage .phi.H ^P are connected at a high level to the power supply V _H becomes nonconductive.
[0035]
When a high level value V _H is output to the vertical scanning pulse φV _m , the first n-channel MOS transistor NMOS1 connected to the power source V _L with the pulse voltage φL ^N at a low level and the pulse voltage φM ^N are low. The second n-channel MOS transistor NMOS2 connected to the power supply V _L at the level becomes non-conductive, and the p-channel MOS transistor PMOS1 connected to the power supply V _H at the low level of the pulse voltage φH ^N becomes conductive.
[0036]
According to the first embodiment, only three switch elements are required in the output stage when the output of the vertical scanning circuit is ternary, and only three types of pulse voltages are required to enter the output stage. For this reason, the output stage that takes the most area in the vertical scanning circuit is reduced, and the scale of the logic circuit in the scanning circuit that generates pulses necessary for the operation of the output stage is reduced, contributing to the downsizing of the amplification type solid-state imaging device. To do.
[0037]
FIG. 6 shows a second embodiment.
In the second embodiment, and it is different from the first embodiment in FIG. 4 described above, a switching element in which the first main electrode to an intermediate level power source V _M (i.e. the source electrode) is connected n-channel MOS A p-channel MOS transistor PMOS2 is used instead of the transistor NMOS2. Other configurations are the same as those in FIG.
[0038]
A timing chart of the second embodiment is shown in FIG. Here, the pulse voltage .phi.M ^P _m for controlling the p-channel MOS transistor PMOS2 a source electrode connected to the intermediate-level power supply V _M is the pulse voltage .phi.M ^N _m that controls the n-channel MOS transistor NMOS2 the first embodiment It is reversed against. Other pulse voltages φH ^P _m and φL ^N _m are the same as those in the first embodiment.
[0039]
The basic operation is the same as in the first embodiment. When outputting the low-level value V _L in the vertical scanning pulse .phi.V _m is to conduct the n-channel MOS transistor NMOS1 connected to the power supply V _L, when outputting V _M of the intermediate level, the power source V _M conducting a second p-channel MOS transistor PMOS2 connected, so the outputs the value V _H of the high-level, to conduct the first p-channel MOS transistor PMOS1 connected to the power supply V _H, the respective switches Pulse voltages φL ^N , φM ^P , and φH ^P are applied to the control electrodes of the elements, that is, the n-channel MOS transistor NMOS 1 and the first and second p-channel MOS transistors PMOS 1 and PMOS 2.
[0040]
In the second embodiment, similarly to the first embodiment, only three switch elements are required in the output stage when the output of the scanning circuit is ternary, and there are three types of pulse voltages entering the output stage. It's okay. Accordingly, the area occupied by the output stage in the scanning circuit is reduced, and the scale of the logic circuit in the scanning circuit that generates the pulse voltage necessary for the operation of the output stage is reduced, and the solid-state imaging device can be miniaturized.
[0041]
The first embodiment of FIG. 4 is advantageous when the output voltage V _M of the intermediate level is a low level closer than approximately mid-height and low levels, the second embodiment of FIG. 6, on the contrary output voltage V _M of the intermediate level is advantageous when a high level closer.
[0042]
The reason is due to the on-resistance of the switch element that conducts when outputting the intermediate level. If the output voltage of the intermediate level is close to the low level at the middle of the high level and the low level, the n-channel MOS transistor is better. If the on-resistance is low and the level is higher, the p-channel MOS transistor has a lower on-resistance, and the size (channel width) of the switch element that outputs an intermediate level can be minimized under the above conditions.
[0043]
In other words, for example, when the value is three or more, the mutual conductance of the n-channel MOS transistor constituting the switch element and the p-channel MOS transistor of the switch element corresponding to the output level other than the high level and the low level are set. When a low potential is output with a boundary potential calculated by the transconductance ratio as a boundary, a switch element that outputs an intermediate level is configured by an n-channel MOS transistor, and a high potential is output with the boundary potential as a boundary. In some cases, the switch element that outputs the intermediate level is preferably composed of a p-channel MOS transistor.
[0044]
In the above example, the output stage of the scanning circuit that outputs ternary voltage levels has been described. However, when a voltage level of three or more values is output, it may be configured with the same number of switch elements as the number of levels. it can.
[0045]
In the CCD solid-state imaging device, the three values given to the vertical transfer register, that is, the low level and the intermediate level at the time of charge transfer in the vertical transfer register, and the signal charge from the light receiving unit are read out to the vertical transfer register. The above-described present invention can also be applied to a circuit configuration of an output stage that outputs a ternary driving pulse with a high level.
[0046]
【The invention's effect】
According to the solid-state imaging device according to the present invention, the circuit that outputs the three voltage levels is composed of the same number of MOS transistors as the number of levels, so that, for example, the scanning circuit of the solid-state imaging device or the read / transfer drive Ru can reduce the MOS transistor of the output stage of the circuit. Therefore, the area occupied by the output stage can be reduced, and at the same time, the scale of the logic circuit for generating a pulse for controlling the MOS transistor can be reduced. As a result, the size of the solid-state imaging device can be reduced.
[0047]
When outputting a ternary voltage level, a total of three MOS transistors including two n-channel MOS transistors and one p-channel MOS transistor, or a total of three MOS transistors including one n-channel MOS transistor and two p-channel MOS transistors. A circuit can be formed using transistors.
[0048]
By making the MOS transistor corresponding to the intermediate level a p-channel MOS transistor or an n-channel MOS transistor, the intermediate output level can be made closer to a high voltage level or a low voltage level.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing an example of a solid-state imaging device according to the present invention.
FIG. 2 is a drive timing chart and an output waveform diagram of the solid-state imaging device according to the present invention.
FIG. 3A is a schematic plan view of a pixel of a solid-state imaging device according to the present invention. B is a cross-sectional view taken along line XX ′ in FIG. 3A.
FIG. 4 is a circuit configuration diagram showing an example of an output stage that outputs ternary voltage levels according to the present invention.
FIG. 5 is a timing chart of FIG. 4;
FIG. 6 is a circuit configuration diagram showing another example of an output stage that outputs ternary voltage levels according to the present invention.
FIG. 7 is a timing chart of FIG.
FIG. 8 is a circuit configuration diagram of an output stage that outputs ternary voltage levels according to a conventional example.
FIG. 9 is a timing chart of FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Amplification type solid-state imaging device, 2 pixel MOS transistor, 3 vertical scanning circuit, 4 vertical selection line, 5 vertical signal line, 6 horizontal scanning circuit, 7 operation switch, 8 load capacitance element, 9 horizontal switch, 10 horizontal signal line, 11 horizontal shift register, 15 horizontal output circuit, PMOS1, PMOS2 p-channel MOS transistor (switch element), NMOS1, NMOS2 n-channel MOS transistor (switch element)

Claims (4)

A solid-state imaging device comprising a plurality of pixels arranged and an output stage circuit that outputs ternary voltage levels in a vertical scanning circuit or horizontal scanning circuit, or a readout / transfer driving circuit,
The circuit of the output stage is
An n-channel MOS transistor in which a first pulse voltage is supplied to the control electrode and the first main electrode is connected to a low-level power supply;
An n-channel MOS transistor in which a second pulse voltage is supplied to the control electrode, and the first main electrode is connected to an intermediate-level power supply;
A third pulse voltage is supplied to the control electrode, and the first main electrode has a p-channel MOS transistor connected to a high-level power source,
A second main electrode of each of the three MOS transistors is connected to a common output terminal;
The solid-state imaging device according to claim 1, wherein the pixel is controlled to at least three operation states by an output of each of the three voltage levels . As the intermediate level voltage output from the output terminal, a voltage close to a low level is output with the middle between the high level and the low level as a boundary.
The solid-state imaging device according to claim 1. A solid-state imaging device comprising a plurality of pixels arranged and an output stage circuit that outputs ternary voltage levels in a vertical scanning circuit or horizontal scanning circuit, or a readout / transfer driving circuit,
The circuit of the output stage is
An n-channel MOS transistor in which a first pulse voltage is supplied to the control electrode and the first main electrode is connected to a low-level power supply;
A p-channel MOS transistor in which a second pulse voltage is supplied to the control electrode and the first main electrode is connected to an intermediate level power supply;
A third pulse voltage is supplied to the control electrode, and the first main electrode has a p-channel MOS transistor connected to a high-level power source,
A second main electrode of each of the three MOS transistors is connected to a common output terminal;
The solid-state imaging device according to claim 1, wherein the pixel is controlled to at least three operation states by an output of each of the three voltage levels . As a middle level voltage output from the output terminal, a voltage close to a high level is output at the middle between the high level and the low level.
The solid-state imaging device according to claim 3.

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