JP3722307B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for realizing a memory macro in which a memory circuit and a logic circuit are integrated on the same semiconductor chip and a memory macro and a number of data input / output lines can be easily changed at high speed. is there.
[0002]
[Prior art]
In recent years, high integration of LSIs has progressed, and it has become possible to integrate a large-capacity memory and a large-scale logic circuit or arithmetic circuit on a semiconductor chip of about 1 cm square. In such a chip, by setting the number of data input / output lines (hereinafter referred to as I / O lines) of the memory to several hundred or more, the data transfer speed between the memory and the logic circuit or the arithmetic circuit is 1 Gbyte. / Sec or more and can be very fast. For this reason, expectations are gathered for image processing applications that require high-speed data transfer to and from the memory.
[0003]
As a prior art applicable to the above-mentioned use, for example, it was described in Toshio Sunaga, et al., “DRAM Macros for ASIC Chips,” IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL. 30, NO. 9, SEPTEMBER 1995. There are examples of memory macros. According to the prior art, the capacity of one memory macro is 256 K bits to 1 M bits, and 8 to 16 I / O lines are output therefrom.
[0004]
[Problems to be solved by the invention]
The present inventors have examined the case where an LSI for image processing is configured using the memory macro. For example, if the capacity of the memory macro is 256K bits, the number of I / O lines is 8, and the number of I / O lines necessary for the LSI is 512, 64 memory macros are required. The capacity at this time is 16M bits.
[0005]
When processing two-dimensional data in the field of image processing, for example, when restoring blurred images, or when recognizing characters or specific patterns, the above memory capacity is not required, but high speed is achieved. Required. In this case, if only the speed is taken into consideration, a large number of conventional memory macros may be arranged and operated in parallel. However, this increases the memory capacity and increases the chip size.
[0006]
On the other hand, when processing three-dimensional data, it is necessary to process a large amount of data at high speed. This case can be dealt with by operating a large number of memory macros in parallel as described above. However, more I / O lines may be required or more capacity may be required depending on the difference in use such as home use or industrial use and the type of data.
[0007]
As described above, even in the same image processing field, the required data transfer speed and memory capacity vary depending on the application of the chip and the type of data, so the conventional memory macro needs to be redesigned each time. There is. In addition, since all the circuits necessary for the operation are contained in the memory macro, there is a problem that the circuit overhead increases when a large number of macros are arranged.
[0008]
As described above, in the conventional memory macro, since the number of I / O lines is increased by increasing the number of memory macros, there is a problem that the number of I / O lines and the memory capacity cannot be freely set. Further, since all the circuits necessary for the operation are contained in the memory macro, there is a problem that the circuit overhead increases if a large number of memory macros are arranged.
[0009]
The problem to be solved by the present invention is to freely change the capacity of the memory macro from a small capacity to a large capacity. Another problem to be solved by the present invention is to increase the data transfer speed between the memory macro and the logic circuit module. Furthermore, another problem to be solved by the present invention is to realize a memory macro with less circuit overhead in the memory macro. Furthermore, another problem to be solved by the present invention is to realize a memory macro suitable for ASIC (Application Specific Integrated Circuit) design.
[0010]
The above and other problems and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0011]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0012]
That is, a large number of I / O lines (global bit lines (GBL)) extending in the bit line direction are arranged in the memory cell array of the bank module (BANK: first module). The memory macro (MMACRO) is configured by a combination of functional modules such as an amplifier module (AMP: second module), a bank module (BANK), and a power supply module (PS: third module). Use multiple bank modules. The modules are connected by simply arranging them adjacent to each other. Furthermore, a circuit is provided in the amplifier module so that they can be activated and deactivated in byte units. One of the plurality of bank modules is a ROM module.
[0013]
The word line (W) and column select line (YSi) of the memory macro are extended in the same direction. A word driver (WD) and a column decoder (YD) on one side of the memory array are arranged. Sense amplifiers (SA) are arranged on both sides of the memory array.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
The memory macro according to the embodiment of the present invention will be described in order according to the items.
[0015]
1. Memory macro configuration and memory macro application examples
FIG. 1 shows a configuration of the memory macro MMACRO and an application example of the memory macro MMACRO to an image processing LSI. In the semiconductor integrated circuit SIC shown in FIG. 1, a logic circuit block LOGIC and a memory macro MMACRO are formed on a single crystal silicon semiconductor substrate and sealed with a resin (sealed in a plastic package). The arrangement and wiring of modules and circuits shown in FIG. 1 generally correspond to the arrangement (layout) on the semiconductor chip.
[0016]
1.1 Memory macro configuration
The feature of the memory macro MMACRO is that it is composed of a combination of modules of different types. The memory macro MMACRO is composed of three types of modules: a bank module BANK (BANK-0 to BANK-n), an amplifier module AMP, and a power supply module PS.
[0017]
The bank module BANK includes a plurality of sub memory cell arrays SUBARY (SUBARY-00 to SUBARY-i7), a bank control circuit BNKCNT-1, and a bank control circuit BNKCNT-2.
[0018]
The sub memory cell array SUBARY includes a plurality of pairs of bit lines B and / B, a plurality of word lines W (only one is shown in FIG. 1 because of the size of the drawing), and a plurality of memory cells. (Indicated by a circle in FIG. 1), a bit line precharge circuit PS for preliminarily setting the potential of the bit line to a predetermined level before reading the memory cell, a sense amplifier SA for amplifying a signal from the memory cell, A Y selection circuit (Y switch Y-SW) that selects one of the paired bit lines B and / B, and a global bit line GBL that connects the selected bit lines B and / B to the amplifier module AMP, / Consists of GBL. The sub memory cell array SUBARY is an I / O line division unit in the bank module BANK. Note that what is composed of a plurality of pairs of bit lines B and / B, a plurality of word lines W, and a plurality of memory cells is usually called a memory cell array, and is used properly in the present application.
[0019]
The bank control circuit BNKCNT-1 includes an X decoder (row decoder) XD for selecting the word line W, a Y decoder (column decoder) YD for selecting the bit lines B and / B, and the like. The bank control circuit BNKCNT-1 automatically generates signals necessary for a series of memory cell read operations such as bit line precharge, word line selection, and sense amplifier activation in response to a bank address and control signal described later. One word line W is selected by the X decoder XD, and (n × 8 × i) pairs intersecting with it (FIG. 1 shows the case of n = 2 due to the size of the drawing. In the embodiment, n = 8.) Of the bit lines B and / B, (8 × i) pairs are further selected by the output signal YSi of the Y decoder YD. The selected bit lines B and / B exchange data with the amplifier module AMP through the global bit lines GBL and / GBL arranged in parallel with the bit lines B and / B.
[0020]
The bank control circuit BNKCNT-2 includes a sensor group that detects that the sense amplifier control signal has reached a certain level.
[0021]
The amplifier module AMP includes a main control circuit MAINCNT that supplies a control signal, an address signal, and the like to the bank module BANK in synchronization with the clock signal, and a byte control circuit that controls reading and writing of data to the bank module group (BANK-0BANK0n). Composed of BYTCNT. The (8 × i) main data input / output lines DQ (DQ00,..., DQ07,..., DQi7,..., DQi7) from outside the memory macro MMACRO are input to the memory cells through this. Here, the byte control signal BEi is a signal for opening and closing the data input / output line DQ in units of bytes.
[0022]
The power supply module PS includes a VCH generation circuit VCHG that generates a word line voltage VCH (> power supply voltage VCC) required for the word line drive circuit WD supplied to the bank module BANK, and a voltage HVC (power supply voltage) required for bit line precharging. Various voltages such as a bit line precharge voltage generation circuit HVCG that generates VCC / 2), an in-array substrate voltage generation circuit VBBG that generates an in-array substrate voltage (back bias voltage) VBB (<power supply voltage VSS (ground potential)) It is a module that generates If the operating voltage is desired to be lower than the external voltage in order to reduce current consumption and improve device reliability, a step-down circuit may be incorporated in the power supply module PS.
[0023]
Control signals and address signals necessary for the bank module BANK are common to the bank modules BANK, and are placed in the form of a bus in the bit line direction on the lower side of the bank module BANK. Therefore, these control signals and address signals can also be included in the bank module BANK. That is, each bank module BANK can have the same cell structure including the control signal and the address signal.
[0024]
However, the row system bank address Ri and the column system bank address Ci are signals unique to each bank module BANK, and therefore, are required by the number of the bank modules BANK. Therefore, in order to make each bank module BANK the same cell including the wiring of the row bank address Ri and the column system bank address Ci, a simple method is to wire the row bank address Ri and the column bank address Ci. Are input from the lower side or the upper side of the memory macro MMACRO in FIG.
[0025]
On the other hand, in order to facilitate the interface with the logic circuit block LOGIC, all signal lines of the control signal, address signal, and data input / output line DQ to the memory macro MMACRO are connected to one side of the cell (left side in FIG. 1). It is better to concentrate on. Therefore, in order to input the wiring of the row bank address Ri and the column bank address Ci from the left side of the memory macro MMACRO in FIG. 1, the wiring is laid out as shown in FIG. When there is no need to use the same cell including the wiring, the wiring is laid out as shown in FIG.
[0026]
Further, the cell heights of the bank module BANK, the amplifier module AMP, and the power supply module PS are the same, and the global bit lines GBL, / GBL, power supply lines, and the like are arranged at the same pitch.
[0027]
As a result, the bank modules BANK are arranged in the required number in the bit line direction according to the capacity required by the system, and the modules of the above-mentioned amplifier module AMP and power supply module PS are arranged on the left and right sides of the desired memory. A macro module can be completed.
[0028]
In the bank module BANK according to the embodiment of the present invention, 256 word lines (8 X addresses), (8 × 8 × i) pairs of bit lines intersect one word line, and 1/8 ( (3 Y addresses) are selected, and (8 × i) pairs of global bit lines are input and output. For example, if i = 16, one bank module BANK inputs and outputs data with a capacity of 256K (K = 1024) bits and a 128-bit width. That is, a memory macro module having a size of 256K bits and a variable capacity can be obtained.
[0029]
For example, a 1M (M = 1048576) bit memory macro is obtained with four bank modules, and a 2M bit memory macro is obtained with eight bank modules. That is, the capacity of the memory macro having a capacity necessary for the application can be obtained instead of increasing the capacity by four times as in the case of 256K bits, 1M bits, 4M bits, 16M bits, etc. of the conventional general purpose dynamic RAM (DRAM).
[0030]
1.2 Memory macro operation modes
The relationship between the external signal of the memory macro MMACRO and the operation mode is shown in FIG. In the memory macro MMACRO, data input / output, address input, and control signal input are performed in synchronization with the clock signal CLK. Here, Ai is an address signal and includes an X address AXij input to the X decoder XD and a Y address AYi input to the Y decoder YD. Unlike conventional general-purpose DRAMs, the address signal is not multiplexed in the X and Y systems.
[0031]
The row bank address Ri and the column bank address Ci for selecting the bank module BANK are signals specific to the bank module BANK without being decoded because the number of bank modules is variable. The row-related and column-related command signals in the same bank module BANK are distinguished by the row-related bank address Ri and the column-related bank address Ci, respectively. There are four control signals: CR, CC, RW, and AC. DQij is an input / output I / O signal. The byte control signal BEi is a signal for independently controlling the data input / output line for each byte, and by this, the amount of data read / written in parallel can be increased or decreased in units of bytes in the range from 1 byte to the maximum i bytes.
[0032]
The bank module BANK is activated (Bank Active) and closed (Bank Close) by fetching CR, AC and the address signal Ai at the rising edge of the clock signal CLK. Active when CR = “H” (High level) and AC = “H”, and closed when CR = “H” and AC = “L” (Low level). At this time, the address signal Ai to be captured is selected only for the row system, the bank module BANK is selected by the row system bank address Ri, and the word line W is selected by the address signal Ai. S0 in FIG. 2 indicates the closed state of the bank module BANK. S1 indicates the active state of the bank module BANK. S2 indicates a read or write state.
[0033]
Note that LA2 shown in FIG. 2 indicates the number of clocks to which a read or write command can be input from the activation command input of the bank module BANK. LA indicates the number of clocks to which a read or write command can be input after changing the X address in the activated same bank module BANK. LR indicates the number of clocks that can be closed command input of the bank module BANK from the read or write command input.
[0034]
The relationship between the column control signal and the operation mode is shown in the lower part of FIG. This takes in CC, BEi, RW and the column address signal (the rest of the address signal Ai and the column bank address Ci) at the rising edge of the clock signal CLK, and controls read / write. In the present embodiment, the number of clocks from when a read command is received until data is output, that is, the latency (Read latency) is 2, and the latency from when a write command is received until input of write data is 1 (Write latency). is there. As a result, the column-related control signal can be input non-waiting without going through the Nop state when reading continuously, writing continuously, or moving from writing to reading. There is a need to. Note that the above-mentioned latency is not optimal and can be appropriately changed according to the system configuration.
[0035]
1.3 Sense amplifier and bit line precharge circuit
FIG. 3 shows a circuit example of the sense amplifier SA and the precharge circuit PC corresponding to a pair of bit lines of the bank module BANK. Q1, Q2, Q3, Q4, Q7, Q8, Q9 and Q10 are N-channel MOS (N-MOS) transistors. Q5 and Q6 are P-channel MOS (P-MOS) transistors. In this example, a dynamic memory cell composed of one transistor (Q1) and one capacitor (MC) is used as the memory cell. Along with this, a bit line precharge circuit PC and a CMOS cross-coupled dynamic sense amplifier SA are used. The bit line precharge circuit PC precharges the bit lines B and / B with the voltage HVC when the bit line precharge signal FPC becomes high level. The CMOS cross-coupled dynamic sense amplifier SA operates when the P-channel sense amplifier common drive line CSP is at a high level and the N-channel sense amplifier common drive line CSN is at a low level. The read / write operation is the same as that of a normal general-purpose DRAM.
[0036]
1.4 Bank control circuit
FIG. 4 shows operation waveforms of the bank control circuit BNKCNT-1 of the embodiment shown in FIG. The bank control circuit BNKCNT-1 receives the row bank address Ri and the control signals CR and AC and receives signals necessary for a series of memory cell read operations such as bit line precharge, word line selection, and sense amplifier activation. It happens automatically. That is, control is performed in an event-driven type. The operation will be described below.
[0037]
First, consider a case where the bank module BANK with CR = "H", AC = "L", and Ri = "H" is closed. When the clock signal CLK rises with CR = "H" and AC = "L", the bank closing flag DCS rises within the main control circuit MAINCNT. The bank closing flag DCS is input to each bank module BANK. At this time, the row bank selection signal iRi rises in the bank module BANK with the row bank address Ri = "H". Since the logical product of the row bank selection signal iRi and the bank closing flag DCS is input to the set terminal S of the set / reset flip-flop RS-1, the bank module BANK having the row bank address Ri = "H" The output STi of the set / reset flip-flop RS-1 becomes “H”.
[0038]
On the other hand, since the result of the logical product is input to the reset terminal of another set / reset flip-flop RS-2 through the logical sum circuit, its output WLPi becomes "L". When WLPi becomes "L", the output of the X decoder XD in the bank control circuit BNKCNT-1 and the gate signal YG of the Y decoder YD become "L", then the word driver WD output becomes "L" and the memory cell Is disconnected from bit lines B and / B.
[0039]
Next, the N channel sense amplifier activation signal FSA becomes "L", the P channel sense amplifier activation signal FSAB becomes "H", and the sense amplifier SA stops operating. Here, the dummy word line DWL is a delay element having the same delay time as the word line W, so that the sense amplifier SA can be stopped after the level of the word line W becomes sufficiently low. This is to prevent the signal level of the bit lines B and / B from being lowered due to the stop of the sense amplifier SA and the level of rewriting to the memory cell from being lowered.
[0040]
Subsequently, the level sense circuit provided in the bank control circuit BNKCNT-2 above the bank module BANK detects “L” of the N-channel sense amplifier activation signal FSA, and the output RE becomes “L”. This signal is input to the precharge signal generation circuit XPC in the bank control circuit BNKCNT-1 below the bank module BANK, and the output bit line precharge signal FPC becomes “H”. The bit line precharge signal FPC is input to a precharge circuit PC provided on the bit lines B and / B, and the bit lines B and / B are in a precharge state. The series of states so far is named S0.
[0041]
Next, consider a case where the state S0 shifts to activation of the bank module BANK with CR = "H", AC = "H", and Ri = "H". When the clock signal CLK rises with CR = "H" and AC = "H", the bank activation flag DCA rises in the main control circuit MAINCNT. The bank activation flag DCA is input to each bank module BANK. At this time, the row bank selection signal iRi rises in the bank module BANK with the row bank address Ri = "H". Since the logical product of the row bank selection signal iRi and the bank activation flag DCA is input to the reset terminal R of the set / reset flip-flop RS-1, the bank module BANK having the row bank address Ri = "H" The output STi of the set / reset flip-flop RS-1 becomes "L".
[0042]
The logical product of the row-related bank selection signal iRi and the bank activation flag DCA is simultaneously input to the X address latch circuit XLT. STi is input to the precharge signal generation circuit XPC, and the output bit line precharge signal FPC is set to "L". The bit line precharge signal FPC reaches the level sense circuit in the bank control circuit BNKCNT-2 while releasing the precharge of the bit lines B and / B. When this level falls below a certain value, the output PCSEN becomes "H". This signal PCSEN is converted into a narrow pulse of several nanoseconds by the one-shot pulse generation circuit ONESHOT in the bank control circuit BNKCNT-1, and then input to the S input terminal of the set / reset flip-flop RS-2. As a result, the output WLPi becomes “H”. When WLPi becomes “H”, the output of the X decoder XD selected by the X address AXij first becomes “H”, then the word driver WD output connected thereto becomes “H”, and the memory cell is changed to the bit line B, Connect to / B.
[0043]
Next, the N channel sense amplifier activation signal FSA becomes “H”, the P channel sense amplifier activation signal FSAB becomes “L”, and the sense amplifier SA starts operating. The dummy word line DWL allows the sense amplifier SA to be operated after the level of the word line W becomes sufficiently high and signals are sufficiently output to the bit lines B and / B. This is to prevent the sense amplifier SA from operating and malfunctioning when the signal is small. Subsequently, the level sense circuit provided in the bank control circuit BNKCNT-2 above the bank module BANK detects "L" of the common drive line on the N-MOS transistor side of the N channel sense amplifier activation signal FSA, and the output RE is "H""become. The signal RE is ANDed with WLPi by the AND circuit in the lower bank control circuit BNKCNT-1 of the bank module BANK, and its output YG becomes "H". This YG enables the Y decoder circuit YD. The series of states so far is named S1.
[0044]
Next, consider a case where the state shifts from the state S1 to the activation of the bank module BANK with CR = "H", AC = "H", and Ri = "H". When the clock signal CLK rises with CR = "H" and AC = "H", the bank activation flag DCA rises in the main control circuit MAINCNT. The bank activation flag DCA is input to each bank module BANK. At this time, the row bank selection signal iRi rises in the bank module BANK with the row bank address Ri = "H". The logical product of the row bank selection signal iRi and the bank activation flag DCA is input to the reset terminal R of the set / reset flip-flop RS-1, but STi is already "L" in the previous cycle, so STi It does not change. The logical product of the row-related bank selection signal iRi and the bank activation flag DCA is simultaneously input to the X address latch circuit XLT.
[0045]
The AND circuit output is input to the R terminal of RS-2 via the OR circuit, and WLPi is set to “L”. When WLPi becomes “L”, the voltage of the word line W and the N-channel sense amplifier activation signal FSA becomes “L” and RE becomes “L” in the same order as S0. When RE becomes “L”, a pulse of about ten nanoseconds in width is output from the one-shot pulse generation circuit ONESHOT in the precharge signal generation circuit XPC. This pulse is input to the drive circuit of the precharge signal generation circuit XPC, and is output to the bit line precharge signal FPC without changing its width. This signal reaches the level sense circuit in the bank control circuit BNKCNT-2 while precharging the bit lines B and / B. When this level falls below a certain value, the output PCSEN becomes "H". This signal is converted into a narrow pulse by the one-shot pulse generation circuit ONESHOT in the bank control circuit BNKCNT-1, and then input to the S input terminal of the set / reset flip-flop RS-2. As a result, the output WLPi becomes “H”. When WLPi becomes “H”, the output of the X decoder XD selected by the X address AXij first becomes “H”, then the word driver WD output connected thereto becomes “H”, and the memory cell is changed to the bit line B, Connect with / B.
[0046]
Next, the N channel sense amplifier activation signal FSA becomes “H”, the P channel sense amplifier activation signal FSAB becomes “L”, and the sense amplifier SA starts operating. The subsequent operation is the same as S1 described above. After the above operation, the bank module BANK is ready for reading and writing, and this state is named S2.
[0047]
1.5 byte control circuit
Next, the column system operation will be described. FIG. 5 shows an example of the byte control circuit BYTCNT. I byte control circuits BYTCNT are included in the amplifier module AMP in FIG.
[0048]
In FIG. 5, WA-0 to WA-7 are write circuits, and RA-0 to RA-7 are read circuits (main amplifiers). In the byte control circuit BYTCNT, eight write circuits WA and read circuits RA are arranged in this way. Here, the write data input from DQ-i0 is transmitted to global bit lines GBL-i0 and / GBL-i0 via inverters I1 and I2 functioning as buffers and switch SW1. Since the global bit lines GBL-i0 and / GBL-0i are connected to the divided input / output lines IO and IOB in each bank module BANK as shown in FIG. 1, they are transmitted to the Y switch Y-SW. Then, the data is further transferred to the bit lines B and / B to the memory cell. Here, the switch SW1 is attached to bring the global bit lines GBL-i0 and / GBL-0i into a high impedance state at the time of reading. This is controlled by the signal WAi.
[0049]
Data read from the memory cell is transmitted from the input / output lines IO and IOB in each bank module BANK to the main amplifier including MOS transistors QA4 to QA8 through the global bit lines GBL-i0 and / GBL-i0 and the switch SW2. The Here, the main amplifier is a drain input type dynamic amplifier, and its input node is precharged to VCC before signals are read from the global bit lines GBL-i0 and / GBL-0i. When a signal is transmitted, a voltage difference appears between the two input terminals, the main amplifier is activated by the signal MAi, and the difference is amplified. Here, the switch SW2 connects the global bit lines GBL-i, / GBL-i and the main amplifier until just before the main amplifier operates, and disconnects them during the operation. This is to reduce the load capacitance during amplification of the main amplifier and to enable high-speed operation. The switch SW2 is controlled by the signal MAGe. The signal amplified by the main amplifier is input to the latch circuit composed of N1 and N2 in the next stage, and further output to the terminal DQ-i0 via the buffer amplifier TI1.
[0050]
Signal DOEi switches between high impedance and low impedance of the TI1 output. The TI1 output is set to high impedance when writing. P-MOS transistors QA1 to QA3 constitute a precharge circuit for global bit lines GBL-i and / GBL-i, and P-MOS transistors QA9 to QA10 constitute a precharge circuit for a main amplifier. Controlled by IOEQiB and MAEQiB, respectively. All the control signals are generated by external signals CC, BEi, RW, and CLK in the read / write control circuit block RWCNT. Here, the read / write control circuit block RWCNTR is provided for each byte control circuit BYTCNT.
[0051]
FIG. 6 shows a timing chart of the column signal. As the clock signal CLK rises, a read command (CC = "H", RW = "H") and a byte control signal (BEi = "H") are input, and the control signals described above are shown in FIG. Switch to Then, data is read out of the memory macro MMACRO during the period of DOEi = "H". “Byte dis.” Is BEi = “L”, indicating that DQ-I0 to DQ-i7 are non-selected bytes.
[0052]
1.6 Main control circuit
FIG. 7 shows an example of the main control circuit MAINCNT. The main control circuit MAINCNT combines standard logic circuits such as NAND circuits, inverters, and D-type flip-flops from the control signals CR, AC, CC, clock signal CLK, and address signal Ai input from the outside of the memory macro MMACRO. The bank closing flag DCS (inverted signal / DCS in FIG. 7), bank activation flag DCA (inverted signal / DCA in FIG. 7), column address enable signal YP, row address signal (X Signals such as an address signal (AXij) and a column address signal (Y address signal) AYi are generated.
[0053]
Here, the circuit RSTCKT generates a reset signal RST when the bank control circuit BNKCNT described later is turned on, and generates a one-shot pulse when the power is turned on. The feature of this circuit RSTCKT is that a capacitor is provided between the power supply line and its terminal so that the voltage of the input terminal of the inverter IV1 rises at high speed even when the power supply voltage rises at high speed. The operation will be described below.
First, when the power supply voltage VCC rises, the gate and drain voltages of the N-MOS transistor QV3 rise. When this voltage is less than or equal to the threshold voltage of the N-MOS transistors QV3 and QV5, no current flows through the N-MOS transistors QV3 and QV5, so the voltage at the input terminal of the inverter IV1 rises at the same voltage as the power supply voltage. Next, when the gate and drain voltages of the N-MOS transistor QV3 exceed the threshold voltage, current flows through the N-MOS transistors QV3 and QV5, and the voltage at the input terminal of the inverter IV1 decreases. Thereby, a one-shot pulse can be generated when the power is turned on. Here, the value of VCC at which the voltage at the input terminal of the inverter IV1 begins to drop is roughly determined by the threshold voltages of QV2 and QV3 and is expressed as VCC = VT (QV2) + VT (QV3). This value can be further adjusted by changing the W / L ratio of P-MOS transistor QV4 and N-MOS transistor QV5, N-MOS transistor QV3 and P-MOS transistor QV1, or N-MOS transistors QV3 and QV5. . Here, the capacitor QV6 is connected between the power supply line and its terminal. This is because the rise of the voltage is delayed due to the capacity of the input terminal of the inverter IV1 when the power supply voltage rises at high speed. This is to prevent a phenomenon in which a current flows through QV5 before the threshold value is exceeded and the node does not exceed the logic threshold value of inverter IV1. As described above, according to the present circuit, it is possible to reliably generate a pulse even at a low speed even when the power supply rises at a high speed.
[0054]
1.7 Read / write control circuit block
FIG. 8 shows an example of the read / write control circuit block RWCNT. Here, as with the main control circuit MAINCNT, standard logic such as NAND circuits, inverters, D-type flip-flops, etc. from the control signals RW, CC, clock signal CLK, byte control signal BEi input from the outside of the memory macro MMACRO The circuit is combined to produce signals such as MAEQiB, WAi, MAi, DOEi (inverted signal DOEiB in FIG. 8), MAGe (inverted signal MAgiB in FIG. 8), etc. shown in FIG. D1, D2, and D3 are delay circuits. The CLK1B, CLK2B, and CLK3B generation circuits shown in the lower part of the figure may be provided for each read / write control circuit block RWCNT, or only one may be provided for the main control circuit block MAINCNT.
[0055]
1.8 Other examples of memory cell arrays
FIG. 9 shows another example of the memory cell array MCA portion in the bank module BANK. The feature of this example is that the sense amplifier SA and the bit line precharge circuit PC are arranged separately on the left and right sides of the memory cell array MCA for each pair of bit lines. As a result, the layout pitch of the sense amplifiers SA is relaxed, so that the length of the sense amplifiers SA in the bit line direction is shortened. become. That is, when the length of the sense amplifier SA in the bit line direction is shortened, the parasitic capacitance of that portion is reduced, and the signal from the memory cell can be increased.
[0056]
1.9 Bank control circuit block
FIG. 10 shows an example of the bank control circuit block BNKCNT-1. In particular, it is suitable for the memory cell array in which sense amplifiers are alternately arranged as shown in FIG. Like the above read / write control circuit block RWCNT, the word line W, bit line precharge signal FPC, column address select signal shown in FIG. YSi, N channel sense amplifier start signal FSA, P channel sense amplifier start signal FSAB, etc. are made. Here, (R) and (L) are signals for the right side sense amplifier SA and the left side sense amplifier SA, respectively. The output RST of the aforementioned power-on reset circuit is input to the WLPI and STi generation circuits, and at the time of power-on, these outputs are set to the same “L” and “H” as in the S0 state, respectively. As a result, the memory cell array enters a precharged state, and an increase in power-on current due to the operation of the sense amplifier SA can be suppressed.
[0057]
The lower part of FIG. 10 is an example of the bank control circuit block BNKCNT-2. Here, PCS is a level sensor for the bit line precharge signal FPC, and SAS is a level sensor for the common drive line on the N-MOS transistor side of the sense amplifier SA. These are for detecting the end of precharge and the end of signal amplification, respectively. The feature of this example is that the logic threshold value of the CMOS logic circuit receiving these signals is lowered to the vicinity of the threshold voltage of the N-MOS transistor in order to detect the point where the input signal is sufficiently lowered. . As a result, even if the threshold voltage of the sense amplifier SA or the memory cell varies, it can be compensated to some extent. A differential amplifier may be used as this level sensor. In this case, if the reference voltage at the sense level is set lower than the threshold voltage of the N-MOS by the amount of variation, it is possible to prevent malfunction due to the variation as in the above-described logic threshold method.
[0058]
1.10 Logic circuit block
The logic circuit block LOGIC shown in FIG. 1 performs processing of functions such as arithmetic processing of image data, drawing to an image memory (memory macro MMACRO), and reading from the image memory to a display device. In addition, the logic circuit block LOGIC includes an address signal Ai, a row bank address Ri, a column bank address Ci, data input / output lines DQ-i0 to DQ-i7, control signals CC, AC, CR, RW, A byte control signal BEi, a clock signal CLK, and the like are supplied. Further, the logic circuit block LOGIC gives a refresh operation instruction and a refresh address to the memory macro MMACRO using the control line, the address signal, and the like.
[0059]
The logic circuit block LOGIC also performs an interface to the outside of the semiconductor integrated circuit SIC. A central processing unit CPU, a display device, and the like are connected to the outside, and data and commands are exchanged by I / O and control signals in FIG.
[0060]
2. Second example of application to memory / logic mixed LSI
FIG. 11 shows another application example to a memory / logic mixed LSI. The feature of this example is that four memory macros MMACRO according to the present invention are mounted, and all data output from the memory macro MMACRO are processed in parallel by the logic circuit blocks LOGIC-1 and LOGIC-2. As a result, the data transfer and processing speed can be quadrupled compared to the case of only one memory macro MMACRO. Further, the data processing speed can be further improved by increasing the number of macros. Here, the logic circuit block LOGIC-3 processes the calculation results of the logic circuit blocks LOGIC-1 and LOGIC-2 into a data format that is easy to import into the elements outside the chip, and conversely a format that makes it easy to calculate data from outside the chip. Has the ability to process. Such a method of processing data from a plurality of memory macros MMACRO in parallel is particularly effective for applications that require high-speed processing of a large amount of data such as three-dimensional graphics.
[0061]
Further, not only the memory macro MMACRO having the same capacity as in this example, but also a memory macro MMACRO having a different capacity depending on the application may be used. For example, when used with a microprocessor, the bank module BANK of the memory macro MMACRO can be changed to one or two, and the amplifier module AMP can be changed to a high-speed type to be used as a cache memory. It is also possible to increase the number of bank modules BANK and use a low-speed or medium-speed amplifier module AMP as a main memory. Here, the reason why the main amplifier is set to low speed or medium speed is to reduce the occupied area of the amplifier. Thus, according to the present invention, since the memory macro is modular, the memory capacity and the amplifier capacity can be freely changed.
[0062]
3. Third example of application to memory / logic mixed LSI
FIG. 12 shows an application example when the internal data bus width is small. In the figure, the data input / output line DQi is commonly connected for each byte. Therefore, the number of input / output lines from one memory macro MMACRO is only 8. Data switching is performed by a byte control signal BEi output from the selection circuit SELECTOR. By performing such connections, the memory macro MMACRO can be used as a built-in memory of a normal 8- to 32-bit one-chip microcomputer.
[0063]
4). ROM bank module
FIG. 13 shows an example in which a part of the bank module BANK of the memory macro MMACRO is replaced with a ROM (Read Only Memory) module. The advantage of this example is that when used as a built-in memory of a one-chip microcomputer, the ROM and RAM control circuits (such as the amplifier module AMP including the main control circuit MAINCNT) can be shared, so that the chip area can be reduced. Further, when it is built in an image processor or DSP (Digital Signal Processor), for example, if the product-sum operation coefficient is stored in the ROM, the RAM and the ROM are close to each other, so that data can be read and operated at high speed.
[0064]
FIG. 14 shows a circuit example of a memory array RMCA of a ROM module suitable for application to the memory macro MMACRO. The feature of this example is that some DRAM memory cells of the same size as the RAM module are used in order to match the number and pitch of the global bit lines with the RAM module (the bank module BANK shown in FIGS. 1, 3, 9 etc.). It is changed and used as a ROM cell. For use as a ROM cell, for example, a mask for removing the insulating film may be added in accordance with data to be written after the insulating film of the memory cell is formed. As a result, the cell from which the insulating film was removed (MC1 in the figure) was short-circuited with the common electrode of the memory cell, and the cell that was not removed (MC2 in the figure) was written by maintaining insulation. become.
[0065]
The operation of the ROM module will be described with reference to FIGS. First, by setting the bit line precharge signal FPC to “H”, the N-MOS transistors QR3, QR4, QR5, QR7 are turned on, and the bit line B and the input terminals N1, N2 of the sense amplifier become the voltage of VCC. Next, the bit line precharge signal FPC is set to “L”, and the word line (W1 in this example) and the transfer signal SC are set to “H” (VCC or higher). Then, the N-MOS transistors QR1, QR6, and QR8 are turned on, so that the node of N1 is lowered to the voltage of HVC, and the node of N2 is lowered to the voltage of 3 / 4VCC. This voltage difference is amplified by operating the sense amplifiers (QR9 to QR12) by setting the P channel sense amplifier common drive line CSP to "H" and the N channel sense amplifier common drive line CSN to "L". If the current continues to flow through the N-MOS transistor QR1, the transfer signal SC is set to "L" to turn off the N-MOS transistors QR6 and QR8. Thus, N1 becomes VSS voltage and N2 becomes VCC voltage. That is, information “0” is read out. If W2 is raised instead of W1, the node of N2 will not be changed to 3 / 4VCC voltage, but the current of N1 node will be VCC voltage because the current does not flow through the memory cell, and the potential relationship will be reversed. This time, N1 becomes the VCC voltage and N2 becomes the VSS voltage. That is, information “1” is read out. Here, when YSi is set to “H”, signals appear on the global bit lines GBL and / GBL via the input / output lines IO and IOB. The timing at which the word line is set to “L” may be anywhere from when SC is set to “L” to when precharge is started.
[0066]
As described above, according to this example, since the same memory cell pattern as that of the RAM can be used as the ROM, the number and pitch of the global bit lines can be easily matched with those of the RAM module. Although the method of removing the insulating film of the DRAM cell has been described here as an example, another method, for example, a method of removing the storage electrode of the memory cell may be used. A conventional ROM cell may be used as long as the pitch of the global bit line can be made the same as that of other bank modules BANK.
[0067]
Here, the ROM is a program-fixed mask ROM in which information is written in advance in the chip manufacturing process, and is a non-volatile memory that retains stored information even when the power is turned off. The RAM is a memory that can rewrite, hold, and read data at any time, and is a volatile memory that cannot hold stored information when the power is turned off.
[0068]
Up to this point, the RAM memory cell has been described as the DRAM cell shown in FIG. 3, but an SRAM cell may be used. In this case, the ROM cell of the ROM bank module may be created by changing a part of the SRAM cell.
[0069]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0070]
A memory macro is composed of a combination of functional modules such as an amplifier module, a bank module, and a power supply. A row system circuit that operates independently and a large number of I / O lines extending in the bit line direction are arranged in the bank module. The I / O line is configured to be connected only by arranging the modules adjacent to each other. Further, a circuit is provided in the amplifier module that can activate and deactivate them in byte units. As a result, the number of memory cell array modules can be increased or decreased while waiting for a large number of I / O lines, so that the capacity can be varied freely from a small capacity to a large capacity while maintaining high data transfer speed. Furthermore, since I / O lines can be activated and deactivated in byte units in the amplifier module, the number of I / O lines that go outside the memory macro can be increased or decreased in byte units. In addition, since the power supply and amplifier can be shared, there is little overhead.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a memory macro according to the present invention and an application example to an image processing LSI.
FIG. 2 is a diagram showing a relationship between an external signal and an operation mode of the memory macro of the present invention.
FIG. 3 is a diagram showing an example of a sense amplifier and a precharge circuit of the present invention.
FIG. 4 is a diagram showing operation timing of a bank control circuit according to the present invention.
FIG. 5 is a diagram showing an example of a byte control circuit according to the present invention.
FIG. 6 is a diagram showing write and read timings according to the present invention.
FIG. 7 is a diagram showing an example of a main control circuit of the present invention.
FIG. 8 is a diagram showing an example of a read / write control circuit of the present invention.
FIG. 9 is a diagram showing a second example of the bank module of the present invention.
FIG. 10 is a diagram showing an example of a bank control circuit of the present invention.
FIG. 11 is a diagram showing a second application example to the memory / logic mixed LSI according to the present invention;
FIG. 12 is a diagram showing a third application example to the memory / logic mixed LSI according to the present invention;
FIG. 13 is a diagram showing a second configuration example of the memory macro of the present invention.
FIG. 14 is a diagram showing a configuration example of a ROM-BANK module of the present invention.
FIG. 15 is a diagram showing operation waveforms of the ROM-BANK module of the present invention.
FIG. 16 is a diagram showing a bank address wiring layout example of the present invention;
[Explanation of symbols]
MMACRO ... Memory macro
LOGIC ... Logic circuit block
AMP ... Amplifier module
BANK ... Bank module
PS… Power supply module
MAINCNT ... Main control circuit block
BYTCNT ... Byte control block
BNKCNT-1… Lower bank control block
BNKCNT-2… Upper bank control block
MCA ... Memory cell array
SUBARY ... Sub memory cell array (I / O line division unit in bank module)
SA ... Sense amplifier
PC: Precharge circuit
MC1, MC2 ... memory cells
WD ... Word driver
XD ... X decoder
YD ... Y decoder
DWL ... Dummy word line
ONESHOT ... One-shot pulse generator
RS-1, RS-2 ... set / reset flip-flop
D-FF ... Delay flip-flop (D flip-flop)
XLT ... X address latch circuit
YLT ... Y address latch circuit
XPC: Precharge signal generator
VCHG ... VCH generation circuit
VBBG ... Array substrate voltage generator
HVCG: Bit line precharge voltage generator
D1, D2, D3, D5, D15 ... delay circuit
Qi, QAi, QRi ... MOS transistors
VCC ... Power supply voltage
VCH: Word line voltage
VSS: Power supply voltage (ground potential)
VBB ... Power supply voltage
HVC: half the power supply voltage
B, /B...bit line
GBLij, /GBLij...Global bit line
I / O: I / O lines in the sub memory cell array block
YSi: Column address select signal
FPC: Bit line precharge signal
FSA: N channel sense amplifier start signal
FSAB ... N channel sense amplifier start signal
W, W1, W2 ... Word line
CSP ... P channel sense amplifier common drive line
CSN: N channel sense amplifier common drive line
DQ-ij: Memory macro data input / output line
BEi ... Byte control signal
CLK: Clock signal
DCA ... Bank activation flag
DCS ... Bank closing flag
YP ... Column address enable signal
AXij: Row address signal (X address signal)
AYi: Column address signal (Y address signal)
Ri ... low bank address
Ci: Column bank address
RST ... Power-on reset signal.

Claims (18)

In a semiconductor integrated circuit in which a plurality of first modules, second modules, third modules, and logic circuit blocks are formed on a single semiconductor substrate,
Each of the plurality of first modules is
A memory array having a plurality of bit lines, a plurality of word lines, and a plurality of memory cells provided at intersections of the plurality of bit lines and the plurality of word lines;
A plurality of sense amplifiers connected to each of the plurality of bit lines to amplify the signals of the plurality of bit lines;
A plurality of word drivers for selectively driving the plurality of word lines;
A data input / output line commonly connected to the plurality of bit lines via a Y switch;
A global bit line connected to the data input / output line and extending in the same direction as the bit line on the memory array;
A column decoder that outputs a column selection signal for selecting a predetermined number of bit lines from the plurality of bit lines and connecting to the global bit lines by controlling the Y switch;
The second module includes
An amplifier for amplifying signals from the plurality of memory cells that transmit the global bit line; and a write circuit for writing data to the plurality of memory cells via the global bit line;
The third module includes
A circuit for generating a voltage used in the plurality of first modules and the second module;
The plurality of first modules are arranged in a row in close proximity to each other, connected to each other by the global bit line,
The second module is disposed at one end of a row in which the plurality of first modules are arranged,
2. The semiconductor integrated circuit according to claim 1, wherein the logic circuit block exchanges data with the second module. In claim 1,
Each of the plurality of first modules is not activated at the same time. In claim 1 or 2,
The semiconductor integrated circuit according to claim 2, wherein the second module is capable of controlling data input / output in byte units. In any one of Claim 1 to 3,
The semiconductor integrated circuit, wherein the plurality of memory cells are dynamic memory cells. In any one of Claim 1 to 3,
A plurality of memory cells included in at least one of the plurality of first modules are ROM cells, and a plurality of memory cells included in the other plurality of first modules are RAM cells. A semiconductor integrated circuit. In claim 5,
The ROM cell is created by adding a process of writing data to the same process as the RAM cell. In any one of Claims 1-6,
The semiconductor integrated circuit, wherein the plurality of word lines and a column selection signal line for transmitting the column selection signal extend in the same direction. In any one of Claims 1-7,
The semiconductor integrated circuit, wherein the column decoder and the plurality of word drivers are arranged along one side of the memory array. In any one of Claims 1-8,
The semiconductor integrated circuit is an ASIC. In any one of Claims 1 to 9,
The plurality of first modules are arranged between the second module and the third module. In a semiconductor integrated circuit in which a plurality of first modules, a second module, a third module, and a logic circuit block that processes data output from the plurality of first modules are formed on a single semiconductor substrate.
Each of the plurality of first modules includes:
A memory array having a plurality of bit lines, a plurality of word lines, and a plurality of memory cells provided at intersections of the plurality of bit lines and the plurality of word lines;
A plurality of Y switches connected to each of the plurality of bit lines;
A plurality of global bit lines Ru extending in a first direction,
A control circuit including a row decoder connected to the plurality of word lines and a column decoder connected to a control node of the plurality of Y switches;
A plurality of address signal lines extending in the first direction and connected to the control circuit;
The second module includes
An amplifier for amplifying signals from the plurality of memory cells that transmit the global bit line; and a write circuit for writing data to the plurality of memory cells via the global bit line;
The third module includes
A circuit for generating a voltage used in the plurality of first modules and the second module;
The plurality of first modules are arranged in a row in the first direction,
Each of the plurality of global bit lines is connected to a plurality of corresponding Y switches among the plurality of Y switches via a data input / output line.
Each of the plurality of global bit lines included in each of the plurality of first modules corresponds to one of the plurality of global bit lines included in the first module arranged adjacent to among the plurality of first modules. Connected to the global bit line on the plurality of first modules,
Each of the plurality of address signal lines included in the plurality of first modules corresponds to a corresponding address among the plurality of address signal lines included in the first module arranged adjacent to among the plurality of first modules. A semiconductor integrated circuit connected to a signal line on the plurality of first modules. In claim 11,
Each of the plurality of first modules further includes a first node for receiving a row bank address and a second node for receiving a column bank address. In claim 11 or 12,
Each of the plurality of first modules further includes a clock signal line extending in the first direction and connected to the control circuit,
The semiconductor integrated circuit according to claim 1, wherein the clock signal line is connected to the control circuit on the first module. In any one of claims 11 to 13,
Each of the plurality of memory cells is a DRAM cell having one transistor and one capacitor. In any one of claims 11 to 13,
Each of the plurality of memory cells included in one of the plurality of first modules is an SRAM cell or a ROM cell,
Each of the plurality of memory cells included in the other plurality of first modules is a DRAM cell having one transistor and one capacitor. In any one of claims 11 to 15,
The semiconductor integrated circuit further includes a second module including a plurality of main amplifiers,
The semiconductor integrated circuit according to claim 1, wherein the second module is disposed adjacent to a module disposed at an end of a row of the plurality of first modules. In any one of claims 11 to 16,
The semiconductor integrated circuit further includes a third module having a voltage generation circuit,
The third module is disposed adjacent to one of the plurality of first modules,
The plurality of first modules further include a plurality of power supply lines extending in the first direction,
Each of the plurality of first modules is connected on the plurality of first modules;
Each of the plurality of power supply lines is connected to the corresponding voltage generation circuit. In any one of Claims 11 to 17,
The column decoder and the control nodes of the plurality of Y switches are connected via a plurality of column selection signal lines.

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