JPH10162589A - Ferroelectric memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a ferroelectric memory device which does not consume much power and can operate at a high speed by providing a cell plate driving circuit which can only drive a necessary cell plate line of selected word lines. SOLUTION: A word line driving circuit WD00 constituted of the AND of a word line driving signal WDS and a row address selecting signal PDA00 drives a word line signal WL00 and a cell plate line driving circuit CPD00 constituted of the AND of a cell plate line driving signal CPS0 and a word line signal WL00 drives a cell plate line signal CP00. A memory cell block MC000 or MC001 is connected between the word line signal WL00 and cell plate line signal CP00 and the bit lines connected to the memory cell blocks are respectively connected to sense amplifiers SA00 and SA01. To each cell plate line driving circuit, a common cell plate line driving signal PSO and word line signals are inputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device.

[0002]

2. Description of the Related Art In recent years, there has been known a semiconductor memory device in which data storage is nonvolatile by using a ferroelectric film made of a ferroelectric material as an insulating film of a capacitor. The transition of the polarization state of the ferroelectric exhibits a hysteresis characteristic, and the residual polarization remains in the ferroelectric even when the voltage applied to the ferroelectric becomes zero, and the non-volatile data is stored using this. Things. In order to read out this non-volatile data from the ferroelectric capacitor, it is necessary to apply a voltage to the ferroelectric capacitor. Generally, a cell plate line forming an electrode of the ferroelectric capacitor is driven. This conventional example is disclosed in JP-A-7-220482. The purpose of this example is to select a cell plate line having a large capacity connected to many memory cell ferroelectric capacitors, a global cell plate line, and a sub-cell plate line by a word line signal. As described above, by selecting the sub-cell plate line by the word line signal, the capacity of the cell plate line to be driven is reduced, and high-speed operation and low power consumption are achieved.

FIG. 6 shows an overall configuration diagram corresponding to this conventional example. FIG. 8 is an operation timing diagram, and FIG. 9 is a configuration diagram of a memory cell. FIG. 7 is an overall configuration diagram of another conventional example.

[0004] WDS is a word line drive signal, WD00, W
D01 is a word line drive circuit, WL00 and WL01 are word line signals, CPS0 is a cell plate line drive signal, CPS
00, CPS01 is a cell plate line dividing circuit, CPD0
0, CPD01 is a cell plate line driving circuit, CP00,
CP01 is a cell plate line signal, PDA00, PDA0
1 is a row address selection signal, MC000 to MC011 are memory cell blocks, SA00 and SA01 are sense amplifiers, BL00T, BL01T, BL00B, and BL01B.
Is a bit line, C1 and C2 are ferroelectric capacitors, Qn
1 and Qn2 are memory cell transistors.

First, a conventional example shown in FIG. 6 will be described. The circuit configuration is such that the word line signal WL00 is driven by the word line drive circuit WD00 formed by the logical product of the word line drive signal WDS and the row address selection signal PDA00. A cell plate line drive signal CPS0 corresponding to a global cell plate line is connected to a cell plate line signal CP00 corresponding to a sub cell plate line via a cell plate line dividing circuit CPS00 composed of a switch circuit of an N-channel MOS transistor. . The gate of the N-channel MOS transistor of the cell plate line dividing circuit CPS00 is connected to the word line WL00. The memory cell blocks MC000 and MC001 are connected between the word line signal WL00 and the cell plate line signal CP00,
The bit lines connected to this memory cell block are connected to sense amplifiers SA00 and SA01, respectively. As for the operation timing, as shown in FIG. 8, a word line is selected between times t1 and t4, and a time t2 and t3 are selected.
Is selected between the cell plate lines. As shown in FIG. 9, the memory cell has a configuration in which one bit is stored by two memory cell transistors and two ferroelectric capacitors. In the conventional example of FIG. 6,
The cell plate line dividing circuit is composed of N-channel MOS transistors, and is driven by an N-channel MOS transistor for driving a cell plate line signal CP00 corresponding to a sub-cell plate line.
There is an influence of the threshold value of the OS transistor. Particularly, when the cell plate line signal CP00 is driven to the logic voltage "H", the resistance value becomes large due to the threshold value of the N-channel MOS transistor, so that the delay is increased and the drive is slow. There is a problem of becoming. The driving of the sub cell plate line signal CP00 is performed by dividing the global cell plate line (cell plate line driving signal) CPS0, and the parasitic capacitance of the cell plate line driving signal CPS0 is the diffusion capacitance of the diffusion layer of the N-channel MOS transistor. There is a problem that the capacitance becomes large including the capacitance, which also causes a drive delay.

Next, a conventional example shown in FIG. 7 will be described. The circuit configuration is such that the word line signal WL00 is driven by the word line drive circuit WD00 formed by the logical product of the word line drive signal WDS and the row address selection signal PDA00. Also,
The cell plate line signal CP00 is driven by the cell plate line drive circuit CPD00 formed by the logical product of the cell plate line drive signal CPS0 and the row address selection signal PDA00. The connection relationship between the memory cell blocks, the bit lines, and the sense amplifiers is the same as in the conventional example of FIG. FIG.
In the conventional example, there is a problem in that each row address selection signal needs to be input to each cell plate line drive circuit. The fact that each row address select signal is required as an input signal means that considering the layout area, it is necessary to arrange the word line drive circuit and cell plate line drive circuit close to each other and use the row address select signal in common. Becomes However, it may be difficult to arrange the word line driving circuit and the cell plate line driving circuit close to each other at the layout pitch of the word lines.

[0007]

In the above conventional example, FIG.
In the conventional example, the driving delay of the cell plate line driving signal becomes a problem. Further, in the conventional example of FIG. 7, each row address selection signal needs to be input to the cell plate line drive circuit, and there is a problem in layout.

[0008]

The following means are used to achieve the above object.

According to the first aspect of the present invention, a first word line signal output from a first word line drive circuit, a first cell plate line signal output from a first cell plate drive circuit, A memory cell transistor having a word line signal as a gate, and a ferroelectric capacitor connected between a drain of the memory cell transistor and the first cell plate line signal, wherein the first cell plate drive circuit is provided. Comprises the first word line signal and the first cell plate drive signal as input signals, and the first cell plate line signal is selected in a certain period of the selection period of the first word line signal. The circuit is a ferroelectric memory device.

According to a second aspect of the present invention, a first word line signal output from a first word line drive circuit, a first cell plate line signal output from a first cell plate drive circuit, a second word line signal, A second cell plate line signal output from a cell plate drive circuit, a memory cell transistor having the first word line signal as a gate, a drain of the memory cell transistor and the first cell plate line signal or the second And a first cell plate drive circuit, wherein the first cell plate drive circuit receives the first word line signal and the first cell plate drive signal as input signals, and A circuit in which the first cell plate line signal is selected during a certain period of the first word line signal selection period, wherein the second cell plate drive circuit includes the first cell plate drive signal; 2. A circuit in which a word line signal and a second cell plate drive signal are used as input signals, and the second cell plate line signal is selected during a certain period of a selection period of the first word line signal. The ferroelectric memory device according to the present invention.

According to a third aspect of the present invention, a first word line signal output from a first word line driving circuit, a first cell plate line signal output from a first cell plate driving circuit, A memory cell transistor having a word line signal as a gate, and a ferroelectric capacitor connected between a drain of the memory cell transistor and the first cell plate line signal, wherein the first cell plate drive circuit is provided. Comprises the first word line signal and the first cell plate drive signal as input signals, and the first cell plate line signal is selected in a certain period of the selection period of the first word line signal. In the circuit, the first word line drive circuit is disposed on a first end side of the first word line, and the first cell plate drive circuit is connected to a first end of the first word line. Opposition first The ferroelectric memory device of the present invention according to claim 1 which is arranged on the end side.

According to a fourth aspect of the present invention, a first word line signal output from the first word line drive circuit, a first cell plate line signal output from the first cell plate drive circuit, A second cell plate line signal output from a cell plate drive circuit, a memory cell transistor having the first word line signal as a gate, a drain of the memory cell transistor and the first cell plate line signal or the second And a first cell plate drive circuit, wherein the first cell plate drive circuit receives the first word line signal and the first cell plate drive signal as input signals, and A circuit in which the first cell plate line signal is selected during a certain period of the first word line signal selection period, wherein the second cell plate drive circuit includes the first cell plate drive signal; A circuit in which a word line signal and a second cell plate drive signal are input signals, and wherein the second cell plate line signal is selected in a certain period of the selection period of the first word line signal; Is disposed in a first region of the first word line, the first cell plate driving circuit is disposed in a second region of the first word line, and the second cell plate driving circuit is disposed in a second region of the first word line. 2. The ferroelectric memory according to claim 1, wherein the cell plate driving circuit is disposed in a third region of the first word line, and the first region is a central portion of the first word line. Equipment.

According to a fifth aspect of the present invention, the second region is on a first end side of the first word line, and the third region is opposite to a first end of the first word line. The ferroelectric memory device according to the fourth aspect of the present invention is the second end side.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION
The cell plate drive circuit is a circuit configured by inputting a word line signal and a cell plate line drive signal corresponding to the cell plate, and does not require a row address signal. Therefore, the layout area of the cell plate drive circuit can be reduced. effective.

According to the invention of claim 2 of the present invention, a plurality of cell plate drive circuits can be freely arranged in one word line, and only required memory cells can be operated, thereby reducing power consumption. There is an effect that power can be used.

According to a third aspect of the present invention, the word line drive circuit and the cell plate drive circuit are provided at both ends of the word line as an application of the degree of freedom of arrangement of the cell plate drive circuit. This has the effect of avoiding the difficulty of layout of arranging at the line pitch, providing a margin for design rules, and improving the yield.

According to a fourth aspect of the present invention, a word line driving circuit is disposed at the center of a word line, and a plurality of cell plate driving circuits are disposed on both sides of the word line driving circuit. And the delay time of the word line signal to each cell plate drive circuit can be equalized.

The present invention according to claim 5 of the present invention is directed to claim 4
In the invention described above, by arranging each cell plate drive circuit on the end side of the word line, there is an effect that difficulty in layout can be avoided.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a ferroelectric memory device according to the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a configuration diagram of a ferroelectric memory device according to a first embodiment of the present invention. The operation timing diagram and the configuration diagram of the memory cell are the same as in the conventional example.

WDS is a word line drive signal, WD00, W
D01 is a word line drive circuit, WL00 and WL01 are word line signals, CPS0 is a cell plate line drive signal, CPD
00, CPD01 is a cell plate line drive circuit, CP0
0, CP01 are cell plate line signals, PDA00, PD
A01 is a row address selection signal, MC000 to MC01
1 is a memory cell block, SA00 and SA01 are sense amplifiers, BL00T, BL01T, BL00B, BL0
1B is a bit line.

The circuit configuration is such that the word line signal WL00 is driven by the word line drive circuit WD00 formed by the logical product of the word line drive signal WDS and the row address selection signal PDA00. The cell plate line signal CP00 is driven by the cell plate line drive circuit CPD00 formed by the logical product of the cell plate line drive signal CPS0 and the word line signal WL00. Word line signal WL00 and cell plate line signal CP0
0 between memory cell blocks MC000 and MC001
And the bit lines connected to the memory cell block are connected to sense amplifiers SA00 and SA01, respectively. Each cell plate line drive circuit (here, CPD0
0, CPD01) are common cell plate line drive signals C
PS0 and the respective word line signals (here, WL00,
WL01) has been input. The cell plate line driving circuit can be arranged in any region where word line signals are wired. Here, the cell plate line driving circuit is arranged near the word line driving circuit. At this time, the P-channel MOS transistor regions constituting these circuits are shared, and the N-channel MOS transistor regions are shared.
There is also an effect that the layout area can be reduced. Although not particularly limited, the cell plate line drive signal CPS
0 is arranged in a direction perpendicular to the word line signal WL00, and is configured to determine the timing of driving the cell plate line and select a memory cell group.

(Second Embodiment) FIG. 2 is a configuration diagram of a ferroelectric memory device according to a second embodiment of the present invention. Basically, it is the same as the first embodiment, except that the cell plate line driving circuits (CPD00, CPD01) are smaller circuits for synthesizing logic circuits. More specifically, the cell plate line driving circuit converts the cell plate line signal into a logical NOT signal which receives a negative signal of the word line signal, which is an intermediate node of the word line driving circuit, and a negative signal of the cell plate line driving signal CPS0. This is the output circuit. The second embodiment has an effect that the size of the cell plate line drive circuit is small and the layout area can be reduced as compared with the first embodiment.

(Third Embodiment) FIG. 3 is a configuration diagram of a ferroelectric memory device according to a third embodiment of the present invention. In addition to the first embodiment, a WMD word line drive signal generation circuit, a CPM
S cell plate line drive start signal, CPMD0, CPM
D1 cell plate line drive signal generation circuit, PDA10,
Column address (block) selection signal of PDA 11, C
PS0, CPS1 cell plate line drive signal, CPD0
0 to CPD11 cell plate line driving circuits.

In the third embodiment, for example, for one word line signal WL00 in the first embodiment,
A plurality of cell plate line drive circuits CPD00, C controlled by a plurality of cell plate line drive signals CPS0, CPS1
One feature is that the PD 10 is arranged. As described above, the memory cell region to be operated by dividing the cell plate line drive signal for one word line signal is limited to a necessary portion, so that power consumption during operation can be reduced and one cell plate signal can be reduced. Since the load of the line drive signal is reduced, high-speed operation becomes possible. Again, although not particularly limited, the cell plate line drive signals CPS0, CP
S1 is arranged in a direction perpendicular to the word line signal WL00 and the like, and these cell plate line drive signals CPS0 to CPS
1 is a column address (block) selection signal PDA10,
This is the configuration selected by the PDA 11. Although not particularly limited, the word line drive signal WDS is the word line signal WL0.
0 is the cell plate line drive signal CP
It is configured to perform a memory cell group larger than the memory cell group selected in S0.

In the third embodiment, a large memory cell group can be selected by a word line drive signal, and a small memory cell group can be selected by a cell plate line drive signal. A small memory cell group can be selected by two drive signals. There is an effect that both the drive signals are timing setting signals and operate as group selection signals. In terms of layout area, there is an effect that a selection circuit is not required for selecting a memory cell group, so that it can be reduced.

(Fourth Embodiment) FIG. 4 is a block diagram of a ferroelectric memory device according to a fourth embodiment of the present invention. Basically, it is the same as the first embodiment, but as an application of the degree of freedom of arrangement of the cell plate drive circuit, the arrangement of the word line drive circuit and the cell plate drive circuit is provided at each end of the word line. This avoids the difficulty of layout of arranging at the pitch of word lines. As a result, there is an effect that a margin in design rules can be provided, which leads to an improvement in yield. Again, although not particularly limited, the word line drive signal W
The DS and the cell plate line drive signal CPS0 are arranged in a direction perpendicular to the word line signal WL00, and have an effect that the operation timing is determined and a memory cell group is selected. Further, the word line driving circuit and the cell plate line driving circuit shown here are not limited to this embodiment.

(Fifth Embodiment) FIG. 5 is a block diagram of a ferroelectric memory device according to a fifth embodiment of the present invention.

In the fifth embodiment, the word line driving circuit is disposed at the center of the word line, and a plurality of cell plate driving circuits are disposed on both sides of the word line driving circuit, thereby reducing the load on the word line. It is intended to equalize and speed up the delay time of the word line signal to each cell plate drive circuit and speed up. Although this is not necessarily required in the present embodiment, similar to the fourth embodiment, each cell plate drive circuit is arranged on the end side of the word line to avoid the difficulty of layout.

Also in this embodiment, a large memory cell group can be selected by a word line drive signal, a small memory cell group can be selected by a cell plate line drive signal, and a small memory cell group can be selected by two drive signals. The drive signals are both timing setting signals and operate as group selection signals. In terms of layout area, there is an effect that a selection circuit is not required for selecting a memory cell group, so that it can be reduced.

Here, only one cell plate driving circuit is arranged on one word line side on one side with respect to the word line driving circuit, but a plurality of cells are arranged on one side as in the second embodiment. A plate drive circuit can be provided.

The present invention is not limited to the above-described embodiment, and it is possible to adopt not only the combination of this embodiment but also a combination with a general memory cell group selection method.

[0033]

According to the ferroelectric memory device of the present invention, a cell plate driving circuit capable of driving only a necessary cell plate line among selected word lines can operate at low power consumption and at high speed. In addition, it is possible to avoid the difficulty of the layout, which leads to an effect of improving the yield.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a ferroelectric memory device according to a first embodiment of the present invention;

FIG. 2 is a configuration diagram of a ferroelectric memory device according to a second embodiment of the present invention;

FIG. 3 is a configuration diagram of a ferroelectric memory device according to a third embodiment of the present invention;

FIG. 4 is a configuration diagram of a ferroelectric memory device according to a fourth embodiment of the present invention;

FIG. 5 is a configuration diagram of a ferroelectric memory device according to a fifth embodiment of the present invention.

FIG. 6 is a configuration diagram of a first conventional ferroelectric memory device.

FIG. 7 is a configuration diagram of a second conventional ferroelectric memory device.

FIG. 8 is an operation timing chart of a conventional ferroelectric memory device.

FIG. 9 is a memory cell configuration diagram of a conventional ferroelectric memory device.

[Explanation of symbols]

WDS Word line drive signal WMS Word line drive start signal WMD Word line drive signal generation circuit WD00-WD03 Word line drive circuit WL00-WL03 Word line signal CPMD0, CPMD1 Cell plate line drive signal generation circuit CPS0, CPS1 Cell plate line drive signal CPS00 , CPS01 Cell plate line division circuit CPMS Cell plate line drive start signal CPD00-CPD21 Cell plate line drive circuit CP00-CP21 Cell plate line signal PDA00-PDA03 Row address selection signal PDA10, PDA11 Column address (block)
Select signal MC000 to MC211 Memory cell block SA00 to SA21 Sense amplifier BL00T to BL11T, BL00B to BL11B Bit line C1, C2 Ferroelectric capacitor Qn1, Qn2 Memory cell transistor

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/8247 29/788 29/792

Claims (5)

[Claims] 1. A first word line signal output from a first word line driving circuit, a first cell plate line signal output from a first cell plate driving circuit, and the first word line signal. A memory cell transistor serving as a gate, a ferroelectric capacitor connected between a drain of the memory cell transistor and the first cell plate line signal, wherein the first cell plate drive circuit comprises: The word line signal and the first cell plate drive signal as input signals,
A ferroelectric memory device, wherein the first cell line signal is selected during a certain period of the first word line signal selection period. 2. A first word line signal output from a first word line drive circuit, a first cell plate line signal output from a first cell plate drive circuit, and a second cell plate drive circuit. A second cell plate line signal to be output, a memory cell transistor having the first word line signal as a gate, a drain of the memory cell transistor and the first cell plate line signal or the second cell plate line signal And the first cell plate drive circuit receives the first word line signal and the first cell plate drive signal as input signals, and
A circuit in which the first cell plate line signal is selected in a certain period of a selection period of the first word line signal, wherein the second cell plate drive circuit includes the first word line signal and the first cell line signal. 2 as the input signal,
2. The ferroelectric memory device according to claim 1, wherein the second cell plate line signal is selected during a certain period of the first word line signal selection period. 3. A first word line signal output from a first word line drive circuit, a first cell plate line signal output from a first cell plate drive circuit, and the first word line signal. A memory cell transistor serving as a gate, a ferroelectric capacitor connected between a drain of the memory cell transistor and the first cell plate line signal, wherein the first cell plate drive circuit comprises: The word line signal and the first cell plate drive signal as input signals,
A circuit in which the first cell plate line signal is selected in a certain period of a selection period of the first word line signal, wherein the first word line driving circuit includes a first word line driving circuit, 2. The ferroelectric element according to claim 1, wherein the first cell plate driving circuit is disposed on an end side, and the first cell plate driving circuit is disposed on a second end side of the first word line opposite to the first end. Body memory device. 4. A first word line signal output from a first word line driving circuit, a first cell plate line signal output from a first cell plate driving circuit, and a second cell plate driving circuit. A second cell plate line signal to be output, a memory cell transistor having the first word line signal as a gate, a drain of the memory cell transistor and the first cell plate line signal or the second cell plate line signal And the first cell plate drive circuit receives the first word line signal and the first cell plate drive signal as input signals, and
A circuit in which the first cell plate line signal is selected in a certain period of a selection period of the first word line signal, wherein the second cell plate drive circuit includes the first word line signal and the first cell line signal. 2 as the input signal,
A circuit in which the second cell plate line signal is selected in a certain period of a selection period of the first word line signal, wherein the first word line driving circuit includes a first word line signal; And the first cell plate driving circuit is disposed in a second region of the first word line, and the second cell plate driving circuit is disposed in a third region of the first word line. 2. The ferroelectric memory device according to claim 1, wherein the first region is a central portion of the first word line. 5. The second region is at a first end of the first word line, and the third region is at a second end of the first word line opposite to the first end. 5. The ferroelectric memory device according to claim 4, wherein: