JP3789259B2 - Digital demodulator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital demodulator that demodulates a modulated wave modulated by a digital signal, and more particularly to a digital demodulator that asynchronously demodulates an angle-modulated wave modulated by differential encoding.
[0002]
[Prior art]
In general, as a modulation / demodulation method of a digital signal, an amplitude modulation method in which the amplitude of a carrier wave is changed according to a state value of the digital signal and a so-called angle modulation method in which a phase or a frequency is changed are well known. In the field, it is common to use an angle modulation method that is not easily affected by amplitude distortion in the transmission path.
First, a π / 4 shift four-phase modulation (π / 4 shift QPSK) method, which has excellent distortion resistance characteristics and is suitable for mobile communication, will be briefly described as an example.
FIG. 7 is a block diagram showing the basic configuration of the π / 4 shift QPSK modulator.
The serial / parallel converter 1 converts the input digital binary data string into unit data (X, Y) having two bits as one set. This unit data is generally referred to as one symbol, and the process proceeds with this as one cycle. The differential encoding circuit 2 generates a baseband signal composed of an I channel and a Q channel in which (X, Y) information is carried with respect to a signal change (difference), and the baseband signal is a low-pass filter. Bandwidth is limited by (LPF) 3 and 4. Thus, after amplitude modulation is performed by multiplying the in-phase and quadrature components of the carrier wave ωC by the band-limited baseband signal, both are combined to obtain a modulated wave.
In the π / 4 shift QPSK system, amplitudes “A” and “−A” are assigned according to binary signals “1” and “0”, and four signal point data (I, Q) are assigned to one symbol. This is based on a four-phase phase modulation (QPSK) system that performs phase modulation based on this.
[0003]
That is, as shown in FIG. 8A showing the signal point arrangement of I and Q, the signal point arrangement indicated by the black dots in the figure for each symbol and the white dots in the figure shifted by π / 4. In this method, phase modulation is performed by alternately using point arrangement. Therefore, the phase difference ΔΦ with respect to the preceding symbol is always an odd multiple of π / 4, and the relationship with the input unit data (X, Y) can be expressed in FIG.
As described above, the angle modulation is briefly described. As a method for demodulating the modulated wave, a synchronous detection method and a delay detection method are well known. Theoretically, the synchronous detection method has better characteristics, but it is disadvantageous under conditions where high-speed fading is likely to occur, especially in digital mobile communications where sudden phase fluctuations are likely to occur, compared to the synchronous detection method. A delay detection method showing good characteristics is suitable.
The delay detection detects the next modulation wave with reference to the modulation wave delayed by the delay circuit having a predetermined delay time. Therefore, the modulation wave modulated by the differentially encoded signal as described above. It is necessary to be. Further, since carrier wave recovery is not required and the configuration is simple compared with synchronous detection, it is suitable for mobile communication.
For example, in the case of the above-described π / 4 shift QPSK, the phase difference ΔΦ between them is obtained by detecting the next modulation wave with reference to the phase of the modulation wave one symbol ahead, and this is decoded according to FIG. do it.
[0004]
FIG. 9 is a block diagram showing an example of a conventional digital demodulator that demodulates a π / 4 shift QPSK modulated wave using delay detection.
The phase-modulated wave becomes an I-channel and Q-channel baseband signal by a signal having the same frequency as that of the carrier wave ωC and a signal obtained by shifting this by π / 2. The I and Q signals are digitized by analog / digital converters (A / D) 7 and 8 via low-pass filters 5 and 6, respectively.
Based on the relationship shown in FIG. 8 (b), the digitized signals I and Q are detected by the delay detection circuit 9 in the signal point arrangement difference from the signal preceding one symbol, that is, the phase difference ΔΦ. Decrypt into Y.
The detection signal from the delay detection circuit 9 is output to the data identification units 11 and 12 and the clock recovery circuit 13. The clock recovery circuit 13 determines a timing point to be described later, and supplies a timing clock signal to the data identification units 11 and 12 for each symbol period based on the timing point. The data identification units 11 and 12 determine basic data (X, Y) from the detection signal based on the timing clock signal, and the basic data (X, Y) is binary data before modulation by the parallel / serial converter 14. Demodulated into a sequence of signals.
[0005]
FIG. 10 is an eye pattern obtained by overwriting the detection signal from the X-side output terminal of the delay detection circuit 9 a plurality of times, and the eye is most open when the binary signal (X =) 1 or 0 is determined. Generally, the signal level at the point (timing point) 10 is identified as demodulated data of each symbol.
The most important point in the above demodulation process is how to determine the timing point, and the conventional clock recovery circuit determines the timing point and generates a timing clock signal. The zero cross detection method is generally used, and a detection signal is taken out from one output terminal of the delay detection circuit 9 and crosses zero (a predetermined level located approximately in the middle of the binary level), that is, 15 in FIG. Is detected, a position 10 that is shifted by 1/2 symbol period from the zero cross point 15 is obtained, and this is output to the data identification units 11 and 12 as timing point signals.
However, in the clock recovery circuit that detects the timing point using the zero cross point as described above, as is apparent from the shape of the eye pattern of FIG. As shown, since it is distributed over a wide range, it is difficult to find an accurate zero cross point.
That is, if a position shifted by a half symbol period from the zero cross point is simply used as a timing point, the most open point of the eye is shifted from the desired position and the rate of occurrence of bit errors increases. A large number of zero cross points were read and the median value was obtained and used as a true zero cross point. However, there was a defect that it took time to be determined.
In particular, a system that frequently switches communication channels and needs to set the timing point each time, such as a digital system for wireless communication, has been a serious drawback.
[0006]
On the other hand, in Japanese Patent Laid-Open No. 03-205940 proposed with digital radio in mind, signal points of I and Q of the baseband signal obtained by quasi-synchronous detection of the preceding modulation wave are on the I and Q coordinate axes. The position of the detection circuit is detected, and when the signal point deviates from the predetermined signal point arrangement, the phase is shifted by changing the delay time of the detection circuit so that the original position is predicted and corrected. A method for performing synchronization correction is proposed.
For example, if the detected signal point is at the position indicated by the point X in FIG. 11, the point X is located at the point P closest to the point X in the predetermined signal point arrangement indicated by the black point in the figure. And the phase shift amount is determined.
However, in this method, when the deviation of the initial timing point is significant, there is a high possibility that erroneous correction is repeated every time one symbol is detected, and it takes time to complete the synchronization pull-in.
As a solution to the above-described problems, Japanese Patent Application Laid-Open No. 06-232931 aims to provide a digital demodulator capable of detecting a demodulation timing point in a short time and obtaining a good demodulated signal. A publication was proposed. In the following, Japanese Patent Laid-Open No. 06-232931 will be described with reference to the drawings.
[0007]
As is apparent from the eye pattern shown in FIG. 10, at the timing point 10 where the eye is most open, the level of the detection signal is a or -a (X = 1 or 0) where the level of the detection signal is concentrated at a relatively high density. Is almost at the same level as the timing point 10. Conversely, the probability that the levels do not match increases as the distance from the timing point 10 approaches the zero cross point 15.
That is, when a plurality of extraction points are set for a detection signal for one symbol period, the signal level at the extraction point is sampled, and the signal levels of two adjacent extraction points are correlated, the signal levels match. The correlation increases in the vicinity of the timing point, and the correlation decreases when the signal levels of the two extraction points are different. In other words, the correlation between the sampling values at 10 points in FIG. 10 increases, but it decreases at 15 points.
By paying attention to this point, the correlation is detected, and by comparing the magnitudes, the timing point is detected, and a good demodulated signal is obtained.
[0008]
Specifically, as shown in FIG. 12, the signal level is sampled at predetermined extraction points (8 points per symbol in the figure) every symbol period, and sampling data of adjacent extraction points are After detecting the correlation between P1 and P2, P2 and P3, etc. in order, the correlation data are compared in magnitude, and the extracted point pair (P4 and P5 pair or P5 P6 pair is predicted), and one of the extracted point pairs is set as a timing point.
FIG. 13 is a block diagram showing the configuration of an embodiment of the digital demodulator disclosed in Japanese Patent Laid-Open No. 06-232931. The clock recovery circuit 16 comprises a correlation detection circuit 17 and a correlation determination circuit 18.
The correlation detection circuit 17 samples the levels of the detection signals X and Y output from the delay detection circuit 9 at a plurality of extraction points set in advance for each symbol period, and two adjacent extraction points. The correlations between the signals sampled as a set are detected, the detected correlations are added for each set of extraction points corresponding to X and Y, and each is accumulated for a plurality of symbols before being output to the correlation determination circuit 18. Is.
[0009]
FIG. 14 is a block diagram showing a specific configuration example of the correlation detection circuit 17.
In the figure, each of the delay circuits 19 and 20 has a delay time τ corresponding to the interval between extraction points, and one input terminal of XOR (exclusive OR) gates 21 and 22 is directly connected to the other input. At the end, the detection signals X and Y are input via the delay circuits 19 and 20 to detect the correlation with the immediately preceding extraction point. Thus, both correlation data are added and output to a plurality of counters 24 via a multiplexer 23 that distributes the data at a period τ. The counter 24 accumulates correlation data for a predetermined plurality of symbols.
The correlation determination circuit 18 compares the correlation data accumulated in the counter 24 to detect a set of extraction points having the largest correlation, determines one of the extraction points as a timing point, and based on the timing point. A timing clock signal is generated.
As is well known, the XOR gate has input / output characteristics as shown in FIG. 15. Therefore, when the correlation is large (when the input levels match), “0” is small (when the input levels do not match). “1” is output. Accordingly, the closer the numerical value accumulated in the counter is to 0, the higher the correlation is, and the correlation determination circuit 18 in the next stage may be configured to obtain the minimum value from a plurality of inputs.
On the other hand, the detection signals X and Y output from the delay detection circuit 9 are input to the data identification units 11 and 12, and the data identification units 11 and 12 detect the detection signals based on the timing clock signal generated by the correlation determination circuit 18. X and Y are decoded. The decoded signal is demodulated into a data string by the parallel / serial converter 14.
Previously, the timing point was predicted based on an unstable point such as a zero cross point, but in the above example, the timing point where the eye of the eye pattern, which is a relatively stable point, was most open was directly obtained. In addition, it is strong against a rapid phase shift due to fading or the like, and it is possible to determine a timing point in a short time for a large phase shift.
[0010]
In addition, as a second embodiment in Japanese Patent Laid-Open No. 06-232931, there is one that demodulates a phase-modulated wave converted to an intermediate frequency (IF). In principle, the description is omitted since it is not changed in principle.
The clock recovery circuit described in Japanese Patent Application Laid-Open No. 06-232931 described above performs predetermined sampling on the decoded digital signal and correlates adjacent data, so that timing points can be obtained in a short time. It is effective when trying to do so, and because it is a method that directly captures the point where the eye of the eye pattern is most open, it is not easily affected by noise near the zero cross, and the timing point is set every time a modulated wave is demodulated by one symbol. Since it is updated, it follows the phase shift due to fading at high speed.
However, if the timing point is updated every time a modulated wave is actually demodulated by one symbol, synchronization is achieved at the true synchronization timing, for example, but the point that does not happen to be a timing point such as a zero-cross point is synchronized due to noise or the like. Since it looks like the timing and the number of errors increases, in reality, what is accumulated over a plurality of symbols is used for the synchronization point determination.
After all, the method of clock recovery after pulling in the clock recovery circuit described in Japanese Patent Laid-Open No. 06-232931 described above is the extraction point pair that maximizes the correlation, that is, the pair of P4 and P5 or P5 and P6 in FIG. Since one of the extracted point pairs is set as a timing point, that is, as a control method, a counter value accumulated over a plurality of symbol periods in a pair of P4 and P5, and P5 and P6 The paired clocks are compared, and the timing of the recovered clock is determined so that the synchronization point comes to the smaller value (the more correlated). Even in this case, if the symbol rate of the Japanese digital cellular phone PDC is about 21 Ksps, the timing can be sufficiently maintained.
[0011]
[Problems to be solved by the invention]
However, in recent years, the demand for data capacity for digital wireless devices has been increasing, and the data transmission speed has been increasing accordingly. An increase in data transmission rate leads to an increase in symbol rate, which means that the wavelength of one symbol is shortened. Therefore, the phase shift due to movement of the mobile communication device is equal distance compared to the case where the symbol rate is low. In this case, it is relatively large.
Then, in the control method in which only two extracted point pairs are compared and held in synchronization as described above, elements such as sudden movement and fading of the mobile communication device occur or overlap at a certain moment. Thus, when the phase changes greatly and the synchronization is shifted to the zero cross point, that is, when the pair of P8 and P1 and the pair of P1 and P2 in FIG. There is a possibility that the counter value for the pair takes a fairly large value, but the magnitude relationship alternately changes, so that it stays here as a synchronization point, and continues to be mis-synchronized and communication becomes impossible.
In addition, in order to solve the above problems, the control method in which the correlation is always observed for all timings and the maximum point is the synchronization timing, the circuit portion that does not contribute to synchronization maintenance is always operating, It will consume useless electric power. In addition, even though the power consumption increases even with an increase in transmission speed, it is not preferable in terms of the circuit configuration to increase the power consumption.
The present invention improves the above-mentioned drawbacks of the prior art (Japanese Patent Laid-Open No. 06-232931), and can cope with a higher-speed data transmission system and can maintain synchronization even when the frequency is deviated. An object of the present invention is to provide a low power consumption digital demodulator capable of obtaining a signal.
[0012]
[Means for Solving the Problems]
In order to achieve the above-mentioned object, the present invention determines a synchronous timing point from delay detection means for obtaining a detection signal X, Y by delay detection of a modulated wave, and detection signals X, Y from the delay detection means. Synchronizing means for outputting a timing clock signal for each symbol period based on the synchronization timing point, and binary data by determining basic data from the detection signal from the delay detecting means based on the timing clock signal from the synchronizing means. A digital demodulator having data identifying means for demodulating the signal into a column signal, wherein the synchronizing means is a plurality of preset levels of detection signals X and Y output from the delay detecting means for each symbol period. Each sampling point is sampled, and in the initial state (asynchronous state), two adjacent extraction points are identified. Sampled signal as Mutual , A means for adding the detected correlation for each set of extraction points corresponding to X and Y, an accumulating means for accumulating each of the added correlations for a plurality of symbols, and the accumulating One extraction point in which one of sampling data of a correlation determination unit that performs correlation determination from the correlation value obtained and captures initial synchronization and an extraction point pair that exhibits the maximum correlation based on the output of the correlation determination unit is set in advance Shift means for shifting the sampling period of the correlation detection means so as to be output at (timing point), A threshold value for restricting the shift operation in the shift means is preset, In the state where the synchronization is acquired, correlation detection is performed only at two sampling points on both sides of the central point, accumulation is performed over a plurality of symbols, and synchronization is maintained based on the detection. It is characterized in that the operation other than the part is stopped.
Another feature of the present invention is that the synchronizing means further comprises threshold value determining means for changing the threshold value based on a value of Eb / No corresponding to noise.
Another feature of the present invention is that the synchronizing means further comprises period value determining means for changing a period for accumulating autocorrelation based on a value of Eb / No corresponding to noise.
Another feature of the present invention is that the synchronizing means further comprises computer means having a learning mode for changing the threshold value based on the value of Eb / No corresponding to noise and finding the optimum threshold value by itself. That is.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described based on illustrated embodiments.
FIG. 1 is a block diagram showing the configuration of a first embodiment of a digital demodulator according to the present invention.
As shown in FIG. 1, the digital demodulator includes a first synthesizer 25 and a second synthesizer 25 to which a modulated wave is input and a signal having a frequency equal to the carrier wave ωC and a signal shifted by π / 2 are input. 26, the first and second low-pass filters 5, 6 connected to the first and second combiners 25, 26, respectively, and the first and second low-pass filters 5, 6 connected to the first and second combiners 25, 26, respectively. The first and second A / D converters 7 and 8, the delay detection circuit 9 connected to the first and second A / D converters 7 and 8, and the delay detection circuit 9 The first and second data identification units 11 and 12, the delay detection circuit 9 and the synchronization unit 41 connected to the first and second data identification units 11 and 12, and the digital connected to the synchronization unit 41 Oscillator 42, and the first and second devices described above. And a parallel / serial converter 14 connected to the data identification units 11 and 12.
[0014]
FIG. 2 is a block diagram showing an internal configuration of the synchronization unit 41.
As shown in FIG. 2, the synchronizer 41 includes first and second serial / parallel conversion circuits 43 and 44 for receiving detection signals X and Y from the delay detection circuit 9, and the first and second XOR gate group 49 connected to the serial / parallel conversion circuits 43 and 44, an adder group 50 connected to the XOR gate group 49, a counter group 45 connected to the adder group 50, and the counter A correlation determination circuit 46 connected to the group 45; a synchronization holding circuit 47 connected to the counter group 45 and the correlation determination circuit 46; a clock generation circuit 47 connected to the correlation determination circuit 46 and the synchronization holding circuit 47; have.
The synchronization holding circuit 47 is not connected to all the counters of the counter group 45, and is connected only to a predetermined number (four in this case) of counters at the sample timing as will be described later. It is like.
[0015]
Next, the operation of the digital demodulator will be described. The phase-modulated wave is synthesized by a signal having a frequency equal to the carrier wave ωC and a signal obtained by shifting the phase-modulated wave by π / 2 by the first and second combiners 25 and 26. These are baseband signals of I channel and Q channel, respectively. The I and Q signals are digitized by first and second A / D converters 7 and 8 via first and second low-pass filters 5 and 6, respectively.
Based on the relationship shown in FIG. 8 (b), the digitized signals I and Q are detected by the delay detection circuit 9 in the signal point arrangement difference from the signal preceding one symbol, that is, the phase difference ΔΦ. Decrypt into Y.
The detection signal from the delay detection circuit 9 is output to the data identification units 11 and 12 and the synchronization unit 41.
The synchronization unit 41 samples the levels of the detection signals X and Y output from the delay detection circuit 9 at a plurality of extraction points set in advance for each symbol period, and is in an initial state (asynchronous state). For example, the correlation between signals sampled by using two adjacent extraction points as a set is detected, and the detected correlation is added for each set of extraction points corresponding to X and Y, and each of them is accumulated for a plurality of symbols. The correlation is determined above and initial synchronization is captured.
Further, in a state where synchronization is acquired, correlation detection and accumulation over a plurality of symbols are performed only at two extraction points on both sides of the central point, and the timing of the symbol clock is adjusted based on this to maintain synchronization. On the other hand, a signal VCOcont is output to control the digital oscillator 42 in order to follow the frequency shift. The digital oscillator 42 is a so-called VCO (voltage controlled oscillator) capable of controlling its frequency by an external voltage input, and a clock output from this is not shown in detail, but the A / D converter 7 is not shown. , 8, the delay detection circuit 9, the synchronization unit 41, and the P / S circuit 14 are the reference for operation.
[0016]
In FIG. 2, S / P (Serial / Parallel Conversion) circuits 43 and 44 each have a number of registers obtained by adding 1 to the number of a plurality of extraction points set in advance for each symbol period, and the interval between the extraction points. Two extractions adjacent to the correlation detection circuit constituted by the XOR gate group 49 in the subsequent stage are shifted for each symbol period outputted by the clock generation circuit 48 by shifting the respective inputs X and Y for each corresponding delay time τ. This is for realizing correlation detection at a later stage by inputting points as a set.
After the XOR gate group 49 obtains the correlation between a plurality of extraction points set in advance for each symbol period of X and Y output from the S / P circuits 43 and 44, the X and Y What is added by the adder group 50 for each extraction point with respect to the correlation at the same timing is added by the counter group 45. A value accumulated over a plurality of symbol periods output from the counter group 45 is a correlation value, and based on this, the correlation determination circuit 46 captures symbol synchronization and captures symbol synchronization in the initial state. Then, in order for the synchronization holding circuit 47 to maintain synchronization, the clock generation circuit 48 is controlled so that a clock synchronized with the symbol is output therefrom.
[0017]
For the correlation determination circuit 46, based on the correlation value output from the correlation detection circuit, for example, the fifth bit of the S / P circuit (that is, the timing of P5 in FIG. 12) comes to the highest point of the correlation. The clock generation circuit 48 is configured to be controlled. Further, it is determined that synchronization has been acquired when the correlation value at the synchronization point falls below a preset threshold value. In this case, a flag is output to shift to the synchronization holding state. Then, the correlation determination circuit 46 stops its operation to reduce power consumption.
In the synchronization holding state, only two correlation values are used on both sides of the point which is the symbol synchronization timing for synchronization holding. That is, in FIG. 3, if the number of preset extraction points is set to 8, the correlation value between timings P1 and P2 is A1, the correlation value between P2 and P3 is A2,..., P8 and the next P1 Assuming that the correlation value is A8, the synchronization is captured so that the point P5 is the symbol synchronization point, but the two correlation values on both sides are A3, A4, A5, and A6. As can be seen from the above description, these relationships should satisfy A3 ≧ A4, A4 = A5, and A5 ≦ A6. The equals appearing in relation to A3, A4 and A5, A6 are those when there is no noise.
[0018]
Therefore, in the present invention, this relationship is used to maintain synchronization with low power consumption. First, when a synchronization acquisition completion flag is output from the correlation determination circuit 46, operations other than those necessary for maintaining synchronization are stopped in order to reduce power consumption. That is, each of the S / P circuits 43 and 44 outputs only signals related to synchronization holding, that is, signals P3 to P7 necessary for accumulating the correlation values A3 to A6 of FIG. However, only those corresponding to A3 to A6 perform the count-up operation, and the others are stopped. Furthermore, the synchronization holding circuit 47 stops operating until the flag is output, and the operation is not started until the flag is output.
The synchronization holding circuit 47 performs the following control on the demodulation timing using only the correlation values A3 to A6 output from the predetermined counter 45 connected as described above. First, when the relationship of A3 ≧ A4 is reversed, that is, when A3 <A4, the value of | A3−A4 |, that is, where | · | represents the absolute value of • A3 When the difference between A4 and A4 exceeds a preset threshold value (which varies depending on the number of accumulated symbols), it is assumed that the synchronization point has shifted to P4 from P5. The circuit 48 is controlled so that P5 comes to the position of P4 in the current situation from the next symbol timing.
[0019]
The threshold value is provided here to prevent the synchronization point from being switched too frequently. The relationship between A5 and A6 is also observed at the same time, and control is performed in the same manner as described above (in this case, the synchronization point is shifted toward P6). Also, in the unlikely event that a contradiction of relations occurs at the same time, that is, A3 <A4, A5> A6, and when each exceeds the threshold value, the difference is moved to a smaller one.
The relationship of A4 = A5 is handled by controlling the digital oscillator 42 because P5 is considered to deviate from the true symbol timing by a value smaller than the time τ if it does not hold.
Specifically, when the value of | A4-A5 | exceeds a certain threshold value, if A4-A5 is negative, it is considered that the synchronization point is shifted to P4 from P5. The value of VCOcont is adjusted to reduce the frequency of 42. When A4-A5 is positive, the value of VCOcont is adjusted to increase the frequency of the digital oscillator 42. However, when a situation occurs in which the sample timing is changed as described above, the value of VCOcont is left as it is.
By performing such control, it is possible to determine on the spot whether the synchronization point is shifted, whether it is a timing point shift or a smaller symbol frequency shift. Since the deviation can be corrected from the next symbol, it is possible to cope with a high-speed data transmission system in which a frequency and phase deviation is likely to occur.
[0020]
On the other hand, the detection signals X and Y output from the delay detection circuit 9 are input to the data identification units 11 and 12, and the data identification units 11 and 12 detect the detection signals based on the timing clock signal generated by the correlation determination circuit 46. X and Y are decoded. The decoded signal is demodulated into a data string by the parallel / serial converter 14.
As described above, according to the present embodiment, the delay detector 9 also operates only at the timing points P3 to P7 necessary for synchronization holding when in the synchronization holding state, that is, when the flag is output from the correlation determination circuit 46. Since the control is performed to stop at other timings, the power consumption can be further suppressed.
Also, in the correlation detection circuit, the number of symbols accumulated in the counter group 45 takes into account the difference between the characteristics of synchronization acquisition and synchronization retention, and if the accumulation is longer than the acquisition, the faster synchronization acquisition. Stable synchronization can be achieved.
Further, if the timing holding point is controlled in the synchronization holding circuit 47 with a longer cycle than the control of the control signal VCOcont to the digital oscillator 42, a more stable synchronization holding state can be obtained.
[0021]
Next, a second embodiment of the digital demodulator according to the present invention will be described with reference to FIGS.
FIG. 4 is a block diagram showing a configuration of a synchronization unit in the second embodiment of the digital demodulator according to the present invention. The configuration of the other digital demodulator is the same as that of the first embodiment shown in FIG.
In the second embodiment, the threshold value or the period for accumulating the autocorrelation for the synchronization point switching determination in the first embodiment described above is a value (E _b / N _o ) Is changed according to the size of
That is, in the first embodiment, E _b / N _o Since the noise increases with respect to the signal at a small value, the synchronization point is frequently switched when the threshold value is small. For this reason, when the threshold value is small, the bit error rate BER at that time is inferior to the original ability value.
Conversely, E _b / N _o When the threshold value is large, if the threshold value is large, the timing is not easily corrected even if a synchronization shift occurs, and the bit error rate BER is still inferior to the original ability value.
In other words, whether the threshold value is large or small, E _b / N _o In order to avoid the occurrence of deterioration depending on the value of the second embodiment, the second embodiment is as described above.
[0022]
In the second embodiment, the overall configuration of the digital demodulator is the same as that in FIG. 1 (first embodiment). However, as shown in FIG. 4, the configuration of the synchronization unit 41 in FIG. Is different.
That is, as shown in FIG. 4, the synchronization unit 41 of the second embodiment further includes thresholds connected to the correlation determination circuit 46 and the synchronization holding circuit 47 in addition to the synchronization unit 41 of the first embodiment shown in FIG. 2. The value determination circuit 52 is added.
As an operation, the threshold value determination circuit 52 performs an E corresponding to the noise level from the autocorrelation signal from the correlation determination circuit 46. _b / N _o Get the signal and its E _b / N _o An optimum threshold value corresponding to the magnitude of the signal is determined and sent to the synchronization holding circuit 47. FIG. 5 shows the bit error rate BER and autocorrelation with E on the horizontal axis. _b / N _o , The vertical axis is an error rate (in the case of autocorrelation, the difference rate from the horizontal timing) and is plotted. From this graph, the autocorrelation shows the E _b / N _o It can be seen that can be estimated.
The synchronization holding circuit 47 determines synchronization point switching based on the determined optimum threshold value.
In determining the optimum threshold value, noise (E _b / N _o ) In an environment with a large amount of noise (E _b / N _o ) So that the timing always follows in a small environment. _b / N _o And a threshold value optimum at that time are obtained by experiments in advance and a table is prepared and determined from the table.
In the above embodiment, E _b / N _o However, as a modified example, a period value determining circuit is provided in place of the threshold value determining circuit, and E _b / N _o It is also possible to obtain the period for accumulating the optimum autocorrelation from the values of the values and perform the correlation determination in synchronization with accumulating the optimum autocorrelation.
According to this second embodiment, noise (E _b / N _o ) In an environment with a large amount of noise (E _b / N _o ) Can be controlled so as to always follow the timing.
[0023]
Next, a third embodiment of the digital demodulator according to the present invention will be described with reference to FIG.
As in the second embodiment, E _b / N _o By changing the threshold value or the synchronization for accumulating the autocorrelation, the appropriate timing control is performed. However, it is also conceivable that the optimum threshold value at that time changes depending on the conditions such as fading even with the same cumulative number of autocorrelation.
Under such various conditions, it has been difficult to create a circuit that always demodulates at the optimum timing by hardware.
Therefore, in the third embodiment, E is calculated using autocorrelation. _b / N _o And the corresponding threshold value, or the period for accumulating the autocorrelation
By changing dynamically, control such that synchronization is always maintained at an optimal timing is performed by software such as a CPU and a DSP, thereby enabling finer timing control.
In the third embodiment, the overall configuration of the digital demodulator is the same as that in FIG. 1 (first embodiment). However, as shown in FIG. 6, the configuration of the synchronization unit 41 in FIG. Is different.
That is, as shown in FIG. 6, the synchronization unit 41 of the third embodiment is further connected to the correlation determination circuit 46 and the synchronization holding circuit 47 in addition to the synchronization unit 41 of the first embodiment shown in FIG. The CPU 53 is added.
As an operation, the control CPU 53 determines the E level corresponding to the noise level from the autocorrelation signal from the correlation determination circuit 46. _b / N _o Get the signal and its E _b / N _o An optimum threshold value corresponding to the magnitude of the signal is determined and sent to the synchronization holding circuit 47.
[0024]
The synchronization holding circuit 47 determines synchronization point switching based on the determined optimum threshold value.
In determining the optimum threshold value, the number of accumulated autocorrelation differences and the E _b / N _o , E _b / N _o Value and the optimum threshold value at that time are obtained in advance by experiment, and the correspondence between the cumulative difference number of autocorrelation and the optimum threshold value at that time is made. The optimum threshold value is set based on the number, and further, the result of channel quality estimation and the like in the upper layer is reflected in the determination of the threshold value. That is, if the channel state estimation is not successful, the CPU 53 finds the optimum value by moving the threshold value using the cumulative difference in autocorrelation and the channel quality estimation result in the upper layer as parameters. It has a learning mode.
According to the third embodiment, as described above, the threshold value is controlled by software such as a CPU and a DSP, and the intelligence can be easily realized by software. This configuration allows more flexible and fine-grained control, and always performs demodulation at the optimal timing in any environment, such as noisy environments, fading environments, or combinations of these. As a result, the average bit error rate BER is improved.
[0025]
【The invention's effect】
As described above, the present invention performs finer timing control as compared with the conventional configuration, so that power consumption can be reduced and it is easy to follow frequency and phase shift in a high-speed data transmission system. is there.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a first embodiment of a digital demodulator according to the present invention.
FIG. 2 is a diagram showing an internal configuration of a synchronization unit shown in FIG. 1;
FIG. 3 is a diagram showing input / output characteristics of the XOR gate shown in FIG. 2;
FIG. 4 is a block diagram showing a configuration of a second embodiment of a digital demodulator according to the present invention.
FIG. 5 E _b / N _o It is a graph showing the relationship between BER and autocorrelation rate.
FIG. 6 is a block diagram showing a configuration of a third embodiment of a digital demodulator according to the present invention.
FIG. 7 is a block diagram showing a basic configuration of a conventional π / 4 shift QPSK modulator.
8A and 8B are diagrams for explaining the π / 4 shift QPSK modulation method shown in FIG.
FIG. 9 is a block diagram showing a basic configuration of a conventional demodulator.
10 is an eye pattern diagram of a detection signal in the demodulator shown in FIG. 9. FIG.
11 is a diagram for explaining conventional phase shift predicting means in the demodulator shown in FIG. 9. FIG.
12 is a diagram for explaining a relationship between an eye pattern of a detection signal and an extraction point in the demodulating apparatus illustrated in FIG. 9;
FIG. 13 is a block diagram showing a configuration of an embodiment of a digital demodulator in Japanese Patent Laid-Open No. 06-232931.
14 is a diagram showing a configuration of a correlation detection circuit shown in FIG. 13;
15 is a diagram showing input / output characteristics of the XOR gate shown in FIG. 14;
[Explanation of symbols]
9 ... Delay detection circuit, 10 ... Timing point,
11, 12 ... Data identification unit, 13 ... Clock recovery circuit,
15 ... Zero cross point, 16 ... Clock recovery circuit,
17 ... correlation detection circuit, 18, 46 ... correlation determination circuit,
21 ... XOR gate, 24 ... counter,
41 ... Synchronizer circuit,
43, 44 ... serial / parallel converter, 45 ... counter group,
47: Synchronization holding circuit, 48: Synchronization clock generating circuit,
49 ... XOR gate group, 50 ... adder group,
52 ... Threshold value determination circuit, 53 ... Control CPU

Claims (4)

A delay detection means for delay-detecting the modulated wave to obtain detection signals X and Y;
Synchronization means for determining a synchronization timing point from the detection signals X and Y from the delay detection means, and outputting a timing clock signal for each symbol period based on the synchronization timing point;
A digital demodulator having data identification means for determining basic data from a detection signal from the delay detection means based on a timing clock signal from the synchronization means and demodulating it into a binary data string signal;
The synchronization means samples the levels of the detection signals X and Y output from the delay detection means at a plurality of extraction points set in advance for each symbol period,
In an initial state (asynchronous state), a gate means for detecting a correlation between signals sampled by setting two adjacent extraction points as a set;
Adding means for adding the detected correlation for each set of extraction points corresponding to each of X and Y;
Accumulating means for accumulating each of the added correlations for a plurality of symbols;
Correlation determination means for performing correlation determination from the accumulated correlation value and capturing initial synchronization;
The sampling period of the correlation detection means is set so that the sampling data of any one of the extraction point pairs exhibiting the maximum correlation based on the output of the correlation determination means is output at one preset extraction point (timing point). Shift means for shifting;
Comprising
A threshold value for restricting the shift operation in the shift means is set in advance, and in the state where the synchronization is captured, correlation detection is performed only at two extraction points on both sides of the central point, and accumulation over a plurality of symbols is performed. A digital demodulating apparatus characterized in that synchronization is held based on this, and operations other than those necessary for the synchronization holding are stopped. 2. The digital demodulator according to claim 1 , wherein the synchronizing means further comprises threshold value determining means for changing the threshold value based on a value of Eb / No corresponding to noise. 2. The digital demodulator according to claim 1 , wherein said synchronizing means further comprises period value determining means for changing a period for accumulating autocorrelation based on a value of Eb / No corresponding to noise. 2. The computer according to claim 1 , wherein the synchronizing means further comprises computer means having a learning mode for changing the threshold value based on a value of Eb / No corresponding to noise and finding the optimum threshold value by itself. The digital demodulator according to 1.

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