JP2001086178A - Digital demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute correspondence to a data transmission system at higher speed, to hold synchronization in spite of a deviation in frequency and to obtain an excellent demodulating signal by low power consumption by stopping an operation in a part except the one required for holding the synchronization. SOLUTION: Mutually adjacent correlations in a plurality of previously set extraction points at every symbol period in X and Y outputted from serial/ parallel(S/P) circuits 43 and 44 are obtained by an XOR gate group 49 and, then, the correlations which are respectively added by an adder group 50 at every extraction point are respectively added in a counter group 45 concerning the same timing correlations of X and Y. Values accumulated over the plurality of symbol periods, which are outputted from the counter group 45, are relative values. Then the S/P circuits 43 and 44 respectively outputs only signals related to synchronization holding, that is, the signals required for accumulating the relative values, only counters corresponding to the relative values execute a count-up operation in the counter group 45 and the other ones stop operating.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital demodulator for demodulating a modulated wave modulated by a digital signal,
The present invention relates to a digital demodulator for asynchronously demodulating an angle-modulated wave modulated by differential encoding.

[0002]

2. Description of the Related Art In general, as a modulation / demodulation method of a digital signal, an amplitude modulation method in which the amplitude of a carrier is changed according to a state value of the digital signal, and a so-called angle modulation method in which a phase or a frequency is changed are well known. ,
In the field of digital mobile communication, it is common to use an angle modulation method that is not easily affected by amplitude distortion in a transmission path. First, π / 4 shift quadrature phase modulation (π / 4 shift QPS) which has excellent distortion resistance and is suitable for mobile communication
K) The method will be briefly described as an example. FIG. 7 shows a π / 4 shift Q
FIG. 3 is a block diagram illustrating a basic configuration of a PSK modulation device. The serial / parallel converter 1 converts the input digital binary data sequence into unit data (X, Y) having two bits as a set. This unit data is generally called one symbol,
The process proceeds as one cycle. The differential encoding circuit 2 generates a baseband signal composed of an I channel and a Q channel in which information of (X, Y) is assigned to a change (difference) of the signal, and the baseband signal is a low-pass filter. The band is limited by (LPF) 3 and 4. Then
The amplitude modulation is performed by multiplying the in-phase and quadrature components of the carrier ωC by the band-limited baseband signal, and then combining the two to obtain a modulated wave. Note that π
In the / 4 shift QPSK system, amplitudes “A” and “−A” are assigned according to binary signals “1” and “0”, and four signal point data (I, Q) are given for one symbol.
It is based on a four-phase phase modulation (QPSK) system that performs phase modulation based on this.

FIG. 8 shows a signal point arrangement of I and Q.
As shown in (a), QPSK indicated by black dots in the figure for each symbol
And the signal point arrangement indicated by white points in the figure, which is obtained by shifting the signal point by π / 4, is used to perform phase modulation. Therefore, the phase difference ΔΦ from the preceding symbol is always an odd multiple of π / 4, and the input unit data (X,
The relationship with Y) can be expressed in FIG. As described above, the angle modulation has been briefly described. As a method of demodulating a modulated wave, a synchronous detection method and a delay detection method are well known.
Theoretically, the synchronous detection method has better characteristics,
It is rather disadvantageous under the condition that high-speed fading is likely to occur. In digital mobile communication, in which abrupt phase fluctuation is likely to occur, the delay detection method which has better characteristics than the synchronous detection method is suitable. The delay detection is to detect the next modulation wave with reference to the modulation wave delayed by a delay circuit having a predetermined delay time, so that the modulation wave modulated by the differentially encoded signal as described above is used. It is necessary to be. Further, since carrier wave regeneration is not required and the configuration is simpler than synchronous detection, it is suitable for mobile communication. For example, in the case of the above-mentioned π / 4 shift QPSK, the phase difference ΔΦ between the two is determined by detecting the next modulated wave with reference to the phase of the modulated wave preceding one symbol, and this is decoded according to FIG. do it.

FIG. 9 is a block diagram showing an example of a conventional digital demodulator for demodulating a π / 4 shift QPSK modulated wave by using delay detection. The phase-modulated wave becomes a baseband signal of the I channel and the Q channel by a signal having the same frequency as the carrier ωC and a signal obtained by shifting the carrier by π / 2, respectively. The I and Q signals are passed through low-pass filters 5 and 6, respectively, to an analog / digital converter (A
/ D) digitized in 7 and 8. The digitized signals I and Q are detected by a differential detection circuit 9 to detect a difference in signal point arrangement from a signal preceding by one symbol, that is, a phase difference ΔΦ, and based on the relationship shown in FIG. Decode to Y. The detection signal from the delay detection circuit 9 is output to the data identification units 11 and 12 and the clock recovery circuit 13. The clock recovery circuit 13 determines a timing point to be described later, and supplies a timing clock signal to the data identification units 11 and 12 every symbol period based on the timing point. The data discriminators 11 and 12 determine basic data (X, Y) from the detection signal based on the timing clock signal, and the basic data (X, Y) is converted into binary data before modulation by the parallel / serial converter 14. The signal is demodulated into a column signal.

FIG. 10 shows an eye pattern obtained by overwriting the detection signal from the X-side output terminal of the delay detection circuit 9 a plurality of times, wherein the binary signal (X =) 1 or 0 is determined. In general, the signal level at the most open point (timing point) 10 is identified as demodulated data of each symbol. A very important point in the above demodulation process is how to determine the timing point. Conventionally, a clock recovery circuit determines the timing point and generates a timing clock signal. Is generally a zero-crossing detection method.
A detection signal is taken out from one output terminal of the first and second detection points, and a point crossing zero (a predetermined level located substantially in the middle of the binary level), that is, a zero cross point indicated by 15 in FIG. A position 10 shifted by a half symbol period is obtained, and this is output to the data identification units 11 and 12 as a timing point signal.
However, the clock recovery circuit that detects the timing point using the zero cross point as described above is
As is apparent from the shape of the eye pattern in FIG. 10, the point where the data actually crosses zero is indicated by an arrow Δ in the figure.
Since it is distributed over a wide range as shown by t, it was difficult to find an accurate zero cross point. In other words, if a position simply shifted from the zero cross point by a half symbol period is used as a timing point, the point where the eye is most open deviates from a desired position, and the rate of occurrence of bit errors increases. A large number of zero-cross points are read and the median thereof is determined, and this is taken as a true zero-cross point. However, there is a defect that it takes time until this is determined. In particular, in a system such as a digitization system for wireless communication, in which a communication channel is frequently switched and the timing point needs to be set each time, this is a very serious drawback.

On the other hand, in Japanese Patent Laid-Open Publication No. 03-205940 proposed with digital radio in mind, I and Q signal points of a baseband signal obtained by quasi-synchronous detection of a preceding modulated wave are represented by I and Q, respectively. The position on the Q coordinate axis is detected, and if the signal point is deviated from a predetermined signal point arrangement, the delay time of the detection circuit is changed and the phase is changed so that the original position is predicted and corrected. A method of performing synchronization correction by shifting has been proposed.
For example, if the detected signal point is located at the position indicated by the point X in FIG. 11, the X point is a predetermined signal point arrangement indicated by a black point in FIG. And the amount of phase shift is determined. However,
In this method, when the deviation of the initial timing point is remarkable, there is a high possibility that erroneous correction is repeated every time one symbol is detected, and it takes a long time to complete synchronization. As a solution to the above problems, the demodulation timing point is detected in a short time,
SUMMARY OF THE INVENTION An object of the present invention is to provide a digital demodulator capable of obtaining a good demodulated signal.
Publication was proposed. In the following, JP-A-06-23
No. 2931 will be described with reference to the drawings.

As is apparent from the eye pattern shown in FIG. 10, at the timing point 10 where the eye is most open, the level of the detection signal becomes a or -a (X = 1 or 0) where the level of the detection signal is concentrated at a relatively high density. In the vicinity, the level is almost the same as the timing point 10 in most cases. Conversely, as the distance from the timing point 10 approaches the zero cross point 15, the probability that the levels do not match increases. That is, when a plurality of extraction points are set for the detection signal for one symbol period, the signal levels at the extraction points are sampled, and the correlation between the signal levels of two adjacent extraction points is obtained.
The correlation increases near the timing point where the signal levels match, and decreases when the signal levels of the two extraction points are different. In other words, 10 in FIG.
The correlation between the sampling values at the point
It at point 5 becomes smaller. Focusing on this point, the correlation is detected, and the magnitude is compared to detect the timing point, thereby obtaining a good demodulated signal.

More specifically, as shown in FIG. 12, the signal level is sampled at predetermined extraction points (8 points per symbol in FIG. 12) every symbol period, and sampling of adjacent extraction points is performed. After sequentially detecting correlations between the data, P1 and P2, P2 and P3,..., The magnitudes of the correlation data are compared, and an extracted point pair (corresponding to a pair of P4 and P5 in FIG. Alternatively, one of the extracted point pairs is set as a timing point. FIG. 13 is a block diagram showing a configuration of an embodiment of a digital demodulator disclosed in Japanese Patent Application Laid-Open No. H06-229331.
7 and a correlation determination circuit 18. Correlation detection circuit 1
7 samples the levels of the detection signals X and Y output from the delay detection circuit 9 at a plurality of extraction points set in advance for each symbol period, and sets a pair of two adjacent extraction points. The correlation between the sampled signals is detected, the detected correlations are added for each pair of extraction points corresponding to X and Y, and each is accumulated for a plurality of symbols and output to the correlation determination circuit 18. .

FIG. 14 is a block diagram showing a specific configuration example of the correlation detection circuit 17. In the figure, a delay circuit 1
9 and 20 both have a delay time τ corresponding to the interval between the extraction points. The XOR (exclusive OR) gates 21 and 22 are directly connected to one input terminal and the delay circuit is connected to the other input terminal. By detecting the detected signals X and Y via 19 and 20, the correlation with the immediately preceding extraction point is detected. Then, the two correlation data are added and output to a plurality of counters 24 via a multiplexer 23 for distributing the data at a period τ. The counter 24 accumulates correlation data for a predetermined plurality of symbols.
The correlation determination circuit 18 compares the magnitudes of the correlation data stored in the counter 24 to detect a set of extraction points having the highest correlation, determines one of the extraction points as a timing point, and based on the timing point, Generate a timing clock signal. As is well known, the XOR gate has input / output characteristics as shown in FIG. 15, so that when the correlation is large (when the input levels match)
When "0" is small (when input levels do not match)
Output "1". Therefore, the closer the value stored in the counter is to 0, the higher the correlation point, so that the correlation determination circuit 18 at the next stage may be configured to obtain the minimum value from a plurality of inputs. On the other hand, the detection signals X and Y output from the delay detection circuit 9 are
The data identification units 11 and 12 decode the detection signals X and Y based on the timing clock signal generated by the correlation determination circuit 18. The decoded signal is demodulated by a parallel / serial converter 14 into a data string. Conventionally, the timing point is predicted based on an unstable point such as a zero cross point, but in the above example, the timing point at which the eye of the eye pattern, which is a relatively stable point, is the most open is obtained directly. However, it is strong against a rapid phase shift due to fading or the like, and it is possible to determine a timing point in a short time for a large phase shift.

[0010] In addition, as a second embodiment in Japanese Patent Application Laid-Open No. H06-229331, a phase modulation wave converted into an intermediate frequency (IF) is demodulated. The description is omitted because it is in principle unchanged from the first embodiment. The clock recovery circuit described in Japanese Patent Application Laid-Open No. H06-229331 described above performs a predetermined sampling on the decoded digital signal and takes a correlation between adjacent data, so that a timing point can be obtained in a short time. This method is effective in cases such as the above, and because it is a system that directly captures the point where the eye of the eye pattern is the most open, it is hardly affected by noise near the zero cross, and the timing point is set every time one symbol of the modulated wave is demodulated. Since it is updated, it follows the phase shift due to fading at a high speed.
However, if the timing point is updated every time one symbol of the modulated wave is actually demodulated, the point that is not a timing point such as a zero cross point happens to be synchronized due to noise etc. Since it looks like a timing, and errors increase rather, actually, an accumulation over a plurality of symbols is used for the synchronization point determination. After all, the method of clock recovery after pull-in in the clock recovery circuit described in JP-A-06-229331 described above is based on the extraction point pair with the maximum correlation, ie, the pair of P4 and P5 or the pair of P5 and P6 in FIG. , And one of the extracted point pairs is set as a timing point. That is, as a control method, a counter value accumulated over a plurality of symbol periods in a pair of P4 and P5 and a counter value of P5 and P6 The pair is compared with each other, and the timing of the reproduction clock is determined such that the synchronization point comes to the smaller value (the larger correlation). Even with this, if the symbol rate of the Japanese digital cellular phone PDC is about 21 Ksps, the timing can be sufficiently maintained.

[0011]

However, in recent years, the demand for data capacity of digital radios has been increasing, and the data transmission rate has tended to increase accordingly. An increase in data transmission rate leads to an increase in symbol rate,
That is, since the wavelength of one symbol becomes shorter, the phase shift due to the movement of the mobile communication device becomes relatively large even when the distance is equal, as compared with the case where the symbol rate is low. Then, as described above, in the control method in which only two extraction point pairs are compared after the pull-in and the synchronization is maintained, elements such as rapid movement and fading of the mobile communication device occur or overlap at a certain moment. As a result, when the phase changes greatly and the synchronization is shifted to the point of zero cross, that is,
In the case where there is a shift to the pair of P8 and P1 and the pair of P1 and P2 in FIG. 12, the value of the counter for each pair changes considerably while taking a considerably large value. Here, there is a possibility that the communication may remain as a synchronization point, continue erroneous synchronization, and become unable to communicate. In addition, in a control method that attempts to solve the above problem, always observes the correlation for all timings, and sets the maximum point as the synchronization timing, the circuit part that does not contribute to maintaining the synchronization always operates. Unnecessary power is consumed. In addition, it is not preferable in terms of circuit configuration to further increase the power consumption even though the power consumption is increasing as the transmission speed increases. The present invention relates to the above-mentioned prior art (Japanese Patent Laid-Open No. 06-232).
No. 931), a low power consumption digital demodulation which can cope with a higher speed data transmission system, maintain synchronization even when the frequency is shifted, and obtain a good demodulated signal. It is intended to provide a device.

[0012]

In order to achieve the above object, the present invention provides a delay detecting means for detecting a modulated wave by delay detection to obtain detection signals X and Y, and detecting signals X and Y from the delay detecting means. A synchronization means for determining a synchronization timing point and outputting a timing clock signal for each symbol synchronization based on the synchronization timing point, and a detection signal from the delay detection means based on the timing clock signal from the synchronization means. In a digital demodulation device having data discriminating means for determining basic data and demodulating it into a binary data string signal, the synchronizing means changes the level of the detection signals X and Y output from the delay detection means every one symbol period. Sampling at a plurality of extraction points set in advance, and adjacent in the initial state (asynchronous state). Gate means for detecting a correlation between signals sampled as a set of two extracted points to be extracted, adding means for adding the detected correlation to each of a pair of extracted points corresponding to each of X and Y, Accumulation means for accumulating each of the symbols for a plurality of symbols, correlation judgment means for making a correlation judgment from the accumulated correlation values and capturing initial synchronization, and an extraction point pair exhibiting the maximum correlation based on the output of the correlation judgment means. Shift means for shifting the sampling period of the correlation detection means so that one of the sampling data is output at one preset extraction point (timing point). Correlation detection at only two extraction points on both sides of the center point, over multiple symbols Performs cumulative, as well as to as to maintain synchronization based on it, is characterized by stopping the operation of the other parts necessary for the synchronization hold. Another feature of the present invention is that a threshold value for restricting a shift operation in the shift means is set in advance. Another feature of the present invention, the synchronization means is that provided with the threshold value determining means for varying the threshold value based on the value of the E _b / N _o for further corresponding to the noise. Another feature of the present invention, the synchronization means is that provided with the period value determination means for varying the period of accumulating the autocorrelation based on the value of the E _b / N _o for further corresponding to the noise. Another feature of the present invention is that the synchronization means includes:
Further, the present invention is provided with a computer means having a learning mode for changing the threshold value based on the value of E _b / N _o corresponding to noise and finding an optimum threshold value by itself.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on illustrated embodiments. FIG. 1 is a block diagram showing a configuration of a first embodiment of a digital demodulator according to the present invention. As shown in FIG. 1, this digital demodulation apparatus has a first and second signals to which a modulated wave is input and a signal having a frequency equal to the carrier ωC and a signal obtained by shifting the signal by π / 2 are input.
Combiners 25 and 26 and the first and second combiners 2
First and second low-pass filters 5 and 6 respectively connected to first and second low-pass filters 5 and 26, and first and second low-pass filters 5 and 6 connected to the first and second low-pass filters 5 and 6, respectively.
/ D converters 7 and 8, delay detection circuit 9 connected to the first and second A / D converters 7 and 8, and first and second data connected to delay detection circuit 9 Identification unit 1
1 and 12; a synchronization section 41 connected to the delay detection circuit 9 and the first and second data identification sections 11 and 12; a digital oscillator 42 connected to the synchronization section 41; It has a parallel / serial converter 14 connected to the second data identification units 11 and 12.

FIG. 2 is a block diagram showing the internal configuration of the synchronization section 41. As shown in FIG.
The first and second serial / parallel conversion circuits 43 to which the detection signals X and Y from the delay detection circuit 9 are input,
44, an XOR gate group 49 connected to the first and second serial / parallel conversion circuits 43 and 44, an adder group 50 connected to the XOR gate group 49, and a connection to the adder group 50 Counter group 45, a correlation determination circuit 46 connected to the counter group 45, a synchronization holding circuit 47 connected to the counter group 45 and the correlation determination circuit 46, a correlation determination circuit 46 and a synchronization holding circuit 47 And a clock generating circuit 47 connected to the Note that the synchronization holding circuit 47 is not connected to all the counters of the counter group 45, but is connected only to a predetermined number (in this case, four) of counters whose sample timing is an intermediate portion as described later. It is like.

Next, the operation of the digital demodulator will be described. The phase modulated wave is a signal having a frequency equal to the carrier ωC, a signal obtained by shifting the carrier by π / 2, and the first and second combiners 25 and 26. The signals are combined to become I-channel and Q-channel baseband signals. The I signal and the Q signal are digitized by first and second A / D converters 7 and 8 via first and second low-pass filters 5 and 6, respectively. The digitized signals I and Q are detected by a differential detection circuit 9 to detect a difference in signal point arrangement from a signal preceding by one symbol, that is, a phase difference ΔΦ, and based on the relationship shown in FIG. Decode to Y. The detection signal from the delay detection circuit 9 is transmitted to the data identification unit 1
1 and 12 and output to the synchronization unit 41. Synchronization unit 4
1 samples the levels of the detection signals X and Y output from the delay detection circuit 9 at a plurality of extraction points preset for each symbol period,
In the initial state (asynchronous state), two adjacent sampling points are set as a set to detect the correlation between the sampled signals, and the detected correlation is added for each of the corresponding sets of the X and Y extracted points. , Each of which is accumulated for a plurality of symbols, and a correlation determination is performed to capture initial synchronization. In a state where synchronization is captured, correlation detection and accumulation over a plurality of symbols are performed only at two extraction points on both sides of the center point, and the timing of the symbol clock is adjusted based on the correlation detection to maintain synchronization. On the other hand, it outputs a signal VCOcont to control the digital oscillator 42 in order to follow the frequency shift. The digital oscillator 42 is a so-called VCO whose frequency can be controlled by an external voltage input.
(Voltage-controlled oscillator). The clock output therefrom is not shown in detail, but is used as a reference for the operation of the A / D converters 7 and 8, the delay detection circuit 9, the synchronization section 41, and the P / S circuit 14. Has become.

In FIG. 2, the S / P (serial / parallel conversion) circuits 43 and 44 each have as many registers as the number obtained by adding 1 to a predetermined number of extraction points for each symbol period. The input X and Y are shifted for each delay time τ corresponding to the interval of, and are adjacent to the correlation detection circuit constituted by the XOR gate group 49 at the subsequent stage for each symbol period output from the clock generation circuit. This is for realizing correlation detection at a later stage by inputting two extraction points as one set. The XOR gate group 49 calculates adjacent correlations of a plurality of preset extraction points for each symbol period of X and Y output from the S / P circuits 43 and 44, and then calculates X and Y values. What is added by the adder group 50 for each extraction point for the correlation of the same timing is added by the counter group 45. The value accumulated over a plurality of symbol periods output from the counter group 45 is a correlation value, and based on the correlation value, the correlation determination circuit 46 captures symbol synchronization and captures symbol synchronization in an initial state. Then, the clock generation circuit 48 is controlled so that a clock synchronized with the symbol is output from the clock generation circuit 48 so that the synchronization holding circuit 47 maintains the synchronization.

For the correlation judgment circuit 46, based on the correlation value output from the correlation detection circuit, for example, the fifth bit of the S / P circuit (ie, the timing of P5 in FIG. 12) is added to the point having the highest correlation. Is configured to control the clock generation circuit 48 so that When the correlation value at the synchronization point falls below a preset threshold value, it is determined that synchronization has been acquired. In this case, a flag is output to shift to the synchronization holding state. Then, the correlation judging circuit 46 stops its operation to reduce power consumption. In the synchronization holding state, only two correlation values are used on both sides of a point used as a symbol synchronization timing for holding synchronization. That is, in FIG. 3, the preset number of extraction points is 8
Assuming that the correlation value between timings P1 and P2 is A1, the correlation value between P2 and P3 is A2,..., And the correlation value between P8 and the next P1 is A8, the point of P5 is now Synchronization was captured as if it were a symbol synchronization point, but the two correlation values on each side are A3,
A4, A5, and A6. As can be understood from the above description, A3 ≧ A4, A4 = A5, A5 ≦ A
It should be 6. Equals appearing in the relationship of A3, A4 and A5, A6 are when there is no noise.

Therefore, in the present invention, synchronization is maintained with low power consumption using this relationship. First, when a flag indicating completion of synchronization acquisition is output from the correlation determination circuit 46, operations other than those required for maintaining synchronization are stopped in order to suppress power consumption. That is, the S / P circuits 43 and 44 output only the signals related to the synchronization holding, that is, the signals P3 to P7 necessary for accumulating the correlation values A3 to A6 in FIG. A3
Only those corresponding to .about.A6 perform the count-up operation and stop the others. Further, the operation of the synchronization holding circuit 47 is stopped until the flag is output, and the operation is started only after the flag is output. The synchronization holding circuit 47 performs the following control on the demodulation timing using only the correlation values of A3 to A6 output from the predetermined counter 45 connected as described above. First,
When the relationship of A3 ≧ A4 is reversed, that is, A3
In the case of <A4, the value of | A3-A4 |, that is, if | · | represents the absolute value of
If the difference between A3 and A4 exceeds a predetermined threshold value (which depends on the number of accumulated symbols), it is determined that the synchronization point is shifted to P4 as viewed from P5, The generation circuit 48 is controlled so that P5 comes to P4 in the current situation from the next symbol timing.

The reason for setting the threshold value here is to prevent the synchronization point from being switched too frequently. The relationship between A5 and A6 is also observed at the same time, and control is performed in the same manner as described above (in this case, the synchronization point is shifted to P6). Also, if contradictions occur simultaneously, that is, A3 <A4,
A5> A6, and when each exceeds the threshold value, the difference is moved to a smaller one.
If the relation A4 = A5 is not satisfied, it is considered that P5 deviates from the true symbol timing by a value smaller than the time τ, and therefore, it is dealt with by controlling the digital oscillator 42. Specifically |
When the value of A4-A5 | exceeds a certain threshold value, when the value of A4-A5 is negative, the synchronization point becomes P4 from P5.
Therefore, the value of VCOcont is adjusted so that the frequency of the digital oscillator 42 is reduced. If A4-A5 is positive, the value of VCOcont is adjusted so that the frequency of the digital oscillator 42 is increased. However, when a situation such as changing the sample timing occurs as described above, VCOcont
Value remains as before. By performing such control, it is possible to determine on the spot whether the synchronization point is shifted, whether the timing point is shifted or the symbol frequency is shifted more minutely. Since the shift can be corrected from the next symbol, it is possible to cope with a high-speed data transmission system in which frequency and phase shifts easily occur.

On the other hand, the detection signals X and Y output from the delay detection circuit 9 are input to data identification sections 11 and 12, and the data identification sections 11 and 12 are based on the timing clock signal generated by the correlation determination circuit 46. To decode the detection signals X and Y. The decoded signal is supplied to the parallel / serial converter 1
At 4 the signal is demodulated into a data string. As described above, according to the present embodiment, when the synchronization is maintained, that is, when the flag is output from the correlation determination circuit 46, the delay detector 9 also operates only at the timing points P3 to P7 necessary for maintaining the synchronization. Is performed, and control is performed so as to stop at other timings, so that power consumption can be further suppressed. Also, in the correlation detection circuit, the number of symbols accumulated by the counter group 45 is taken into account by taking into account the difference between the characteristics of synchronization acquisition and synchronization holding, and if the accumulation is longer at the time of holding than at the time of acquisition, synchronization acquisition can be made faster. Stable synchronization can be maintained. Further, if the synchronization holding circuit 47 controls the timing point in a longer cycle than the control of the control signal VCOcont to the digital oscillator 42, a more stable synchronization holding state can be obtained.

Next, a digital demodulator according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a block diagram illustrating a configuration of a synchronization unit in a digital demodulation device according to a second embodiment of the present invention. The configuration of the other digital demodulation devices is the same as that of the first embodiment shown in FIG. In the second embodiment,
Is obtained by the manner is changed according to the magnitude of the value corresponding to the noise period for accumulating the threshold value or autocorrelation for synchronization point change judgment in the first embodiment described above (E _b / N _o). That is, in the first embodiment, since the noise increases relative to the signal where E _b / N _o is small, the synchronization point is frequently switched when the threshold value is small. For this reason, when the threshold value is small, the bit error rate BER at that time is inferior to the original ability value. Conversely, where E _b / N _o is large, if the threshold value is large, even if a synchronization shift occurs, it is difficult to correct the timing, and the bit error rate BER is also inferior to the original ability value. . That is, the second embodiment in order to avoid degradation by the value of E _b / N _o be taken smaller largely take the threshold value occurs is the manner described above.

In the second embodiment, the overall configuration of the digital demodulator is the same as that of FIG. 1 (first embodiment), but FIG.
As shown in FIG. 1, the configuration of the synchronization unit 41 in FIG.
This is different from the embodiment. That is, as shown in FIG.
The synchronization section 41 of the second embodiment has a configuration in which a threshold value determination circuit 52 connected to a correlation determination circuit 46 and a synchronization holding circuit 47 is added to the synchronization section 41 of the first embodiment shown in FIG. Has become. Then, as the operation, the threshold value determination circuit 52 obtains the E _b / N _o signal corresponding to the level of noise from the autocorrelation signal from the correlation determination circuit 46, the E _b / N _o signal magnitude The optimum threshold value is determined according to
Send to 7. Incidentally, FIG. 5, the bit error rate BER and autocorrelation, E _b / N _o on the horizontal axis, (in the case of auto-correlation difference rate between the lateral timing) error rate on the vertical axis in the graph was plotted taking There, from this graph, it can be seen that can estimate the E _b / N _o at that time from the autocorrelation. The synchronization holding circuit 47 determines whether to switch the synchronization point based on the determined optimum threshold value. In the determination of the optimum threshold value, the timing for small environment noisy (E _b / N _o) as much as possible to retain the timing lock once a large environment noise (E _b / N _o) and in the manner determined from the table in advance to create a table obtained in advance by experiment the value as the optimal threshold value at that time of E _b / N _o as always to follow. Further, in the above embodiment, although the manner obtaining an optimum threshold value from the value of E _b / N _o, as a variant, provided period value determining circuit in place of the threshold value determination circuit, E _b /
Obtains a value period to accumulate optimum autocorrelation from N _o, may be as a correlation determination synchronously to accumulate its optimal autocorrelation. According to the second embodiment, the noise (E _b /
In an environment with a large N _o ), it is possible to control so as to keep the timing once locked as much as possible, and in an environment with a small noise (E _b / N _o ) so as to always follow the timing.

Next, a digital demodulator according to a third embodiment of the present invention will be described with reference to FIG. The second
As embodiments, becomes as proper timing control is performed by changing the synchronizing of accumulating threshold value or autocorrelation by the value of E _b / N _o. However, it is also conceivable that the optimum threshold value at that time changes even with the same number of accumulated differences in autocorrelation due to conditions such as fading. Under such various conditions, it has been difficult to create a circuit for demodulating at the optimum timing at all times by hardware. Therefore, in the third embodiment, E _b / N _o is estimated using the autocorrelation, and a predetermined threshold value corresponding thereto or a cycle of accumulating the autocorrelation is dynamically changed, so that the optimum value is always obtained. By performing control to maintain synchronization at the timing described above by software such as a CPU and a DSP, finer timing control is made possible. In the third embodiment, the overall configuration of the digital demodulator is the same as that of FIG. 1 (first embodiment),
As shown in FIG. 6, the configuration of the synchronization unit 41 in FIG. 1 is different from that of the first embodiment. That is, as shown in FIG. 6, the synchronization section 41 of the third embodiment is different from the synchronization section 41 of the first embodiment shown in FIG. And a CPU 53 is added. Then, as the operation, the control CPU53 is to obtain E _b / N _o signal corresponding to the level of noise from the autocorrelation signal from the correlation determination circuit 46, depending on the size of the E _b / N _o signal The optimum threshold value is determined and sent to the synchronization holding circuit 47.

The synchronization holding circuit 47 determines whether or not to switch the synchronization point based on the determined optimum threshold value. In determining the optimum threshold value, the cumulative difference number of the autocorrelation, the value of E _b / N _o , the value of E _b / N _o at that time, and the optimum threshold value at that time are obtained in advance by experiments. Create a correspondence between the number of cumulative differences in autocorrelation and the optimal threshold value at that time,
Then, based on the correspondence, the CPU 53 sets the optimum threshold value from the number of accumulated differences in the autocorrelation, and further reflects the result of the channel quality estimation and the like in the upper layer in the determination of the threshold value. Constitute. In other words, when the estimation of the line state is not successful, the CPU 53 moves the threshold value by using the cumulative difference number of the autocorrelation and the line quality estimation result in the upper layer as parameters, and finds the optimum value by itself. It has a learning mode. According to the third embodiment, the control of the threshold value is performed by the CPU or the D
The operation can be easily changed by software such as SP, and the complicated control can be relatively easily realized by software. In any environment, such as a fading environment or a combination thereof, demodulation can always be performed at an optimal timing, and as a result, the average of the bit error rate BER is improved.

[0025]

As described above, the present invention performs finer timing control as compared with the conventional configuration, so that the power consumption is reduced and the high-speed data transmission system follows the frequency and phase shifts. It is also easy to do.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a first embodiment of a digital demodulation device according to the present invention.

FIG. 2 is a diagram illustrating an internal configuration of a synchronization unit illustrated in FIG. 1;

FIG. 3 is a diagram showing input / output characteristics of the XOR gate shown in FIG. 2;

FIG. 4 is a block diagram illustrating a configuration of a digital demodulation device according to a second embodiment of the present invention.

5 is a graph showing the relationship between E _b / N _o and BER and autocorrelation rate.

FIG. 6 is a block diagram illustrating a configuration of a digital demodulation device according to a third embodiment of the present invention.

FIG. 7 is a block diagram showing a basic configuration of a conventional π / 4 shift QPSK modulator.

8 (a) and (b) show the π / 4 shift Q shown in FIG. 7;
FIG. 3 is a diagram illustrating a PSK modulation method.

FIG. 9 is a block diagram illustrating a basic configuration of a conventional demodulation device.

10 is an eye pattern diagram of a detection signal in the demodulation device shown in FIG.

11 is a diagram illustrating a conventional phase shift prediction unit in the demodulation device illustrated in FIG. 9;

12 is a diagram illustrating a relationship between an eye pattern of a detection signal and an extraction point in the demodulation device illustrated in FIG. 9;

FIG. 13 is a block diagram showing a configuration of an embodiment of a digital demodulation device disclosed in JP-A-06-229331.

FIG. 14 is a diagram illustrating a configuration of the correlation detection circuit illustrated in FIG. 13;

15 is a diagram showing input / output characteristics of the XOR gate shown in FIG.

[Explanation of symbols]

9: delay detection circuit, 10: timing point, 11, 12: data identification unit,
13: Clock recovery circuit, 15: Zero cross point, 16: Clock recovery circuit, 17:
Correlation detection circuit, 18, 46 correlation determination circuit, 21 XOR gate,
24: counter, 41: synchronization circuit, 43, 44: serial / parallel converter, 45: counter group, 47: synchronization holding circuit, 48: synchronization clock generation circuit, 49: XOR gate group,
50: adder group, 52: threshold value determination circuit,
53 ... Control CPU

Claims (5)

[Claims] A synchronous detection point is determined from delay detection means for delay detection of a modulated wave to obtain detection signals X and Y, and detection signals X and Y from the delay detection means, and based on the synchronization timing points. Synchronizing means for outputting a timing clock signal for each symbol synchronization, and data for determining basic data from the detection signal from the delay detecting means based on the timing clock signal from the synchronizing means and demodulating it into a binary data string signal A digital demodulation device having identification means, wherein the synchronization means samples the levels of the detection signals X and Y output from the delay detection means at a plurality of extraction points preset at every symbol period. In the initial state (asynchronous state), two adjacent sampling points are sampled as a set. Gate means for detecting the correlation between the detected signals, addition means for adding the detected correlation for each pair of extraction points corresponding to X and Y, and accumulation means for accumulating each of the added correlations for a plurality of symbols. A correlation determining means for performing a correlation determination from the accumulated correlation value to capture initial synchronization; and a sampling data of one of extraction point pairs exhibiting a maximum correlation based on an output of the correlation determination means. Shift means for shifting the sampling period of the correlation detection means so as to be output at the time of the extraction point (timing point). In the state where the synchronization is acquired, two extraction points are respectively provided on both sides of the center point of the synchronization point. Only, correlation detection and accumulation over multiple symbols are performed, and synchronization is maintained based on that. And a digital demodulating device for stopping operations other than those required for maintaining the synchronization. 2. The digital demodulator according to claim 1, wherein a threshold value for restricting a shift operation in said shift means is set in advance. Wherein said synchronization means, digital demodulation of claim 2, characterized by comprising a threshold value determining means for varying the threshold value based on the value of the E _b / N _o for further corresponding to the noise apparatus. It is wherein said synchronizing means, according to claim 2, characterized by comprising a cycle value determination means for varying the period of accumulating the autocorrelation based on the value of the E _b / N _o for further corresponding to the noise Digital demodulator. Wherein said synchronization means, changing the threshold value based on the value of the E _b / N _o for further corresponding to noise,
3. The digital demodulation device according to claim 2, further comprising computer means having a learning mode for finding an optimum threshold value by itself.