JP3770034B2 - Photodiode array module - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a photodiode array module having a plurality of channels, and in particular, by making the distance of clock signal wiring of a shift register for reading signals of each photodiode equal in all channels, The present invention relates to a photodiode array module capable of making a read delay amount constant.
[0002]
[Prior art]
The photodiode array module is used as a sensor of a spectrum analyzer that measures the power spectrum of an incident light source, for example.
[0003]
FIG. 11 is a configuration diagram of a spectrum analyzer using a conventional photodiode array module. In the figure, a spectrum analyzer 10 diffracts incident light 2 incident from an optical fiber 1 by a diffraction grating 4 through a lens 3, and separates the diffracted light 5 separated for each wavelength into individual photodiode arrays 6. Light is received by the photodiodes F1 to F256, and an electrical output signal OTS (hereinafter simply referred to as an output signal OTS) corresponding to the optical power for each wavelength output from the photodiodes F1 to F256 is read by the shift register 7, The power spectrum 8 of the incident light 2 can be obtained by graphing the output signal OTS read here in the order of arrangement of the photodiodes F1 to F256.
[0004]
FIG. 12 is a configuration diagram of a conventional photodiode array module. In the same figure, a photodiode array using a photodiode array composed of 256 photodiodes F1 to F256 will be described.
[0005]
In FIG. 12, the output terminal of the first photodiode F1 constituting the photodiode 100 is connected to the fixed contact c of the changeover switch SW1, and the movable contact a of the changeover switch SW1 is connected to the output signal pad OTP to be movable. The contact b is connected to a common potential.
[0006]
The input terminal D of the flip-flop X1 is connected to the start signal pad STP, and the clock signal input terminal CK is connected to the clock signal pad CKP.
[0007]
The output terminal Q of the flip-flop X1 and the clock signal pad CKP are each input to the AND gate A1, and the output of the AND gate A1 is input to the control terminal of the changeover switch SW1.
[0008]
The change-over switch SW1, the flip-flop X1, and the AND gate A1 having such a configuration constitute a multiplexer M1 that reads the output signal of the photodiode F1.
[0009]
On the substrate 10, a photodiode array 100 and multiplexers M1 to M256 having the same configuration as described above are provided, and the output terminal Q of the previous flip-flop is sequentially connected to the input terminal D of the next flip-flop, A 256-channel photodiode array module is formed by connecting the movable contact a of the changeover switch SW1 to the output signal pad OTP and connecting the clock signal input terminal CK of each flip-flop to the clock signal pad CKP. (Hereinafter, the multiplexers M1 to M256 are collectively referred to as the shift register 20.)
[0010]
The clock signal pad CKP is an input pad for inputting the clock signal CKS output from the external circuit to the substrate 10 on which the photodiode array module is formed (hereinafter referred to as the photodiode array module 10). The signal pad STP is an input pad for inputting a read start pulse signal output from the external circuit, and the output signal pad OTP is a signal output pad for outputting the output signal of the photodiode array module 10 to the external circuit. is there.
[0011]
In the photodiode array module 10 having such a configuration, by inputting a read start pulse signal to the start signal pad STP, this pulse signal is sequentially transmitted to the flip-flop of the next stage, and the direction from the changeover switch 1 to the changeover switch 256 is changed. Since the fixed contact c is switched to the movable contact a for a certain time, the output signals from the photodiode F1 to the photodiode F256 are sequentially output from the output signal pad OTP.
[0012]
13 shows a waveform diagram of the photodiode array module 10. FIG. The figure shows a read start pulse signal STS, a clock signal CKS, output signals Q1, Q2, and Q256 of flip-flops X1, X2, and X256, and output signals E1, E2, and E256 of AND gates A1, A2, and A256, It is a waveform diagram of the output signal OTS output from the output signal pad OTP.
[0013]
In the figure, when a read start pulse signal STS is input, flip-flops X1, X2, and X256 generate output signals Q1, Q2, and Q256 according to the timing of the clock signal CKS. Since the logical product signals of the output signals Q1, Q2, Q256 and the clock signal CKS are output from the AND gates A1, A2, A256 to the control terminals of the changeover switches SW1 to SW256, the photodiode F1 is output during the period T1 of the output signal OTS. Is output from the output signal pad OTP. In the period T2, the output signal of the photodiode F2 is output from the output signal pad OTP. In the period T256, the output signal of the photodiode F256 is output from the output signal pad OTP. .
[0014]
In the conventional photodiode array module 10, it is possible to read out the output signal OTS of each channel by such an operation. The output signal read out here can be converted into a power spectrum of incident light by graphing in the order of arrangement of the photodiodes F1 to F256 by a spectrum analyzer, for example.
[0015]
[Problems to be solved by the invention]
Since the photodiode array module is an element that handles optical signals, high-speed reading of output signals is indispensable. In order to realize this, it is necessary to speed up the clock signal. However, if the clock signal is speeded up, there are the following problems.
[0016]
The photodiode array module is configured by arranging a large number of photodiodes and multiplexers in series. Therefore, the wiring distance from the clock signal pad CKP to each flip-flop becomes longer as the flip-flop in the subsequent stage becomes.
[0017]
As described above, when a high-speed clock signal is input from the clock signal pad CKP to a large number of flip-flops having different wiring distances, actually, as illustrated in FIG. As the wiring distance from the clock signal pad CKP to the clock signal input terminal CK increases, delays D1 to D256 occur in the clock signal CKS input to the flip-flop.
[0018]
Therefore, since the delay of AD output signals AD1 to AD256 increases as the order of arrangement of the multiplexers becomes later, variations occur in reading out the output signals of the respective photodiodes. This variation in readout appears as jitter when the output signal is converted into a power spectrum of incident light by a spectrum analyzer.
[0019]
That is, the conventional photodiode array module has a problem in that the output signal of each photodiode varies depending on the wiring distance from the clock signal pad CKP to the clock signal input terminal CK.
[0020]
SUMMARY OF THE INVENTION The present invention solves the above-described problems, and an object thereof is to provide a photodiode array module that can make the output signal readout timing of each photodiode constituting the photodiode array uniform.
[0021]
[Means for Solving the Problems]
In order to achieve such an object, in the invention described in claim 1,
In a photodiode array module having a plurality of channels including a photodiode array composed of a plurality of photodiodes and a read shift register for sequentially reading out each electrical output signal output from the plurality of photodiodes according to the timing of a clock signal ,
The read shift register is configured such that all wiring distances from the signal input pad for inputting the clock signal input to all channels to the clock signal input terminal of each channel of the read shift register are equal, A first shift register for reading out the output signal of the odd-numbered channel photodiode and a second shift register for reading out the output signal of the even-numbered channel photodiode;
The first and second shift registers can be read in the forward direction and the reverse direction and have the same configuration . The first and second shift registers are arranged in the opposite direction on the upper and lower sides of the photodiode array by inverting one of the read directions. ,
The first, each of the signal input pad for inputting the clock signal of the second shift register, characterized in that disposed at positions symmetric substrate photodiode array module is formed is there.
[0022]
According to such a configuration, since the values of the floating resistance and the floating capacitance existing in the wiring on the substrate from the clock signal pad to the multiplexer of each channel are constant, they are input to the flip-flops provided in each multiplexer. The delay of the clock signal can be made constant.
The shift register is composed of two shift registers that read out the output signal of the odd-numbered channel photodiode and the output signal of the even-numbered channel photodiode, whereby the photodiode output signal can be read at high speed.
This is because two shift registers that can be read in the forward direction and the reverse direction are used, for example, a shift register that reads an output signal in the forward direction is arranged below the photodiode array, and thus an odd-numbered photodiode is arranged. This is realized by arranging a shift register for reading out the output signal of No. 1 and reading the output signal in the reverse direction above the photodiode array, thereby reading out the output signals of even-numbered photodiodes.
Two shift registers used for such applications are installed in opposite directions by installing signal input pads for inputting the clock signals at symmetrical positions on the substrate on which the photodiode array module is formed. It is possible to input a clock signal from a single direction to these shift registers.
[0023]
Such a configuration can be realized by inputting the clock signal to each channel of the read shift register through wiring having a tree structure as in claim 2.
[0024]
The invention according to claim 3 is the invention according to claim 1,
Said first, second shift register,
A flip-flop receives the clock signal to the clock signal input terminal,
An AND gate that controls reading of the output signal of the photodiode based on the output of the flip-flop and the clock signal;
When reading in the forward direction, connect the input terminal of the flip-flop to the output terminal of the previous flip-flop, and when reading in the reverse direction, connect the switch that connects the input terminal of the flip-flop to the output terminal of the next-stage flip-flop. It is characterized by providing.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a photodiode array module according to the present invention. In the figure, the same components as those of the conventional example are denoted by the same reference numerals, and the description thereof is omitted.
[0028]
In FIG. 1, the photodiode array 100 provided in the photodiode array module 200 is connected to a shift register SL2 that reads out the output of the odd-numbered photodiode and a shift register SL3 that reads out the output of the even-numbered photodiode.
[0029]
FIG. 2 is a configuration diagram of the shift register SL2. In the figure, a clock signal CKS is input to multiplexers M1 to M256 by wiring (hereinafter referred to as a clock wiring section) 202 having a tree structure. A buffer BF is provided at each branch point of the wiring forming the tree structure. Further, the clock signal pad CKP, the start signal pad STP, and the output signal pad OTP are provided at symmetrical positions on both ends of the substrate 201.
[0030]
By connecting the clock signal CKS to the multiplexers M1 to M256 by the clock wiring unit 202 having the tree structure as described above, the wiring distance from the clock signal pad CKP to each of the multiplexers M1 to M256 can be unified.
[0031]
As a result, the values of the stray resistance and stray capacitance existing in the wiring on the substrate from the clock signal pad CKP to each of the multiplexers M1 to M256 are constant, so that the multiplexers M1 to M256 are provided as shown in FIG. Delays D1 to D256 of the clock signal CKS input to the flip-flops X1 to X256 are constant.
[0032]
Accordingly, since the readout timing of the output signal of each photodiode becomes uniform, no jitter occurs when this output signal is converted into a power spectrum by a spectrum analyzer.
[0033]
Further, as described above, since the read timing of the output signal of each photodiode is uniform in the shift register SL2, the output signal of the photodiode array 100 is read in the vertical direction using the shift register SL3 having the same configuration. Is possible. As a result, reading of the output signal can be speeded up.
[0034]
In order to realize the photodiode array module having such a configuration, it is necessary to reverse the reading direction of either the shift register SL2 or SL3, which is realized by the configuration as shown in FIG. Can do.
[0035]
In FIG. 4, the start signal pad STP is connected to the movable contact b of the changeover switch SWD1, and the fixed contact c of the changeover switch SWD1 is connected to the input terminal D of the flip-flop X1.
[0036]
The movable contact a of the changeover switch SWD1 is connected to the output terminal Q of the flip-flop X2 at the next stage.
[0037]
The movable contact b of the changeover switch SWD2 having the fixed contact c connected to the input terminal D of the flip-flop X2 is connected to the output terminal Q of the preceding lip flop X2, and the movable contact a is the output terminal of the next flip-flop X3. Connected to Q.
[0038]
Hereinafter, the selector switches SWD3 to SWD256 are connected to the flip-flops X3 to X256 in the same connection form. The movable contact a of the changeover switch SWD256 connected to the final flip-flop X256 is connected to the start signal pad STP.
[0039]
The control terminals of the changeover switches SWD1 to SWD256 are connected to the changeover signal input pad SLP. A switching signal SL input from an external circuit is input to the switching signal input pad SLP. When the switching signal SL is high, the fixed contact c of the switches SWD1 to SWD256 is connected to the movable contact b, and when the switching signal SL is low, The fixed contact c of the switches SWD1 to SWD256 is connected to the movable contact a.
[0040]
In the shift registers SF2 and SF3 having such a configuration, when the switching signal SL is made high, the connection form of the flip-flops X1 to X256 becomes the same as in FIG. 11, and by making the switching signal SL low, the flip-flops All the connection forms of X1 to X256 are connected in the reverse direction.
[0041]
Therefore, in the photodiode array module configured as shown in FIG. 3, the readout direction of the photodiode array module can be controlled by the switching signal SL.
[0042]
Furthermore, by providing the clock signal pad CKP, the start signal pad STP, the output signal pad OTP, and the switching signal input pad SLP at symmetrical positions on both ends of the substrate, the two shift registers are reversed as shown in FIG. In this case, the clock signal CKS and the start signal STS can be input from one direction from either side of the left and right ends, and the output signal OTS can be extracted from one direction from either side of the left and right ends. Is possible.
[0043]
The above description merely shows a specific preferred embodiment for the purpose of explanation and illustration of the present invention. Therefore, the present invention is not limited to the above-described embodiments, and includes many changes and modifications without departing from the essence thereof.
[0044]
【The invention's effect】
As is apparent from the above description, the present invention has the following effects.
According to the first aspect of the present invention, the delay of the clock signal input to the flip-flop provided in each multiplexer can be made constant, so that the readout timing of the output signal of each photodiode becomes uniform, and the output It is possible to suppress the occurrence of jitter when a signal is converted into a power spectrum.
Further, the shift register is constituted by two shift registers that read out the output signal of the odd-numbered channel photodiode and the output signal of the even-numbered channel photodiode, so that the photodiode output signal can be read at high speed. .
Further, such a configuration uses two shift registers that can read in the forward direction and the reverse direction, for example, arranges a shift register that reads an output signal in the forward direction below the photodiode array, and thereby It is possible to realize by reading out the output signal of the odd-numbered photodiode and arranging the shift register that reads the output signal in the reverse direction on the upper side of the photodiode array, thereby reading out the output signal of the even-numbered photodiode is there.
In addition, a shift register used for such a purpose is a signal for inputting the clock signal.
It is possible to input a clock signal from a single direction to two shift registers installed in opposite directions by installing the signal input pad at a symmetrical position on the substrate on which the photodiode array module is formed. is there.
[0045]
Such a configuration can be easily realized by inputting the clock signal to each channel of the read shift register through a wiring having a tree structure as in claim 2. ]
FIG. 1 is a configuration diagram showing an embodiment of a photodiode array module according to the present invention.
FIG. 2 is a configuration diagram of a shift register according to the present invention.
FIG. 3 is a waveform diagram of a photodiode array module according to the present invention.
FIG. 4 is a configuration diagram of a spectrum analyzer.
FIG. 5 is a block diagram showing an example of a conventional photodiode array module.
FIG. 6 is a block diagram showing an example of a conventional photodiode array module.
FIG. 7 is a waveform diagram of a conventional photodiode array module.
FIG. 8 is a waveform diagram of a conventional photodiode array module.
[Explanation of symbols]
100 photodiode array SF1, SF2, SF3 shift register 10, 200 photodiode array module CKP clock signal pad STP start signal pad OTP output signal pad SLP switching signal pads SW1 to SW256, SWD1 to SWD256 switching switches X1 to X256 flip-flops A1 to A256 Andgate M1-M256 Multiplexer

Claims (3)

In a photodiode array module having a plurality of channels including a photodiode array composed of a plurality of photodiodes and a read shift register for sequentially reading out each electrical output signal output from the plurality of photodiodes according to the timing of a clock signal ,
The read shift register is configured such that all wiring distances from the signal input pad for inputting the clock signal input to all channels to the clock signal input terminal of each channel of the read shift register are equal, A first shift register for reading out the output signal of the odd-numbered channel photodiode and a second shift register for reading out the output signal of the even-numbered channel photodiode;
The first and second shift registers can be read in the forward direction and in the reverse direction and have the same configuration . The first and second shift registers are arranged in the opposite direction on the upper and lower sides of the photodiode array by inverting one of the read directions. ,
The first, each of the signal input pad for inputting the clock signal of the second shift register, a photodiode, characterized in that disposed at positions symmetric substrate photodiode array module is formed Array module.   2. The photodiode array module according to claim 1, wherein the clock signal is configured to be input to each channel of the read shift register through wiring having a tree structure. 3. Said first, second shift register,
A flip-flop receives the clock signal to the clock signal input terminal,
An AND gate that controls reading of the output signal of the photodiode based on the output of the flip-flop and the clock signal;
When reading in the forward direction, connect the input terminal of the flip-flop to the output terminal of the previous flip-flop, and when reading in the reverse direction, connect the switch that connects the input terminal of the flip-flop to the output terminal of the next-stage flip-flop. The photodiode array module according to claim 1, wherein the photodiode array module is provided.

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