JP3753948B2 - Group III nitride compound semiconductor manufacturing method and group III nitride compound semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for producing a group III nitride compound semiconductor and a semiconductor element. The group III nitride compound semiconductor is, for example, a binary system such as AlN, GaN, InN, Al _x Ga _1-x N, Al _x In _1-x N, Ga _x In _1-x N (whichever Also includes ternary systems such as 0 <x <1) and quaternary systems of Al _x Ga _y In _1-xy N (0 <x <1, 0 <y <1, 0 <x + y <1) general formula is _{Al x Ga y in 1-xy} N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) with those represented. In this specification, unless otherwise specified, the group III nitride compound semiconductor is simply referred to as a group III nitride compound semiconductor doped with an impurity for making the conductivity type p-type or n-type. An expression that also includes
[0002]
[Prior art]
Group III nitride compound semiconductors, for example, when used as light-emitting elements, are direct transition semiconductors whose emission spectrum covers a wide range from ultraviolet to red, and are used in light-emitting elements such as light-emitting diodes (LEDs) and laser diodes (LDs). Applied. In addition, since the band gap is wide, stable operation can be expected at a higher temperature than elements using other semiconductors. Therefore, applications to transistors such as FETs have been actively developed. In addition, since it does not contain arsenic (As) as the main component, it is expected to develop various semiconductor devices in general from the environmental viewpoint. Some of these Group III nitride compound semiconductors use sapphire as a substrate and a silicon (Si) substrate in addition to elements formed thereon.
[0003]
When a group III nitride compound semiconductor is formed on a silicon (Si) substrate, epitaxial growth should always be performed under stress due to a lattice constant misfit between the silicon (Si) substrate and the group III nitride compound semiconductor. It becomes. In addition, the difference in thermal expansion coefficient between the silicon (Si) substrate and the group III nitride compound semiconductor increases the stress when the temperature is lowered, causing a number of cracks in the group III nitride compound semiconductor layer. It will be. As a result, when a crack occurs in a region where a light emitting element or other element is formed, the element becomes a defective product, and the yield is extremely poor.
[0004]
Therefore, for example, there is a technique in which the growth region is divided into the size of each element formation region (1 mm ² or less) and a window frame-shaped mask is formed in addition to the growth region. As a result, each region becomes smaller, and the occurrence of cracks (breaks) is suppressed by not transmitting stress from adjacent regions, and even if a crack occurs, it should be limited to the element region where the crack has occurred. Can do.
[0005]
[Problems to be solved by the invention]
However, even if selective growth is performed so that cracks do not occur in this way, stress relaxation cannot actually be performed sufficiently, and threading dislocations in particular did not decrease. That is, the occurrence of a crack (fracture) means stress relaxation caused by the crack. Therefore, if the crack is suppressed, the threading dislocation remains stressed, and each threading dislocation disappears during the epitaxial growth (propagation upward). It was to be obstructed on the contrary.
[0006]
The present invention has been made to solve the above-described problems, and the object of the present invention is to suppress cracks and reduce threading dislocations simultaneously in the epitaxial growth of group III nitride compound semiconductors. Is to do.
[0007]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, according to the invention described in claim 1, in the method for producing a group III nitride compound semiconductor obtained by epitaxial growth of a group III nitride compound semiconductor on a substrate, Forming a mask material in which a group nitride-based compound semiconductor is not epitaxially grown in a lattice shape, separating the substrate surface from each other, and exposing the substrate surface above each separately exposed substrate surface in two different temperature ranges; Or a step of forming a strain relaxation layer in which group III nitride compound semiconductors of different compositions are alternately formed twice or more and a step of forming a desired group III nitride compound semiconductor on the strain relaxation layer. And a group III nitride compound semiconductor formed above the substrate surface is formed separately from each other. Here, the lattice shape as the shape of the mask material does not have to have a rectangular window portion. For example, it may have a polygonal window like a honeycomb. Two different temperature ranges mean that the two types of temperatures do not have to be completely the same when they are alternately formed.
[0008]
According to the invention described in claim 2, the two different temperature ranges are 200 ° C. or more and 600 ° C. or less and 900 ° C. or more and 1200 ° C. or less. According to the third aspect of the present invention, the group III nitride compound semiconductor layer formed at 200 ° C. to 600 ° C. has a thickness of 10 nm to 100 nm and is formed at 900 ° C. to 1200 ° C. III. The group nitride compound semiconductor layer has a thickness of 200 nm to 1 μm .
[0009]
According to a fourth aspect of the present invention, the area of the substrate surface that is separately exposed is 1 mm ² or less. According to a fifth aspect of the present invention, the area of the substrate surface exposed separately is 0.3 mm ² or less.
[0010]
According to a sixth aspect of the present invention, the substrate is made of silicon (Si). According to a seventh aspect of the present invention, the mask material is mainly composed of silicon dioxide (SiO ₂ ). According to the invention described in claim 8 , the single crystal is mainly formed on the surface of the substrate which is separately exposed so that the substrate and the upper group III nitride compound semiconductor do not cause a chemical reaction during the manufacturing process. And a step of forming a reaction preventing layer. Here, the reaction prevention layer mainly composed of a single crystal means that the reaction prevention layer is formed under conditions such as the temperature at which the single crystal is formed, regardless of the crystalline state in the vicinity of the substrate surface. According to the ninth aspect of the present invention, the thickness of the reaction preventing layer is 100 nm or more and 1 μm or less. According to the invention of claim 10 , the reaction preventing layer is a group III nitride compound semiconductor, and the composition of aluminum (Al) in group III is 30% or more in molar ratio. To do.
[0011]
The invention according to claim 11 is provided on a group III nitride compound semiconductor layer obtained by the method for producing a group III nitride compound semiconductor according to any one of claims 1 to 10. A Group III nitride compound semiconductor device characterized by being formed. The invention according to claim 12 is provided on a group III nitride compound semiconductor layer obtained by the method for producing a group III nitride compound semiconductor according to any one of claims 1 to 10. A Group III nitride compound semiconductor light-emitting device obtained by stacking different Group III nitride compound semiconductor layers.
[0012]
[Operation and effect of the invention]
A mask material that does not allow group III nitride compound semiconductors to grow epitaxially is formed in a lattice pattern, and the surface of the substrate is separated and exposed, so that the regions where group III nitride compound semiconductors are epitaxially grown become independent small regions. be able to. After that, the stress between the substrate and the upper layer can be relieved by forming a strain relaxation layer in which group III nitride compound semiconductors of the same or different composition are alternately formed in two different temperature ranges. Generation | occurrence | production can be suppressed or a threading dislocation can be eliminated in an epitaxial upper layer. The desired group III nitride compound semiconductor formed thereon can be made to suppress threading dislocations while preventing cracks . Since the strain relaxation layer has more layers formed alternately, the stress is relaxed. Therefore, it is desirable to form two or more low temperature growth layers and two high temperature growth layers .
[0013]
The two different temperature ranges are 200 ° C. or more and 600 ° C. or less and 900 ° C. or more and 1200 ° C. or less, and it is desirable to alternately form a layer grown at a low temperature and a layer grown at a high temperature. The stress is relaxed in the low-temperature growth layer, and the high-temperature growth layer becomes a single crystal layer, so that the stress is relaxed in the upper layer, and a threading dislocation can be suppressed (claim 2). The low-temperature growth layer is preferably thin, and the high-temperature growth layer is preferably thick, and is preferably 10 nm to 100 nm and 200 nm to 1 μm, respectively .
[0014]
The area of the substrate surface exposed separately is preferably 0.01 mm ² or more and 1 mm ² or less, more preferably 0.01 mm ² or more and 0.3 mm ² or less. When the epitaxial growth layer formed on the exposed surface exceeding 1 mm ² is formed to a thickness of several μm, the generation of cracks due to stress becomes very large. If the exposed surface is 0.3 mm ² or less, each epitaxial formation region is about one element unit, and the yield can be further increased ( claims 4 and 5 ). If it is less than 0.01 mm ^{2, the} size is not sufficient for one element.
[0015]
The present invention is particularly effective when the silicon (Si) substrate has a large difference in thermal expansion coefficient from the group III nitride compound semiconductor ( claim 6 ). In addition, it is convenient to use silicon dioxide (SiO ₂ ) as the mask material ( claim 7 ). By forming a reaction-preventing layer mainly composed of a single crystal on the exposed substrate surface, due to stress during the manufacturing process, that is, during epitaxial growth, electrode formation, photolithography, etching and other treatments, temperature increase and temperature decrease to room temperature, It is possible to prevent a chemical reaction between the substrate and the upper group III-nitride compound semiconductor ( claim 8 ). The thickness of the reaction preventing layer must be at least 100 nm ( Claim 9 ), and the composition thereof is a group III nitride compound semiconductor in which the composition of aluminum (Al) in group III is 30% or more. More desirable ( Claim 10 ). As a result, for example, when AlGaN is formed between a silicon (Si) substrate and gallium nitride (GaN), the silicon (Si) substrate and gallium nitride (GaN) are not in direct contact with each other, so that nitrogen atoms are formed between them. It is possible to prevent the generation of silicon nitride, metal gallium and the like by moving. In addition, it is useful to form a reaction preventing layer between a group III nitride compound semiconductor and a substrate that can react depending on conditions.
[0016]
If any element is formed on the desired group III nitride compound semiconductor layer formed as described above, or a light emitting element is formed by stacking different group III nitride compound semiconductor layers, cracks will occur. In addition, since the threading dislocation is suppressed at the same time, the yield is high and a high-quality element or light-emitting element can be obtained ( claims 11 and 12 ). Further, by dividing the growth region, the warpage of the substrate can be significantly reduced as compared with the case where the growth is performed on the entire substrate, so that the yield in the element manufacturing process is improved.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a cross-sectional view showing a configuration in a specific embodiment of the present invention. A mask material 2 made of silicon oxide (SiO ₂ ) is formed on a silicon (Si) substrate 1. The mask material 2 is formed in a window frame shape, and the silicon (Si) substrate 1 surface is exposed at the window portion. Next, a reaction preventing layer 3 made of AlGaN is formed on the exposed silicon (Si) substrate 1 by epitaxial growth. The reaction preventing layer 3 is for preventing the reaction between the silicon (Si) substrate 1 and the upper group III nitride compound semiconductor, and is mainly composed of a single crystal. Next, a strain relaxation layer 4 made of a multilayer film is formed by epitaxial growth. The strain relaxation layer 4 is formed by alternately stacking GaN layers 411 and 412 and AlGaN layers 421 and 422 formed in different temperature ranges. On the strain relaxation layer 4, a GaN layer 5 which is a desired group III nitride compound semiconductor layer is formed by epitaxial growth. Here, the laminated portion composed of the reaction preventing layer 3, the strain relaxation layer 4, and the GaN layer 5 is formed from the reaction prevention layer 3 ′, the strain relaxation layer 4 ′, and the GaN layer 5 ′ formed on the adjacent exposed substrate 1 surface. The laminated portion formed is formed under a condition that it is not connected during epitaxial growth. That is, even if the strain relaxation layer 4 and the group III nitride compound semiconductor layer 5 are formed above the edge of the mask material 2, epitaxial growth is performed under the condition that the central portion of the mask material 2 is not covered. Specifically, this is easily achieved by taking a sufficient frame width of the window frame-shaped mask material 2. Note that the laminated portion composed of the reaction preventing layer 3, the strain relaxation layer 4, and the GaN layer 5 may have a surface perpendicular to the surface of the substrate 1 above the mask material 2 as shown in FIG. Even if it is an inclined surface as shown in FIG. 2B, both are included in the present invention. In FIG. 1 and FIG. 3 and subsequent figures, it is described in the form of FIG. 2A, but in any case, the stacking as shown in FIG. 2B is not excluded.
[0018]
The embodiment of the above invention can be selected from the following.
[0019]
In the case of sequentially forming a group III nitride compound semiconductor on a substrate, the substrate is sapphire, silicon (Si), silicon carbide (SiC), spinel (MgAl ₂ O ₄ ), LiGaO ₂ , NdGaO ₃ , ZnO MgO and other inorganic crystal substrates, III-V group compound semiconductors such as gallium phosphide or gallium arsenide, gallium nitride (GaN) and other group III nitride compound semiconductors can be used. Of course, a substrate on which a gallium nitride (GaN) or other group III nitride compound semiconductor film is formed, particularly a substrate on which a thick film is formed as a buffer layer may be used.
[0020]
As a method for forming a group III nitride compound semiconductor layer, metal organic vapor phase epitaxy (MOCVD or MOVPE) is preferable, but molecular beam vapor phase epitaxy (MBE), halide vapor phase epitaxy (Halide VPE), liquid A phase growth method (LPE) or the like may be used, and each layer may be formed by a different growth method.
[0021]
In Group III nitride compound semiconductors, part of the composition of Group III elements may be replaced by boron (B) and thallium (Tl), and part of the composition of nitrogen (N) may be phosphorus (P) and arsenic. The present invention can be substantially applied even if it is replaced with (As), antimony (Sb), or bismuth (Bi). Moreover, what doped such an extent that these elements cannot be displayed on a composition may be used. For example, Al _x Ga _1-x N (0 ≦ x ≦ 1), which is a group III nitride compound semiconductor that does not contain indium (In) and arsenic (As), is composed of aluminum (Al) and gallium (Ga). Indium (In), which has a large atomic radius, or arsenic (As), which has a larger atomic radius than nitrogen (N), can compensate for the expansion strain of the crystal due to the loss of nitrogen atoms by compressive strain and improve crystallinity. You may do it. In this case, since the acceptor impurity easily enters the position of the group III atom, a p-type crystal can be obtained as-grown. By improving the crystallinity in this manner, the threading dislocation can be further reduced to about 100 to 1/1000 in combination with the present invention. In the case of constituting a light emitting element, it is desirable to use a binary or ternary group III-nitride compound semiconductor.
[0022]
When an n-type group III nitride compound semiconductor layer is formed, a group IV element such as Si, Ge, Se, Te, C, or a group VI element can be added as an n-type impurity. Further, as a p-type impurity, a group II element or group IV element such as Zn, Mg, Be, Ca, Sr, or Ba can be added. A plurality of these or n-type impurities and p-type impurities may be doped in the same layer.
[0023]
It is good also as a structure which performs what is called lateral epitaxial growth combining with this application. That is, for each region above the exposed surface of the substrate, various configurations in which threading dislocations are reduced by various lateral epitaxial growth may be combined. As the lateral epitaxial growth, it is desirable that the growth surface is perpendicular to the substrate, but growth may be performed with the facet surface oblique to the substrate. At this time, the bottom of the step may be V-shaped with no bottom surface.
[0024]
The mask material that defines the substrate exposed surface of the present application is polycrystalline silicon, polycrystalline semiconductor such as polycrystalline nitride semiconductor, silicon oxide (SiO _x ), silicon nitride (SiN _x ), titanium oxide (TiO _x ), zirconium oxide (ZrO _X) oxide such as, nitrides, titanium (Ti), a refractory metal such as tungsten (W), it is possible to employ these multilayer films. These film forming methods are arbitrary in addition to vapor phase growth methods such as vapor deposition, sputtering, and CVD.
[0025]
The reaction preventing layer prevents the substrate and the upper group III nitride compound semiconductor from reacting during the manufacturing process. For example, when there is no layer between the silicon (Si) substrate and GaN, or there is only a thin layer between them, the reaction is accelerated by stress during the manufacturing process, nitrogen atoms move from GaN, and silicon (Si ) It is known to form silicon nitride with a substrate. Therefore, thicker well in single-crystal, aluminum III nitride compound rich in (Al) semiconductor _{Al x Ga y In 1-xy} N ( e.g. x ≧ 0.3) is preferable. This is because the bond between aluminum (Al) and nitrogen is strong, making it difficult for silicon (Si) and GaN to react. In addition, it is important that it is not a so-called buffer layer amorphous material but a single crystal.
[0026]
The strain relaxation layer is formed by laminating an amorphous layer and a single crystal layer. A plurality of periods may be formed with the amorphous layer and the single crystal layer as one period, and the repetition may be any period. The more repeats, the better the crystallinity. As the amorphous layer, a group III nitride compound semiconductor grown at a low temperature is preferable, and a layer containing aluminum (Al) is more preferable. The single crystal layer is preferably a group III nitride compound semiconductor grown at a high temperature, and a binary group III nitride compound semiconductor is more preferable if a conductive dopant is excluded. Note that the single crystal layer may be doped with indium (In) or other elements having a large atomic radius.
[0027]
Reactive ion etching (RIE) is desirable when etching a group III nitride compound semiconductor when electrode formation or lateral epitaxial growth is used, but any etching method can be used. As an example in which the side surface perpendicular to the substrate surface is not formed, for example, a substrate having no bottom surface at the bottom and having a V-shaped cross section may be formed by anisotropic etching.
[0028]
A semiconductor element such as an FET or a light emitting element can be formed on the group III nitride compound semiconductor having a region in which threading dislocations are suppressed. In the case of a light emitting device, the light emitting layer may be a multi-quantum well structure (MQW), a single quantum well structure (SQW), a homo structure, a hetero structure, or a double hetero structure, but a pin junction or a pn junction, etc. You may form by.
[0029]
Hereinafter, the present invention will be described based on specific examples. Although a light emitting element is given as an example, the present invention is not limited to the following example, and discloses a method for producing a group III nitride compound semiconductor applicable to an arbitrary element.
[0030]
The group III nitride compound semiconductor of the present invention was produced by vapor phase growth using a metal organic compound vapor phase growth method (hereinafter referred to as “MOVPE”). The gases used were ammonia (NH ₃ ), carrier gas (H ₂ or N ₂ ), trimethylgallium (Ga (CH ₃ ) ₃ , hereinafter referred to as “TMG”) and trimethylaluminum (Al (CH ₃ ) ₃ , (Hereinafter referred to as “TMA”), trimethylindium (In (CH ₃ ) ₃ , hereinafter referred to as “TMI”), cyclopentadienylmagnesium (Mg (C ₅ H ₅ ) ₂ , hereinafter referred to as “Cp ₂ Mg”) It is.
[0031]
[First embodiment]
A silicon oxide (SiO ₂ ) film 2 having a thickness of 500 nm was formed on the (111) surface of the n-type silicon (Si) substrate 1 by sputtering. A resist mask was formed by photolithography, and the silicon oxide (SiO ₂ ) film was removed in a window frame shape by wet etching with buffered HF. The window frame has a width of 50 μm, and the (111) plane of the silicon (Si) substrate 1 from which the silicon oxide (SiO ₂ ) film 2 has been removed has a rectangular shape of 300 μm × 300 μm. In this manner, a large number of separated exposed surfaces of the 300 μm × 300 μm square silicon (Si) substrate 1 were formed.
[0032]
Next, the n-type silicon (Si) substrate 1 is held at 1100 ° C., TMA, TMG, SiH ₄ and NH ₃ are introduced, and the (111) silicon (Si) substrate 1 exposed in a 300 μm × 300 μm square shape is formed. The reaction preventing layer 3 made of an n-AlGaN: Si layer having a thickness of 300 nm was formed on the surface. The molar ratio of Al and Ga in the formed n-AlGaN: Si layer 3 was about 3: 7.
[0033]
Next, TMG, SiH ₄ and NH ₃ were introduced to form an n-GaN: Si layer 411 having a thickness of 500 nm on the reaction preventing layer 3 composed of the n-AlGaN: Si layer. Next, the temperature of the n-type silicon (Si) substrate 1 was lowered to 500 ° C., and TMA, TMG, SiH ₄ and NH ₃ were introduced to form an n-AlGaN: Si layer 421 having a thickness of 20 nm. The molar ratio of Al to Ga in the n-AlGaN: Si layer 421 was about 3: 7. Next, the temperature of the n-type silicon (Si) substrate 1 was raised to 1100 ° C., and TMG, SiH ₄ and NH ₃ were introduced to form an n-GaN: Si layer 412 having a thickness of 500 nm. Further, the temperature of the n-type silicon (Si) substrate 1 was lowered to 500 ° C., and TMA, TMG, SiH ₄ and NH ₃ were introduced to form an n-AlGaN: Si layer 422 having a thickness of 20 nm. The molar ratio of Al to Ga in the n-AlGaN: Si layer 422 was about 3: 7. In this way, n-GaN: Si layers 411 and 412 formed to a thickness of 500 nm at a high temperature of 1100 ° C., and n-AlGaN: Si layers 421 and 422 formed to a thickness of 20 nm at a low temperature of 500 ° C. A strain relaxation layer 4 having a thickness of about 1 μm formed alternately was formed.
[0034]
Next, the temperature of the n-type silicon (Si) substrate 1 is raised to 1100 ° C., TMG, SiH ₄ and NH ₃ are introduced, and the n-GaN: Si having a thickness of 5 μm is formed on the strain relaxation layer 4. Layer 5 was formed. After that, the n-GaN: Si layer 5 formed in this way is the surface of the silicon (Si) substrate 1 exposed in a 300 μm × 300 μm square shape separated by the window frame-like silicon oxide (SiO ₂ ) film 2. Even if the strain relaxation layer 4 and the n-GaN: Si layer 5 are formed above the edge of the silicon oxide (SiO ₂ ) film 2 that is formed in a part of the window frame, the adjacent 300 μm × 300 μm The strain relaxation layer 4 ′ and the n-GaN: Si layer 5 ′ formed above the surface of the silicon (Si) substrate 1 exposed in the shape remained separated. The n-GaN: Si layer 5 thus formed was cooled to 20 ° C./min and returned to room temperature, but no cracks were generated.
[0035]
[Second Embodiment]
As in the first embodiment, an n-GaN: Si layer 5 having a strain relaxation layer 4 on the (111) plane of a silicon (Si) substrate 1 exposed in a 300 μm × 300 μm square shape is stacked, and then Thus, the light emitting diode 100 shown in FIG. 3 was formed by stacking group III nitride compound semiconductors.
[0036]
On the n-GaN: Si layer 5, an n-cladding layer 106 made of silicon (Si) -doped Al _0.15 Ga _0.85 N, a light-emitting layer 107, and a p-cladding layer 108 made of magnesium (Mg) -doped Al _0.15 Ga _0.85 N A p-contact layer 109 made of magnesium (Mg) -doped GaN was formed. Next, an electrode 110 made of gold (Au) was formed on the p contact layer 109, and an electrode 111 made of aluminum (Al) was formed on the back surface of the silicon substrate 1. The light emitting diode (LED) 100 formed in this way has significantly improved element lifetime and luminous efficiency.
[0037]
[Third embodiment]
As in the first embodiment, an n-GaN: Si layer 5 having a strain relaxation layer 4 on the (111) plane of a silicon (Si) substrate 1 exposed in a 300 μm × 300 μm square shape is stacked, and then Thus, a laser diode 200 shown in FIG. 4 was formed by stacking group III nitride compound semiconductors.
[0038]
On the n-GaN: Si layer 5, an n clad layer 206 made of silicon (Si) -doped Al _0.15 Ga _0.85 N, an n guide layer 207 made of silicon (Si) -doped GaN, a light emitting layer 208 having an MQW structure, A p guide layer 209 made of magnesium (Mg) -doped GaN, a p-cladding layer 210 made of magnesium (Mg) -doped Al _0.15 Ga _0.85 N, and a p-contact layer 211 made of magnesium (Mg) -doped GaN were formed. Next, an electrode 212 made of gold (Au) was formed on the p contact layer 211, and an electrode 213 made of aluminum (Al) was formed on the back surface of the silicon substrate 1. The laser diode (LD) 100 thus formed has significantly improved device lifetime and light emission efficiency.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a process for manufacturing a group III nitride compound semiconductor according to a first specific example of the present invention.
FIG. 2 is a cross-sectional view showing details of a side surface of an epitaxially grown layer in the first embodiment.
FIG. 3 is a cross-sectional view showing a configuration of a group III nitride compound semiconductor light emitting device according to a second specific example of the present invention.
FIG. 4 is a cross-sectional view showing a configuration of a group III nitride compound semiconductor light emitting device according to a third specific example of the present invention.
[Explanation of symbols]
1 Silicon (Si) substrate silicon dioxide (SiO ₂₎ film 3 n-AlGaN: high temperature growth n-GaN forming a reaction preventing layer 4 strain reducing layer 411 and 412 strain reducing layer made of Si: Si layer 421 strain Low-temperature grown n-AlGaN: Si layer forming a relaxation layer 5 GaN layer 100 Light-emitting diode 200 Laser diode 106, 206 n-AlGaN cladding layer 207 n-GaN guide layer 107, 208 Light-emitting layer 209 p-GaN guide layer 108, 210 p-AlGaN cladding layer 109, 211 p-GaN layer 110, 212 p-electrode 111, 213 n-electrode

Claims (12)

In the method for producing a group III nitride compound semiconductor obtained by epitaxial growth of a group III nitride compound semiconductor on a substrate,
On the substrate surface, a mask material in which the group III nitride compound semiconductor is not epitaxially grown is formed in a lattice shape, and the substrate surface is separated and exposed, and
Forming a strain relaxation layer in which a group III nitride compound semiconductor of the same or different composition is alternately formed twice or more in two different temperature ranges above the separately exposed substrate surfaces;
Forming a desired group III nitride compound semiconductor on the strain relaxation layer,
A method for producing a group III nitride compound semiconductor, wherein group III nitride compound semiconductors formed above a substrate surface are formed separately from each other.   2. The method for producing a group III nitride compound semiconductor according to claim 1, wherein the two different temperature ranges are 200 ° C. or more and 600 ° C. or less and 900 ° C. or more and 1200 ° C. or less.   The group III nitride compound semiconductor layer formed at 200 ° C. to 600 ° C. has a thickness of 10 nm to 100 nm, and the group III nitride compound semiconductor layer formed at 900 ° C. to 1200 ° C. has a thickness of 200 nm. 3. The method for producing a group III nitride compound semiconductor according to claim 2, wherein the thickness is 1 μm or less. Area of the each separated by exposed substrate surface, III nitride compound semiconductor according to any one of claims 1 to 3, characterized in that at 0.01 mm ² or more 1 mm ² or less Manufacturing method. The group III nitride compound according to any one of claims 1 to 3 , wherein an area of the substrate surface exposed separately is 0.01 mm ² or more and 0.3 mm ² or less. Semiconductor manufacturing method. The method for producing a group III nitride compound semiconductor according to any one of claims 1 to 5 , wherein the substrate is made of silicon (Si). The method for producing a group III nitride compound semiconductor according to any one of claims 1 to 6 , wherein the mask material is mainly made of silicon dioxide (SiO ₂ ). Including a step of forming a reaction prevention layer mainly composed of a single crystal on the surface of the substrate exposed separately in order to prevent a chemical reaction between the substrate and the upper group III nitride compound semiconductor during the manufacturing process. The method for producing a group III nitride compound semiconductor according to any one of claims 1 to 7 , wherein: 9. The method for producing a group III nitride compound semiconductor according to claim 8 , wherein the thickness of the reaction preventing layer is 100 nm or more and 1 μm or less. The reaction preventing layer, any one of claims 1 to 9, wherein the composition of a Group III nitride compound semiconductor aluminum in Group III (Al) is the molar ratio of 30% or more 1 A method for producing a Group III nitride compound semiconductor according to Item. A group III nitride formed on a group III nitride compound semiconductor layer obtained by the method for producing a group III nitride compound semiconductor according to any one of claims 1 to 10 . Compound semiconductor device. A different group III nitride compound semiconductor layer is formed on the group III nitride compound semiconductor layer obtained by the method for producing a group III nitride compound semiconductor according to any one of claims 1 to 10. A group III nitride compound semiconductor light emitting device obtained by stacking.

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