[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JP3628028B2 - Electronic circuit equipment - Google Patents

Electronic circuit equipment Download PDF

Info

Publication number
JP3628028B2
JP3628028B2 JP19699192A JP19699192A JP3628028B2 JP 3628028 B2 JP3628028 B2 JP 3628028B2 JP 19699192 A JP19699192 A JP 19699192A JP 19699192 A JP19699192 A JP 19699192A JP 3628028 B2 JP3628028 B2 JP 3628028B2
Authority
JP
Japan
Prior art keywords
circuit board
resistor
resistors
circuit
resistance value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP19699192A
Other languages
Japanese (ja)
Other versions
JPH0645111A (en
Inventor
長坂  崇
祐司 大谷
賢吾 岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP19699192A priority Critical patent/JP3628028B2/en
Priority to US08/091,718 priority patent/US5483217A/en
Publication of JPH0645111A publication Critical patent/JPH0645111A/en
Application granted granted Critical
Publication of JP3628028B2 publication Critical patent/JP3628028B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【0001】
【産業上の利用分野】
本発明は、電子回路装置に関し、例えば特に樹脂パッケージ型ハイブリッドICに関する。
【0002】
【従来の技術】
従来の樹脂パッケージ型ハイブリッドICは、リード取り出し構造によりSIPタイプ及びDIPタイプに分類されるが、いずれも樹脂封止(モールド)の場合は、注型法、浸漬法、トランスファ法などにより金型又はケースに回路基板を予め挿入しておき、液状又は粉体状の熱硬化性樹脂(例えばエポキシ樹脂やシリコーン樹脂)を用いて封止している。
【0003】
【発明が解決しようとする課題】
しかしながら上記した従来の樹脂パッケージ型ハイブリッドICでは、主として封止樹脂硬化時の収縮やその後の冷却による樹脂の膨張収縮過程で、モールド樹脂部と回路基板との間の収縮率や熱膨張率の差により両者間に応力が発生し、この応力が回路基板に固定された抵抗器に作用し、その結果、この抵抗器の抵抗値が受承する応力に応じて変化してしまう。
【0004】
本発明者らの試験、解析によれば、封止樹脂部の収縮により回路基板には圧縮応力及び面直方向の曲げ応力が作用し、この曲げ応力により上記抵抗器に圧縮もしくは引張り応力が掛かることがわかった。上記曲げ応力は回路基板各部においてばらつくので、回路基板上の抵抗器の固定位置によって抵抗器の抵抗値がばらつき、その結果、回路の出力がばらつく。また、ハイブリッドICに外部から加えられる力によっても抵抗器の抵抗値が変化することを確認した。
【0005】
本発明は、上記問題点に鑑みなされたものであり、封止樹脂部と回路基板との間に生じる応力に起因する抵抗器の抵抗値変動による回路の出力ばらつきを低減可能な電子回路装置を提供することを、その目的としている。
【0006】
【課題を解決するための手段】
本発明の電子回路装置は、ケース内に収納された回路基板と、前記ケースの内面に配設されて前記回路基板の短辺を保持する一対のガイド突起と、前記回路基板の両面に固定された複数の抵抗器を相互接続してなる合成抵抗器と、前記回路基板上に搭載された受動回路素子及び能動回路素子と、前記ケース内に充填されたモールド樹脂部とを備え、前記回路基板の両面に個別に固定された複数の抵抗器は、前記回路基板の短辺から等しい距離の位置に固定されていることを特徴としている。
好適態様において、前記回路基板の両面に個別に固定された複数の抵抗器は、互いに直列接続される。
【0007】
本発明でいう抵抗器として、印刷後、焼成して形成した厚膜抵抗体の他、各種PVD法やCVD法で形成された薄膜抵抗体を採用することができる。これら抵抗器は、回路基板に導電ペーストや接着剤や半田などにより接着、固定されることができ、その他、回路基板上に直接形成される抵抗器も包含される。そして、これら抵抗器は、コンデンサなどの他の受動回路素子やIC及びトランジスタなどの能動回路素子とともに回路基板に搭載される。
【0008】
【作用及び発明の効果】
封止樹脂部の硬化時の収縮及びその後の加熱・冷却に伴う膨張・収縮により封止樹脂部と回路基板との間に応力が発生し、回路基板の表裏に作用する応力の差により回路基板が反る。又は外部からの力により回路基板が反る。この反りにより、回路基板の一面に固定された抵抗器に圧縮応力が掛かり、他面に固定された抵抗器に引張り応力が掛かる。圧縮応力を受ける抵抗器の抵抗値は減少し、引張り応力を受ける抵抗器の抵抗値は増加する。
【0009】
本発明では、複数の抵抗器を相互接続して合成抵抗器を構成し、抵抗値減少の抵抗器が合成抵抗器の抵抗変化に与える影響により、抵抗値増加の抵抗器が合成抵抗器の抵抗変化に与える影響の一部又は全部をキャンセルする。
このようにすれば、封止樹脂部と回路基板との間の応力又は外力による回路基板の変形にもかかわらず、回路基板に固定された合成抵抗器の抵抗値の変化が減少又は相殺される。
【0010】
【実施例】
(実施例1)
本発明の電子回路装置の一実施例を図1〜図3に示す。
この電子回路装置はハイブリッドICであって、ケ−ス1と、ケ−ス1内に収容された回路基板2と、ケ−ス1内に充填されたモールド樹脂部3と、一端が回路基板2に固定され他端がモールド樹脂部3を貫通して外部に突出するリード4とを備えている。なお、図1では回路基板2の主面上のモールド樹脂部3は剥離して図示している。
【0011】
ケ−ス1は、縦、横、高さが18mm×50mm×6mmの直方中空体形状を有し、底面が開口されている。ケ−ス1の壁厚は約1mmで、PBT樹脂の射出成形により形成されている。ケ−ス1の長手方向両端に位置する両内端面には、一対のガイド突起11(図3参照)が互いに平行に突設されている。
回路基板2はアルミナを素材とする多層基板であって、回路基板2の両短辺21、22はそれぞれガイド突起対11の間にゆるやかに嵌入されて保持されている。回路基板2の寸法は、縦、横、厚さ13mm×47.5mm×0.8mmであり、その線膨張率は約7.5×10−6/℃である。回路基板2には単層もしくは多層の配線パターン(図示せず)が形成されている。回路基板2の一面には、各種回路部品が固定され、電気接続されている。特にこの実施例では、回路基板2の回路素子搭載面Aに回路基板2の短辺21に近接しかつ短辺21からL1の距離に位置して抵抗器R1が固定され、同様に、回路基板2の裏面Bに回路基板2の短辺21に近接しかつ短辺21からからL1の距離に位置して抵抗器R2が固定されている(図3参照)。
【0012】
抵抗器R1、R2は、縦、横、厚さが1.5mm×0.85mm×10μmの長方形の膜からなり、抵抗器R1、R2の長手方向は短辺21と平行となっている。抵抗器R1、R2は図4に示すように、厚膜抵抗ペーストをスクリーン印刷技術により形成され、焼成された厚膜抵抗体であって、それらの両端にはAg,Ag/Pd,Cu,等を素材とする厚さ約10μmの配線層5a〜5dが形成されている。
【0013】
また、回路基板2にはスルーホール6が開口され、スルーホール6には埋め込み導体7が埋め込まれ、埋め込み導体7は配線層5bと配線層5cとを接続し、これにより抵抗器R1、R2が直列接続されて合成抵抗Rを構成している。
モールド樹脂部3は、ケ−ス1内へ回路基板2を挿入後、エポキシ樹脂をケ−ス1内に注入し、熱硬化させ、冷却して形成される。このエポキシ樹脂の線膨張率は約51×10−6/℃、液状態から硬化後の体積収縮率は約96%である。
【0014】
上記した回路基板2上の回路は、モノリシックのオペアンプOPと、抵抗器R1、2からなる初段センスアンプを有し、このオペアンプ増幅回路の電圧増幅率kは、合成抵抗器Rの抵抗値に比例するようになっている。
上記したハイブリッドICは、封止樹脂部3の硬化収縮により図5に略示するように回路素子搭載面A側へ反る。これは、ケース内の回路素子搭載面A側の封止樹脂量が、裏面側の樹脂量よりも多いために、回路基板2の回路素子搭載面Aに掛かる圧縮力(特にその長手方向における)が、裏面Bのそれに優り、そのために、回路基板2の中央部が回路基板2の両短辺21、22に対して回路素子搭載面Aを窪ませる方向に反るためと考えられる。なお、この反り量すなわち基板への応力は当然、温度変化に応じても変化する。また、回路基板2の中央部は回路基板2の両長辺23、24に対しても回路素子搭載面Aを窪ませる方向に反るが、この反り量は比較的小さい。また、回路素子搭載面A上に固定した各回路素子により回路基板2の各部は局部的に剛性強化され、各部の反り量及び応力分布はばらつくが、この実施例では無視する。
【0015】
このような回路基板2の反り(すなわち回路基板2の面直方向の曲げ応力)により、その上に固定された抵抗器R1に圧縮応力が、抵抗器R2に引張り応力が加えられる。
回路基板2に加えられる応力と回路基板に固定された抵抗器の抵抗値変化との関係を調べた。試験用の回路基板20は、図6に示すように、縦、横、厚さが13mm×47.5mm×0.8mmの寸法を有し、台座90で回路基板20の長手方向の両端部を支持した。抵抗器Rは回路基板20の短辺21から15.3mmの位置に固定され、回路基板20の中央を回路基板20に向けて押圧して、抵抗値の変化を調べた。その結果を図7に示す。
【0016】
図7から、押圧力(曲げ応力)と抵抗値の変化とはほぼ直線関係にあり、この押圧力による回路基板2の湾曲により、抵抗器R1に圧縮応力が生じる場合には抵抗減少、抵抗器R1に引張り応力が生じる場合には抵抗増加が生じることがわかった。なお、この実施例では、抵抗器R1の長手方向すなわち通電方向は回路基板2の長手方向としたが、抵抗器R1の長手方向すなわち通電方向を回路基板2の長手方向との角度を変えても、抵抗器R1に圧縮応力が生じる場合には抵抗減少、抵抗器R1に引張り応力が生じる場合には抵抗増加が生じることがわかった。
【0017】
次に、図6の回路基板20における反り量(変位量)と抵抗値変化量との関係を調べた。その結果を図8に示す。ただし、反り量は基板中央部の最大変位量とした。
なお、回路基板2の両短辺21、22を支持して中央部を押圧した場合、回路基板2の弾性変形により回路基板2の長手方向各部に作用する圧縮あるいは引張り応力は図9の略図に示すように、中央部が最大で両短辺21、22でほぼ0となるように変化する。
【0018】
次に、抵抗器Rが上記位置に固定された回路基板20をケ−ス1に収容し、モールド樹脂部で全面モールドした場合の抵抗器Rの抵抗値変化を調べた。その結果、この抵抗器R1の抵抗値変化率の平均値は約−0.7%であった。
以下、本実施例の特徴点を説明する。
この実施例では、抵抗器R1、R2は、その抵抗値が等しく、かつ短辺21から回路基板2の長手方向に等距離に位置して回路基板2の表裏に固定されている。その結果、上記した回路基板2を通じて抵抗器R1、R2に作用する圧縮応力と引張り応力とは等しくなり、抵抗器R1、R2の抵抗値変化量は等しくその増減方向が反対となる。
【0019】
したがって、図11に示すように印加応力が0の場合の抵抗値がrである両抵抗器R1、R2を直列接続した場合、印加応力による抵抗値変化はΔr、−Δrとすれば、合成抵抗Rの抵抗値はr+r+Δr−Δr=2rとなり、印加応力に対して抵抗値変化をキャンセルできる。
またこの実施例では、抵抗器R1、R2を短辺21に近接して配置するため、回路基板2の曲げ応力に比例する抵抗器R1、R2に作用する応力も小さく、応力のばらつきも小さくできる。その結果、このオペアンプ電圧増幅回路の出力特性(電圧増幅率k)に対する回路基板2の反りの影響が低減される。
【0020】
更にこの実施例では、抵抗器R1、R2の長手方向が短辺21と平行に配置されている。このようにすれば、抵抗器R1、R2の各部に作用する圧縮応力のばらつきが小さく、両抵抗器R1、R2の抵抗値のばらつきも小さくなる。
以上の結果として、このオペアンプ電圧増幅回路からなる初段センスアンプ の電圧増幅率のばらつきを大幅に低減することができた。通常、微小な入力信号電圧又は信号電流を増幅する初段センスアンプの電圧増幅率はより大きな信号電圧を扱うその後の回路段に比べて格段に高い安定度が要求されるが、本実施例によれば電圧増幅率のばらつきを大幅に低減でき、このような初段センスアンプに好適である。
【0021】
なお、抵抗器R1、R2の各長手方向を回路基板2の長辺23、24と平行とすることも可能であり、また抵抗器R1、R2の長手方向と回路基板2の長手方向との角度を所定値としてもよい。また、図12に示すようにスルーホールを2個設けて抵抗器R1、R2を並列接続することも可能である。また、両側の抵抗器R1、R2の表面に応力緩和用のシリコンゲルなどの膜を被覆することも可能である。また、上記実施例では抵抗器R1、R2の初期抵抗値は等しく設定したが、等しくなくてもよい。すなわち、等しい場合には短辺21から等距離であるので、抵抗値の変化をほぼ0にできるが、初期抵抗値が多少差があっても合成抵抗器Rの抵抗値の変化を減少させることはできる。更に、上記実施例では両抵抗器R1、R2の短辺21からの距離を等しくしたが、等しくなくても抵抗値Rの変化を低減することはできる。
【0022】
(実施例2)
他の実施例を図10に示す。
この実施例では、抵抗器R1を短辺21からL1の距離に、抵抗器R2を短辺21からL2の距離に固定している。各々の抵抗体の応力に対する抵抗値変動量は基板端部からの距離の関数(F(L),F(L))である。このため使用する抵抗体(材料、形状等に依存)の抵抗値変動量を考慮して抵抗体を配置(固定)すれば、2つの抵抗体の合成抵抗値変動を0にできる。
【0023】
以上の実施例では、一対の抵抗器R1、R2による抵抗値変化の相殺を説明したが、合成抵抗器Rを3個以上の抵抗器で構成できることは当然である。
(実施例3)
他の実施例を図13に示す。
この実施例は、抵抗器R1、R2の配線層5b、5cをスルーホールの代わりにリード4により短絡するものである。8は半田である。
【0024】
このようにすれば、スルーホールの省略が可能となる。
なお上記各実施例ではオペアンプ電圧増幅回路への応用例を説明したが、本発明は電流増幅、波形処理、周波数処理、デジタル処理、コンパレータ、A/D変換、D/A変換などの諸回路に広く応用できることは当然であり、特に最も高精度を要求されるこれら回路の初段部分に好適である。
【図面の簡単な説明】
【図1】実施例1を示す断面図、
【図2】実施例1を示す断面図、
【図3】実施例1を示す断面図、
【図4】図1の抵抗器の拡大R2断面図、
【図5】回路基板の反りを示す模式図、
【図6】回路基板への曲げ力と抵抗器の抵抗値変化率との関係を試験するための試験装置を示す模式図、
【図7】図6の試験装置による試験結果を示す特性図、
【図8】回路基板への変位量(厚さ方向)と抵抗器の抵抗値変化量との関係を示す特性図、
【図9】回路基板の湾曲に伴い抵抗器に加わる応力の回路基板の長手方向への変化を示す特性図、
【図10】実施例2を示す断面図、
【図11】抵抗器R1、R2の直列接続を示す回路図、
【図12】抵抗器R1、R2の並列接続を示す回路図、
【図13】実施例3を示す断面図、
【符号の簡単な説明】
1はケース、2は回路基板、3はモールド樹脂部、4はリード、R1、R2は抵抗器、
[0001]
[Industrial application fields]
The present invention relates to an electronic circuit device, and more particularly to a resin package type hybrid IC.
[0002]
[Prior art]
Conventional resin package type hybrid ICs are classified into SIP type and DIP type according to the lead take-out structure. However, in the case of resin sealing (mold), the mold or immersion method, transfer method, etc. A circuit board is inserted in the case in advance and sealed with a liquid or powdery thermosetting resin (for example, epoxy resin or silicone resin).
[0003]
[Problems to be solved by the invention]
However, in the conventional resin package type hybrid IC described above, the difference in shrinkage rate and thermal expansion coefficient between the mold resin part and the circuit board mainly during shrinkage when the sealing resin is cured and subsequent expansion and shrinkage of the resin due to cooling. As a result, a stress is generated between the two, and this stress acts on the resistor fixed to the circuit board. As a result, the resistance value of the resistor changes according to the received stress.
[0004]
According to the test and analysis by the present inventors, the compressive stress and the bending stress in the direction perpendicular to the surface act on the circuit board due to the shrinkage of the sealing resin portion, and the bending stress exerts compressive or tensile stress on the resistor. I understood it. Since the bending stress varies in each part of the circuit board, the resistance value of the resistor varies depending on the fixed position of the resistor on the circuit board. As a result, the output of the circuit varies. In addition, it was confirmed that the resistance value of the resistor also changed due to the external force applied to the hybrid IC.
[0005]
The present invention has been made in view of the above problems, and provides an electronic circuit device that can reduce circuit output variations due to resistance value fluctuations of resistors caused by stress generated between a sealing resin portion and a circuit board. Its purpose is to provide.
[0006]
[Means for Solving the Problems]
An electronic circuit device of the present invention is fixed to both sides of a circuit board housed in a case, a pair of guide protrusions disposed on an inner surface of the case and holding a short side of the circuit board, and the circuit board. It includes a plurality of resistors interconnected formed by combining resistors and a passive circuit element and the active circuit element mounted on the circuit board, and a mold resin portion filled in the case was, the circuit board a plurality of resistors that are individually fixed to both sides of the is characterized that you have been fixed at a position equal distance from the short side of the circuit board.
In a preferred embodiment, the plurality of resistors individually fixed on both surfaces of the circuit board are connected in series with each other.
[0007]
As the resistor referred to in the present invention, a thin film resistor formed by various PVD methods or CVD methods can be employed in addition to a thick film resistor formed by firing after printing. These resistors can be bonded and fixed to the circuit board with a conductive paste, adhesive, solder, or the like, and other resistors formed directly on the circuit board are also included. These resistors are mounted on a circuit board together with other passive circuit elements such as capacitors and active circuit elements such as ICs and transistors.
[0008]
[Operation and effect of the invention]
Stress is generated between the sealing resin part and the circuit board due to shrinkage at the time of curing of the sealing resin part and expansion / shrinkage after heating / cooling, and the circuit board is caused by a difference in stress acting on the front and back of the circuit board. Is warped. Alternatively, the circuit board is warped by an external force. Due to this warpage, a compressive stress is applied to the resistor fixed to one surface of the circuit board, and a tensile stress is applied to the resistor fixed to the other surface. The resistance value of the resistor subjected to compressive stress decreases and the resistance value of the resistor subjected to tensile stress increases.
[0009]
In the present invention, a plurality of resistors are interconnected to form a combined resistor, and the resistor having the increased resistance value is the resistance of the combined resistor due to the influence of the resistor having the decreased resistance value on the resistance change of the combined resistor. Cancel some or all of the impact on the change.
In this way, the change in the resistance value of the composite resistor fixed to the circuit board is reduced or offset despite the deformation of the circuit board due to the stress or external force between the sealing resin portion and the circuit board. .
[0010]
【Example】
(Example 1)
One embodiment of the electronic circuit device of the present invention is shown in FIGS.
This electronic circuit device is a hybrid IC, and includes a case 1, a circuit board 2 accommodated in the case 1, a mold resin portion 3 filled in the case 1, and one end of the circuit board. 2 and a lead 4 that protrudes to the outside through the mold resin portion 3. In FIG. 1, the mold resin portion 3 on the main surface of the circuit board 2 is separated and shown.
[0011]
The case 1 has a rectangular hollow body shape of 18 mm × 50 mm × 6 mm in height, width, and height, and the bottom surface is opened. The wall thickness of the case 1 is about 1 mm, and is formed by injection molding of PBT resin. A pair of guide protrusions 11 (see FIG. 3) are provided in parallel with each other on both inner end faces located at both longitudinal ends of the case 1.
The circuit board 2 is a multilayer board made of alumina, and both short sides 21 and 22 of the circuit board 2 are gently fitted and held between the pair of guide protrusions 11. The dimensions of the circuit board 2 are vertical, horizontal, thickness 13 mm × 47.5 mm × 0.8 mm, and its linear expansion coefficient is about 7.5 × 10 −6 / ° C. A single-layer or multilayer wiring pattern (not shown) is formed on the circuit board 2. Various circuit components are fixed and electrically connected to one surface of the circuit board 2. Particularly in this embodiment, the resistor R1 is fixed to the circuit element mounting surface A of the circuit board 2 so as to be close to the short side 21 of the circuit board 2 and at a distance L1 from the short side 21. A resistor R2 is fixed to the back surface B of 2 near the short side 21 of the circuit board 2 and at a distance L1 from the short side 21 (see FIG. 3).
[0012]
The resistors R1 and R2 are formed of a rectangular film having a length, width, and thickness of 1.5 mm × 0.85 mm × 10 μm, and the longitudinal directions of the resistors R1 and R2 are parallel to the short side 21. As shown in FIG. 4, the resistors R1 and R2 are thick film resistors formed by baking a thick film resistor paste by a screen printing technique and baked, and Ag, Ag / Pd, Cu, etc. are provided at both ends thereof. Wiring layers 5a to 5d having a thickness of about 10 μm are formed.
[0013]
Further, a through hole 6 is opened in the circuit board 2, and a buried conductor 7 is buried in the through hole 6, and the buried conductor 7 connects the wiring layer 5b and the wiring layer 5c, whereby the resistors R1 and R2 are connected to each other. The combined resistor R is connected in series.
The mold resin portion 3 is formed by inserting the circuit board 2 into the case 1, injecting an epoxy resin into the case 1, thermosetting, and cooling. The linear expansion coefficient of this epoxy resin is about 51 × 10 −6 / ° C., and the volume shrinkage ratio after curing from the liquid state is about 96%.
[0014]
The circuit on the circuit board 2 has a monolithic operational amplifier OP and a first-stage sense amplifier composed of resistors R1 and R2. The voltage amplification factor k of the operational amplifier amplifier circuit is proportional to the resistance value of the combined resistor R. It is supposed to be.
The hybrid IC described above warps to the circuit element mounting surface A side as schematically shown in FIG. 5 due to curing shrinkage of the sealing resin portion 3. This is because the amount of sealing resin on the circuit element mounting surface A side in the case is larger than the amount of resin on the back surface side, so that the compressive force applied to the circuit element mounting surface A of the circuit board 2 (particularly in the longitudinal direction). However, it is considered that it is superior to that of the back surface B, and for this reason, the center portion of the circuit board 2 warps in the direction in which the circuit element mounting surface A is depressed with respect to both short sides 21 and 22 of the circuit board 2. The amount of warpage, that is, the stress on the substrate, naturally changes depending on the temperature change. Further, although the center portion of the circuit board 2 warps in the direction in which the circuit element mounting surface A is depressed with respect to both the long sides 23 and 24 of the circuit board 2, the amount of warpage is relatively small. Further, each part of the circuit board 2 is locally strengthened by each circuit element fixed on the circuit element mounting surface A, and the amount of warpage and stress distribution of each part varies, but in this embodiment it is ignored.
[0015]
Due to the warp of the circuit board 2 (that is, the bending stress in the direction perpendicular to the surface of the circuit board 2), a compressive stress is applied to the resistor R1 fixed thereon, and a tensile stress is applied to the resistor R2.
The relationship between the stress applied to the circuit board 2 and the change in the resistance value of the resistor fixed to the circuit board was examined. As shown in FIG. 6, the test circuit board 20 has dimensions of 13 mm × 47.5 mm × 0.8 mm in length, width, and thickness. Supported. The resistor R was fixed at a position of 15.3 mm from the short side 21 of the circuit board 20, and the center of the circuit board 20 was pressed toward the circuit board 20 to examine a change in resistance value. The result is shown in FIG.
[0016]
From FIG. 7, the pressing force (bending stress) and the change of the resistance value are in a substantially linear relationship. When the compressive stress is generated in the resistor R1 due to the bending of the circuit board 2 due to the pressing force, the resistance is decreased. It has been found that resistance increases when tensile stress is generated in R1. In this embodiment, the longitudinal direction of the resistor R1, that is, the energizing direction, is the longitudinal direction of the circuit board 2. It has been found that when compressive stress is generated in the resistor R1, the resistance is decreased, and when tensile stress is generated in the resistor R1, the resistance is increased.
[0017]
Next, the relationship between the warpage amount (displacement amount) and the resistance value change amount in the circuit board 20 of FIG. 6 was examined. The result is shown in FIG. However, the amount of warpage was the maximum displacement at the center of the substrate.
In addition, when both the short sides 21 and 22 of the circuit board 2 are supported and the center part is pressed, the compressive or tensile stress acting on each part in the longitudinal direction of the circuit board 2 due to elastic deformation of the circuit board 2 is shown in the schematic diagram of FIG. As shown in the figure, the central portion changes so as to be approximately 0 at both short sides 21 and 22 at the maximum.
[0018]
Next, the change in the resistance value of the resistor R when the circuit board 20 having the resistor R fixed at the above-described position was accommodated in the case 1 and molded entirely with the mold resin portion was examined. As a result, the average value of the resistance value change rate of the resistor R1 was about -0.7%.
Hereinafter, features of the present embodiment will be described.
In this embodiment, the resistors R <b> 1 and R <b> 2 have the same resistance value, and are fixed on the front and back of the circuit board 2 at an equal distance from the short side 21 in the longitudinal direction of the circuit board 2. As a result, the compressive stress and the tensile stress acting on the resistors R1 and R2 through the circuit board 2 described above are equal, and the resistance value change amounts of the resistors R1 and R2 are equal, and the increasing / decreasing directions are opposite.
[0019]
Therefore, as shown in FIG. 11, when both resistors R1 and R2 having a resistance value r when the applied stress is 0 are connected in series, if the resistance value change due to the applied stress is Δr and −Δr, the combined resistance The resistance value of R becomes r + r + Δr−Δr = 2r, and the resistance value change can be canceled with respect to the applied stress.
In this embodiment, the resistors R1 and R2 are arranged close to the short side 21, so that the stress acting on the resistors R1 and R2 proportional to the bending stress of the circuit board 2 is small, and the variation in stress can be reduced. . As a result, the influence of the warp of the circuit board 2 on the output characteristics (voltage amplification factor k) of the operational amplifier voltage amplifier circuit is reduced.
[0020]
Furthermore, in this embodiment, the longitudinal directions of the resistors R1 and R2 are arranged in parallel with the short side 21. In this way, variation in compressive stress acting on each part of resistors R1 and R2 is small, and variation in resistance values of both resistors R1 and R2 is also small.
As a result of the above, the variation in the voltage amplification factor of the first-stage sense amplifier comprising this operational amplifier voltage amplifier circuit could be greatly reduced. Normally, the voltage amplification factor of the first-stage sense amplifier that amplifies a minute input signal voltage or signal current requires much higher stability than the subsequent circuit stage that handles a larger signal voltage. Therefore, the variation in voltage amplification factor can be greatly reduced, which is suitable for such a first-stage sense amplifier.
[0021]
The longitudinal directions of the resistors R1 and R2 can be parallel to the long sides 23 and 24 of the circuit board 2, and the angle between the longitudinal direction of the resistors R1 and R2 and the longitudinal direction of the circuit board 2 is also possible. May be a predetermined value. Moreover, as shown in FIG. 12, it is also possible to provide two through holes and connect the resistors R1 and R2 in parallel. It is also possible to cover the surfaces of the resistors R1 and R2 on both sides with a film such as silicon gel for stress relaxation. In the above embodiment, the initial resistance values of the resistors R1 and R2 are set to be equal, but may not be equal. That is, since the distance is equal from the short side 21 when they are equal, the change in the resistance value can be almost zero, but the change in the resistance value of the composite resistor R can be reduced even if the initial resistance value is slightly different. I can. Further, in the above embodiment, the distances from the short sides 21 of both resistors R1 and R2 are made equal, but the change in resistance value R can be reduced even if they are not equal.
[0022]
(Example 2)
Another embodiment is shown in FIG.
In this embodiment, the resistor R1 is fixed at a distance from the short side 21 to L1, and the resistor R2 is fixed at a distance from the short side 21 to L2. The resistance value fluctuation amount with respect to the stress of each resistor is a function (F (L 1 ), F (L 2 )) of the distance from the edge of the substrate. For this reason, if the resistors are arranged (fixed) in consideration of the resistance value fluctuation amount of the resistor used (depending on the material, shape, etc.), the combined resistance value fluctuation of the two resistors can be reduced to zero.
[0023]
In the above embodiment, the canceling of the resistance value change by the pair of resistors R1 and R2 has been described. However, it is natural that the combined resistor R can be configured by three or more resistors.
(Example 3)
Another embodiment is shown in FIG.
In this embodiment, the wiring layers 5b and 5c of the resistors R1 and R2 are short-circuited by leads 4 instead of through holes. 8 is solder.
[0024]
In this way, the through hole can be omitted.
In the above embodiments, application examples to the operational amplifier voltage amplification circuit have been described. However, the present invention is applied to various circuits such as current amplification, waveform processing, frequency processing, digital processing, comparator, A / D conversion, and D / A conversion. Naturally, it can be widely applied, and is particularly suitable for the first stage portion of these circuits requiring the highest precision.
[Brief description of the drawings]
1 is a cross-sectional view showing Example 1;
FIG. 2 is a sectional view showing Example 1;
FIG. 3 is a sectional view showing Example 1;
4 is an enlarged R2 cross-sectional view of the resistor of FIG.
FIG. 5 is a schematic diagram showing warpage of a circuit board;
FIG. 6 is a schematic diagram showing a test apparatus for testing the relationship between the bending force to the circuit board and the resistance value change rate of the resistor;
FIG. 7 is a characteristic diagram showing a test result by the test apparatus of FIG.
FIG. 8 is a characteristic diagram showing the relationship between the displacement amount (thickness direction) to the circuit board and the resistance value change amount of the resistor;
FIG. 9 is a characteristic diagram showing the change in the longitudinal direction of the circuit board of the stress applied to the resistor as the circuit board is curved;
FIG. 10 is a sectional view showing Example 2.
FIG. 11 is a circuit diagram showing series connection of resistors R1 and R2.
FIG. 12 is a circuit diagram showing parallel connection of resistors R1 and R2.
FIG. 13 is a sectional view showing Example 3.
[Brief description of symbols]
1 is a case, 2 is a circuit board, 3 is a mold resin part, 4 is a lead, R1 and R2 are resistors,

Claims (2)

ケース内に収納された回路基板と、
前記ケースの内面に配設されて前記回路基板の短辺を保持する一対のガイド突起と、
前記回路基板の両面に個別に固定された複数の抵抗器を相互接続してなる合成抵抗器と、
前記回路基板上に搭載された受動回路素子及び能動回路素子と、
前記ケース内に充填されたモールド樹脂部とを備え、
前記回路基板の両面に個別に固定された複数の抵抗器は、前記回路基板の短辺から等しい距離の位置に固定されていることを特徴とする電子回路装置。
A circuit board housed in a case;
A pair of guide protrusions disposed on the inner surface of the case to hold the short side of the circuit board;
A combined resistor formed by interconnecting a plurality of resistors individually fixed on both sides of the circuit board;
A passive circuit element and an active circuit element mounted on the circuit board;
A mold resin portion filled in the case ,
The electronic circuit device, wherein the plurality of resistors individually fixed on both surfaces of the circuit board are fixed at positions at an equal distance from the short side of the circuit board.
前記回路基板の両面に個別に固定された複数の抵抗器は、互いに直列接続される請求項1記載の電子回路装置。The electronic circuit device according to claim 1, wherein the plurality of resistors individually fixed to both surfaces of the circuit board are connected in series to each other.
JP19699192A 1992-07-15 1992-07-23 Electronic circuit equipment Expired - Fee Related JP3628028B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP19699192A JP3628028B2 (en) 1992-07-23 1992-07-23 Electronic circuit equipment
US08/091,718 US5483217A (en) 1992-07-15 1993-07-15 Electronic circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19699192A JP3628028B2 (en) 1992-07-23 1992-07-23 Electronic circuit equipment

Publications (2)

Publication Number Publication Date
JPH0645111A JPH0645111A (en) 1994-02-18
JP3628028B2 true JP3628028B2 (en) 2005-03-09

Family

ID=16367014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19699192A Expired - Fee Related JP3628028B2 (en) 1992-07-15 1992-07-23 Electronic circuit equipment

Country Status (1)

Country Link
JP (1) JP3628028B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180093461A (en) * 2017-02-13 2018-08-22 삼성전기주식회사 Resistor element, manufacturing method of the same and resistor element assembly

Also Published As

Publication number Publication date
JPH0645111A (en) 1994-02-18

Similar Documents

Publication Publication Date Title
DE19727214C2 (en) Semiconductor acceleration sensor, especially for airbags
US7441467B2 (en) Compression strain sensor
JP3193752B2 (en) Accelerometer device
US7098580B2 (en) Piezoelectric oscillator
KR920000076B1 (en) Semiconductor device
US7394610B2 (en) Acceleration sensor and magnetic disk device using the same
JP3628028B2 (en) Electronic circuit equipment
JP3685501B2 (en) Electronic circuit equipment
JP3070272B2 (en) Electronic circuit device
JPH0262069A (en) Semiconductor device
US5483217A (en) Electronic circuit device
JP3047632B2 (en) Electronic circuit device
JPS61136249A (en) Hybrid ic
US20240059554A1 (en) Mems module
JPH06307950A (en) Strain sensor
JP2771923B2 (en) Semiconductor pressure sensor
JPS586951B2 (en) electronic circuit equipment
JPS60208801A (en) Chip resistor
JP2010230513A (en) Acceleration sensor and method of manufacturing the same
EP1204305A2 (en) Device comprising an electrical circuit carried by a carrier element and method for the manufacture of such a device
JP2003207406A (en) Semiconductor sensor device
JPH03248029A (en) Semiconductor pressure sensor
JPS60202983A (en) Integrated circuit
JPS63261841A (en) Structure of burying and packaging semiconductor device in multilayered interconnection substrate
JPH04111386A (en) Electronic device

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20041104

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20041207

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071217

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101217

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees