JPH04111386A - Electronic device - Google Patents
Electronic deviceInfo
- Publication number
- JPH04111386A JPH04111386A JP2229308A JP22930890A JPH04111386A JP H04111386 A JPH04111386 A JP H04111386A JP 2229308 A JP2229308 A JP 2229308A JP 22930890 A JP22930890 A JP 22930890A JP H04111386 A JPH04111386 A JP H04111386A
- Authority
- JP
- Japan
- Prior art keywords
- electronic device
- tsop
- package
- board
- multilayer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 239000011889 copper foil Substances 0.000 claims description 7
- 238000005476 soldering Methods 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 5
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 239000004744 fabric Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 20
- 229910000679 solder Inorganic materials 0.000 description 19
- 239000011162 core material Substances 0.000 description 12
- 230000007547 defect Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000006903 response to temperature Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
- H05K3/4676—Single layer compositions
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置を有する電子装置に関し、特に、
薄型ICパッケージ(TSOP:Th1n Small
0 utlina P ackage)の半導体装置
を多数箇搭載するメモリモジュール又はTSOP搭載薄
型メモリに適用して有効な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic device having a semiconductor device, and in particular,
Thin IC package (TSOP: Th1n Small
The present invention relates to a technique that is effective when applied to a memory module equipped with a large number of semiconductor devices of 0 utlina package or a thin memory equipped with a TSOP.
従来の半導体集積回路(IC)ボードは、搭載パッケー
ジにSOJ(Small○utline J−1ead
edP ackage)、S OP (S wall
0utline Package)等、基板面からのパ
ッケージ高さが2n以上、リード高さが1mm以上のI
Cパッケージを使用している。Conventional semiconductor integrated circuit (IC) boards have an SOJ (Small*utline J-1ead) mounted on the mounting package.
edP ackage), S OP (S wall
0utline Package), the package height from the board surface is 2n or more, and the lead height is 1mm or more.
I am using C package.
前記ICパッケージボードに関する技術は、「日経エレ
クトロニクスJ 、1987年9月7日号、p99〜1
07に記載されている。The technology related to the IC package board is described in "Nikkei Electronics J, September 7, 1987 issue, p.99-1.
It is described in 07.
しかしながら、本発明者は、前記従来技術を検討した結
果、以下のような問題点を見出した。However, as a result of studying the above-mentioned prior art, the inventor found the following problems.
上記従来技術では、厚さ1膳罵程度の薄型ICパッケー
ジを基板にはんだ付は実装する際のTCバッケージと基
板の熱膨張係数を合わせる考え方を取っておらず、リー
ドのはんだ接合部に、熱膨張係数の差による歪が加わり
、クラック又は破断を生じ、はんだ接合の信頼性が問題
となっていた。The above conventional technology does not take into account the concept of matching the thermal expansion coefficients of the TC package and the board when mounting a thin IC package with a thickness of about one inch on the board, and the solder joints of the leads are soldered. Strain due to the difference in expansion coefficients is added, causing cracks or breaks, and the reliability of solder joints has become a problem.
本発明の目的は、基板側の熱膨張係数をICパッケージ
の値にできるだけ合わせた仕様のものを適用することに
より、ICを多数搭載したモジュールにおいて、はんだ
付は部の信頼性を確保することが可能な技術を提供する
ことにある。The purpose of the present invention is to ensure the reliability of the soldering part in modules equipped with a large number of ICs by applying specifications that match the coefficient of thermal expansion of the board as much as possible to the value of the IC package. Our goal is to provide the technology that is possible.
本発明の前記ならびにその他の目的と新規な特徴は1本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち1代表的なものの概
要を簡単に説明すれば、以下のとおりである。A brief overview of one typical invention disclosed in this application is as follows.
熱膨張係数が7.0×10−”〜3.OXI○′″1の
単層又は10層以下の多層基板を用い、対向リード端子
間の間隔が10mmz以上であり、当該基板からのリー
ドの高さが0 、7 mm以下のパッケージの半導体装
置を、少なくとも1箇面実装した電子装置である。A single layer or multilayer board of 10 or less layers with a thermal expansion coefficient of 7.0 x 10-" to 3.OXI○'"1 is used, the spacing between opposing lead terminals is 10 mmz or more, and the lead from the board is This is an electronic device in which at least one semiconductor device of a package with a height of 0.7 mm or less is mounted.
前記多層配線基板は、セラミックコア板の両面にそれぞ
れ銅箔を張り付け、その上にガラス布にエポキシ樹脂を
含浸して乾燥したプリプレグを重ねて積層し、その上に
銅箔を張り付けた多層配線構造になっている
前記面実装は、はんだ付けで行うものである。The multilayer wiring board has a multilayer wiring structure in which copper foil is pasted on both sides of a ceramic core board, prepreg made by impregnating glass cloth with epoxy resin and dried is laminated, and copper foil is pasted on top of that. The above-mentioned surface mounting is performed by soldering.
前述した手段によれば、TSOPをモジュール基板には
んだ付実装すると、TSOPのモールド部の両端のリー
ドが夫々基板にはんだ接合されることになる。このため
、リードの根元は温度変化に対し、TSOPの熱膨張係
に比例した変位が発生するが、基板側にはんだ付けされ
たリード先端は、基板の熱膨張係数に比例した変化量と
なる。According to the above-described means, when the TSOP is soldered and mounted on the module board, the leads at both ends of the molded portion of the TSOP are soldered to the board, respectively. Therefore, the base of the lead undergoes a displacement proportional to the coefficient of thermal expansion of the TSOP in response to temperature changes, but the tip of the lead soldered to the substrate side undergoes a change proportional to the coefficient of thermal expansion of the substrate.
従って、TSOPと基板の熱膨張係数の差が大きいと、
リード根元とリード先端の変位の差が大きくなり、この
歪がリード先端のはんだ付は部に加わる。Therefore, if the difference in thermal expansion coefficient between TSOP and substrate is large,
The difference in displacement between the lead base and the lead tip becomes large, and this strain is applied to the soldering part of the lead tip.
よって、TSOPと基板の熱膨張係数を合わせることに
より、温度変化によるはんだ接続部への歪を最小限に抑
えることができる。Therefore, by matching the thermal expansion coefficients of the TSOP and the substrate, it is possible to minimize strain on the solder joints due to temperature changes.
以下、本発明の一実施例を図面を用いて具体的に説明す
る。Hereinafter, one embodiment of the present invention will be specifically described using the drawings.
なお、実施例を説明するための全図において、同一機能
を有するものは、同一符号を付け、その繰り返しの説明
は省略する。In all the figures for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.
第1図は、本発明をセラミックコア基板にTSOP型半
導体装置を実装した電子装置に適用した一実施例の概略
構成を説明するための断面図。FIG. 1 is a cross-sectional view for explaining the schematic configuration of an embodiment in which the present invention is applied to an electronic device in which a TSOP type semiconductor device is mounted on a ceramic core substrate.
第2図は、第1図のセラミックコア基板の構成を示す断
面図、
第3図は、第1図の面実装部の拡大図である。2 is a cross-sectional view showing the structure of the ceramic core substrate shown in FIG. 1, and FIG. 3 is an enlarged view of the surface mounting section shown in FIG. 1.
本実施例の電子装置は、第1図に示すように、セラミッ
ク基板1の上にTSOP型半導体装置2のリード3をは
んだ4で接合(はんだ付け)シ。In the electronic device of this embodiment, as shown in FIG. 1, leads 3 of a TSOP type semiconductor device 2 are bonded (soldered) onto a ceramic substrate 1 with solder 4.
実装したものである。TSOP型半導体装置2のパッケ
ージの厚さは、約1.27mmである6前記セラミツク
コア基板1は、第2図に示すように、セラミックコア材
IAの両面に約18μ重厚の銅箔IBを張り付け、その
上にガラス布にエポキシ樹脂を含浸して乾燥した約10
0μ冨厚のプリプレグICを重ねて積層し、その上に約
18μ朧厚の銅箔IBを張り付け、その上に約100μ
■厚のプリプレグICを積層し、その上に約18μ朧厚
の銅箔IBを張り付けた多層配線構造になっている。It has been implemented. The thickness of the package of the TSOP type semiconductor device 2 is approximately 1.27 mm.6 As shown in FIG. , on top of that, a glass cloth was impregnated with epoxy resin and dried.
Prepreg ICs with a thickness of 0 μm are layered, a copper foil IB with a thickness of approximately 18 μm is pasted on top of the prepreg ICs, and a copper foil IB with a thickness of approximately 100 μm is placed on top of it.
■It has a multilayer wiring structure in which thick prepreg ICs are laminated and copper foil IB with a thickness of about 18 μm is pasted on top of it.
前記半導体装置2のTSOP (パッケージ)ボディ2
Aを挟んだり−ド3の間隔が長い程、TSOPと基板1
の熱膨張係数の差による歪が大きくなる。TSOP (package) body 2 of the semiconductor device 2
The longer the distance between A and C, the longer the distance between TSOP and board 1.
Distortion due to the difference in thermal expansion coefficients increases.
前述した歪による力がはんだ接合部に加わると、第3図
に示すように、半導体装置2のTSOPボディ2A、リ
ード3、セラミックコア基板1の3者に比較し、フット
プリント配線5上のはんだ4の強度が小さいため、はん
だ4の部分で破断が生じる場合がある。そこで、本発明
では、第2図に示すように、セラミックコア基板1の材
質にセラミックコア材を採用し、セラミックコア基板l
とTSOPボディ2Aの熱膨張係数の差を小さくし、は
んだ接合部の高信頼化を図ったものである。When the force due to the aforementioned strain is applied to the solder joint, as shown in FIG. Since the strength of solder 4 is low, breakage may occur at the solder 4 portion. Therefore, in the present invention, as shown in FIG. 2, a ceramic core material is adopted as the material of the ceramic core substrate 1, and the ceramic core substrate l
The difference in coefficient of thermal expansion between the TSOP body 2A and the TSOP body 2A is reduced, and the reliability of the solder joint is increased.
前記TSOPの種類、リードの剛性、はんだ付は状況等
により変わるが、比較にガラスエポキシ基板(熱膨張係
数15 X 10−’/”C)をとると、Tsopとの
熱膨張係数の差は、約7.6X10’−’となり、セラ
ミック基板lの場合の差(1,9X104)の4倍とな
る。このため、はんだ接合部の寿命は、セラミックコア
基板1を使用することにより、約10倍程度に伸びると
推定される。The type of TSOP, lead rigidity, and soldering will vary depending on the situation, etc., but if we take a glass epoxy board (thermal expansion coefficient 15 x 10-'/''C) for comparison, the difference in thermal expansion coefficient with Tsop is: This is approximately 7.6X10'-', which is four times the difference (1,9X104) in the case of ceramic substrate 1. Therefore, by using ceramic core substrate 1, the life of the solder joint is approximately 10 times longer. It is estimated that it will grow to a certain extent.
このように、本実施例によれば、セラミックコア基板1
と搭載するTSOP (薄型パッケージ)の熱膨張係数
の差を小さくできるため、温度変化時に、はんだ接合部
にかかる歪を小さくでき、はんだ接合部の信頼性を向上
することができる。In this way, according to this embodiment, the ceramic core substrate 1
Since it is possible to reduce the difference in the coefficient of thermal expansion between the TSOP and the mounted TSOP (thin package), the strain applied to the solder joints during temperature changes can be reduced, and the reliability of the solder joints can be improved.
また、TSOP型半導体装置2をはんだ実装した後の温
度サイクル試験において、はんだはがれ不良発生率は、
表1に示すように、サイクル数1000回では、ガラス
エポキシ基板は14箇のうち7箇が不良になった。これ
に対して、セラミックコア基板1では18箇のうち不良
は0であった。In addition, in a temperature cycle test after soldering the TSOP semiconductor device 2, the solder peeling failure rate was
As shown in Table 1, after 1000 cycles, 7 out of 14 glass epoxy substrates became defective. On the other hand, in ceramic core substrate 1, there were 0 defects out of 18 defects.
これに対して、セラミックコア基板1ではサイクル数1
5oO回で18箇のうち不良はOであった。On the other hand, in ceramic core substrate 1, the number of cycles is 1.
There were 0 defects out of 18 in 5oO cycles.
この実験結果からもわかるように、本実施例によれば、
温度変化時にはんだ接合部にかかる歪を小さくでき、は
んだ接合部の信頼性を向上することができる。As can be seen from the experimental results, according to this example,
It is possible to reduce the strain applied to the solder joint when the temperature changes, and improve the reliability of the solder joint.
表1 第4図に1本実施例の変形例を示す。Table 1 FIG. 4 shows a modification of this embodiment.
この変形例は、セラミックコア基板1側にチップコンデ
ンサ等の電子部品7を搭載する溝6を設けたものである
。このように構成することにより、溝6の部分でセラミ
ック基板1が変形し易いため、はんだ接合部に加わる力
が減少し、はんだ接合部の信頼性が向上する。In this modification, a groove 6 for mounting an electronic component 7 such as a chip capacitor is provided on the ceramic core substrate 1 side. With this configuration, the ceramic substrate 1 is easily deformed in the groove 6, so the force applied to the solder joint is reduced, and the reliability of the solder joint is improved.
以上、本発明を実施例にもとづき具体的に説明したが、
本発明は、前記実施例に限定されるものではなく、その
要旨を逸脱しないIi!囲において種々変更可能である
ことは言うまでもない。The present invention has been specifically explained above based on examples, but
The present invention is not limited to the embodiments described above, and does not depart from the gist thereof! It goes without saying that various changes can be made in the surroundings.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る
基板と搭載する薄型パッケージの熱膨張係数の差を小さ
くできるため、温度変化時にはんだ接合部にかかる歪を
小さくでき、はんだ接合部の信頼性を向上することがで
きる。To briefly explain the effects obtained by the representative inventions disclosed in this application, the difference in thermal expansion coefficient between the board and the mounted thin package can be reduced, so that solder joints can be bonded even when the temperature changes. The strain applied to the solder joint can be reduced, and the reliability of the soldered joint can be improved.
第1図は、本発明をセラミック基板にTS。
P型半導体装置を実装した電子装置に適用した一実施例
の概略構成を説明するための断面図、第2図は、第1図
のセラミックコア基板の構成を示す断面図、
第3図は、第1図の面実装部の拡大図、第4図は、本実
施例の変形例を示す図である。
図中、1・・・セラミック基板、2・・・半導体装置。
2A・・・半導体装置のTSOPボディ、3・・・リー
ド、4・・・はんだ、5・・・フットプリント配線、6
・・・溝、7・・・電子部品。Figure 1 shows a TS of the present invention on a ceramic substrate. A cross-sectional view for explaining the schematic configuration of an embodiment applied to an electronic device mounted with a P-type semiconductor device, FIG. 2 is a cross-sectional view showing the configuration of the ceramic core substrate of FIG. 1, and FIG. FIG. 1 is an enlarged view of the surface mounting section, and FIG. 4 is a diagram showing a modification of this embodiment. In the figure, 1...ceramic substrate, 2...semiconductor device. 2A... TSOP body of semiconductor device, 3... Lead, 4... Solder, 5... Footprint wiring, 6
...Groove, 7...Electronic parts.
Claims (3)
^−^6の単層又は10層以下の多層配線基板を用い、
対向リード端子間の間隔が10mm以上であり、当該多
層配線基板からのリードの高さが0.7mm以下のパッ
ケージの半導体装置を、少なくとも1箇面実装したこと
を特徴とする電子装置。1. Thermal expansion coefficient is 7.0×10^-^6~3.0×10
^-^Using a 6-layer single-layer or 10-layer or less multilayer wiring board,
An electronic device, characterized in that at least one semiconductor device is mounted in a package in which the distance between opposing lead terminals is 10 mm or more and the height of the leads from the multilayer wiring board is 0.7 mm or less.
れぞれ銅箔を張り付け、その上にガラス布にエポキシ樹
脂を含浸して乾燥したプリプレグを重ねて積層し、その
上に銅箔を張り付けた多層配線構造になっていることを
特徴とする請求項1に記載の電子装置。2. The multilayer wiring board has a multilayer wiring structure in which copper foil is pasted on both sides of a ceramic core board, prepreg made by impregnating glass cloth with epoxy resin and dried is laminated, and copper foil is pasted on top of that. The electronic device according to claim 1, characterized in that the electronic device has the following characteristics.
請求項1又は2に記載の電子装置。3. 3. The electronic device according to claim 1, wherein the surface mounting is performed by soldering.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2229308A JPH04111386A (en) | 1990-08-30 | 1990-08-30 | Electronic device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2229308A JPH04111386A (en) | 1990-08-30 | 1990-08-30 | Electronic device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04111386A true JPH04111386A (en) | 1992-04-13 |
Family
ID=16890108
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2229308A Pending JPH04111386A (en) | 1990-08-30 | 1990-08-30 | Electronic device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04111386A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04109565U (en) * | 1991-03-08 | 1992-09-22 | 富士通テン株式会社 | Composite board structure |
-
1990
- 1990-08-30 JP JP2229308A patent/JPH04111386A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04109565U (en) * | 1991-03-08 | 1992-09-22 | 富士通テン株式会社 | Composite board structure |
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